WO2018094858A1 - 像素驱动电路 - Google Patents

像素驱动电路 Download PDF

Info

Publication number
WO2018094858A1
WO2018094858A1 PCT/CN2017/070196 CN2017070196W WO2018094858A1 WO 2018094858 A1 WO2018094858 A1 WO 2018094858A1 CN 2017070196 W CN2017070196 W CN 2017070196W WO 2018094858 A1 WO2018094858 A1 WO 2018094858A1
Authority
WO
WIPO (PCT)
Prior art keywords
controllable switch
data
control
capacitor
reset
Prior art date
Application number
PCT/CN2017/070196
Other languages
English (en)
French (fr)
Inventor
王硕晟
张娣
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/324,689 priority Critical patent/US10249240B2/en
Publication of WO2018094858A1 publication Critical patent/WO2018094858A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel driving circuit.
  • the pixel driving circuit of the OLED display driving technology is of a current type, and a GOA (gate on array) is required to supply a scanning signal.
  • GOA gate on array
  • the OLED pixel drive circuit used in the market contains many functional thin film transistors (TFTs), for example, can compensate
  • TFTs thin film transistors
  • 6T1C/7T1C pixel drive circuit that drives the threshold voltage of the transistor, the use of multiple transistors makes the circuit design complicated and increases the cost.
  • the main technical problem to be solved by the present invention is to provide a pixel driving circuit to simplify circuits and reduce cost by using fewer thin film transistors.
  • the present invention adopts a technical solution to provide a pixel driving circuit, wherein the pixel driving circuit includes a plurality of pixel driving units that are cascaded, and each of the pixel driving units includes:
  • a first reset circuit connected to the first pixel, for receiving an input voltage and resetting the first pixel
  • a second reset circuit connected to the second pixel, for receiving the input voltage and resetting the second pixel
  • a first control circuit connected to the first and second reset circuits, for receiving a reference voltage and providing the first and second reset circuits
  • a second control circuit connecting the first and second reset circuits for receiving a data voltage and providing Giving the first and second reset circuits to simultaneously drive the first and second pixels;
  • the first control circuit includes a reference controllable switch, the control end of the reference controllable switch receives a lighting signal, the first end of the reference controllable switch receives the reference voltage, and the second of the reference controllable switch Connecting the second control circuit, the first and second reset circuits;
  • the first reset circuit includes first to third controllable switches and a first capacitor, the first end of the first controllable switch receives the input voltage, and the control end of the first controllable switch is connected to the a first end of the first capacitor, a second end of the first capacitor is connected to a second end of the reference controllable switch, the second reset circuit and the second control circuit, the first controllable switch The second end is connected to the first end of the second controllable switch and the first end of the third controllable switch, the control end of the second controllable switch receives the first scan signal, and the second The second end of the control switch is connected to the first end of the first capacitor and the control end of the first controllable switch, and the control end of the third controllable switch receives the illumination signal, and the third controllable a second end of the switch is connected to the anode of the first pixel, and a cathode of the first pixel is grounded;
  • the second reset circuit includes fourth to sixth controllable switches and a second capacitor, the first end of the fourth controllable switch receives the input voltage, and the control end of the fourth controllable switch is connected to the a first end of the second capacitor, the second end of the second capacitor is connected to the second end of the first capacitor, the second end of the reference controllable switch, and the second control circuit, the fourth a second end of the controllable switch is connected to the first end of the fifth controllable switch and a first end of the sixth controllable switch, and the control end of the fifth controllable switch receives a second scan signal, a second end of the fifth controllable switch is connected to the first end of the second capacitor and a control end of the fourth controllable switch, and the control end of the sixth controllable switch receives the illuminating signal, the a second end of the six controllable switch is connected to the anode of the second pixel, and a cathode of the second pixel is grounded;
  • the first reset circuit or the second reset circuit further includes a seventh controllable switch, the control end of the seventh controllable switch receives a reset signal, and the first end of the seventh controllable switch receives the input voltage,
  • the second end of the seventh controllable switch is connected to the first end of the first controllable switch and the first end of the fourth controllable switch;
  • the first reset circuit further includes an eighth controllable switch, the control end of the eighth controllable switch receives a reset signal, and the first end of the eighth controllable switch receives an initial signal, and the eighth controllable switch The second end is connected to the control end of the first controllable switch and the first end of the first capacitor;
  • the second reset circuit further includes a ninth controllable switch, the control end of the ninth controllable switch receives the reset signal, and the first end of the ninth controllable switch receives the initial signal, the first The second end of the nine controllable switch is connected to the control end of the fourth controllable switch and the first end of the second capacitor.
  • a technical solution adopted by the present invention is to provide a pixel driving circuit, the pixel driving circuit includes a plurality of pixel driving units that are cascaded, and each of the pixel driving units includes:
  • a first reset circuit connected to the first pixel, for receiving an input voltage and resetting the first pixel
  • a second reset circuit connected to the second pixel, for receiving the input voltage and resetting the second pixel
  • a first control circuit connected to the first and second reset circuits, for receiving a reference voltage and providing the first and second reset circuits
  • a second control circuit connected to the first and second reset circuits for receiving a data voltage and providing the first and second reset circuits to simultaneously drive the first and second pixels.
  • the first control circuit includes a reference controllable switch, and the control end of the reference controllable switch receives the illumination signal, the first end of the reference controllable switch receives the reference voltage, and the reference controllable switch The second end is connected to the second control circuit, the first and second reset circuits.
  • the first reset circuit includes first to third controllable switches and a first capacitor, the first end of the first controllable switch receives the input voltage, and the control end of the first controllable switch is connected. a first end of the first capacitor, a second end of the first capacitor is connected to a second end of the reference controllable switch, the second reset circuit, and the second control circuit, the first The second end of the control switch is connected to the first end of the second controllable switch and the first end of the third controllable switch, and the control end of the second controllable switch receives the first scan signal, the a second end of the second controllable switch is connected to the first end of the first capacitor and a control end of the first controllable switch, and the control end of the third controllable switch receives the illuminating signal, the third a second end of the controllable switch is connected to an anode of the first pixel, and a cathode of the first pixel is grounded;
  • the second reset circuit includes fourth to sixth controllable switches and a second capacitor, the first end of the fourth controllable switch receives the input voltage, and the control end of the fourth controllable switch is connected to the a first end of the second capacitor, the second end of the second capacitor is connected to the second end of the first capacitor, the second end of the reference controllable switch, and the second control circuit, the fourth a second end of the controllable switch is connected to the first end of the fifth controllable switch and a first end of the sixth controllable switch, and the control end of the fifth controllable switch receives a second scan signal, a second end of the fifth controllable switch is connected to the first end of the second capacitor and a control end of the fourth controllable switch, and the control end of the sixth controllable switch receives the illuminating signal, the a second end of the six controllable switch is connected to the anode of the second pixel, and a cathode of the second pixel is connected Ground.
  • the first reset circuit or the second reset circuit further includes a seventh controllable switch, the control end of the seventh controllable switch receives a reset signal, and the first end of the seventh controllable switch receives the input
  • the second end of the seventh controllable switch is connected to the first end of the first controllable switch and the first end of the fourth controllable switch.
  • the first to seventh controllable switches and the reference controllable switch are both P-type thin film transistors, and the first to seventh controllable switches and the control end and the first end of the reference controllable switch And the second end corresponds to a gate, a drain and a source of the P-type thin film transistor, respectively.
  • the first reset circuit further includes a seventh controllable switch, the control end of the seventh controllable switch receives a reset signal, and the first end of the seventh controllable switch receives an initial signal, and the seventh a second end of the control switch is connected to the control end of the first controllable switch and the first end of the first capacitor;
  • the second reset circuit further includes an eighth controllable switch, the control end of the eighth controllable switch receives the reset signal, and the first end of the eighth controllable switch receives the initial signal, the first The second end of the eight controllable switch is connected to the control end of the fourth controllable switch and the first end of the second capacitor.
  • the first reset circuit further includes a ninth controllable switch, the control end of the ninth controllable switch receives the reset signal, and the first end of the ninth controllable switch is connected to the third controllable a second end of the switch, the second end of the ninth controllable switch receiving the initial signal;
  • the second reset circuit further includes a tenth controllable switch, the control end of the tenth controllable switch receives the reset signal, and the first end of the tenth controllable switch is connected to the sixth controllable switch At a second end, the second end of the tenth controllable switch receives the initial signal.
  • the first to tenth controllable switches are all P-type thin film transistors, and the control ends, the first ends and the second ends of the first to tenth controllable switches respectively correspond to the gates of the P-type thin film transistors Pole, drain and source.
  • the second control circuit includes a data controllable switch, and the control end of the data controllable switch receives a scan reset signal, the first end of the data controllable switch receives the data voltage, and the data controllable switch
  • the second end of the first capacitor is connected to the second end of the first capacitor and the second end of the second capacitor
  • the data controllable switch is a P-type thin film transistor
  • the control end and the first end of the data controllable switch And the second end corresponds to a gate, a drain and a source of the P-type thin film transistor, respectively.
  • the second control circuit includes a data controllable switch, and the control end of the data controllable switch receives the illumination signal, and the first end of the data controllable switch receives the data voltage, and the data is controllable a second end of the switch is connected to the second end of the first capacitor and the second end of the second capacitor,
  • the data controllable switch is an N-type thin film transistor, and the control end, the first end and the second end of the data controllable switch respectively correspond to a gate, a drain and a source of the N-type thin film transistor.
  • the pixel driving circuit of the present invention uses a simple single rectangular pulse level transmission signal as a driving control signal, and controls two rows by the first and second scanning signals.
  • the pixel driving circuits are combined to save the number of transistors, and the threshold voltage compensation in the circuit is realized, thereby avoiding pixel flicker.
  • FIG. 1 is a schematic structural view of a first embodiment of a pixel driving unit of a pixel driving circuit of the present invention
  • Figure 2 is a time waveform diagram of Figure 1;
  • Figure 3 is another time waveform diagram of Figure 1;
  • Figure 4 is a waveform diagram of the simulation result of Figure 1;
  • FIG. 5 is a schematic structural view of a second embodiment of a scan driving unit of the pixel driving circuit of the present invention.
  • Figure 6 is a time waveform diagram of Figure 5;
  • FIG. 7 is a schematic structural view of a third embodiment of a scan driving unit of the pixel driving circuit of the present invention.
  • Figure 8 is a time waveform diagram of Figure 7;
  • Figure 9 is a waveform diagram of the simulation result of Figure 7.
  • FIG. 10 is a schematic structural view of a fourth embodiment of a scan driving unit of the pixel driving circuit of the present invention.
  • Figure 11 is a time waveform diagram of Figure 10.
  • FIG. 12 is a schematic structural view of a fifth embodiment of a scan driving unit of the pixel driving circuit of the present invention.
  • Figure 13 is a time waveform diagram of Figure 10
  • Figure 14 is a block diagram showing the structure of a sixth embodiment of a scan driving unit of the pixel driving circuit of the present invention.
  • Figure 15 is a time waveform diagram of Figure 14;
  • Figure 16 is a block diagram showing a seventh embodiment of a scan driving unit of the pixel driving circuit of the present invention.
  • Figure 17 is a time waveform diagram of Figure 16.
  • FIG. 18 is a schematic structural view of an eighth embodiment of a scan driving unit of the pixel driving circuit of the present invention.
  • Figure 19 is a time waveform diagram of Figure 18;
  • Fig. 20 is a waveform diagram of the simulation result of Fig. 18.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a pixel driving unit of a pixel driving circuit of the present invention.
  • the pixel driving circuit includes a plurality of pixel driving units that are cascaded, and each of the pixel driving units includes:
  • the first reset circuit 10 is connected to the first pixel OLED1 for receiving the input voltage VDD and resetting the first pixel OLED1;
  • the second reset circuit 20 is connected to the second pixel, and receives the input voltage VDD and resets the second pixel OLED2 by using the OLED 2;
  • a first control circuit 30, connected to the first and second reset circuits 10, 20 for receiving a reference voltage Vref and providing the first and second reset circuits 10, 20;
  • the second control circuit 40 is connected to the first and second reset circuits 10, 20 for receiving the data voltage Vdata and providing the first and second reset circuits 10, 20 to simultaneously drive the first and The second pixel OLED1, OLED2.
  • the first control circuit 30 includes a reference controllable switch T11, and the control end of the reference controllable switch T11 receives the illumination signal EM, and the first end of the reference controllable switch T11 receives the reference voltage Vref, The second end of the reference controllable switch T11 is connected to the second control circuit 40, the first and second reset circuits 10, 20.
  • the first reset circuit 10 includes first to third controllable switches T1-T3 and a first capacitor C1, and the first end of the first controllable switch T1 receives the input voltage VDD, the first controllable a control end of the switch T1 is connected to the first end of the first capacitor C1, a second end of the first capacitor C1 is connected to the second end of the reference controllable switch T11, the second reset circuit 20, and the a second control circuit 40, the second end of the first controllable switch T1 is connected to the first end of the second controllable switch T2 and the first end of the third controllable switch T3, the second The control end of the control switch T2 receives the first scan signal SG1, and the second end of the second controllable switch T2 is connected to the first end of the first capacitor C1 and the control end of the first controllable switch T1.
  • the control end of the third controllable switch T3 receives the illumination signal EM,
  • the second end of the third controllable switch T3 is connected to the anode of the first pixel OLED1, and the cathode of the first pixel OLED1 is grounded;
  • the second reset circuit 20 includes fourth to sixth controllable switches T4-T6 and a second capacitor C2, and the first end of the fourth controllable switch T4 receives the input voltage VDD, and the fourth controllable The control terminal of the open T4 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second end of the first capacitor C1 and the second end of the reference controllable switch T11.
  • the second end of the fourth controllable switch T4 is connected to the first end of the fifth controllable switch T5 and the first end of the sixth controllable switch T6,
  • the control end of the fifth controllable switch T5 receives the second scan signal SG2, and the second end of the fifth controllable switch T5 is connected to the first end of the second capacitor C2 and the control of the fourth controllable switch T4
  • the control end of the sixth controllable switch T6 receives the illumination signal EM
  • the second end of the sixth controllable switch T6 is connected to the anode of the second pixel OLED2, and the cathode of the second pixel OLED2 Ground.
  • the second control circuit 40 includes a data controllable switch T12.
  • the control end of the data controllable switch T12 receives a scan reset signal SG, and the first end of the data controllable switch T12 receives the data voltage Vdata.
  • the second end of the data controllable switch T12 is connected to the second end of the first capacitor C1 and the second end of the second capacitor C2.
  • the data controllable switch T12 is a P-type thin film transistor, and the data is controllable.
  • the control terminal, the first terminal and the second terminal of the switch T12 respectively correspond to a gate, a drain and a source of the P-type thin film transistor.
  • the first to sixth controllable switches T1-T6 and the reference controllable switch T11 are P-type thin film transistors, the first to sixth controllable switches T1-T6 and the The control terminal, the first end and the second end of the reference controllable switch T11 respectively correspond to the gate, the drain and the source of the P-type thin film transistor.
  • the first stage the second and third controllable switches T2 and T3 are turned on, and the control end of the first controllable switch T1 is reset by discharging to prepare for writing the first threshold voltage Vth1;
  • a signal Vdata1 the threshold voltage Vth1 of the first controllable switch T1 is obtained, and the voltage across the first capacitor C1 is VDD-Vth1 and data1, respectively, where VDD is an input voltage;
  • the third stage the fifth and sixth controllable switches T5 and T6 are both turned on, and the control end of the fourth controllable switch T4 is reset by discharging to prepare for writing the second threshold voltage Vth2;
  • the fourth stage the data controllable switch T12 and the fifth controllable switch T5 are both turned on, the reference The controllable switch T11 and the sixth controllable switch T6 are both turned off.
  • the second data signal Vdata2 is written to obtain the threshold voltage Vth2 of the fourth controllable switch T4, and the second capacitor C2 is The voltage at the terminals is VDD-Vth2 and Vdata2, respectively;
  • the fifth stage when the illuminating signal EM is at a low level, the potential of the first capacitor C1 is VDD-Vth1-Vdata1+Vref and Vref due to coupling, respectively; and the potential of the second capacitor C2 is due to coupling VDD-Vth2-Vdata2+Vref and Vref; wherein Vref is a reference voltage, and the currents of the first and second pixels OLED1 and OLED2 are respectively
  • the first and second pixels OLED1 and OLED2 are simultaneously driven by the pixel driving unit, and the threshold voltage Vth compensation is realized.
  • the input voltage VDD adopts a high-low level alternate signal to prevent flicker problems.
  • FIG. 5 is a schematic structural diagram of a second embodiment of a pixel driving unit of the pixel driving circuit of the present invention.
  • the second embodiment of the pixel driving unit is different from the first embodiment of the pixel driving unit in that the second control circuit 40 includes a data controllable switch T12, and the control of the data controllable switch T12 Receiving the illuminating signal EM, the first end of the data controllable switch T12 receives the data voltage Vdata, and the second end of the data controllable switch T12 is connected to the second end of the first capacitor C1
  • the second end of the second capacitor C2 the data controllable switch T12 is an N-type thin film transistor, and the control end, the first end and the second end of the data controllable switch T12 respectively correspond to the N-type thin film transistor Gate, drain and source.
  • control end of the data controllable switch T12 of the pixel driving circuit receives the illuminating signal EM, thereby reducing the number of driving signals, and the working principle is the same as that of the first embodiment of the pixel driving circuit. , will not repeat them here.
  • FIG. 9 is a schematic structural diagram of a third embodiment of a pixel driving unit of the pixel driving circuit of the present invention.
  • the third embodiment of the pixel driving unit is different from the first embodiment of the pixel driving unit in that the first reset circuit 10 or the second reset circuit 20 further includes a seventh controllable switch T7.
  • the control terminal of the seventh controllable switch T7 receives the reset signal Reset, the first end of the seventh controllable switch T7 receives the input voltage VDD, and the second end of the seventh controllable switch T7 is connected to the first a first end of the controllable switch T1 and a first end of the fourth controllable switch T4.
  • the seventh controllable switch T7 is a P-type thin film transistor, and the control end, the first end, and the second end of the seventh controllable switch T7 respectively correspond to the gate of the P-type thin film transistor , drain and source.
  • the first stage the second and third controllable switches T2 and T3 are turned on, the sixth controllable switch T6 is turned off, and the control end of the first controllable switch T1 is reset by discharging, for writing the threshold voltage Vth1 Preparing while the input voltage VDD is cut off, the current passed by the first pixel OLED1 is not abrupt;
  • the third stage the fifth and sixth controllable switches T5 and T6 are both turned on, the sixth controllable switch T6 is turned off, and the control end of the fourth controllable switch T4 is reset by discharging, for writing
  • the threshold voltage Vth2 is prepared, and the current passed by the second pixel OLED2 is not abrupt;
  • the fifth stage when the illuminating signal EM is at a low level, the potential of the first capacitor C1 is VDD-Vth1-Vdata1+Vref and Vref due to coupling, respectively; and the potential of the second capacitor C2 is due to coupling VDD-Vth2-Vdata2+Vref and Vref are respectively; the currents of the first and second pixels OLED1 and OLED2 are respectively:
  • the first and second pixels OLED1 and OLED2 are simultaneously driven by the pixel driving unit, and the threshold voltage Vth compensation is realized, thereby avoiding the problem of flickering of the first and second pixels OLED1, OLED2 in the reset phase.
  • FIG. 10 and FIG. 11 are structural diagrams of a fourth embodiment of a pixel driving unit of the pixel driving circuit of the present invention.
  • the fourth embodiment of the pixel driving unit is different from the third embodiment of the pixel driving unit in that the second control circuit 40 includes a data controllable switch T12.
  • the control end of the data controllable switch T12 receives the illumination signal EM, the first end of the data controllable switch T12 receives the data voltage Vdata, and the second end of the data controllable switch T12 is connected to the first The second end of the capacitor C1 and the second end of the second capacitor C2, the data controllable switch T12 is an N-type thin film transistor, and the control end, the first end and the second end of the data controllable switch T12 are respectively Corresponding to the gate, drain and source of the N-type thin film transistor.
  • control end of the data controllable switch T12 of the pixel driving circuit receives the illuminating signal EM, thereby reducing the number of driving signals, and the working principle is the same as that of the third embodiment of the pixel driving circuit. , will not repeat them here.
  • FIG. 12 is a schematic structural diagram of a fifth embodiment of a pixel driving unit of the pixel driving circuit of the present invention.
  • the fifth embodiment of the pixel driving unit is different from the first embodiment of the pixel driving unit in that the first reset circuit 10 further includes a seventh controllable switch T7, the seventh controllable switch The control terminal of the T7 receives the reset signal Reset, the first end of the seventh controllable switch T7 receives the initial signal VI, and the second end of the seventh controllable switch T7 is connected to the control end of the first controllable switch T1. And the first end of the first capacitor C1;
  • the second reset circuit 20 further includes an eighth controllable switch T8, the control end of the eighth controllable switch T8 receives the reset signal Reset, and the first end of the eighth controllable switch T8 receives the initial The signal VI, the second end of the eighth controllable switch T8 is connected to the control end of the fourth controllable switch T4 and the first end of the second capacitor C2.
  • the seventh and eighth controllable switches T7 and T8 are P-type thin film transistors, and the control ends, the first end and the second end of the seventh and eighth controllable switches T7 and T8 are Corresponding to the gate, drain and source of the P-type thin film transistor, respectively.
  • the first stage the seventh and eighth controllable switches T7 and T8 are both turned on, and the first and fourth controllable switches T1 and T4 are reset by the initial signal VI, and are written for the threshold voltages Vth1 and Vth2. Preparation; at this time, the potentials of the first and second capacitors C1, C2 are both VI and Vref;
  • the second stage the data controllable switch T12 and the second controllable switch T2 are both turned on, at which time the data signal Vdata1 is written, and the threshold voltage Vth1 of the first controllable switch T1 is obtained, the first The voltage across capacitor C1 is VDD-Vth1 and Vdata1, respectively;
  • the third stage the data controllable switch T12 and the fifth controllable switch T5 are both turned on, at this time, the data signal Vdata2 is written, and the threshold voltage Vth2 of the fourth controllable switch T4 is obtained, the second The voltage across capacitor C2 is VDD-Vth2 and Vdata2, respectively;
  • the fourth stage when the illuminating signal EM is at a low level, the potential of the first capacitor C1 is VDD-Vth1-Vdata1+Vref and Vref due to coupling, respectively; and the potential of the second capacitor C2 is due to coupling
  • the currents of the first and second pixels OLED1 and OLED2 are respectively: VDD-Vth2-Vdata2+Vref and Vref;
  • the first and second pixels OLED1 and OLED2 are simultaneously driven by the pixel driving unit, and the threshold voltage Vth compensation is realized.
  • FIG. 14 is a schematic structural diagram of a sixth embodiment of a pixel driving unit of the pixel driving circuit of the present invention.
  • the sixth embodiment of the pixel driving unit is different from the fifth embodiment of the pixel driving unit in that the second control circuit 40 includes a data controllable switch T12, and the data controllable switch T12 is controlled.
  • the first end of the data controllable switch T12 receives the data voltage Vdata, and the second end of the data controllable switch T12 is connected to the second end of the first capacitor C1
  • the second end of the second capacitor C2 the data controllable switch T12 is an N-type thin film transistor, and the control end, the first end and the second end of the data controllable switch T12 respectively correspond to the N-type thin film transistor Gate, drain and source.
  • control end of the data controllable switch T12 of the pixel driving circuit receives the illuminating signal EM, thereby reducing the number of driving signals, and the working principle is the same as that of the fifth embodiment of the pixel driving circuit. , will not repeat them here.
  • FIG. 16 and FIG. 17, are structural diagrams of a seventh embodiment of a pixel driving unit of the pixel driving circuit of the present invention.
  • the seventh embodiment of the pixel driving unit is different from the fifth embodiment of the pixel driving unit in that the first reset circuit 10 further includes a ninth controllable switch T9, the ninth controllable switch The control terminal of T9 receives the reset signal Reset, the first end of the ninth controllable switch T9 is connected to the second end of the third controllable switch T3, and the second end of the ninth controllable switch T9 is received.
  • the initial signal VI is the reset signal
  • the second reset circuit 20 further includes a tenth controllable switch T10, the control end of the tenth controllable switch T10 receives the reset signal Reset, and the first end of the tenth controllable switch T10 is connected to the first The second end of the six controllable switch T6, the second end of the tenth controllable switch T10 receives the initial signal VI.
  • the ninth and tenth controllable switches T9 and T10 are P-type thin film transistors, and the control ends, the first end and the second end of the ninth and tenth controllable switches T9 and T10 are Corresponding to the gate, drain and source of the P-type thin film transistor, respectively.
  • the second stage the data controllable switch T12 and the second controllable switch T2 are both turned on, at which time the data signal Vdata1 is written, and the threshold voltage Vth1 of the first controllable switch T1 is obtained, the first The voltage across capacitor C1 is VDD-Vth1 and Vdata1, respectively;
  • the third stage the data controllable switch T12 and the fifth controllable switch T5 are both turned on, at this time, the data signal Vdata2 is written, and the threshold voltage Vth2 of the fourth controllable switch T4 is obtained, the second The voltage across capacitor C2 is VDD-Vth2 and Vdata2, respectively;
  • the fourth stage when the illuminating signal EM is at a low level, the potential of the first capacitor C1 is VDD-Vth1-Vdata1+Vref and Vref due to coupling, respectively; and the potential of the second capacitor C2 is due to coupling
  • the currents of the first and second pixels OLED1 and OLED2 are respectively: VDD-Vth2-Vdata2+Vref and Vref;
  • the first and second pixels OLED1 and OLED2 are simultaneously driven by the pixel driving unit, and the threshold voltage Vth compensation is realized.
  • FIG. 18 is a schematic structural diagram of an eighth embodiment of a pixel driving unit of the pixel driving circuit of the present invention.
  • the eighth embodiment of the pixel driving unit is different from the seventh embodiment of the pixel driving unit in that the second control circuit 40 includes a data controllable switch T12, and the data controllable switch T12 is controlled.
  • the first end of the data controllable switch T12 receives the data voltage Vdata, and the second end of the data controllable switch T12 is connected to the second end of the first capacitor C1
  • the second end of the second capacitor C2 the data controllable switch T12 is an N-type thin film transistor, and the control end, the first end and the second end of the data controllable switch T12 respectively correspond to the N-type thin film transistor Gate, drain and source.
  • control end of the data controllable switch T12 of the pixel driving circuit receives the illuminating signal EM, thereby reducing the number of driving signals, and the working principle is the same as that of the seventh embodiment of the pixel driving circuit. , will not repeat them here.
  • the pixel driving circuit uses a simple single rectangular pulse-level signal as a driving control signal, and combines two rows of pixel driving circuits controlled by the first and second scanning signals to save the number of transistors and realize the circuit.
  • Medium threshold voltage compensation avoids pixel flicker problems.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素驱动电路，包括级联的多个像素驱动单元，每一像素驱动单元包括第一复位电路（10），连接第一像素（OLED1），接收输入电压（VDD）并对第一像素（OLED1）进行复位；第二复位电路（20），连接第二像素（OLED2），接收输入电压（VDD）并对第二像素（OLED2）进行复位；第一控制电路（30），连接第一及第二复位电路（10，20），接收参考电压（Vref）并提供给第一及第二复位电路（10，20）；第二控制电路（40），连接第一及第二复位电路（10，20），接收数据电压（Vdata）并提供给第一及第二复位电路（10，20），以同时驱动第一及第二像素（OLED1，OLED2）。

Description

像素驱动电路 【技术领域】
本发明涉及显示技术领域，特别是涉及一种像素驱动电路。
【背景技术】
随着高清显示屏的发展，人们追求更大屏，更高的分辨率，更刺激的视觉效果，广视角、高色域、高PPI显示技术的开发已经成为了行业的趋势。OLED屏高对比度、宽视角、高饱和度、低能耗等优势，无疑将其推向显示市场发展前沿。然而OLED显示驱动技术的像素驱动电路属于电流型，需要GOA(gate on array)供给扫描信号，同时，为了较佳的显示效果和阈值电压补偿效果，需要额外为像素驱动电路提供多重信号。其次，为了实现较高画面均匀和舒适的画面体验感，2T1C的OLED像素驱动电路已经逐渐退出大众视野，市面上所用的OLED像素驱动电路中包含很多功能性的薄膜晶体管(TFT)，例如可以补偿驱动晶体管阈值电压的6T1C/7T1C像素驱动电路，多重晶体管的使用使得电路设计复杂而且会增加成本。
【发明内容】
本发明主要解决的技术问题是提供一种像素驱动电路，以使用较少的薄膜晶体管来简化电路并降低成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素驱动电路，其中，所述像素驱动电路包括级联的多个像素驱动单元，每一所述像素驱动单元包括：
第一复位电路，连接第一像素，用于接收输入电压并对所述第一像素进行复位；
第二复位电路，连接第二像素，用于接收输入电压并对所述第二像素进行复位；
第一控制电路，连接所述第一及第二复位电路，用于接收参考电压并提供给所述第一及第二复位电路；及
第二控制电路，连接所述第一及第二复位电路，用于接收数据电压并提供 给所述第一及第二复位电路，以同时驱动所述第一及第二像素；
所述第一控制电路包括参考可控开关，所述参考可控开关的控制端接收发光信号，所述参考可控开关的第一端接收所述参考电压，所述参考可控开关的第二端连接所述第二控制电路、第一及第二复位电路；
所述第一复位电路包括第一至第三可控开关及第一电容，所述第一可控开关的第一端接收所述输入电压，所述第一可控开关的控制端连接所述第一电容的第一端，所述第一电容的第二端连接所述参考可控开关的第二端、所述第二复位电路及所述第二控制电路，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述第三可控开关的第一端，所述第二可控开关的控制端接收第一扫描信号，所述第二可控开关的第二端连接所述第一电容的第一端及所述第一可控开关的控制端，所述第三可控开关的控制端接收所述发光信号，所述第三可控开关的第二端连接所述第一像素的阳极，所述第一像素的阴极接地；
所述第二复位电路包括第四至第六可控开关及第二电容，所述第四可控开关的第一端接收所述输入电压，所述第四可控开关的控制端连接所述第二电容的第一端，所述第二电容的第二端连接所述第一电容的第二端、所述参考可控开关的第二端及所述第二控制电路，所述第四可控开关的第二端连接所述第五可控开关的第一端及所述第六可控开关的第一端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第二端连接所述第二电容的第一端及所述第四可控开关的控制端，所述第六可控开关的控制端接收所述发光信号，所述第六可控开关的第二端连接所述第二像素的阳极，所述第二像素的阴极接地；
所述第一复位电路或所述第二复位电路还包括第七可控开关，所述第七可控开关的控制端接收复位信号，所述第七可控开关的第一端接收输入电压，所述第七可控开关的第二端连接所述第一可控开关的第一端及所述第四可控开关的第一端；
所述第一复位电路还包括第八可控开关，所述第八可控开关的控制端接收复位信号，所述第八可控开关的第一端接收初始信号，所述第八可控开关的第二端连接所述第一可控开关的控制端及所述第一电容的第一端；
所述第二复位电路还包括第九可控开关，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端接收所述初始信号，所述第九可控开关的第二端连接所述第四可控开关的控制端及所述第二电容的第一端。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素驱动电路，所述像素驱动电路包括级联的多个像素驱动单元，每一所述像素驱动单元包括：
第一复位电路，连接第一像素，用于接收输入电压并对所述第一像素进行复位；
第二复位电路，连接第二像素，用于接收输入电压并对所述第二像素进行复位；
第一控制电路，连接所述第一及第二复位电路，用于接收参考电压并提供给所述第一及第二复位电路；及
第二控制电路，连接所述第一及第二复位电路，用于接收数据电压并提供给所述第一及第二复位电路，以同时驱动所述第一及第二像素。
其中，所述第一控制电路包括参考可控开关，所述参考可控开关的控制端接收发光信号，所述参考可控开关的第一端接收所述参考电压，所述参考可控开关的第二端连接所述第二控制电路、第一及第二复位电路。
其中，所述第一复位电路包括第一至第三可控开关及第一电容，所述第一可控开关的第一端接收所述输入电压，所述第一可控开关的控制端连接所述第一电容的第一端，所述第一电容的第二端连接所述参考可控开关的第二端、所述第二复位电路及所述第二控制电路，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述第三可控开关的第一端，所述第二可控开关的控制端接收第一扫描信号，所述第二可控开关的第二端连接所述第一电容的第一端及所述第一可控开关的控制端，所述第三可控开关的控制端接收所述发光信号，所述第三可控开关的第二端连接所述第一像素的阳极，所述第一像素的阴极接地；
所述第二复位电路包括第四至第六可控开关及第二电容，所述第四可控开关的第一端接收所述输入电压，所述第四可控开关的控制端连接所述第二电容的第一端，所述第二电容的第二端连接所述第一电容的第二端、所述参考可控开关的第二端及所述第二控制电路，所述第四可控开关的第二端连接所述第五可控开关的第一端及所述第六可控开关的第一端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第二端连接所述第二电容的第一端及所述第四可控开关的控制端，所述第六可控开关的控制端接收所述发光信号，所述第六可控开关的第二端连接所述第二像素的阳极，所述第二像素的阴极接 地。
其中，所述第一复位电路或所述第二复位电路还包括第七可控开关，所述第七可控开关的控制端接收复位信号，所述第七可控开关的第一端接收输入电压，所述第七可控开关的第二端连接所述第一可控开关的第一端及所述第四可控开关的第一端。
其中，所述第一至第七可控开关及所述参考可控开关均为P型薄膜晶体管，所述第一至第七可控开关及所述参考可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
其中，所述第一复位电路还包括第七可控开关，所述第七可控开关的控制端接收复位信号，所述第七可控开关的第一端接收初始信号，所述第七可控开关的第二端连接所述第一可控开关的控制端及所述第一电容的第一端；
所述第二复位电路还包括第八可控开关，所述第八可控开关的控制端接收所述复位信号，所述第八可控开关的第一端接收所述初始信号，所述第八可控开关的第二端连接所述第四可控开关的控制端及所述第二电容的第一端。
其中，所述第一复位电路还包括第九可控开关，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第三可控开关的第二端，所述第九可控开关的第二端接收所述初始信号；
所述第二复位电路还包括第十可控开关，所述第十可控开关的控制端接收所述复位信号，所述第十可控开关的第一端连接所述第六可控开关的第二端，所述第十可控开关的第二端接收所述初始信号。
其中，所述第一至第十可控开关均为P型薄膜晶体管，所述第一至第十可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收扫描复位信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为P型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收所述发光信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述 数据可控开关为N型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
本发明的有益效果是：区别于现有技术的情况，本发明的所述像素驱动电路将简单的单矩形脉冲级传信号作为驱动控制信号，把两行由第一及第二扫描信号控制的像素驱动电路合并，来达到节省电晶体数目的目的，同时实现了电路中阈值电压补偿，避免了像素闪烁问题。
【附图说明】
图1是本发明的像素驱动电路的一个像素驱动单元的第一实施例的结构示意图；
图2是图1的一种时间波形图；
图3是图1的另一种时间波形图；
图4是图1的模拟结果波形图；
图5是本发明的像素驱动电路的一个扫描驱动单元的第二实施例的结构示意图；
图6是图5的时间波形图；
图7是本发明的像素驱动电路的一个扫描驱动单元的第三实施例的结构示意图；
图8是图7的时间波形图；
图9是图7的模拟结果波形图；
图10是本发明的像素驱动电路的一个扫描驱动单元的第四实施例的结构示意图；
图11是图10的时间波形图；
图12是本发明的像素驱动电路的一个扫描驱动单元的第五实施例的结构示意图；
图13是图10的时间波形图；
图14是本发明的像素驱动电路的一个扫描驱动单元的第六实施例的结构示意图；
图15是图14的时间波形图；
图16是本发明的像素驱动电路的一个扫描驱动单元的第七实施例的结构示意图；
图17是图16的时间波形图；
图18是本发明的像素驱动电路的一个扫描驱动单元的第八实施例的结构示意图；
图19是图18的时间波形图；
图20是图18的模拟结果波形图。
【具体实施方式】
请参阅图1，请参阅图1至图4，是本发明的像素驱动电路的一个像素驱动单元的第一实施例的结构示意图。所述像素驱动电路包括级联的多个像素驱动单元，每一所述像素驱动单元包括：
第一复位电路10，连接第一像素OLED1，用于接收输入电压VDD并对所述第一像素OLED1进行复位；
第二复位电路20，连接第二像素，用OLED2于接收输入电压VDD并对所述第二像素OLED2进行复位；
第一控制电路30，连接所述第一及第二复位电路10、20，用于接收参考电压Vref并提供给所述第一及第二复位电路10、20；及
第二控制电路40，连接所述第一及第二复位电路10、20，用于接收数据电压Vdata并提供给所述第一及第二复位电路10、20，以同时驱动所述第一及第二像素OLED1、OLED2。
具体地，所述第一控制电路30包括参考可控开关T11，所述参考可控开关T11的控制端接收发光信号EM，所述参考可控开关T11的第一端接收所述参考电压Vref，所述参考可控开关T11的第二端连接所述第二控制电路40、第一及第二复位电路10、20。
所述第一复位电路10包括第一至第三可控开关T1-T3及第一电容C1，所述第一可控开关T1的第一端接收所述输入电压VDD，所述第一可控开关T1的控制端连接所述第一电容C1的第一端，所述第一电容C1的第二端连接所述参考可控开关T11的第二端、所述第二复位电路20及所述第二控制电路40，所述第一可控开关T1的第二端连接所述第二可控开关T2的第一端及所述第三可控开关T3的第一端，所述第二可控开关T2的控制端接收第一扫描信号SG1，所述第二可控开关T2的第二端连接所述第一电容C1的第一端及所述第一可控开关T1的控制端，所述第三可控开关T3的控制端接收所述发光信号EM，所述 第三可控开关T3的第二端连接所述第一像素OLED1的阳极，所述第一像素OLED1的阴极接地；
所述第二复位电路20包括第四至第六可控开关T4-T6及第二电容C2，所述第四可控开关T4的第一端接收所述输入电压VDD，所述第四可控开T4的控制端连接所述第二电容C2的第一端，所述第二电容C2的第二端连接所述第一电容C1的第二端、所述参考可控开关T11的第二端及所述第二控制电路40，所述第四可控开关T4的第二端连接所述第五可控开关T5的第一端及所述第六可控开关T6的第一端，所述第五可控开关T5的控制端接收第二扫描信号SG2，所述第五可控开关T5的第二端连接所述第二电容C2的第一端及所述第四可控开关T4的控制端，所述第六可控开关T6的控制端接收所述发光信号EM，所述第六可控开关T6的第二端连接所述第二像素OLED2的阳极，所述第二像素OLED2的阴极接地。
所述第二控制电路40包括数据可控开关T12，所述数据可控开关T12的控制端接收扫描复位信号SG，所述数据可控开关T12的第一端接收所述数据电压Vdata，所述数据可控开关T12的第二端连接所述第一电容C1的第二端及所述第二电容C2的第二端，所述数据可控开关T12为P型薄膜晶体管，所述数据可控开关T12的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
在本实施例中，所述第一至第六可控开关T1-T6及所述参考可控开关T11均为P型薄膜晶体管，所述第一至第六可控开关T1-T6及所述参考可控开关T11的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
以下对所述像素驱动电路的第一实施例的工作原理进行详细描述：
第一阶段：所述第二及第三可控开关T2和T3导通，所述第一可控开关T1的控制端通过放电进行复位，为写入第一阈值电压Vth1做准备；
第二阶段：所述数据可控开关T12及所述第二可控开关T2均导通，所述参考可控开关T11及所述第三可控开关T3均截止，此时写入第一数据信号Vdata1，获取所述第一可控开关T1的阈值电压Vth1，此时所述第一电容C1两端的电压分别为VDD-Vth1和data1，其中VDD为输入电压；
第三阶段：所述第五及第六可控开关T5和T6均导通，所述第四可控开关T4的控制端通过放电进行复位，为写入第二阈值电压Vth2做准备；
第四阶段：所述数据可控开关T12及所述第五可控开关T5均导通，所述参 考可控开关T11及所述第六可控开关T6均截止，此时写入第二数据信号Vdata2，获取所述第四可控开关T4的阈值电压Vth2，此时所述第二电容C2两端的电压分别为VDD-Vth2和Vdata2；
第五阶段：所述发光信号EM为低电平时，所述第一电容C1由于耦合作用两端电位分别为VDD-Vth1-Vdata1+Vref和Vref；所述第二电容C2由于耦合作用两端电位分别为VDD-Vth2-Vdata2+Vref和Vref；其中，Vref为参考电压，此时第一及第二像素OLED1、OLED2通过的电流分别为
IOLED1＝K(VGS1-Vth)＝K(Vdata1-Vref)2
IOLED2＝K(VGS2-Vth)＝K(Vdata2-Vref)2
以此实现通过所述像素驱动单元同时驱动第一及第二像素OLED1及OLED2，并且实现阈值电压Vth补偿。
请参阅图3，由于复位时会使通过第一及第二像素OLED1、OLED2的电流瞬间变大，产生屏幕闪烁，所以输入电压VDD采用高低电平交替信号以防止出现闪烁问题。
请参阅图5及图6，是本发明的像素驱动电路的一个像素驱动单元的第二实施例的结构示意图。所述像素驱动单元的第二实施例与所述像素驱动单元的第一实施例的区别之处在于：所述第二控制电路40包括数据可控开关T12，所述数据可控开关T12的控制端接收所述发光信号EM，所述数据可控开关T12的第一端接收所述数据电压Vdata，所述数据可控开关T12的第二端连接所述第一电容C1的第二端及所述第二电容C2的第二端，所述数据可控开关T12为N型薄膜晶体管，所述数据可控开关T12的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
在本实施例中，所述像素驱动电路的数据可控开关T12的控制端接收发光信号EM，以此来减少驱动信号数量，其工作原理与上述像素驱动电路的第一实施例的工作原理相同，在此不再赘述。
请参阅图7至图9，是本发明的像素驱动电路的一个像素驱动单元的第三实施例的结构示意图。所述像素驱动单元的第三实施例与所述像素驱动单元的第一实施例的区别之处在于：所述第一复位电路10或所述第二复位电路20还包括第七可控开关T7，所述第七可控开关T7的控制端接收复位信号Reset，所述第七可控开关T7的第一端接收输入电压VDD，所述第七可控开关T7的第二端连接所述第一可控开关T1的第一端及所述第四可控开关T4的第一端。
在本实施例中，所述第七可控开关T7为P型薄膜晶体管，所述第七可控开关T7的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
以下对所述像素驱动电路的第三实施例的工作原理进行详细描述：
第一阶段：第二及第三可控开关T2和T3导通，所述第六可控开关T6截止，所述第一可控开关T1的控制端通过放电进行复位，为写入阈值电压Vth1做准备，同时所述输入电压VDD被截断，所述第一像素OLED1通过的电流不会突变；
第二阶段：所述第六可控开关T6、所述数据可控开关T12及所述第二可控开关T2均导通，所述参考可控开关T11及所述第三可控开关T3均截止，此时写入数据信号Vdata1，获取所述第一可控开关T1的阈值电压Vth 1，第一电容C1两端的电压分别为VDD-Vth1和Vdata1；
第三阶段：所述第五及第六可控开关T5和T6均导通，所述第六可控开关T6截止，所述第四可控开关T4的控制端通过放电进行复位，为写入阈值电压Vth2做准备，所述第二像素OLED2通过的电流不会突变；
第四阶段：所述第六可控开关T6、所述数据可控开关T12及所述第五可控开关T5均导通，所述参考可控开关T11及所述第六可控开关T6均截止，此时写入数据信号Vdata2，获取所述第四可控开关T4的阈值电压Vth2，所述第二电容C2两端的电压分别为VDD-Vth2和Vdata2；
第五阶段：所述发光信号EM为低电平时，所述第一电容C1由于耦合作用两端电位分别为VDD-Vth1-Vdata1+Vref和Vref；所述第二电容C2由于耦合作用两端电位分别为VDD-Vth2-Vdata2+Vref和Vref；此时第一及第二像素OLED1及OLED2通过的电流分别为：
IOLED1＝K(VGS1-Vth)＝K(Vdata1-Vref)2
IOLED2＝K(VGS2-Vth)＝K(Vdata2-Vref)2
以此实现通过所述像素驱动单元同时驱动第一及第二像素OLED1及OLED2，并且实现阈值电压Vth补偿，避免了复位阶段第一及第二像素OLED1、OLED2的闪烁问题。
请参阅图10及图11，是本发明的像素驱动电路的一个像素驱动单元的第四实施例的结构示意图。所述像素驱动单元的第四实施例与所述像素驱动单元的第三实施例的区别之处在于：所述第二控制电路40包括数据可控开关T12，所 述数据可控开关T12的控制端接收所述发光信号EM，所述数据可控开关T12的第一端接收所述数据电压Vdata，所述数据可控开关T12的第二端连接所述第一电容C1的第二端及所述第二电容C2的第二端，所述数据可控开关T12为N型薄膜晶体管，所述数据可控开关T12的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
在本实施例中，所述像素驱动电路的数据可控开关T12的控制端接收发光信号EM，以此来减少驱动信号数量，其工作原理与上述像素驱动电路的第三实施例的工作原理相同，在此不再赘述。
请参阅图12及图13，是本发明的像素驱动电路的一个像素驱动单元的第五实施例的结构示意图。所述像素驱动单元的第五实施例与所述像素驱动单元的第一实施例的区别之处在于：所述第一复位电路10还包括第七可控开关T7，所述第七可控开关T7的控制端接收复位信号Reset，所述第七可控开关T7的第一端接收初始信号VI，所述第七可控开关T7的第二端连接所述第一可控开关T1的控制端及所述第一电容C1的第一端；
所述第二复位电路20还包括第八可控开关T8，所述第八可控开关T8的控制端接收所述复位信号Reset，所述第八可控开关T8的第一端接收所述初始信号VI，所述第八可控开关T8的第二端连接所述第四可控开关T4的控制端及所述第二电容C2的第一端。
在本实施例中，所述第七及第八可控开关T7、T8均为P型薄膜晶体管，所述第七及第八可控开关T7、T8的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
以下对所述像素驱动电路的第五实施例的工作原理进行详细描述：
第一阶段：所述第七及第八可控开关T7和T8均导通，所述第一及第四可控开关T1、T4通过初始讯号VI进行复位，为写入阈值电压Vth1及Vth2做准备；此时第一及第二电容C1、C2两端电位均为VI和Vref；
第二阶段：所述数据可控开关T12及所述第二可控开关T2均导通，此时写入数据信号Vdata1，获取所述第一可控开关T1的阈值电压Vth1，所述第一电容C1两端的电压分别为VDD-Vth1和Vdata1；
第三阶段：所述数据可控开关T12及所述第五可控开关T5均导通，此时写入数据信号Vdata2，获取所述第四可控开关T4的阈值电压Vth2，所述第二电容C2两端的电压分别为VDD-Vth2和Vdata2；
第四阶段：所述发光信号EM为低电平时，所述第一电容C1由于耦合作用两端电位分别为VDD-Vth1-Vdata1+Vref和Vref；所述第二电容C2由于耦合作用两端电位分别为VDD-Vth2-Vdata2+Vref和Vref；此时所述第一及第二像素OLED1、OLED2通过的电流分别为：
IOLED1＝K(VGS1-Vth)＝K(Vdata1-Vref)2
IOLED2＝K(VGS2-Vth)＝K(Vdata2-Vref)2
以此实现通过所述像素驱动单元同时驱动第一及第二像素OLED1及OLED2，并且实现阈值电压Vth补偿。
请参阅图14及图15，是本发明的像素驱动电路的一个像素驱动单元的第六实施例的结构示意图。所述像素驱动单元的第六实施例与所述像素驱动单元的第五实施例的区别之处在于：所述第二控制电路40包括数据可控开关T12，所述数据可控开关T12的控制端接收所述发光信号EM，所述数据可控开关T12的第一端接收所述数据电压Vdata，所述数据可控开关T12的第二端连接所述第一电容C1的第二端及所述第二电容C2的第二端，所述数据可控开关T12为N型薄膜晶体管，所述数据可控开关T12的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
在本实施例中，所述像素驱动电路的数据可控开关T12的控制端接收发光信号EM，以此来减少驱动信号数量，其工作原理与上述像素驱动电路的第五实施例的工作原理相同，在此不再赘述。
请参阅图16及图17，是本发明的像素驱动电路的一个像素驱动单元的第七实施例的结构示意图。所述像素驱动单元的第七实施例与所述像素驱动单元的第五实施例的区别之处在于：所述第一复位电路10还包括第九可控开关T9，所述第九可控开关T9的控制端接收所述复位信号Reset，所述第九可控开关T9的第一端连接所述第三可控开关T3的第二端，所述第九可控开关T9的第二端接收所述初始信号VI；
所述第二复位电路20还包括第十可控开关T10，所述第十可控开关T10的控制端接收所述复位信号Reset，所述第十可控开关T10的第一端连接所述第六可控开关T6的第二端，所述第十可控开关T10的第二端接收所述初始信号VI。
在本实施例中，所述第九及第十可控开关T9、T10均为P型薄膜晶体管，所述第九及第十可控开关T9、T10的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
以下对所述像素驱动电路的第七实施例的工作原理进行详细描述：
第一阶段：所述第七可控开关T7、所述第八可控开关T8、所述第九可控开关T9及所述第十可控开关T10均导通，所述第一可控开关T1和所述第四可控开关T4均通过初始讯号VI进行复位，为写入阈值电压Vth1及Vth2做准备；此时第一及第二电容C1和C2两端电位均为VI和Vref；同时所述第一及第二像素OLED1及OLED2的阳极通过所述第九及第十可控开关T9、T10进行复位；
第二阶段：所述数据可控开关T12及所述第二可控开关T2均导通，此时写入数据信号Vdata1，获取所述第一可控开关T1的阈值电压Vth1，所述第一电容C1两端的电压分别为VDD-Vth1和Vdata1；
第三阶段：所述数据可控开关T12及所述第五可控开关T5均导通，此时写入数据信号Vdata2，获取所述第四可控开关T4的阈值电压Vth2，所述第二电容C2两端的电压分别为VDD-Vth2和Vdata2；
第四阶段：所述发光信号EM为低电平时，所述第一电容C1由于耦合作用两端电位分别为VDD-Vth1-Vdata1+Vref和Vref；所述第二电容C2由于耦合作用两端电位分别为VDD-Vth2-Vdata2+Vref和Vref；此时所述第一及第二像素OLED1、OLED2通过的电流分别为：
IOLED1＝K(VGS1-Vth)＝K(Vdata1-Vref)2
IOLED2＝K(VGS2-Vth)＝K(Vdata2-Vref)2
以此实现通过所述像素驱动单元同时驱动第一及第二像素OLED1及OLED2，并且实现阈值电压Vth补偿。
请参阅图18至图20，是本发明的像素驱动电路的一个像素驱动单元的第八实施例的结构示意图。所述像素驱动单元的第八实施例与所述像素驱动单元的第七实施例的区别之处在于：所述第二控制电路40包括数据可控开关T12，所述数据可控开关T12的控制端接收所述发光信号EM，所述数据可控开关T12的第一端接收所述数据电压Vdata，所述数据可控开关T12的第二端连接所述第一电容C1的第二端及所述第二电容C2的第二端，所述数据可控开关T12为N型薄膜晶体管，所述数据可控开关T12的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
在本实施例中，所述像素驱动电路的数据可控开关T12的控制端接收发光信号EM，以此来减少驱动信号数量，其工作原理与上述像素驱动电路的第七实施例的工作原理相同，在此不再赘述。
所述像素驱动电路将简单的单矩形脉冲级传信号作为驱动控制信号，把两行由第一及第二扫描信号控制的像素驱动电路合并，来达到节省电晶体数目的目的，同时实现了电路中阈值电压补偿，避免了像素闪烁问题。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种像素驱动电路，其中，所述像素驱动电路包括级联的多个像素驱动单元，每一所述像素驱动单元包括：
    第一复位电路，连接第一像素，用于接收输入电压并对所述第一像素进行复位；
    第二复位电路，连接第二像素，用于接收输入电压并对所述第二像素进行复位；
    第一控制电路，连接所述第一及第二复位电路，用于接收参考电压并提供给所述第一及第二复位电路；及
    第二控制电路，连接所述第一及第二复位电路，用于接收数据电压并提供给所述第一及第二复位电路，以同时驱动所述第一及第二像素；
    所述第一控制电路包括参考可控开关，所述参考可控开关的控制端接收发光信号，所述参考可控开关的第一端接收所述参考电压，所述参考可控开关的第二端连接所述第二控制电路、第一及第二复位电路；
    所述第一复位电路包括第一至第三可控开关及第一电容，所述第一可控开关的第一端接收所述输入电压，所述第一可控开关的控制端连接所述第一电容的第一端，所述第一电容的第二端连接所述参考可控开关的第二端、所述第二复位电路及所述第二控制电路，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述第三可控开关的第一端，所述第二可控开关的控制端接收第一扫描信号，所述第二可控开关的第二端连接所述第一电容的第一端及所述第一可控开关的控制端，所述第三可控开关的控制端接收所述发光信号，所述第三可控开关的第二端连接所述第一像素的阳极，所述第一像素的阴极接地；
    所述第二复位电路包括第四至第六可控开关及第二电容，所述第四可控开关的第一端接收所述输入电压，所述第四可控开关的控制端连接所述第二电容的第一端，所述第二电容的第二端连接所述第一电容的第二端、所述参考可控开关的第二端及所述第二控制电路，所述第四可控开关的第二端连接所述第五可控开关的第一端及所述第六可控开关的第一端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第二端连接所述第二电容的第一端及所述第四可控开关的控制端，所述第六可控开关的控制端接收所述发光信号，所述第六可控开关的第二端连接所述第二像素的阳极，所述第二像素的阴极接 地；
    所述第一复位电路或所述第二复位电路还包括第七可控开关，所述第七可控开关的控制端接收复位信号，所述第七可控开关的第一端接收输入电压，所述第七可控开关的第二端连接所述第一可控开关的第一端及所述第四可控开关的第一端；
    所述第一复位电路还包括第八可控开关，所述第八可控开关的控制端接收复位信号，所述第八可控开关的第一端接收初始信号，所述第八可控开关的第二端连接所述第一可控开关的控制端及所述第一电容的第一端；
    所述第二复位电路还包括第九可控开关，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端接收所述初始信号，所述第九可控开关的第二端连接所述第四可控开关的控制端及所述第二电容的第一端。
  2. 一种像素驱动电路，其中，所述像素驱动电路包括级联的多个像素驱动单元，每一所述像素驱动单元包括：
    第一复位电路，连接第一像素，用于接收输入电压并对所述第一像素进行复位；
    第二复位电路，连接第二像素，用于接收输入电压并对所述第二像素进行复位；
    第一控制电路，连接所述第一及第二复位电路，用于接收参考电压并提供给所述第一及第二复位电路；及
    第二控制电路，连接所述第一及第二复位电路，用于接收数据电压并提供给所述第一及第二复位电路，以同时驱动所述第一及第二像素。
  3. 根据权利要求2所述的像素驱动电路，其中，所述第一控制电路包括参考可控开关，所述参考可控开关的控制端接收发光信号，所述参考可控开关的第一端接收所述参考电压，所述参考可控开关的第二端连接所述第二控制电路、第一及第二复位电路。
  4. 根据权利要求3所述的像素驱动电路，其中，所述第一复位电路包括第一至第三可控开关及第一电容，所述第一可控开关的第一端接收所述输入电压，所述第一可控开关的控制端连接所述第一电容的第一端，所述第一电容的第二端连接所述参考可控开关的第二端、所述第二复位电路及所述第二控制电路，所述第一可控开关的第二端连接所述第二可控开关的第一端及所述第三可控开关的第一端，所述第二可控开关的控制端接收第一扫描信号，所述第二可控开 关的第二端连接所述第一电容的第一端及所述第一可控开关的控制端，所述第三可控开关的控制端接收所述发光信号，所述第三可控开关的第二端连接所述第一像素的阳极，所述第一像素的阴极接地；
    所述第二复位电路包括第四至第六可控开关及第二电容，所述第四可控开关的第一端接收所述输入电压，所述第四可控开关的控制端连接所述第二电容的第一端，所述第二电容的第二端连接所述第一电容的第二端、所述参考可控开关的第二端及所述第二控制电路，所述第四可控开关的第二端连接所述第五可控开关的第一端及所述第六可控开关的第一端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第二端连接所述第二电容的第一端及所述第四可控开关的控制端，所述第六可控开关的控制端接收所述发光信号，所述第六可控开关的第二端连接所述第二像素的阳极，所述第二像素的阴极接地。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收扫描复位信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为P型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
  6. 根据权利要求4所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收所述发光信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为N型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
  7. 根据权利要求4所述的像素驱动电路，其中，所述第一复位电路或所述第二复位电路还包括第七可控开关，所述第七可控开关的控制端接收复位信号，所述第七可控开关的第一端接收输入电压，所述第七可控开关的第二端连接所述第一可控开关的第一端及所述第四可控开关的第一端。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收扫描复位信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容 的第二端及所述第二电容的第二端，所述数据可控开关为P型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
  9. 根据权利要求7所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收所述发光信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为N型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
  10. 根据权利要求7所述的像素驱动电路，其中，所述第一至第七可控开关及所述参考可控开关均为P型薄膜晶体管，所述第一至第七可控开关及所述参考可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
  11. 根据权利要求4所述的像素驱动电路，其中，所述第一复位电路还包括第七可控开关，所述第七可控开关的控制端接收复位信号，所述第七可控开关的第一端接收初始信号，所述第七可控开关的第二端连接所述第一可控开关的控制端及所述第一电容的第一端；
    所述第二复位电路还包括第八可控开关，所述第八可控开关的控制端接收所述复位信号，所述第八可控开关的第一端接收所述初始信号，所述第八可控开关的第二端连接所述第四可控开关的控制端及所述第二电容的第一端。
  12. 根据权利要求11所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收扫描复位信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为P型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
  13. 根据权利要求11所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收所述发光信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为N型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的 栅极、漏极及源极。
  14. 根据权利要求11所述的像素驱动电路，其中，所述第一复位电路还包括第九可控开关，所述第九可控开关的控制端接收所述复位信号，所述第九可控开关的第一端连接所述第三可控开关的第二端，所述第九可控开关的第二端接收所述初始信号；
    所述第二复位电路还包括第十可控开关，所述第十可控开关的控制端接收所述复位信号，所述第十可控开关的第一端连接所述第六可控开关的第二端，所述第十可控开关的第二端接收所述初始信号。
  15. 根据权利要求14所述的像素驱动电路，其中，所述第一至第十可控开关均为P型薄膜晶体管，所述第一至第十可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
  16. 根据权利要求14所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收扫描复位信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为P型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、漏极及源极。
  17. 根据权利要求14所述的像素驱动电路，其中，所述第二控制电路包括数据可控开关，所述数据可控开关的控制端接收所述发光信号，所述数据可控开关的第一端接收所述数据电压，所述数据可控开关的第二端连接所述第一电容的第二端及所述第二电容的第二端，所述数据可控开关为N型薄膜晶体管，所述数据可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、漏极及源极。
PCT/CN2017/070196 2016-11-22 2017-01-05 像素驱动电路 WO2018094858A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/324,689 US10249240B2 (en) 2016-11-22 2017-01-05 Pixel drive circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611050661.0 2016-11-22
CN201611050661.0A CN107093401B (zh) 2016-11-22 2016-11-22 像素驱动电路

Publications (1)

Publication Number Publication Date
WO2018094858A1 true WO2018094858A1 (zh) 2018-05-31

Family

ID=59649191

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/070196 WO2018094858A1 (zh) 2016-11-22 2017-01-05 像素驱动电路

Country Status (3)

Country Link
US (1) US10249240B2 (zh)
CN (1) CN107093401B (zh)
WO (1) WO2018094858A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106297672B (zh) * 2016-10-28 2017-08-29 京东方科技集团股份有限公司 像素驱动电路、驱动方法和显示设备
CN108364607B (zh) * 2018-05-25 2020-01-17 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109117733B (zh) * 2018-07-17 2020-06-30 武汉华星光电半导体显示技术有限公司 一种指纹识别oled显示面板及显示装置
CN110246459B (zh) * 2019-06-20 2021-01-22 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板及显示装置
CN110444167A (zh) * 2019-06-28 2019-11-12 福建华佳彩有限公司 一种amoled补偿电路
CN111540303A (zh) 2020-01-17 2020-08-14 重庆康佳光电技术研究院有限公司 一种驱动电路及显示装置
CN113077754B (zh) * 2020-06-10 2022-09-13 友达光电股份有限公司 像素驱动电路
CN114267313B (zh) * 2021-12-30 2023-01-13 惠科股份有限公司 驱动电路以及驱动方法、栅极驱动电路和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060186822A1 (en) * 2005-02-18 2006-08-24 Samsung Sdi Co., Ltd. Time-divisional driving organic electroluminescence display
CN103531149A (zh) * 2013-10-31 2014-01-22 京东方科技集团股份有限公司 一种交流驱动的像素电路、驱动方法及显示装置
CN104064142A (zh) * 2014-06-13 2014-09-24 上海天马有机发光显示技术有限公司 一种有机发光二极管像素驱动电路及显示装置
CN105513534A (zh) * 2016-02-04 2016-04-20 京东方科技集团股份有限公司 一种像素结构、显示装置及驱动方法
CN105609052A (zh) * 2016-03-29 2016-05-25 上海天马有机发光显示技术有限公司 有机电致发光二极管显示器的驱动电路
CN106023889A (zh) * 2016-07-20 2016-10-12 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法、显示面板及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003173166A (ja) * 2001-09-28 2003-06-20 Sanyo Electric Co Ltd 表示装置
KR100635509B1 (ko) * 2005-08-16 2006-10-17 삼성에스디아이 주식회사 유기 전계발광 표시장치
US20090103807A1 (en) * 2007-10-18 2009-04-23 Spatial Photonics, Inc. Multi-imager display apparatus
KR102196908B1 (ko) * 2014-07-18 2020-12-31 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그의 구동방법
CN105528992A (zh) * 2016-01-29 2016-04-27 深圳市华星光电技术有限公司 像素补偿电路、方法、扫描驱动电路及平面显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060186822A1 (en) * 2005-02-18 2006-08-24 Samsung Sdi Co., Ltd. Time-divisional driving organic electroluminescence display
CN103531149A (zh) * 2013-10-31 2014-01-22 京东方科技集团股份有限公司 一种交流驱动的像素电路、驱动方法及显示装置
CN104064142A (zh) * 2014-06-13 2014-09-24 上海天马有机发光显示技术有限公司 一种有机发光二极管像素驱动电路及显示装置
CN105513534A (zh) * 2016-02-04 2016-04-20 京东方科技集团股份有限公司 一种像素结构、显示装置及驱动方法
CN105609052A (zh) * 2016-03-29 2016-05-25 上海天马有机发光显示技术有限公司 有机电致发光二极管显示器的驱动电路
CN106023889A (zh) * 2016-07-20 2016-10-12 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法、显示面板及显示装置

Also Published As

Publication number Publication date
US10249240B2 (en) 2019-04-02
CN107093401A (zh) 2017-08-25
US20180182296A1 (en) 2018-06-28
CN107093401B (zh) 2019-06-11

Similar Documents

Publication Publication Date Title
WO2018094858A1 (zh) 像素驱动电路
US11257426B2 (en) Electronic devices with low refresh rate display pixels
US10565929B2 (en) Organic light emitting display
US10249238B2 (en) Pixel driving circuit, array substrate, display panel and display apparatus having the same, and driving method thereof
US10783848B2 (en) Display device subpixel activation patterns
WO2020062802A1 (zh) 显示面板及像素电路的驱动方法
US8791883B2 (en) Organic EL display device and control method thereof
US10593278B2 (en) Display device subpixel activation patterns
US20160063921A1 (en) Organic Light-Emitting Diode Display With Reduced Capacitive Sensitivity
WO2018032899A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
US10043431B2 (en) Display device and electronic apparatus
US9035936B2 (en) Level shifter circuit, scanning circuit, display device and electronic equipment
US11195473B2 (en) Display device using inverted signal and driving method thereof
US20150145849A1 (en) Display With Threshold Voltage Compensation Circuitry
US20210183317A1 (en) Gate driver on array circuit, pixel circuit of an amoled display panel, amoled display panel, and method of driving pixel circuit of amoled display panel
US10235943B2 (en) Display panel, method for controlling display panel and display device
TW202027056A (zh) 畫素電路及其驅動方法
TWI567715B (zh) A display device, a display driving device, a driving method of a display device, and an electronic device having a display device
WO2018153096A1 (zh) 像素驱动电路、像素驱动电路的驱动方法及显示装置
US11119377B2 (en) LCD panel and EOA module thereof
WO2022170567A1 (zh) 像素电路及其驱动方法、显示装置
CN116844486A (zh) 显示面板及其驱动方法、显示装置
CN111048043A (zh) Oled像素电路及显示装置
JP2010282223A (ja) 画像表示装置および画像表示装置の駆動方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15324689

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17874984

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17874984

Country of ref document: EP

Kind code of ref document: A1