WO2018054098A1 - 阵列基板及其制造方法、显示面板和显示设备 - Google Patents

阵列基板及其制造方法、显示面板和显示设备 Download PDF

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Publication number
WO2018054098A1
WO2018054098A1 PCT/CN2017/087445 CN2017087445W WO2018054098A1 WO 2018054098 A1 WO2018054098 A1 WO 2018054098A1 CN 2017087445 W CN2017087445 W CN 2017087445W WO 2018054098 A1 WO2018054098 A1 WO 2018054098A1
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pixel electrode
common line
common
substrate
line
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PCT/CN2017/087445
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English (en)
French (fr)
Inventor
臧鹏程
徐元杰
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/737,087 priority Critical patent/US10658394B2/en
Publication of WO2018054098A1 publication Critical patent/WO2018054098A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a method of fabricating the same, a display panel, and a display device.
  • Twisted nematic liquid crystal displays are widely used in the display field due to their good time response, contrast and transmittance characteristics.
  • people have put forward higher and higher requirements for the resolution of liquid crystal display panels.
  • the increase in resolution leads to an increase in the cost of the IC (Integrated Circuit) and a decrease in the crimp yield.
  • IC cost some panel designs use a double-grid design.
  • the double gate line design refers to two gate lines for each row of pixels, and two columns of adjacent pixels share one data line. Since the cost of the data line driver IC is lower than the cost of the gate line driver IC, the overall IC cost of the liquid crystal display is lowered.
  • the double grid design will reduce the aperture ratio of the liquid crystal display panel.
  • An embodiment of the present disclosure provides an array substrate, including: a substrate substrate; a first electrode layer including a plurality of pixel electrode pairs arranged in an array, wherein each of the pixel electrode pairs includes a first pixel electrode and a a second pixel electrode adjacent to the first pixel electrode in the row direction; a data line disposed between the first pixel electrode and the second pixel electrode of the same pixel electrode pair in the row direction and along the column direction And extending, and the first common portion, at least one of the first pixel electrode and the second pixel electrode adjacent to the two of the pixel electrode pairs adjacent to the row direction are on the substrate
  • the orthographic projections on the substrate at least partially overlap, wherein the first common portion and the first electrode layer are insulated from each other.
  • the data line and the first common portion are included in a second electrode layer different from the first electrode layer.
  • the first common portion is a first common line extending in the column direction.
  • the array substrate further includes: a third electrode layer disposed on the base substrate; a gate insulating layer disposed on the third electrode layer, wherein the data line and the a first common portion disposed on the gate insulating layer; and an insulating layer disposed on the data line and the The first common portion, wherein the first electrode layer is disposed on the insulating layer.
  • the third electrode layer includes a second common line that overlaps an orthographic projection of the first common portion on the substrate.
  • the second common line does not overlap with the orthographic projection of the adjacent first pixel electrode and the second pixel electrode on the substrate.
  • the third electrode layer includes a third common line extending in the row direction, and the first pixel electrode and the first portion of the at least one of the pixel electrode pairs An orthographic projection of at least one of the two pixel electrodes on the substrate substrate at least partially overlaps.
  • the first common portion is electrically coupled to the third common line.
  • the array substrate further includes at least one of a fourth common line and a fifth common line, the fourth common line being disposed on a first side of the data line and adjacent to the data The first pixel electrode of the line at least partially overlaps the orthographic projection of the fourth common line on the base substrate; the fifth common line is disposed on the opposite side of the data line from the first side The two sides, and the orthogonal projection of the second pixel electrode adjacent to the data line and the fifth common line on the substrate substrate at least partially overlap.
  • At least one of the fourth common line and the fifth common line is included in the third electrode layer.
  • the array substrate preferably includes at least one of a sixth common line and a seventh common line, the sixth common line being disposed on a first side of the data line and adjacent to the data line The first pixel electrode and the orthographic projection of the sixth common line on the substrate substrate at least partially overlap; the seventh common line is disposed on the second opposite to the first side of the data line The side, and the orthographic projection of the second pixel electrode adjacent to the data line and the seventh common line on the substrate substrate at least partially overlap.
  • At least one of the sixth common line and the seventh common line is included in the second electrode layer.
  • Another embodiment of the present disclosure provides a display panel including any of the above array substrates.
  • Yet another embodiment of the present disclosure provides a display device including the above display panel.
  • Yet another embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: providing a substrate; forming a data line and a first common portion on the substrate; and above the data line and the first common portion Forming a first electrode layer; wherein the first electrode layer comprises a plurality of images distributed in an array a pair of pixel electrodes, each of the pair of pixel electrodes includes a first pixel electrode and a second pixel electrode adjacent to the first pixel electrode in a row direction, the data lines being in the same pixel unit pair in the row direction Between the first pixel electrode and the second pixel electrode, the first common portion is located between two pairs of the pixel electrodes adjacent in the row direction, and the first common portion and two An orthographic projection of the pixel electrodes of the pair of pixel electrodes on the substrate substrate at least partially overlaps, wherein the first common portion and the first electrode layer are insulated from each other.
  • the method further includes: forming a third electrode layer on the base substrate; forming a gate insulating layer on the third electrode layer; wherein the data line and the first common portion Located on the gate insulating layer.
  • the third electrode layer includes a second common line that overlaps an orthographic projection of the first common portion on the substrate.
  • the third electrode layer includes a third common line extending in the row direction, and the first pixel electrode and the first portion of the at least one of the pixel electrode pairs An orthographic projection of at least one of the two pixel electrodes on the substrate substrate at least partially overlaps.
  • the method further includes forming at least one of a fourth common line and a fifth common line, wherein the fourth common line is disposed on a first side of the data line and adjacent to the The first pixel electrode of the data line and the orthographic projection of the fourth common line on the substrate substrate at least partially overlap; the fifth common line is disposed on the opposite side of the data line from the first side a second side, and an orthographic projection of the second pixel electrode adjacent to the data line and the fifth common line on the substrate substrate at least partially overlaps.
  • the method further includes forming at least one of a sixth common line and a seventh common line, wherein the sixth common line is disposed on a first side of the data line and adjacent to the The first pixel electrode of the data line and the orthographic projection of the sixth common line on the substrate substrate at least partially overlap; the seventh common line is disposed on the opposite side of the data line from the first side a second side, and an orthographic projection of the second pixel electrode adjacent to the data line and the seventh common line on the substrate substrate at least partially overlaps.
  • the storage capacitance of the array substrate can be increased, thereby improving the display quality.
  • 1(a) is a plan view showing the structure of an array substrate
  • Figure 1 (b) is a schematic cross-sectional view of the array substrate shown in Figure 1 (a) along the line A-A';
  • FIG. 2(a) is a schematic plan view showing the structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 2(b) is a schematic cross-sectional view of the array substrate shown in FIG. 2(a) taken along line A-A';
  • FIG. 3 is a schematic cross-sectional view showing the structure of an array substrate according to another embodiment of the present disclosure.
  • FIG. 4 is a schematic plan view showing the structure of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 5(a) is a schematic plan view showing the structure of an array substrate according to still another embodiment of the present disclosure.
  • Figure 5 (b) is a schematic cross-sectional view of the array substrate shown in Figure 5 (a) along the line A-A';
  • FIG. 5(c) is a schematic cross-sectional view showing another structure of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 5(d) is a cross-sectional view showing still another structure of the array substrate according to still another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a display panel according to still another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a display device according to still another embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for fabricating an array substrate according to still another embodiment of the present disclosure.
  • FIG. 1(a) and FIG. 1(b) respectively show a planar structure diagram and a cross-sectional structure diagram of an array substrate 1000.
  • Fig. 1(b) is a cross-sectional structural view taken along line A-A' of the array substrate shown in Fig. 1(a).
  • the array substrate 1000 includes a substrate substrate 1600, a third electrode layer 1500, a gate insulating layer 1400, a second electrode layer 1300, a passivation layer 1200, and a first electrode layer 1100 disposed in sequence.
  • the first electrode layer 1100 includes a plurality of pixel electrodes arranged in an array, and two pixel electrodes adjacent in the row direction (ie, the D1 direction shown in FIG. 1(a)) constitute a pixel electrode pair 1110, and each pixel electrode pair
  • the 1110 includes a first pixel electrode 1111 and a second pixel electrode 1112 adjacent to the first pixel electrode in the row direction (ie, the D1 direction shown in FIG. 1(a)).
  • the second electrode layer 1300 includes a data line 1310 that is disposed between the first pixel electrode 1111 and the second pixel electrode 1112 in the row direction and that extends in the column direction (ie, the D2 direction shown in FIG. 1(a)).
  • the third electrode layer 1500 includes a third common line 1510, a gate line 1520, a second common line 1531, a fourth common line 1532, and a fifth common line 1533.
  • the third common line 1510 is disposed between the two pixel electrode pairs 1110 adjacent in the column direction and extending in the row direction, and may overlap with at least one of the pixel electrode pairs.
  • a gate line 1520 is disposed on both sides of each of the third common lines 1510 and substantially parallel to the third common line 1510.
  • the second common line 1531 is disposed between the two pixel electrode pairs 1110 adjacent in the row direction and extending in the column direction, and the second common line 1531 is a pixel electrode (for example, one of the two pixel electrode pairs 1110 on both sides thereof)
  • the first pixel electrode 1111 of the pixel electrode pair and the second pixel electrode 1112 of the other pixel electrode pair adjacent thereto partially overlap.
  • the fourth common line 1532 is disposed on one side of the data line 1310 and partially overlaps the pixel electrode (for example, the first pixel electrode 1111) adjacent to the data line 1310 on the side.
  • the fifth common line 1533 is disposed on the other side of the data line 1310 and partially overlaps the pixel electrode (for example, the second pixel electrode 1112) adjacent to the data line 1310 on the other side.
  • the pixel unit in which the second pixel electrode 1112 is located will be described as an example.
  • the third common line 1510 partially overlaps the second pixel electrode 1112 to form a storage capacitor.
  • the second common line 1531 and the fifth common line 1533 partially overlap the second pixel electrode 1112, and the overlapping portion can form a storage capacitor and can block light leakage to enhance display contrast.
  • Embodiments of the present disclosure provide an array substrate and a manufacturing method, a display panel, and a display device, which can increase an aperture ratio without increasing a process flow, and can enhance stability of a storage capacitor and thereby improve stability of a display image.
  • FIGS. 2(a) and 2(b) are a schematic plan view and a cross-sectional view, respectively, of the structure of the array substrate 2000 of one embodiment of the present disclosure.
  • the cross-sectional structural view shown in Fig. 2(b) is taken along the line A-A' of the array substrate 2000 shown in Fig. 2(a).
  • the array substrate 2000 includes a first electrode layer 2100, a second electrode layer 2300, and an insulating layer 2200.
  • the first electrode layer 2100 includes a plurality of pixel electrodes arranged in an array, and two pixel electrodes adjacent in the row direction (ie, the D1 direction shown in FIG.
  • each pixel electrode pair 2110 includes a first pixel electrode 2111 and a second pixel electrode 2112 adjacent to the first pixel electrode 2111 in the row direction;
  • the second electrode layer 2300 includes a data line 2310 and a first common line 2321 (eg, as the first common portion)
  • the data line 2310 is disposed between the first pixel electrode 2111 and the second pixel electrode 2112 in the row direction and extends in the column direction
  • the first common line 2321 is disposed in the two pixel electrode pairs 2110 adjacent in the row direction. And extending in the column direction (ie, the D2 direction shown in FIG.
  • an insulating layer 2200 is disposed between the first electrode layer 2100 and the second electrode layer 2300 to insulate the two from each other.
  • the array substrate 2000 further includes a base substrate 2600, a third electrode layer 2500 disposed on the base substrate 2600, and a setting A gate insulating layer 2400 is over the third electrode layer 2500.
  • the third electrode layer 2500 can include a gate line 2520.
  • the second electrode layer 2300 is disposed on the gate insulating layer 2400
  • the insulating layer 2200 is disposed on the second electrode layer 2300
  • the first electrode layer 2100 is disposed on the insulating layer 2200.
  • the pixel electrode may be formed, for example, using a transparent conductive material.
  • the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the first common line 2321 and the data line 2310 may be formed, for example, of a metal material such as copper, aluminum, or aluminum alloy.
  • the insulating layer 2200 may be formed using an inorganic or organic material.
  • the insulating layer 2200 may be formed using an organic resin, silicon oxide (SiOx), silicon oxynitride (SiNxOy), or silicon nitride (SiNx).
  • the base substrate 2600 may be a glass substrate, a quartz substrate, or a substrate made of other suitable materials.
  • the material of the third electrode layer 2500 may be copper, aluminum, aluminum alloy or other suitable material.
  • the material of the gate insulating layer 2400 may be silicon oxide (SiOx), Silicon oxynitride (SiNxOy), silicon nitride (SiNx) or other suitable materials.
  • a portion where the pixel electrode and the first common line 2321 overlap each other forms a storage capacitor.
  • the area, d is the distance between the pixel electrode and the first common line 2321. Since only the insulating layer 2200 is disposed between the pixel electrode and the first common line 2321, the pixel electrode and the first common line 2321 are directly opposite to each other as compared with the case shown in FIGS. 1(a) and 1(b).
  • the distance d can be reduced, and therefore, under the same insulating layer preparation conditions, the storage capacitance formed between the pixel electrodes 2112 and 2111 and the first common line 2321 can be increased, so in the case where the same capacitance value c is reached, the pixel
  • the area S of the electrodes 2112 and 2111 overlapping the first common line 2321 may be correspondingly reduced, that is, the area occupied by the first common line 2321 may be correspondingly reduced (for example, the width of the first common line may be reduced to occupy less The area) increases the aperture ratio of the array substrate.
  • first common line 2321 can be formed in the same patterning process flow as the data line 2310 (ie, the first common line 2321 can be formed in the same layer as the data line 2310), so that no additional process flow can be added. Increase the aperture ratio of the array substrate.
  • the gate insulating layer 2400 is disposed between the first common line 2321 and the gate line 2520, the first common line 2321 and the gate line 2520 are not short-circuited. Therefore, the first common line 2321 can extend in the column direction, form a storage capacitor with the plurality of rows of pixel electrodes, improve the stability of the storage capacitor, and thereby improve the stability of the display image.
  • FIG. 3 shows a cross-sectional view of the structure of an array substrate 2000 of another embodiment of the present disclosure.
  • the third electrode layer 2500 of the array substrate 2000 includes a second common line 2531, and the second common line 2531 is disposed between two pixel electrode pairs 2110 adjacent in the row direction.
  • the area of the second common line 2531 may be smaller than the area of the first common line 2321 such that the first common line 2321 and the pixel electrode form a stepped structure in a direction substantially perpendicular to the base substrate 2600.
  • the stepped structure can increase the area where the first common line 2321 and the pixel electrode overlap, so that the storage capacitance formed between the two can be increased, and the aperture ratio can be increased.
  • the second common line 2531 can be located directly below the first common line 2321, so that the storage capacitance on the array substrate 2000 can be evenly distributed, thereby improving the quality of the displayed image.
  • the second common line 2531 can be electrically connected to the first common line 2321 (eg, electrically connected through vias).
  • FIG. 4 shows a plan view of the structure of an array substrate 2000 in still another embodiment of the present disclosure.
  • the third electrode layer 2500 of the array substrate 2000 includes a third common line 2510 that extends in the row direction and partially overlaps the second pixel electrode 2112.
  • the first common line 2321 may be electrically connected to the third common line 2510.
  • the first common line 2321 and the third common line 2510 are electrically connected via vias 2410 in the gate insulating layer 2400.
  • the storage capacitor formed between the plurality of first common lines 2321 and the pixel electrodes and the storage capacitor formed by the third common line 2510 and the pixel electrodes are connected together by the third common line 2510, thereby further improving the storage capacitor. Stability, which in turn improves the stability of the displayed image.
  • FIGS. 5(a) and 5(b) respectively show a schematic plan view and a cross-sectional view of the structure of an array substrate 2000 according to still another embodiment of the present disclosure.
  • the third electrode layer 2500 of the array substrate 2000 further includes a fourth common line 2532 and a fifth common line 2533.
  • the fourth common line 2532 is disposed on one side of the data line 2310 (for example, the left side of the data line shown in FIG. 5(b)), and is adjacent to the data line 2310 (for example, the data line shown in FIG. 5(b)
  • the fifth common line 2533 is disposed on the other side of the data line 2310 (for example, the right side of the data line shown in FIG. 5(b)), and is adjacent to the data line 2310.
  • the pixel electrode portions for example, adjacent to the right side of the data line shown in FIG.
  • the storage capacitance formed by the vertical common line and the pixel electrode can be further increased.
  • the storage capacitance formed between the first common line 2321 and the pixel electrode can be correspondingly reduced, that is, The area occupied by the first common line 2321 can be correspondingly reduced, thereby increasing the aperture ratio.
  • FIG. 5(c) is a cross-sectional view showing another structure of the array substrate 2000 of still another embodiment of the present disclosure.
  • the second electrode layer 2300 of the array substrate 2000 includes a sixth common line 2322 and a seventh common line 2323.
  • the sixth common line 2322 is disposed on one side of the data line 2310 (for example, the left side of the data line shown in FIG. 5(c)), and is adjacent to the data line 2310 (for example, the data line shown in FIG. 5(c)
  • the pixel electrode portions adjacent to the left side overlap;
  • the seventh common line 2323 is disposed on the other side of the data line 2310 (for example, the right side of the data line shown in FIG. 5(c)), and is adjacent to the data line 2310.
  • the pixel electrode portions (for example, adjacent to the right side of the data line shown in FIG. 5(c)) overlap.
  • the sixth common line 2322 and the seventh common line 2323 and the image There is only the insulating layer 2200 between the element electrodes, and therefore, the distance between the sixth common line 2322 and the seventh common line 2323 and the pixel electrode is reduced, and the capacitance value of the storage capacitor is compared with the case shown in FIG. 5(b). Increase, which in turn can further increase the aperture ratio.
  • FIG. 5(d) shows a schematic cross-sectional view of still another structure of the array substrate 2000 of still another embodiment of the present disclosure.
  • the second electrode layer 2300 of the array substrate 2000 includes a sixth common line 2322 and a seventh common line 2323
  • the third electrode layer 2500 includes the first array substrate 2000 shown in FIGS. 5(b) and 5(c).
  • the fourth common line 2532 and the fifth common line 2533 located in the third electrode layer 2500 are such that the sixth common line 2322 and the seventh common line 2323 located at the second electrode layer 2300 and the corresponding pixel electrode are substantially perpendicular to the base substrate 2600
  • a stepped structure is formed in the direction, thereby increasing the storage capacitance formed between the sixth common line 2322 and the seventh common line 2323 and the pixel electrode, thereby further increasing the aperture ratio.
  • the data line 2310 is disposed at the recess formed by the gate insulating layer 2400, and the portion of the sixth common line 2322 and the seventh common line 2323 are disposed at the bump formed by the gate insulating layer 2400, the data line 2310 can be avoided.
  • the distance from the gate insulating layer 2400 is too close or short-circuited.
  • the number and position of the fourth common line, the fifth common line, the sixth common line, and the seventh common line are not limited to the cases illustrated in FIGS. 5( a ) to 5 ( d ) It can be set according to the actual shading needs and the required storage capacitance.
  • the fourth common line 2532 may be disposed only in the third electrode layer 2500; for example, the seventh common line 2323 may be disposed only in the second electrode layer 2300.
  • the first common line, the second common line, the third common line, the fourth common line, the fifth common line, the sixth common line, and the seventh common line of the array substrate in the above different embodiments are disposed.
  • the examples can be combined with each other to give a new embodiment.
  • the number of layers or the structure of the film layer may be increased or decreased according to actual production requirements, which is not limited herein.
  • each of the first common line to the seventh common line is configured to provide a common voltage.
  • any two of the first common line to the seventh common line are electrically connected.
  • any one of the first common line to the seventh common line is electrically insulated from the pixel electrode.
  • each of the first pixel electrodes and the corresponding data line are electrically connected through a thin film transistor; each of the second pixel electrodes and the corresponding data line are electrically connected through the thin film transistor.
  • any one of the first common line to the seventh common line is electrically insulated from each other with any of the first pixel electrode and the second pixel electrode.
  • the structures in the same layer can be formed by the same patterning process.
  • positive projection on a base substrate means “projection in a direction substantially perpendicular to the main surface of the base substrate”.
  • a display panel 100 is provided. As shown in FIG. 6, the display panel 100 includes the array substrate 2000 according to any embodiment of the present disclosure.
  • the display panel can increase the aperture ratio without increasing the process flow, and can enhance the stability of the storage capacitor and thereby increase the stability of the display image.
  • the display panel 100 may further include a color filter substrate 3000, which may include a black matrix 3001 corresponding to the array substrate 2000 disposed between the regions covering the pixel electrodes. To shield light from the gap between the pixel electrodes on the array substrate and improve image contrast.
  • the array substrate 2000 and the color filter substrate 3000 are combined with each other to form a liquid crystal cell, for example, by a sealant 350, and the liquid crystal cell 400 is filled in the liquid crystal cell.
  • a backlight module 500 may also be disposed on the non-display side of the liquid crystal panel (the lower side in FIG. 6) to provide a light source for the display operation of the display panel.
  • Still another embodiment of the present disclosure provides a display device 10, as shown in FIG. 7, the display device includes a display panel 100 including the array substrate 2000 according to any of the embodiments of the present disclosure.
  • the display device 10 can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device can increase the aperture ratio without increasing the process flow, and can enhance the stability of the storage capacitor and the stability of the displayed image.
  • the embodiment of the present disclosure further provides a method for manufacturing the array substrate 2000 provided by the embodiment of the present disclosure, and the case shown in FIG. 2(a) and FIG. 2(b) is taken as an example.
  • the manufacturing method may include the following steps:
  • Step S10 forming a second electrode layer 2300, the second electrode layer 2300 includes a data line 2310 and a first common line 2321;
  • Step S20 forming an insulating layer 2200 on the second electrode layer 2300;
  • Step S30 forming a first electrode layer 2100 on the insulating layer 2200, the first electrode layer 2100 includes a plurality of pixel electrode pairs 2110 distributed in an array, and each pixel electrode pair 2110 includes a first pixel The electrode 2111 and the second pixel electrode 2112 adjacent to the first pixel electrode 2111 in the row direction, the data line 2310 is located between the first pixel electrode 2111 and the second pixel electrode 2112 in the row direction, and the first common line 2321 is located at the row side The two adjacent pixel electrode pairs 2110 are overlapped, and the first common line 2321 overlaps the pixel electrode portions of the two pixel electrode pairs 2110.
  • the distance between the pixel electrode and the third common line is reduced, so the pixel electrode and the The storage capacitance formed between the three common lines is increased.
  • the area where the pixel electrode overlaps with the first common line can be correspondingly reduced, that is, the area occupied by the first common line can be correspondingly reduced.
  • Small which in turn increases the aperture ratio.
  • the first common line 2321 can be formed in the same process flow as the data line 2310 (ie, the first common line can be formed in the same layer as the data line), the storage capacitor and the opening can be increased without adding an additional process flow. rate.
  • the first common line and the gate line 2520 are not short-circuited. Therefore, the first common line can continuously extend in the column direction, and the first common line is combined with the storage capacitor formed by the entire column of pixel electrodes, thereby improving the stability of the storage capacitor without adding an additional process flow. Shows the stability of the image.
  • the substrate substrate 2600 may be further provided; the third electrode layer 2500 is formed on the substrate substrate 2600; and the gate insulating layer is formed on the third electrode layer 2500. 2400; the second electrode layer 2300 is located on the gate insulating layer 2400.
  • the method for fabricating the array substrate is not limited to the cases shown in FIG. 2( a ) and FIG. 2( b ), and may further include FIG. 3 , FIG. 4 , and FIG. 5( a ) to 5 (b). ) The situation shown.
  • the third electrode layer 2500 may include a second common line 2531 between the two pixel electrode pairs 2110 adjacent in the row direction. (See Figure 3).
  • the area of the second common line 2531 may be smaller than the first common line 2321, and the stepped structure may increase the area where the first common line 2321 overlaps with the pixel electrode, thereby increasing the storage capacitance formed between the two. Can increase the aperture ratio.
  • the third electrode layer 2500 includes a third common line 2510 that extends in the row direction and at least partially overlaps an orthographic projection of the pixel electrode of at least one pixel electrode pair 2110 on the substrate substrate (see FIG. 4).
  • the method further includes forming a via hole 2410 in the gate insulating layer 2400, and the first common line 2321 and the third common line 2510 are electrically connected through the via hole 2410. Further, the storage capacitor formed between all the first common lines 2321 and the pixel electrodes and the storage capacitor formed between the third common line 2510 and the pixel electrodes can be combined into a whole by the third common line, thereby further improving the storage. The stability of the capacitor, which in turn improves the stability of the displayed image.
  • the method further includes forming a fourth common line and a fifth common line in the third electrode layer 2500, and the fourth common line 2532 is disposed on one side of the data line 2310 ( For example, the left side of the data line shown in FIG. 5(b), and the pixel electrode portion adjacent to the data line 2310 (for example, adjacent to the left side of the data line shown in FIG. 5(b)) overlaps;
  • the common line 2533 is disposed on the other side of the data line 2310 (for example, the right side of the data line shown in FIG. 5(b)), and is adjacent to the data line 2310 (for example, the right of the data line shown in FIG. 5(b)
  • the pixel electrodes of the side adjacent sides overlap. This further increases the storage capacitance, which in turn increases the aperture ratio.
  • the method further includes forming a sixth common line and a seventh common line in the second electrode layer 2300, and the sixth common line 2322 is disposed on one side of the data line 2310 ( For example, the left side of the data line shown in FIG. 5(c), and the pixel electrode portion adjacent to the data line 2310 (for example, adjacent to the left side of the data line shown in FIG. 5(c)) overlaps;
  • the common line 2323 is disposed on the other side of the data line 2310 (for example, the right side of the data line shown in FIG. 5(c)), and is adjacent to the data line 2310 (for example, the right of the data line shown in FIG. 5(c)
  • the pixel electrodes of the side adjacent sides overlap. Thereby, the storage capacitance formed by the vertical common line and the pixel electrode can be further increased, thereby increasing the aperture ratio.
  • Embodiments of the present disclosure provide an array substrate and a manufacturing method, a display panel, and a display device, which can increase a storage capacitor, increase an aperture ratio, and enhance stability of a storage capacitor and display image stability without increasing a process flow. Sex.

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Abstract

一种阵列基板及制造方法、显示面板和显示设备。该阵列基板(1000；2000)包括：衬底基板(1600；2600)；第一电极层(1100；2100)，包括阵列排布的多个像素电极对(1110；2110)，其中，每个所述像素电极对(1110；2110)包括第一像素电极(1111；2111)和与所述第一像素电极(1111；2111)在行方向(D1)上相邻的第二像素电极(1112；2112)；数据线(1310；2310)，在所述行方向(D1)上设置于同一像素电极对(1110；2110)的所述第一像素电极(1111；2111)和所述第二像素电极(1112；2112)之间且沿列方向(D2)延伸；以及第一公共部分(1531；2321)，与所述相邻的两个所述像素电极对(1110；2110)中相邻的所述第一像素电极(1111；2111)和所述第二像素电极(1112；2112)中的至少之一在所述衬底基板(1600；2600)上的正投影至少部分交叠，其中，所述第一公共部分(1531；2321)与所述第一电极层(1100；2100)彼此绝缘。该阵列基板可以在不增加工艺流程的情况下增加开口率以及提升显示图像的稳定性。

Description

阵列基板及其制造方法、显示面板和显示设备 技术领域
本公开的实施例涉及一种阵列基板及其制造方法、显示面板和显示设备。
背景技术
由于具有良好的时间响应、对比度和透过率特性，扭曲向列型液晶显示器被广泛应用于显示领域。随着显示技术的不断发展，人们对于液晶显示面板的分辨率提出了越来越高的要求。分辨率的提升使得IC(集成电路)成本增加、压接良率降低。为了降低IC成本，一些面板设计采用了双栅线设计。双栅线设计是指为每行像素设置两条栅线，而两列相邻的像素共用一条数据线。由于数据线驱动IC成本低于栅线驱动IC成本，使得液晶显示器总体的IC成本降低。但双栅线设计会使得液晶显示面板的开口率降低。
发明内容
本公开的实施例提供一种阵列基板，包括：衬底基板；第一电极层，包括阵列排布的多个像素电极对，其中，每个所述像素电极对包括第一像素电极和与所述第一像素电极在行方向上相邻的第二像素电极；数据线，在所述行方向上设置于同一像素电极对的所述第一像素电极和所述第二像素电极之间且沿列方向延伸；以及第一公共部分，与所述行方向上相邻的两个所述像素电极对中相邻的所述第一像素电极和所述第二像素电极中的至少之一在所述衬底基板上的正投影至少部分交叠，其中，所述第一公共部分与所述第一电极层彼此绝缘。
在一个示例中，所述数据线和所述第一公共部分包括于不同于第一电极层的第二电极层中。
在一个示例中，所述第一公共部分为在所述列方向延伸的第一公共线。
在一个示例中，所述的阵列基板还包括：第三电极层，设置于所述衬底基板上；栅绝缘层，设置于所述第三电极层上，其中，所述数据线和所述第一公共部分设置于所述栅绝缘层上；以及绝缘层，设置于所述数据线和所述 第一公共部分上，其中，所述第一电极层设置于所述绝缘层上。
在一个示例中，所述第三电极层包括第二公共线，所述第二公共线与所述第一公共部分在所述衬底基板上的正投影重叠。
在一个示例中，所述第二公共线与相邻的所述第一像素电极以及所述第二像素电极在所述衬底基板上的正投影不重叠。
在一个示例中，所述第三电极层包括第三公共线，所述第三公共线沿所述行方向延伸，并且与至少一个所述像素电极对的所述第一像素电极和所述第二像素电极的至少之一在所述衬底基板上的正投影至少部分交叠。
在一个示例中，所述第一公共部分与所述第三公共线电连接。
在一个示例中，所述的阵列基板还包括第四公共线和第五公共线的至少之一，所述第四公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第四公共线在所述衬底基板上的正投影至少部分交叠；所述第五公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第五公共线在所述衬底基板上的正投影至少部分交叠。
在一个示例中，所述第四公共线和第五公共线的至少之一包括在第三电极层中。
在一个示例中，所述阵列基板好包括第六公共线和第七公共线的至少之一，所述第六公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第六公共线在所述衬底基板上的正投影至少部分交叠；所述第七公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第七公共线在所述衬底基板上的正投影至少部分交叠。
在一个示例中，所述第六公共线和第七公共线的至少之一包括在第二电极层中。
本公开的另一实施例提供一种显示面板，包括上述任一阵列基板。
本公开的又一实施例提供一种显示设备，包括上述的显示面板。
本公开的又一实施例提供一种阵列基板制造方法，包括：提供衬底基板；在所述衬底基板上形成数据线和第一公共部分；以及在所述数据线和第一公共部分上方形成第一电极层；其中，所述第一电极层包括阵列分布的多个像 素电极对，每一个所述像素电极对包括第一像素电极和与所述第一像素电极在行方向上相邻的第二像素电极，所述数据线在所述行方向上位于同一像素单元对的所述第一像素电极和所述第二像素电极之间，所述第一公共部分位于在所述行方向上相邻的两个所述像素电极对之间，并且所述第一公共部分与两个所述像素电极对中的像素电极在所述衬底基板上的正投影至少部分交叠，其中，所述第一公共部分与所述第一电极层彼此绝缘。
在一个示例中，所述方法还包括：在所述衬底基板上形成第三电极层；在所述第三电极层上形成栅绝缘层；其中，所述数据线和所述第一公共部分位于所述栅绝缘层上。
在一个示例中，所述第三电极层包括第二公共线，所述第二公共线与所述第一公共部分在所述衬底基板上的正投影重叠。
在一个示例中，所述第三电极层包括第三公共线，所述第三公共线沿所述行方向延伸，并且与至少一个所述像素电极对的所述第一像素电极和所述第二像素电极的至少之一在所述衬底基板上的正投影至少部分交叠。
在一个示例中，所述方法还包括形成第四公共线和第五公共线的至少之一，其中，所述第四公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第四公共线在所述衬底基板上的正投影至少部分交叠；所述第五公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第五公共线在所述衬底基板上的正投影至少部分交叠。
在一个示例中，所述方法还包括形成第六公共线和第七公共线的至少之一，其中，所述第六公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第六公共线在所述衬底基板上的正投影至少部分交叠；所述第七公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第七公共线在所述衬底基板上的正投影至少部分交叠。
这样，可以增加阵列基板的存储电容，进而可以提升显示质量。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1(a)是一种阵列基板的结构的平面示意图；
图1(b)是图1(a)所示的阵列基板沿A-A’线的剖面示意图；
图2(a)是本公开一个实施例提供的阵列基板的结构的平面示意图；
图2(b)是图2(a)所示的阵列基板沿A-A’线的剖面示意图；
图3是本公开另一个实施例提供的阵列基板的结构的剖面示意图；
图4是本公开再一个实施例提供的阵列基板的结构的平面示意图；
图5(a)是本公开再一个实施例提供的阵列基板的结构的平面示意图；
图5(b)是图5(a)所示的阵列基板沿A-A’线的剖面示意图；
图5(c)是本公开再一个实施例提供的阵列基板的另一种结构的剖面示意图；
图5(d)是本公开再一个实施例提供的阵列基板的再一种结构的剖面示意图；
图6是本公开再一个实施例提供的显示面板的示意图；
图7是本公开再一个实施例提供的显示设备的示意图；以及
图8是本公开再一个实施例提供的一种阵列基板的制作方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，本公开所使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
例如，图1(a)和图1(b)分别示出了一种阵列基板1000的平面结构示意图和剖面结构示意图。图1(b)示出的剖面结构示意图是沿图1(a)所示阵列基板的A-A’线得到。
如图所示，该阵列基板1000包括依次设置的衬底基板1600、第三电极层1500、栅绝缘层1400、第二电极层1300、钝化层1200和第一电极层1100。第一电极层1100包括阵列排布的多个像素电极，行方向(即图1(a)中所示的D1方向)上相邻的两个像素电极组成像素电极对1110，每个像素电极对1110包括第一像素电极1111和与第一像素电极在行方向(即图1(a)中所示的D1方向)上相邻的第二像素电极1112。第二电极层1300包括在行方向上设置于第一像素电极1111和第二像素电极1112之间且沿列方向(即图1(a)中所示的D2方向)延伸的数据线1310。第三电极层1500包括第三公共线1510、栅线1520、第二公共线1531、第四公共线1532和第五公共线1533。第三公共线1510设置于在列方向上相邻的两个像素电极对1110之间且沿行方向延伸，并且可以与一个像素电极对中的至少一个像素电极部分交叠。栅线1520设置在每个第三公共线1510两侧并与第三公共线1510实质平行。第二公共线1531设置于在行方向上相邻的两个像素电极对1110之间且沿列方向延伸，并且第二公共线1531与其两侧的两个像素电极对1110中的像素电极(例如一个像素电极对中的第一像素电极1111和与其相邻的另一个像素电极对中的第二像素电极1112)部分交叠。第四公共线1532设置于数据线1310的一侧，并且与在所述侧与数据线1310相邻的像素电极(例如第一像素电极1111)部分交叠。第五公共线1533设置于数据线1310的另一侧，并且与在另一侧与数据线1310相邻的像素电极(例如第二像素电极1112)部分交叠。
例如，如图1(a)和图1(b)所示，以第二像素电极1112所在的像素单元为例进行说明。第三公共线1510与第二像素电极1112部分交叠，以形成存储电容。第二公共线1531和第五公共线1533与第二像素电极1112部分交叠，该交叠部分既可以形成存储电容，又能够起到遮挡漏光进而提升显示对比度的作用。
本公开的实施例提供一种阵列基板及制造方法、显示面板和显示设备，可以在不增加工艺流程的情况下提升开口率，并且可以增强存储电容的稳定性进而提高显示图像的稳定性。
例如，图2(a)和图2(b)分别是本公开一个实施例的阵列基板2000的结构的平面示意图和剖面示意图。图2(b)示出的剖面结构示意图是沿图2(a)所示阵列基板2000的A-A’线得到。
阵列基板2000包括第一电极层2100、第二电极层2300和绝缘层2200。第一电极层2100包括阵列排布的多个像素电极，行方向(即图2(a)中所示的D1方向)上相邻的两个像素电极组成像素电极对2110，每个像素电极对2110包括第一像素电极2111和与第一像素电极2111在行方向上相邻的第二像素电极2112；第二电极层2300包括数据线2310和第一公共线2321(例如，作为第一公共部分的示例)，数据线2310在行方向上设置于第一像素电极2111和第二像素电极2112之间且沿列方向延伸，第一公共线2321设置于在行方向上相邻的两个像素电极对2110之间且沿列方向(即图2(a)中所示的D2方向)延伸，并且第一公共线2321与两个像素电极对2110中的像素电极(例如一个像素电极对中的第一像素电极2111和与其相邻的另一个像素电极对中的第二像素电极2112)部分交叠；绝缘层2200设置于第一电极层2100与第二电极层2300之间以使二者彼此绝缘。
例如，在本公开的实施例中，如图2(a)和图2(b)所示，阵列基板2000还包括衬底基板2600、设置于衬底基板2600上的第三电极层2500以及设置于第三电极层2500上栅绝缘层2400。例如，第三电极层2500可以包括栅线2520。例如，第二电极层2300设置于栅绝缘层2400上，绝缘层2200设置于第二电极层2300上，第一电极层2100设置于绝缘层2200上。
例如，在本公开的实施例中，像素电极例如可以采用透明导电材料形成。例如，透明导电材料为氧化铟锡(ITO)或氧化铟锌(IZO)。
例如，第一公共线2321和数据线2310例如可以采用金属材料(例如，铜、铝或者铝合金)形成。
例如，绝缘层2200可以采用无机或有机材料形成。例如，绝缘层2200可以采用有机树脂、氧化硅(SiOx)、氧氮化硅(SiNxOy)或者氮化硅(SiNx)形成。
例如，在本公开的实施例中，衬底基板2600可以是玻璃基板、石英基板或者由其它适合的材料制成的基板。第三电极层2500的材料可以是铜、铝、铝合金或者其它适合的材料。栅绝缘层2400的材料可以是氧化硅(SiOx)、 氧氮化硅(SiNxOy)、氮化硅(SiNx)或者其它适合的材料。
例如，在本公开的实施例中，像素电极与第一公共线2321相互交叠的部分形成了存储电容。存储电容电容值c可以由电容公式c＝εS/d来确定，ε为像素电极与第一公共线2321之间绝缘层2200的介电常数，S为像素电极与第一公共线2321交叠的面积，d为像素电极与第一公共线2321之间的正对距离。由于像素电极与第一公共线2321之间仅设置有绝缘层2200，相比于图1(a)和图1(b)所示的情形，像素电极与第一公共线2321之间的正对距离d可以得到降低，因此，在相同绝缘层制备条件下，像素电极2112和2111与第一公共线2321之间形成的存储电容可以得到增加，因此在达到相同电容值c的情况下，则像素电极2112和2111与第一公共线2321交叠的面积S可以相应减小，也就是说，第一公共线2321占用的面积可以相应减小(例如可减小第一公共线的宽度减小占用的面积)，提升了阵列基板的开口率。此外，第一公共线2321可以与数据线2310在同一个图案化工艺流程中形成(即第一公共线2321可以与数据线2310同层形成)，因此可以在不增加额外的工艺流程的情况下增加阵列基板的开口率。
例如，在本公开的实施例中，由于第一公共线2321与栅线2520之间设置有栅绝缘层2400，因此第一公共线2321与栅线2520不会短路。所以第一公共线2321可以在列方向上延伸，与多行像素电极形成存储电容，提升存储电容的稳定性，进而提高显示图像的稳定性。
例如，图3示出了本公开另一个实施例的阵列基板2000的结构的剖面示意图。
如图3所示，阵列基板2000的第三电极层2500包括第二公共线2531，并且第二公共线2531设置于在行方向上相邻的两个像素电极对2110之间。例如，第二公共线2531的面积可以小于第一公共线2321的面积，使得第一公共线2321和像素电极在实质上垂直于衬底基板2600的方向上形成阶梯状的结构。该阶梯状的结构可以增加第一公共线2321和像素电极交叠的面积，因此可以增加两者之间形成的存储电容，进而可以提升开口率。例如，第二公共线2531可以位于第一公共线2321的正下方，可使阵列基板2000上的存储电容分布均匀，进而可以提升显示图像的质量。例如，第二公共线2531可以与第一公共线2321电连接(例如通过过孔电连接)。
例如，图4示出了本公开再一个实施例的阵列基板2000的结构的平面示意图。
如图4所示，阵列基板2000的第三电极层2500包括第三公共线2510，第三公共线2510沿行方向延伸，并且与第二像素电极2112部分交叠。第一公共线2321可以与第三公共线2510电连接。例如，第一公共线2321与第三公共线2510之间经由栅绝缘层2400中的过孔2410电连接。进而可以通过第三公共线2510将多条第一公共线2321与像素电极之间形成的存储电容与第三公共线2510与像素电极形成的存储电容连接成一个整体，进而可以进一步的提升存储电容的稳定性，进而提高显示图像的稳定性。
例如，图5(a)和图5(b)分别示出了本公开再一个实施例的阵列基板2000的结构的平面示意图和剖面示意图。
如图5(a)和图5(b)所示，阵列基板2000的第三电极层2500还包括第四公共线2532和第五公共线2533。第四公共线2532设置于数据线2310的一侧(例如图5(b)所示的数据线的左侧)，并且与数据线2310相邻(例如图5(b)所示的数据线的左侧相邻)的像素电极部分交叠；第五公共线2533设置于数据线2310的另一侧(例如图5(b)所示的数据线的右侧)，并且与数据线2310相邻(例如图5(b)所示的数据线的右侧相邻)的像素电极部分交叠。由此可以进一步增加垂直公共线与像素电极形成的存储电容，在达到相同的存储电容电容值的情况下，第一公共线2321与像素电极之间形成的存储电容可以相应减小，也就是说，可以相应减小第一公共线2321占用的面积，进而可以提升开口率。
例如，图5(c)示出了本公开再一个实施例的阵列基板2000的另一种结构的剖面示意图。
如图5(c)所示，阵列基板2000的第二电极层2300包括第六公共线2322和第七公共线2323。第六公共线2322设置于数据线2310的一侧(例如图5(c)所示的数据线的左侧)，并且与数据线2310相邻(例如图5(c)所示的数据线的左侧相邻)的像素电极部分交叠；第七公共线2323设置于数据线2310的另一侧(例如图5(c)所示的数据线的右侧)，并且与数据线2310相邻(例如图5(c)所示的数据线的右侧相邻)的像素电极部分交叠。相比于图5(b)所示的阵列基板2000，第六公共线2322和第七公共线2323与像 素电极之间仅存在绝缘层2200，因此，相比于图5(b)所示的情形，第六公共线2322和第七公共线2323与像素电极之间距离减小，存储电容的电容值增加，进而可以进一步提升开口率。
例如，图5(d)示出了本公开再一个实施例的阵列基板2000的再一种结构的剖面示意图。
相比于图5(b)和图5(c)示出的阵列基板2000，阵列基板2000的第二电极层2300包括第六公共线2322和第七公共线2323，第三电极层2500包括第四公共线和第五公共线。位于第三电极层2500的第四公共线2532和第五公共线2533使得位于第二电极层2300的第六公共线2322和第七公共线2323以及对应的像素电极在实质垂直于衬底基板2600的方向上形成了阶梯状结构，因而增加了第六公共线2322和第七公共线2323与像素电极之间形成的存储电容，进而可以进一步提升开口率。此外，由于数据线2310被设置于栅绝缘层2400形成的凹陷处，而部分第六公共线2322和第七公共线2323被设置于栅绝缘层2400形成的凸起处，因此可以避免数据线2310与栅绝缘层2400距离过近或者短路。
例如，在本公开的实施例中，第四公共线、第五公共线、第六公共线和第七公共线的个数和位置不限于图5(a)至5(d)示出的情形，可以根据实际的遮光需求和所需的存储电容情况设置。例如，可以仅在第三电极层2500设置第四公共线2532；例如，可以仅在第二电极层2300设置第七公共线2323。
例如，根据实际应用需求，上述不同实施例中阵列基板的设置第一公共线、第二公共线、第三公共线、第四公共线、第五公共线、第六公共线和第七公共线的示例可以相互组合得到新的实施例。例如，可根据实际生产需要，增减或改变其膜层的层数或结构，在此不作限定。
这里，第一公共线至第七公共线中的每个构造为在提供公共电压。例如，第一公共线至第七公共线中的任意两个电性连接。
例如，第一公共线至第七公共线中任一个均与像素电极电绝缘。例如，每个第一像素电极与对应的数据线通过薄膜晶体管电性连接；每个第二像素电极与对应的数据线通过薄膜晶体管电性连接。
例如，第一公共线至第七公共线中任一个与第一像素电极和第二像素电极中的任一个彼此电绝缘。
这里，在同一层中的结构可通过同一构图工艺形成。
这里，表述“在衬底基板上的正投影”是指“在实质垂直于所述衬底基板的主表面的方向上的投影”。
例如，本公开的再一个实施例的提供了一种显示面板100，如图6所示，该显示面板100包括本公开任一实施例所述的阵列基板2000。例如，该显示面板可以在不增加工艺流程的情况下提升开口率，并且可以增强存储电容的稳定性进而增加显示图像的稳定性。例如，在本公开的实施例中，显示面板100还可包括彩膜基板3000，该彩膜基板3000可以包括黑矩阵3001，该黑矩阵3001对应于阵列基板2000设置在覆盖像素电极之间的区域，以遮挡阵列基板上的像素电极之间的间隙的光线并提升图像对比度。阵列基板2000和彩膜基板3000例如通过封框胶350彼此结合形成液晶盒，在液晶盒内填充有液晶材料400。在液晶面板非显示侧(图6中的下侧)还可以设置背光模块500，以为显示面板进行显示操作时提供光源。
例如，本公开的再一个实施例的提供了一种显示设备10，如图7所示，该显示设备包括显示面板100，显示面板100包括本公开任一实施例所述的阵列基板2000。
例如，该显示设备10可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，对于该显示设备的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示设备可以在不增加工艺流程的情况下提升开口率，并且可以增强存储电容的稳定性以及显示图像的稳定性。
例如，基于同一发明构思，本公开实施例还提供了一种本公开实施例提供的阵列基板2000的制造方法，以图2(a)和图2(b)所示出的情形为例，如图8所示，该制造方法可以包括以下步骤：
步骤S10：形成第二电极层2300，第二电极层2300包括数据线2310和第一公共线2321；
步骤S20：在第二电极层2300上形成绝缘层2200；
步骤S30：在绝缘层2200上形成第一电极层2100，第一电极层2100包括阵列分布的多个像素电极对2110，每一个像素电极对2110包括第一像素 电极2111和与第一像素电极2111在行方向上相邻的第二像素电极2112，数据线2310在行方向上位于第一像素电极2111和第二像素电极2112之间，第一公共线2321位于在行方向上相邻的两个像素电极对2110之间，并且第一公共线2321与两个像素电极对2110中的像素电极部分交叠。
在本公开实施例提供的阵列基板2000的制作方法中，由于像素电极与第三公共线之间仅间隔绝缘层2200，像素电极与第三公共线之间的距离减小，因此像素电极与第三公共线之间形成的存储电容增加，在达到相同电容值的情况下，像素电极与第一公共线交叠的面积可以相应减小，也就是说，第一公共线占用的面积可以相应减小，进而提升了开口率。由于第一公共线2321可以与数据线2310在同一个工艺流程中形成(即第一公共线可以与数据线同层形成)，因此可以在不增加额外的工艺流程的情况下增加存储电容和开口率。
例如，由于第一公共线与栅线2520之间存在栅绝缘层2400，因此第一公共线与栅线2520不会短路。所以第一公共线可以在列方向上连续延伸，并使得第一公共线与整列像素电极形成的存储电容合并在一起，进而可以在不增加额外的工艺流程的情况下提升存储电容的稳定性以及显示图像的稳定性。
例如，在本公开实施例提供的阵列基板2000的制作方法中，还可包括提供衬底基板2600；在衬底基板2600上形成第三电极层2500；在第三电极层2500上形成栅绝缘层2400；第二电极层2300位于栅绝缘层2400上。
显然，本公开实施例提供的阵列基板的制作方法不限于图2(a)和图2(b)所示的情形，还可以包括如图3、图4以及图5(a)～5(b)所示的情形。
例如，在本公开实施例提供的阵列基板2000的制作方法中，第三电极层2500可以包括第二公共线2531，第二公共线2531位于在行方向上相邻的两个像素电极对2110之间(参见图3)。例如，第二公共线2531的面积可以小于第一公共线2321，进而阶梯状的结构可以增加第一公共线2321和像素电极交叠的面积，因此可以增加两者之间形成的存储电容，进而可以提升开口率。
例如，在本公开实施例提供的阵列基板2000的制作方法中，第三电极层 2500包括第三公共线2510，第三公共线2510沿行方向延伸，并且与至少一个像素电极对2110的像素电极在所述衬底基板上的正投影至少部分交叠(参见图4)。
例如，在本公开实施例提供的阵列基板2000的制作方法中，还包括在栅绝缘层2400中形成过孔2410，第一公共线2321与第三公共线2510通过过孔2410电连接。进而使得可以通过第三公共线将所有第一公共线2321与像素电极之间形成的存储电容与第三公共线2510与像素电极之间形成的存储电容合并成一个整体，进而可以进一步的提升存储电容的稳定性，进而提高显示图像的稳定性。
例如，在本公开实施例提供的阵列基板2000的制作方法中，还包括在第三电极层2500形成第四公共线和第五公共线，第四公共线2532设置于数据线2310的一侧(例如图5(b)所示的数据线的左侧)，并且与数据线2310相邻(例如图5(b)所示的数据线的左侧相邻)的像素电极部分交叠；第五公共线2533设置于数据线2310的另一侧(例如图5(b)所示的数据线的右侧)，并且与数据线2310相邻(例如图5(b)所示的数据线的右侧相邻)的像素电极部分交叠。由此可以进一步增加存储电容，进而可以提升开口率。
例如，在本公开实施例提供的阵列基板2000的制作方法中，还包括在第二电极层2300形成第六公共线和第七公共线，第六公共线2322设置于数据线2310的一侧(例如图5(c)所示的数据线的左侧)，并且与数据线2310相邻(例如图5(c)所示的数据线的左侧相邻)的像素电极部分交叠；第七公共线2323设置于数据线2310的另一侧(例如图5(c)所示的数据线的右侧)，并且与数据线2310相邻(例如图5(c)所示的数据线的右侧相邻)的像素电极部分交叠。由此可以进一步增加垂直公共线与像素电极形成的存储电容，进而可以提升开口率。
本公开的实施例提供一种阵列基板及制造方法、显示面板和显示设备，可以在不增加工艺流程的情况下增加存储电容、提升开口率，并且可以增强存储电容的稳定性以及显示图像的稳定性。
以上仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2016年9月26日递交的中国专利申请第201610849815.6 号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    第一电极层，包括阵列排布的多个像素电极对，其中，每个所述像素电极对包括第一像素电极和与所述第一像素电极在行方向上相邻的第二像素电极；
    数据线，在所述行方向上设置于同一像素电极对的所述第一像素电极和所述第二像素电极之间且沿列方向延伸；以及
    第一公共部分，与所述行方向上相邻的两个所述像素电极对中相邻的所述第一像素电极和所述第二像素电极中的至少之一在所述衬底基板上的正投影至少部分交叠，其中，所述第一公共部分与所述第一电极层彼此绝缘。
  2. 如权利要求1所述的阵列基板，其中，所述数据线和所述第一公共部分包括于不同于第一电极层的第二电极层中。
  3. 如权利要求1或2所述的阵列基板，其中，所述第一公共部分为在所述列方向延伸的第一公共线。
  4. 如权利要求1至3中任一项所述的阵列基板，还包括：
    第三电极层，设置于所述衬底基板上；
    栅绝缘层，设置于所述第三电极层上，其中，所述数据线和所述第一公共部分设置于所述栅绝缘层上；以及
    绝缘层，设置于所述数据线和所述第一公共部分上，其中，所述第一电极层设置于所述绝缘层上。
  5. 如权利要求4所述的阵列基板，其中，所述第三电极层包括第二公共线，所述第二公共线与所述第一公共部分在所述衬底基板上的正投影重叠。
  6. 如权利要求5所述的阵列基板，其中，所述第二公共线与相邻的所述第一像素电极以及所述第二像素电极在所述衬底基板上的正投影不重叠。
  7. 如权利要求4至6中任一项所述的阵列基板，其中，所述第三电极层包括第三公共线，所述第三公共线沿所述行方向延伸，并且与至少一个所述像素电极对的所述第一像素电极和所述第二像素电极的至少之一在所述衬底基板上的正投影至少部分交叠。
  8. 如权利要求7所述的阵列基板，其中，所述第一公共部分与所述第三公共线电连接。
  9. 如权利要求1至8中任一所述的阵列基板，还包括第四公共线和第五公共线的至少之一，所述第四公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第四公共线在所述衬底基板上的正投影至少部分交叠；所述第五公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第五公共线在所述衬底基板上的正投影至少部分交叠。
  10. 如权利要求9所述的阵列基板，其中，所述第四公共线和第五公共线的至少之一包括在第三电极层中。
  11. 如权利要求1至10中任一所述的阵列基板，还包括第六公共线和第七公共线的至少之一，所述第六公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第六公共线在所述衬底基板上的正投影至少部分交叠；所述第七公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第七公共线在所述衬底基板上的正投影至少部分交叠。
  12. 如权利要求9所述的阵列基板，其中，所述第六公共线和第七公共线的至少之一包括在第二电极层中。
  13. 一种显示面板，包括如权利要求1至12中任一所述的阵列基板。
  14. 一种显示设备，包括如权利要求13所述的显示面板。
  15. 一种阵列基板制造方法，包括：
    提供衬底基板；
    在所述衬底基板上形成数据线和第一公共部分；以及
    在所述数据线和第一公共部分上方形成第一电极层；
    其中，所述第一电极层包括阵列分布的多个像素电极对，每一个所述像素电极对包括第一像素电极和与所述第一像素电极在行方向上相邻的第二像素电极，所述数据线在所述行方向上位于同一像素单元对的所述第一像素电极和所述第二像素电极之间，所述第一公共部分位于在所述行方向上相邻的两个所述像素电极对之间，并且所述第一公共部分与两个所述像素电极对中的像素电极在所述衬底基板上的正投影至少部分交叠，其中，所述第一公共 部分与所述第一电极层彼此绝缘。
  16. 如权利要求15所述的方法，还包括：
    在所述衬底基板上形成第三电极层；
    在所述第三电极层上形成栅绝缘层；其中，所述数据线和所述第一公共部分位于所述栅绝缘层上。
  17. 如权利要求16所述的方法，其中，所述第三电极层包括第二公共线，所述第二公共线与所述第一公共部分在所述衬底基板上的正投影重叠。
  18. 如权利要求16或17所述的方法，其中，所述第三电极层包括第三公共线，所述第三公共线沿所述行方向延伸，并且与至少一个所述像素电极对的所述第一像素电极和所述第二像素电极的至少之一在所述衬底基板上的正投影至少部分交叠。
  19. 如权利要求15至18中任一所述的方法，还包括形成第四公共线和第五公共线的至少之一，其中，所述第四公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第四公共线在所述衬底基板上的正投影至少部分交叠；所述第五公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第五公共线在所述衬底基板上的正投影至少部分交叠。
  20. 如权利要求15至19中任一所述的方法，还包括形成第六公共线和第七公共线的至少之一，其中，所述第六公共线设置于所述数据线的第一侧，且相邻于所述数据线的第一像素电极与所述第六公共线在所述衬底基板上的正投影至少部分交叠；所述第七公共线设置于所述数据线的与所述第一侧相反的第二侧，且相邻于所述数据线的第二像素电极与所述第七公共线在所述衬底基板上的正投影至少部分交叠。
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