WO2018010056A1 - 逆导绝缘栅双极型晶体管结构及其对应的制造方法 - Google Patents

逆导绝缘栅双极型晶体管结构及其对应的制造方法 Download PDF

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Publication number
WO2018010056A1
WO2018010056A1 PCT/CN2016/089596 CN2016089596W WO2018010056A1 WO 2018010056 A1 WO2018010056 A1 WO 2018010056A1 CN 2016089596 W CN2016089596 W CN 2016089596W WO 2018010056 A1 WO2018010056 A1 WO 2018010056A1
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conductivity type
region
emitter
collector
buffer
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PCT/CN2016/089596
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English (en)
French (fr)
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刘佩斯
周贤达
单建安
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刘佩斯
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Priority to PCT/CN2016/089596 priority Critical patent/WO2018010056A1/zh
Priority to US15/571,188 priority patent/US10593788B2/en
Publication of WO2018010056A1 publication Critical patent/WO2018010056A1/zh

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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
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    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
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    • H01L29/0692—Surface layout
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    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Definitions

  • the present invention relates generally to the structure and fabrication process of power semiconductor devices, and more particularly to reverse conducting insulated gate bipolar transistors (RC-IGBTs).
  • RC-IGBT consists of two devices that are monolithically integrated on the same chip: Insulated Gate Bipolar Transistor (IGBT) and Freewheeling Diode (FWD).
  • IGBT Insulated Gate Bipolar Transistor
  • FWD Freewheeling Diode
  • RC-IGBTs have been widely used in high voltage power electronic systems such as inductive heaters.
  • the fabrication of RC-IGBTs typically requires a thin wafer process, which makes the manufacturing process quite challenging. Accordingly, it is an object of the present invention to provide a high performance RC-IGBT structure that can be fabricated without a thin wafer process.
  • FIG. 1 A cross section of a prior art RC-IGBT device 100 is shown in FIG.
  • the device 100 includes an emitter (120), a plurality of cells under the emitter (120), an n-drift region (114) under the cell, and an n-buffer under the n-drift region (114).
  • the cells comprising: a p-base region (113) at the top of the n-drift region (114); an n+ emitter region (111) partially surrounded by the upper surface of the p-base region (113) and connected to the emitter (120); The base region (113) is connected to the P + diffusion region (112) of the emitter (120); covers the sidewall surface of the p-base region (113) and thus the n + emitter region (111) and the n-drift region (114)
  • a gate dielectric (131) is formed between the trenches; a trench gate electrode (121) surrounded by a gate dielectric (131).
  • the emitter (120) and collector (122) of the integrated IGBT are also the anode and cathode electrodes of the integrated FWD, respectively.
  • the wafer thickness of device 100 should be fairly thin to implement a field stop design. For example, if device 100 has a nominal voltage of 600 V, then the wafer thickness will be approximately 60 ⁇ . A dedicated system is needed to handle such thin wafers, and the manufacturing cost is quite high. In addition, even with a dedicated system, achieving high yields without breaking the wafer is quite challenging.
  • the present invention provides an RC-IGBT structure including: an emitter at a front surface; a plurality of cells under the emitter; under the cell N-drift region; collector at the back; a plurality of trenches at the backside and filled by the collector; mechanically supporting the semiconductor region between the trenches; at the top of each trench and connected to the collector a p + collector region; an n-buffer at the top of each p + collector region and below the n-drift region; as part of the mechanically supported semiconductor region at the sidewall of each trench and connected to the collector the n + cathode region.
  • a reverse conducting insulated gate bipolar transistor structure comprising:
  • a collector region of a second conductivity type is at the top of each trench and is connected to the collector
  • a buffer of a first conductivity type is at a top of each collector region of the second conductivity type and below a drift region of the first conductivity type, the first A conductivity type buffer separates the drift region from the collector region;
  • a cathode region of a first conductivity type the cathode region of the first conductivity type as part of a mechanically supported semiconductor region at each trench sidewall and connected to the collector.
  • the cell structure includes:
  • the base region of the second conductivity type being at the top of the drift region of the first conductivity type
  • an emission region of a first conductivity type, the emitter region of the first conductivity type and the base region of the second conductivity type are in contact with and connected to the emitter, a diffusion region of a second conductivity type, the base region of the second conductivity type is in contact with the base region of the second conductivity type, and is in contact with the emission region of the first conductivity type on both sides And contacting the emitter of the second conductivity type with the emitter and connecting the base of the second conductivity type to the emitter,
  • a gate dielectric covering a sidewall surface of the base region of the second conductivity type and thus forming a trench between the emitter region of the first conductivity type and the drift region of the first conductivity type Road,
  • the cell structure includes:
  • the base region of the second conductivity type being located above the drift region of the first conductivity type and in contact with an upper surface of the drift region
  • An emitter region of a first conductivity type, an emitter region of the first conductivity type and an upper surface of the substrate region of the second conductivity type are in contact with and connected to the emitter,
  • the diffusion region of the second conductivity type being in contact with the base region of the emitter and the second conductivity type, respectively, connecting the base region to the emitter,
  • a gate dielectric covering an upper surface of the base region of the second conductivity type and thus forming a channel between the emitter region and the drift region of the first conductivity type
  • a gate electrode the gate electrode is on top of the gate dielectric
  • An interlayer dielectric, the interlayer dielectric isolating the gate electrode and the emitter.
  • drift region of the first conductivity type has a poor concentration from 1 ⁇ 10 12 cm ⁇ 3 to 1 ⁇ 10 15 cm ⁇ 3 and a length between 30 ⁇ and 400 ⁇ .
  • the trench has a circular top view.
  • the trench has a hexagonal top view.
  • the length of the buffer of the first conductivity type is greater than The length of the drift region of the first conductivity type is short.
  • the second conductive type collector region having lxl0 18 cm - 3 to lxl0 21 cm - 3 and exotic doping concentration between 0.1 ⁇ 1 ⁇ depth.
  • the first conductivity type cathode region (217/317) having lxl0 19 cm - 3 IJ to suffer doping concentration of 1x10 21 cm -3.
  • a method of fabricating an RC-IGBT structure comprising the steps of:
  • the buffer of the first conductivity type and the cathode region of the first conductivity type are formed by diffusion homogenization.
  • the buffer of the first conductivity type is formed by diffusion, and then the cathode region of the first conductivity type is formed by oblique ion implantation and annealing.
  • the cathode region of the first conductivity type is formed by diffusion, and then the buffer of the first conductivity type is formed by silicon anisotropic etching and subsequent diffusion.
  • the collector is formed by depositing a metal layer.
  • the collector is formed by depositing a metal layer and then performing planarization.
  • FIG. 1 is a cross-sectional view of a prior art RC-IGBT device 100.
  • FIG. 2 is a cross-sectional view of the present invention implemented in a trench gate RC-IGBT device 200.
  • 3 is a cross-sectional view of the present invention implemented in a planar gate RC-IGBT device 300.
  • FIG. 4 is a back pattern design for device 200 as previously shown in FIG. 2.
  • FIG. 5 is another back pattern design for device 200 as previously shown in FIG. 2.
  • 6 to 12 illustrate a method of fabricating the device 200 as shown previously in FIG. 2.
  • the heavily miscellaneous n-type region is labeled as n + and the heavily miscellaneous p-type region is labeled as p + .
  • the heavily miscellaneous regions typically have a viscous concentration between 1 x 10 19 cm -3 and 1 x 10 2 1 cm 3 .
  • the lightly miscellaneous n-type region is labeled as n-
  • the lightly miscellaneous p-type region is labeled as p-.
  • the lightly miscellaneous region typically has a viscous concentration between lxl0 i3 C m -3 and 1 x lO 17 cm -3 .
  • Device 200 includes: an emitter at the front side (220); a plurality of cell structures under the emitter (220); an n-drift region under the cell structure (214); a collector at the back (222) a plurality of trenches (240) at the back side and filled by the collector (222); a mechanically supported semiconductor region (24 1) between the trenches (240); at the top of each trench (240) And connected to the p + collector region (216) of the collector (222); n buffer (215) at the top of each p + collector region (216) and below the n-drift region (214); A portion of the semiconductor region (241) is mechanically supported at the sidewall of each trench (240) and is connected to the n+ cathode region (217) of the collector (222).
  • Device 200 has the same cell structure as compared to device 100, including: a p-base region (213) at the top of the n-drift region (214); partially surrounded and connected by the upper surface of the p-base region (213) n + to the emitter (220)
  • the sidewall surface of the p-base region (213) is inverted and in the n + emitter region (211) and n - An n-type channel is formed between the drift regions (214), and electrons can flow through the channel. If the on-state current density is small (e.g., well below 100 A/cm2), then the device operates as a power MOSFET and the n+ cathode region (217) is the drain region of the power MOSFET. If the on-state current density is large
  • the p+ collector (216) /n buffer (215) junction will be forward biased and the device operates as an IGBT.
  • the current is blocked by a reverse biased n-drift (214) /p base region (213) junction.
  • the FWD formed by the p base region (213) /n-drift (214) /n + cathode region (217) is forward biased, and the reverse current can flow from the emitter (220) Collector (222).
  • the operational mechanism of device 200 is substantially the same as the operational mechanism of device 100. However, device 200 has a three-dimensional structure at the back, but device 100 does not.
  • the p+ collector region (216) of the integrated IGBT is located at the top side
  • the n+ cathode region (217) of the integrated FWD is located at the sidewall.
  • the structure enables the integrated IGBT to have a relatively thin (e.g., 60 ⁇ m) device thickness, while the semiconductor region (241) between the trenches remains thick (e.g., about 700 ⁇ m) for use as a mechanical support.
  • the thinner device thickness of the integrated IGBT is desirable because it enables the current state of the art field-stopping backside structure, while the mechanically supported semiconductor region (241) enables normal processing of the device wafer without special attention. . Furthermore, since the n + cathode region (217) of the integrated FWD is part of the supporting semiconductor region (241), the mechanically supported semiconductor region (241) is not wasted in terms of electrical performance.
  • the blocking voltage is maintained primarily by the lightly distorted n-drift region (214).
  • the complex concentration and length of the n-drift region (214) depends on the rated voltage of the device. Usually, the IGBT has a rated voltage between 400 V and 6000 V. Based on this range, the impurity concentration of the n-drift region (214) is Between lxl0 12 cm- 3 and lxl0 15 cm- 3 , and the length of the n-drift region (214) is between 30 ⁇ m and 400 ⁇ m.
  • the length of the ⁇ buffer (215) can be much smaller than the length of the ⁇ -drift region (214).
  • the viscous concentration of the ⁇ buffer (215) should be higher than the odious concentration of the ⁇ -drift region (214) because the ⁇ buffer (215) should prevent the expansion of the depletion region in the blocking state.
  • the current density is small (e.g., well below 100 A/cm2), then the device operates as a power MOSFET and the n+ cathode region (217) is the drain region of the power MOSFET.
  • the n + cathode region (217) needs to be heavily miscellaneous. If the on-state current density is large (e.g., about 100 A/cm 2 ), then the p + collector region (216) / n buffer (215 ) junction will be forward biased and the device operates as an IGBT. In the IGBT mode, holes are injected from the p + collector region (216) into the n-drift region (214), resulting in a relatively lower conduction loss compared to the conduction loss in the power MOSFET mode. However, the hole injection efficiency of the back p + collector region (216) / n buffer (215) junction should not be so high that the shutdown speed is significantly reduced. Thus, for a p + collector region (216), preferably from lxl0 18 cm - 3 to lxl0 21 cm - suffer doping concentration depth between 3 and 1 ⁇ and 0.1 ⁇
  • the backside structure of device 300 is identical to the backside structure of device 200, and also includes: an emitter at the front side (320); a plurality of cell structures under the emitter (320); an ⁇ -drift region under the cell structure (314); collector (322) at the back; a plurality of trenches (340) at the backside and filled by the collector (322); mechanically supporting the semiconductor region (341) between the trenches (340) At the top of each trench (340) and connected to the ⁇ + collector region (316) of the collector (322); at the top of each ⁇ + collector region (316) and in the ⁇ -drift region ( 314)
  • the lower n- buffer (315) is part of the mechanically supported semiconductor region (341) at the sidewall of each trench (3240) and is connected to the n+ cathode region (317) of the collector (322).
  • the operating mechanisms of device 300 and device 200 are also the same.
  • the only difference between device 300 and device 200 is the cell structure.
  • the cell includes: a p-base region (313) partially surrounded by an upper surface of the ⁇ -drift region (314); partially surrounded by the upper surface of the p-base region (313) and connected to the emission
  • the ⁇ + emitter region of the pole (320); the ⁇ base region (313) is connected to the emitter region (312) of the emitter (320); covers the upper surface of the ⁇ base region (313) and thus is at ⁇ a gate dielectric (331) forming a channel between the emitter region (311) and the ⁇ -drift region (314); a gate electrode (321) at the top of the gate dielectric (331); an isolation gate electrode (321) and an emitter ( 320) Interlayer dielectric (330).
  • FIG. 4 is a back pattern design for the device 200 as previously shown in FIG. 2. As shown in the figure, the groove
  • (240) has a round top view.
  • the circular pattern will not form any sharp angles at the sidewalls and thus improve the uniformity of the grooves (240) during manufacturing.
  • the same design applies to device 300 as well.
  • FIG. 5 is another back pattern design for device 200 as previously shown in FIG. 2.
  • the groove (240) has a hexagonal top view.
  • the hexagonal pattern allows the grooves (240) to be closely aligned And thus maximize the percentage of the area occupied by the integrated IGBT with the same design rules.
  • the same design is also applicable to device 300.
  • the manufacturing method includes: 1) starting with a lightly miscellaneous n-type substrate wafer; 2) forming a plurality of cells on the front side of the wafer; 3) forming a plurality of holes on the back side of the wafer using a hard mask (232) a trench (240) and a n- drift region (214); 4) forming an n-buffer (215) at the top of each trench and forming an n+ cathode region on the sidewall of each trench (217) 5) Forming a collector region (216) under the buffer (215); 6) removing the hard mask (232); 7) forming a collector (222) on the back side of the wafer; 8) on the wafer
  • the emitter is formed on the front side (220).
  • FIG. 6 illustrates the formation of cells on the front side of the wafer.
  • the starting wafer is a lightly miscellaneous n-type substrate wafer.
  • the bulk concentration of the substrate wafer should be the same as the target concentration of the n-drift region (214).
  • the substrate wafer has a normal thickness. For example, a normal 6 inch wafer has a thickness of about 700 ⁇ .
  • the cells are formed using conventional trench gate technology as is known to those skilled in the art. In order to avoid contamination of the furnace tube in the following steps, the emitter (220) is not formed in this step and the interlayer dielectric (230) is not patterned.
  • FIG. 7 illustrates that a trench (240) is formed at the back surface and an ⁇ -drift region (214) is also formed.
  • a hard mask layer (232) is deposited on the back side and patterned.
  • the trench (240) is then etched using a hard mask (232) and the remaining portion of the wafer becomes the ⁇ -drift region (214).
  • the hard mask (232) is typically, but not limited to, silicon oxide, which is typically, but not limited to, deep reactive ion etching (DRIE).
  • DRIE deep reactive ion etching
  • a normal 6 inch wafer has a thickness of about 700 ⁇ , while a 600 V field prevents the IGBT from requiring an ⁇ -drift (214) length of about 60 ⁇ .
  • the depth of the trench (240) should be 640 ⁇ , which is the difference between the wafer thickness and the length of the target ⁇ -drift region (214).
  • the width of the groove depends on the specific design, and the width is typically between 50 ⁇ and 500 ⁇ .
  • FIG. 8 illustrates the formation of an n buffer (215) and an ⁇ + cathode region (217).
  • the n buffer (215) and the ⁇ + cathode region (217) are formed by diffusion homogenization.
  • phosphorus can be diffused into the silicon at about 1000 degrees Celsius to form a heavily doped n-region at the surface of the trench (240).
  • the manufacturing process is simple. However, this may result in a high concentration in the n-buffer (215), which is not conducive to achieving a field-blocking structure.
  • the n buffer (215) is formed by diffusion, and An n + cathode region (217) is then formed by oblique ion implantation and annealing.
  • the viscous concentration of the n-buffer (215) can be independent of the impurity concentration of the n + cathode region (217), depending on the desired device performance.
  • the n + cathode region (217) can be moved away from the top of the trench, which will be between the n + cathode region (217) and the p + collector region (216) / n buffer (215) junction. A relatively high resistance is formed.
  • the n + cathode region (217) is first formed by diffusion.
  • the n + silicon region at the top of the trench (240) is then etched away by an anisotropic etch.
  • Anisotropic etching is typically not limited to DRIE.
  • diffusion is performed using a relatively small dose to form an n-buffer (215).
  • the n buffer (215) can also be mixed with the n + cathode region.
  • the n + cathode region (217) can also be moved away from the top of the trench (240), and thus the forward curve retrace effect of the device can be suppressed.
  • FIG. 9 illustrates the formation of a p+ collector region (216).
  • the p + collector region (216) is formed by ion implantation and annealing.
  • the formation of the p + collector region (216) partially consumes the n-buffer (215) but does not consume the n + cathode region (217) because it is located at the sidewall of the trench (240). .
  • FIG. 10 illustrates the formation of a collector (222) on the back side of the wafer.
  • a metal layer is then deposited on the back side of the wafer to form a collector (222).
  • the hard mask (232) can usually be removed by wet etching.
  • the metal layer can be deposited by sputtering, evaporation or electroplating.
  • FIG. 11 illustrates an optional planarization step for the collector (222).
  • the planarization can be optionally performed after the metal deposition.
  • Flattening is chemical mechanical polishing after mechanical or chemical mechanical polishing or mechanical polishing.
  • a smooth back surface facilitates packaging because it reduces the gap on the back of the chip during packaging
  • FIG. 12 illustrates the formation of an emitter (220) on the front side of the wafer.
  • the interlayer dielectric (230) is patterned.
  • a metal layer is then deposited on the front side to form an emitter (220).
  • an alloy annealing can be performed to reduce the contact resistance of the emitter (220).
  • the manufacturing method is independent of the cell structure of the device because the cells are formed prior to processing the back side. Therefore, although the manufacturing method is illustrated using the device 200 as an example, The same method is also applicable to device 300.

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Abstract

逆导绝缘栅双极型晶体管结构及其对应的制造方法，能够在无薄晶圆工艺的情况下制造的高性能RC-IGBT结构，提供一种RC-IGBT结构，包括：在正面处的发射极(220/320)；在发射极(220/320)下的多个元胞；在元胞下的n-漂移区(214/314)；在背面处的集电极(222/322)；在背面处并且被集电极(222/322)充满的多个沟槽(240/340)；沟槽(240/340)之间的机械支撑半导体区(241/341)；每个沟槽(240/340)的顶部并且连接到集电极(222/322)的p+集电区(216/316)；每个p+集电区(216/316)的顶部并且在n-漂移区(214/314)下方的n缓冲区(215/315)；作为每个沟槽(240/340)侧壁处的机械支撑半导体区(241/341)的一部分并且连接到集电极(222/322)的n+阴极区(217/317)。

Description

发明名称:逆导绝缘栅双极型晶体管结构及其对应的制造方法 技术领域
[0001] 本发明大体上涉及功率半导体器件的结构和制造过程， 且确切地说， 涉及逆导 绝缘栅双极型晶体管 （RC-IGBT) 。 RC-IGBT包括在同一芯片上单片集成的两 个器件： 绝缘栅双极型晶体管 （IGBT) 和续流二极管 （FWD) 。
背景技术
[0002] 发明背景
[0003] RC-IGBT已经广泛用于感性加热器等高压功率电子***中。 通常 RC-IGBT的制 造需要薄晶圆工艺， 这使得制造过程相当具有挑战性。 因此， 本发明的目的是 提供一种能够在无薄晶圆工艺的情况下制造的高性能 RC-IGBT结构。
技术问题
[0004] 图 1中示出现有技术 RC-IGBT器件 100的横截面。 器件 100包括发射极 （120) 、 在发射极 （120) 下的多个元胞、 在所述元胞下的 n -漂移区 （114) 、 在 n -漂移区 (114) 下的 n缓冲区 （115) 、 在 n缓冲区 （115) 下的多个 n +阴极区 （117) 和 p +集电区 （116) 、 以及在底部处的集电极 （122) ， 所述的元胞包括： 在 n -漂移 区 （114) 的顶部的 p基区 （113) ； 由 p基区 （113) 的上表面部分地包围并且连 接到发射极 （120) 的 n +发射区 （111) ； 将 p基区 （113) 连接到发射极 （120) 的 P +扩散区 （112) ； 覆盖 p基区 （113) 的侧壁表面并且因此在 n +发射区 （111 ) 与 n -漂移区 （114) 之间形成沟道的栅电介质 （131) ； 由栅电介质 （131) 包 围的沟槽式栅电极 （121) 。 集成 IGBT的发射极 （120) 和集电极 （122) 还分别 是集成 FWD的阳极电极和阴极电极。 为了获得优化性能的集成 IGBT, 器件 100 的晶圆厚度应相当薄以实施场阻止设计。 例如， 如果器件 100具有 600 V的额定 电压， 那么晶圆厚度将为约 60 μηι。 需要专用***来处理此类薄晶圆， 并且制造 成本相当高。 此外， 即使使用专用***， 不使晶圆破裂从而实现高良率也是相 当具有挑战性的。
问题的解决方案 技术解决方案
[0005] 因此， 本发明的目的是提供一种能够在无薄晶圆工艺的情况下制造的高性能 R C-IGBT结构。
[0006] 为了实现此目的和其它目的， 本发明提供一种 RC-IGBT结构， 所述 RC-IGBT结 构包括： 在正面处的发射极； 在发射极下的多个元胞； 在元胞下的 n -漂移区； 在 背面处的集电极； 在背面处并且被集电极充满的多个沟槽； 在沟槽之间的机械 支撑半导体区； 在每个沟槽的顶部并且连接到集电极的 p +集电区； 在每个 p +集 电区的顶部并且在 n -漂移区下方的 n缓冲区； 作为在每个沟槽侧壁处的机械支撑 半导体区的一部分并且连接到集电极的 n +阴极区。
[0007] 一种逆导绝缘栅双极型晶体管结构 （RC-IGBT) ， 其包括有：
[0008] 位于正面处顶部的发射极，
[0009] 在所述发射极下的多个元胞结构，
[0010] 在所述元胞结构下的第一导电类型的漂移区，
[0011] 在背面处的集电极，
[0012] 一个以上的沟槽， 所述的沟槽在所述背面处并且被所述集电极充满，
[0013] 在所述沟槽之间的机械支撑半导体区，
[0014] 第二导电类型的集电区， 所述第二导电类型的集电区在每个沟槽的顶部并且连 接到所述集电极，
[0015] 第一导电类型的缓冲区， 所述第一导电类型的缓冲区在每个第二导电类型的集 电区的顶部并且在所述第一导电类型的漂移区下方， 所述的第一导电类型的缓 冲区将漂移区和集电区隔幵；
[0016] 第一导电类型的阴极区， 所述第一导电类型的阴极区作为在每个沟槽侧壁处的 机械支撑半导体区的一部分并且连接到所述集电极。
[0017] 进一步的， 所述的元胞结构包括有：
[0018] 第二导电类型的基区， 所述第二导电类型的基区在所述第一导电类型的漂移区 的顶部，
[0019] 第一导电类型的发射区， 所述第一导电类型的发射区和所述第二导电类型的基 区接触并且连接到所述发射极， [0020] 第二导电类型的扩散区， 所述第二导电类型的扩散区下方和所述的第二导电类 型的基区接触并在上方两侧和所述的第一导电类型的发射区接触， 所述的第二 导电类型的扩散区上方还和所述的发射极接触并将所述第二导电类型的基区连 接到所述发射极，
[0021] 栅电介质， 所述栅电介质覆盖所述第二导电类型的基区的侧壁表面并且因此在 所述第一导电类型的发射区与所述第一导电类型的漂移区之间形成沟道，
[0022] 沟槽式栅电极， 所述沟槽式栅电极被所述栅电介质包围，
[0023] 层间电介质， 所述层间电介质隔离所述栅电极和所述发射极 （220) 。
[0024] 进一步的， 所述的元胞结构包括有：
[0025] 第二导电类型的基区， 所述第二导电类型的基区位于所述的第一导电类型的漂 移区的上方并和所述漂移区的上表面接触，
[0026] 第一导电类型的发射区， 所述第一导电类型的发射区和所述第二导电类型的基 区的上表面接触并且连接到所述发射极，
[0027] 第二导电类型的扩散区， 所述第二导电类型的扩散区分别与所述的发射极和第 二导电类型的基区接触， 将所述基区连接到所述发射极，
[0028] 栅电介质， 所述栅电介质覆盖所述第二导电类型的基区的上表面并且因此在所 述发射区与所述第一导电类型的漂移区之间形成沟道，
[0029] 栅电极， 所述栅电极在所述栅电介质的顶部，
[0030] 层间电介质， 所述层间电介质隔离所述栅电极和所述发射极。
[0031] 进一步的， 其中所述第一导电类型的漂移区具有从 1x10 12cm - 3到 1x10 15 cm -3的 惨杂浓度以及 30 μηι与 400 μηι之间的长度。
[0032] 进一步的， 其中所述沟槽具有圆形顶视图。
[0033] 进一步的， 其中所述沟槽具有六边形顶视图。
[0034] 进一步的， 其中所述第一导电类型的缓冲区的惨杂浓度比所述第一导电类型的 漂移区的惨杂浓度高， 所述第一导电类型的缓冲区的长度比所述第一导电类型 的漂移区的长度短。
[0035] 进一步的， 其中所述第二导电类型的集电区具有 lxl0 18 cm -3到 lxl0 21 cm -3的惨 杂浓度以及 0.1 μηι与 1 μηι之间的深度。 [0036] 进一步的， 其中所述第一导电类型的阴极区 （217/317) 具有 lxl0 19cm - 3 至 IJ 1x10 21 cm -3的惨杂浓度。
[0037] 一种制造 RC-IGBT结构的方法， 其包括有如下步骤：
[0038] 以衬底晶圆幵始，
[0039] 在所述晶圆的正面形成多个元胞结构，
[0040] 使用硬掩模在所述晶圆的背面形成一个以上沟槽并且同吋形成第一导电类型的 漂移区，
[0041] 在每个沟槽的顶部形成第一导电类型的缓冲区并且在每个沟槽的侧壁形成第一 导电类型的阴极区，
[0042] 在所述第一导电类型的缓冲区下形成第二导电类型的集电区，
[0043] 移除所述硬掩模，
[0044] 在所述晶圆的所述背面形成集电极，
[0045] 在所述晶圆的所述正面形成发射极。
[0046] 进一步的， 其中通过扩散同吋形成所述第一导电类型的缓冲区和所述第一导电 类型的阴极区。
[0047] 进一步的， 其中通过扩散形成所述第一导电类型的缓冲区， 且接着通过倾斜离 子注入和退火形成所述第一导电类型的阴极区。
[0048] 进一步的， 其中通过扩散形成所述第一导电类型的阴极区， 且接着通过硅各向 异性蚀刻和随后扩散来形成所述第一导电类型的缓冲区。
[0049] 进一步的， 其中通过淀积金属层形成所述集电极。
[0050] 进一步的， 其中通过淀积金属层且接着执行平坦化来形成所述集电极。
发明的有益效果
有益效果
[0051] 提供一种够在无薄晶圆工艺的情况下制造的高性能 RC-IGBT结构
对附图的简要说明
附图说明
[0052] 图 1是现有技术 RC-IGBT器件 100的截面视图。
[0053] 图 2是实施于沟槽式栅极 RC-IGBT器件 200中的本发明的截面视图。 [0054] 图 3是实施于平面栅极 RC-IGBT器件 300中的本发明的截面视图。
[0055] 图 4是用于如之前在图 2中所示的器件 200的背面图案设计。
[0056] 图 5是用于如之前在图 2中所示的器件 200的另一背面图案设计。
[0057] 图 6到图 12示出用于如之前在图 2中所示的器件 200的制造方法。
本发明的实施方式
[0058] 本发明将使用 n沟道器件进行说明， 但是在以下说明中将被理解， 本发明同样 适用于 p沟道器件。 在本发明说明书中， 重惨杂 n型区标记为 n +， 且重惨杂 p型区 标记为 p +。 除非另外说明， 否则在硅中， 重惨杂区通常具有 lxl0 19 cm -3与 1x10 21 cm 3之间的惨杂浓度。 在本发明说明书中， 轻惨杂 n型区标记为 n -， 且轻惨杂 p 型区标记为 p -。 除非另外说明， 否则在硅中， 轻惨杂区通常具有 lxl0 i3 Cm -3与 1 xlO 17 cm -3之间的惨杂浓度。
[0059] 图 2是实施于沟槽式栅极 RC-IGBT器件 200中的本发明的截面视图。 器件 200包 括： 在正面处的发射极 （220) ； 在发射极 （220) 下的多个元胞结构； 在元胞 结构下的 n -漂移区 （214) ； 在背面处的集电极 （222) ； 在背面处并且被集电极 (222) 充满的多个沟槽 （240) ； 在沟槽 （240) 之间的机械支撑半导体区 （24 1) ； 在每个沟槽 （240) 的顶部并且连接到集电极 （222) 的 p +集电区 （216) ； 在每个 p +集电区 （216) 的顶部并且在 n -漂移区 （214) 下方的 n缓冲区 （215 ) ； 作为在每个沟槽 （240) 侧壁处的机械支撑半导体区 （241) 的一部分并且 连接到集电极 （222) 的 n +阴极区 （217) 。 与器件 100相比较， 器件 200具有相 同的元胞结构， 包括： 在 n - 漂移区 （214) 的顶部的 p基区 （213) ； 由 p基区 （213) 的上表面部分地包围并 且连接到发射极 （220) 的 n +
发射区 （211) ； 将 p基区 （213) 连接到发射极 （220) 的 p +扩散区 （212) ； 覆 盖 p基区 （213) 的侧壁表面并且因此在 n +发射区 （211) 与 n -漂移区 （214) 之 间形成沟道的栅电介质 （231) ； 由栅电介质 （231) 包围的沟槽式栅电极 （221 ) ； 隔离栅电极 （221) 和发射极 （220) 的层间电介质 （230) 。 在器件 200的 导通状态下， p基区 （213) 的侧壁表面反型且在 n +发射区 （211) 与 n - 漂移区 （214) 之间形成 n型沟道， 并且电子可以流过所述沟道。 如果导通状态 电流密度较小 （例如， 远低于 100A/cm2) ， 那么所述器件作为功率 MOSFET运 行， 并且 n+阴极区 （217) 是功率 MOSFET的漏区。 如果导通状态电流密度较大
(例如， lOOA/cm2左右） ， 那么 p+集电区 （216) /n缓冲区 （215) 结将正向偏 置， 并且所述器件作为 IGBT运行。 在器件 200的断幵状态下， 电流被逆向偏置的 n-漂移 （214) /p基区 （213) 结阻断。 在器件 200的逆向导通吋， 由 p基区 （213 ) /n-漂移 （214) /n+阴极区 （217) 形成的 FWD是正向偏置的， 并且逆向电流可 以从发射极 （220) 流向集电极 （222) 。 器件 200的运行机制与器件 100的运行 机制基本上相同。 然而， 器件 200在背面处具有三维结构， 但器件 100并非如此 。 如图中所示， 在器件 200中， 在背面处存在多个深沟槽 （240) 。 在每个沟槽 处， 集成 IGBT的 p+集电区 （216) 位于顶侧处， 并且集成 FWD的 n+阴极区 （217 ) 位于侧壁处。 所述结构使得集成 IGBT能够具有相对较薄的 （例如， 60μηι) 器 件厚度， 同吋沟槽之间的半导体区 （241) 仍然保持较厚 （例如， 约 700μηι) 以 用作机械支撑。 集成 IGBT的较薄的器件厚度是可取的， 因为可以实现当前最新 技术发展水平的场阻止背面结构， 同吋机械支撑半导体区 （241) 使得能够在无 需特别注意的情况下正常地处理器件晶圆。 此外， 由于集成 FWD的 n + 阴极区 （217) 是支撑半导体区 （241) 的一部分， 因此机械支撑半导体区 （241 ) 在电气性能方面并不浪费。
基于器件 200的运行机制， 需要相应地设计结构参数。 在器件 200的阻断状态下 ， 阻断电压主要通过轻惨杂 n-漂移区 （214) 维持。 n-漂移区 （214) 的惨杂浓度 和长度取决于器件的额定电压,通常 IGBT具有 400 V与 6000 V之间的额定电压,基 于此范围， n-漂移区 （214) 的惨杂浓度在 lxl012cm- 3与 lxl015cm- 3之间， 并且 n -漂移区 （214) 的长度在 30μηι与 400μηι之间。 由于阻断电压主要通过被耗尽的 η -漂移区 （214) 维持， 因此 η缓冲区 （215) 的长度可比 η-漂移区 （214) 的长度 小得多。 另一方面， η缓冲区 （215) 的惨杂浓度应高于 η-漂移区 （214) 的惨杂 浓度， 因为 η缓冲区 （215) 应阻止在阻断状态下耗尽区的扩展。 在器件的导通 状态下， 如果电流密度较小 （例如， 远低于 100A/cm2) ， 那么所述器件作为功 率 MOSFET运行， 并且 n+阴极区 （217) 是功率 MOSFET的漏区。 为了与集电极 (222) 形成良好欧姆接触， n +阴极区 （217) 需要是重惨杂的。 如果导通状态 电流密度较大 （例如， lOO A/cm 2左右） ， 那么 p +集电区 （216) /n缓冲区 （215 ) 结将正向偏置， 并且所述器件作为 IGBT运行。 在所述 IGBT模式下， 空穴从 p + 集电区 （216) 注入到 n -漂移区 （214) 中， 从而形成相较于功率 MOSFET模式下 的导通损耗相对更低的导通损耗。 然而， 背面 p +集电区 （216) /n缓冲区 （215) 结的空穴注入效率不应太高以致显著降低幵关速度。 因此， 对于 p +集电区 （216 ) ， 优选的是从 lxl0 18cm -3到 lxl0 21 cm -3的惨杂浓度和 0.1 μηι与 1 μηι之间的深度
[0061] 图 3是实施于平面栅极 RC-IGBT器件 300中的本发明的截面视图。 器件 300的背 面结构与器件 200的背面结构相同， 同样包括： 在正面处的发射极 （320) ； 在 发射极 （320) 下的多个元胞结构； 在元胞结构下的 η-漂移区 （314) ； 在背面处 的集电极 （322) ； 在背面处并且被集电极 （322) 充满的多个沟槽 （340) ； 在 沟槽 （340) 之间的机械支撑半导体区 （341) ； 在每个沟槽 （340) 的顶部并且 连接到集电极 （322) 的 ρ+集电区 （316) ； 在每个 ρ+集电区 （316) 的顶部并且 在 η-漂移区 （314) 下方的 η缓冲区 （315) ； 作为在每个沟槽 （3240) 侧壁处的 机械支撑半导体区 （341) 的一部分并且连接到集电极 （322) 的 η+阴极区 （317 ) 。 器件 300和器件 200的运行机制也相同。 器件 300与器件 200之间的唯一区别 是元胞结构。 在器件 300中， 所述元胞包括： 由 η -漂移区 （314) 的上表面部分地 包围的 ρ基区 (313); 由 ρ基区 (313)的上表面部分地包围并且连接到发射极 （320) 的 η +发射区 （311) ； 将 ρ基区 （313) 连接到发射极 （320) 的!^扩散区 （312) ； 覆盖 ρ基区 （313) 的上表面并且因此在 η +发射区 （311) 与 η -漂移区 （314) 之间形成沟道的栅电介质 （331) ； 在栅电介质 （331) 顶部的栅电极 （321) ； 隔离栅电极 （321) 和发射极 （320) 的层间电介质 （330) 。
[0062] 图 4是用于如之前在图 2中所示的器件 200的背面图案设计。 如图中所示， 沟槽
(240) 具有圆形顶视图。 圆形图案将不会在侧壁处形成任何锐角， 并且因此可 以提高制造过程中沟槽 （240) 的均匀性。 相同的设计也适用于器件 300。
[0063] 图 5是用于如之前在图 2中所示的器件 200的另一背面图案设计。 如图中所示， 沟槽 （240) 具有六边形顶视图。 六边形图案使得沟槽 （240) 能够紧密地排列 ， 并且因此在设计规则不变的情况下使集成 IGBT所占面积的百分比最大化。 相 同的设计也适用于器件 300。
[0064] 图 6到图 12示出用于如之前在图 2中所示的器件 200的制造方法。 所述制造方法 包括： 1 ) 以轻惨杂 n型衬底晶圆幵始； 2) 在晶圆的正面形成多个元胞； 3) 使 用硬掩模 （232) 在晶圆的背面形成多个沟槽 （240) 并且同吋形成 n - 漂移区 （214) ； 4) 在每个沟槽的顶部形成 n缓冲区 （215) 并且在每个沟槽的 侧壁形成 n +阴极区 （217) ； 5) 在缓冲区 （215) 下形成集电区 （216) ； 6) 移 除硬掩模 （232) ； 7) 在晶圆的背面形成集电极 （222) ； 8) 在晶圆的正面形 成发射极 （220) 。
[0065] 图 6示出在晶圆的正面形成元胞。 幵始的晶圆是轻惨杂 n型衬底晶圆。 衬底晶圆 的惨杂浓度应与 n -漂移区 （214) 的目标惨杂浓度相同。 衬底晶圆具有正常厚度 。 例如， 正常 6英寸的晶圆具有约 700 μηι的厚度。 使用如所属领域的技术人员已 知的常用沟槽式栅极技术形成元胞。 为了避免在以下步骤对炉管造成污染， 在 这个步骤不形成发射极 （220) 并且不对层间电介质 （230) 进行图案化。
[0066] 图 7示出在背面处形成沟槽 （240) 并且还形成 η -漂移区 （214) 。 首先， 在背 面处淀积硬掩模层 （232) 并对其进行图案化。 接着使用硬掩模 （232) 蚀刻沟 槽 （240) ， 并且同吋晶圆的剩余部分变为 η -漂移区 （214) 。 硬掩模 （232) 典 型地是但不限于氧化硅， 蚀刻典型地是但不限于深反应离子刻蚀 （DRIE) 。 沟 槽 （240) 的深度取决于 η -漂移区 （214) 的长度和晶圆的厚度。 例如， 正常 6英 寸的晶圆具有约 700 μηι的厚度， 而 600 V的场阻止 IGBT需要约 60 μηι的 η -漂移区 (214) 长度。 在这种情况下， 沟槽 （240) 的深度应为 640 μηι， 即是晶圆厚度 与目标 η -漂移区 （214) 长度之间的差值。 另一方面， 沟槽的宽度取决于特定设 计， 并且宽度典型地在 50 μηι与 500 μηι之间。
[0067] 图 8示出形成 η缓冲区 （215) 和 η +阴极区 （217) 。 在本发明的实施例中， 通过 扩散同吋形成 η缓冲区 （215) 和 η +阴极区 （217) 。 例如， 可以在约 1000摄氏度 下将磷扩散到硅中以在沟槽 （240) 的表面处形成重惨杂 η区。 在这种情况下， 制造过程简单。 然而， 这可能导致 η缓冲区 （215) 中的高惨杂浓度， 不利于实 现场阻止结构。 在本发明的另一实施例中， 通过扩散形成 η缓冲区 （215) ， 且 接着通过倾斜离子注入和退火形成 n +阴极区 （217) 。 在这种情况下， n缓冲区 (215) 的惨杂浓度可以与 n +阴极区 （217) 的惨杂浓度无关， 而根据所需的器 件性能决定。 此外， 通过控制倾斜角， 可以使 n +阴极区 （217) 远离沟槽顶部， 这将在 n +阴极区 （217) 与 p +集电区 （216) /n缓冲区 （215) 结之间形成相对较 高的电阻。 相对较高的电阻利于在相对较低电流使 IGBT运行， 从而抑制 RC-IGB T特有的正向曲线回扫效应。 在本发明的又一实施例中， 首先通过扩散形成 n +阴 极区 （217) 。 接着通过各向异性蚀刻来蚀刻掉沟槽 （240) 顶部的 n +硅区。 各 向异性蚀刻典型地不限于 DRIE。 在那之后， 使用相对较小剂量执行扩散以形成 n 缓冲区 （215) 。 在这种情况下， n缓冲区 （215) 的惨杂浓度也可以与 n +阴极区
(217) 无关。 此外， 通过控制硅的过蚀刻， 也可以使 n +阴极区 （217) 远离沟 槽 （240) 的顶部， 并且因此可以抑制器件的正向曲线回扫效应。 最后， 值得指 出的是， 在所有这些实施例中， 在 n缓冲区 （215) 与 n +阴极区 （217) 之间不存 在固定边界， 因为这两个区彼此靠近并且具有相同的惨杂类型。
[0068] 图 9示出形成 p +集电区 （216) 。 通过离子注入和退火形成 p +集电区 （216) 。
值得指出的是， p +集电区 （216) 的形成会部分地消耗 n缓冲区 （215) ， 但是不 会消耗 n +阴极区 （217) ， 因为其位于沟槽 （240) 的侧壁处。
[0069] 图 10示出在晶圆的背面形成集电极 （222) 。 首先， 移除硬掩模 （232) 。 接着 在晶圆的背面淀积金属层以形成集电极 （222) 。 通常可以通过湿法蚀刻移除硬 掩模 （232) 。 可以通过溅镀、 蒸镀或电镀淀积金属层。
[0070] 图 11示出针对集电极 （222) 的可选的平坦化步骤。 可以在金属淀积之后可选 地执行平坦化。 平坦化是机械研磨或化学机械抛光或机械研磨之后化学机械抛 光。 平滑的背面表面有利于封装， 因为其可以减少封装过程中芯片背面的空隙
[0071] 图 12示出在晶圆的正面形成发射极 （220) 。 首先， 对层间电介质 （230) 进行 图案化。 接着在正面淀积金属层以形成发射极 （220) 。 在那之后， 可以执行合 金退火以减小发射极 （220) 的接触电阻。
[0072] 最后， 值得指出的是， 所述制造方法与器件的元胞结构无关， 因为元胞是在处 理背面之前形成的。 因此， 虽然使用器件 200作为实例说明了所述制造方法， 但 是相同的方法也适用于器件 300。

Claims

权利要求书
[权利要求 1] 一种逆导绝缘栅双极型晶体管结构， 其特征在于， 其包括有:
位于正面处顶部的发射极 （220/320) ，
在所述发射极 （220/320) 下的多个元胞结构，
在所述元胞结构下的第一导电类型的漂移区 （214/314) ，
在背面处的集电极 （222/322) ，
一个以上的沟槽 （240/340) ， 所述的沟槽 （240/340) 在所述背面处 并且被所述集电极 （222/322) 充满，
在所述沟槽 （240/340) 之间的机械支撑半导体区 （241/341) ， 第二导电类型的集电区 （216/316) ， 所述第二导电类型的集电区 （2 16/316) 在每个沟槽 （240/340) 的顶部并且连接到所述集电极 （222/ 322) ，
第一导电类型的缓冲区 （215/315) ， 所述第一导电类型的缓冲区 （2 15/315) 在每个第二导电类型的集电区 （216/316) 的顶部并且在所述 第一导电类型的漂移区 （214/314) 下方， 所述的第一导电类型的缓 冲区 （215/315) 将漂移区 （214/314) 和集电区 （216/316) 隔幵； 第一导电类型的阴极区 （217/317) ， 所述第一导电类型的阴极区 (2 17/317) 作为在每个沟槽 （240/340) 侧壁处的机械支撑半导体区 （24 1/341) 的一部分并且连接到所述集电极 （222/322) 。
[权利要求 2] 根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 所述的元胞结构包括有：
第二导电类型的基区 （213) ， 所述第二导电类型的基区 （213) 在所 述第一导电类型的漂移区 （214) 的顶部，
第一导电类型的发射区 （211) ， 所述第一导电类型的发射区 （211) 所述第二导电类型的基区 （213) 接触并且连接到所述发射极 （220) 第二导电类型的扩散区 （212) ， 所述第二导电类型的扩散区 （212) 下方和所述的第二导电类型的基区 （213) 接触并在上方两侧和所述 的第一导电类型的发射区 （211) 接触， 所述的第二导电类型的扩散 区 （212) 上方还和所述的发射极 （220) 接触并将所述第二导电类型 的基区 （213) 连接到所述发射极 （220) ，
栅电介质 （231) ， 所述栅电介质覆盖所述第二导电类型的基区 （213 ) 的侧壁表面并且因此在所述第一导电类型的发射区 （211) 与所述 第一导电类型的漂移区 （214) 之间形成沟道，
沟槽式栅电极 （221) ， 所述沟槽式栅电极 （221) 被所述栅电介质 ( 231) 包围，
层间电介质 （230) ， 所述层间电介质 （230) 隔离所述栅电极 （221 ) 和所述发射极 （220) 。
[权利要求 3] 根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 所述的元胞结构包括有：
第二导电类型的基区 （313) ， 所述第二导电类型的基区 （313) 位于 所述的第一导电类型的漂移区 （314) 的上方并和所述漂移区 （314) 的上表面接触，
第一导电类型的发射区 （311) ， 所述第一导电类型的发射区 （311) 和所述第二导电类型的基区 （313) 的上表面接触并且连接到所述发 射极 （320) ，
第二导电类型的扩散区 （312) ， 所述第二导电类型的扩散区 （312) 分别与所述的发射极 （320) 和第二导电类型的基区 （313) 接触， 将 所述基区 （313) 连接到所述发射极 （320) ，
栅电介质 （331) ， 所述栅电介质 （331) 覆盖所述第二导电类型的基 区 （313) 的上表面并且因此在所述发射区 （311) 与所述第一导电类 型的漂移区 （314) 之间形成沟道，
栅电极 （321) ， 所述栅电极 （321) 在所述栅电介质 （331) 的顶部 层间电介质 （330) ， 所述层间电介质隔离所述栅电极 （321) 和所述 发射极 （320) 。 根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 其中所述第一导电类型的漂移区 214/314) 具有从 1x10 cm -3到 1x10 15 cm 3的惨杂浓度以及 30 μηι与 400 μηι之间的长度。
根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 其中所述沟槽 （240/340) 具有圆形顶视图。
根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 其中所述沟槽 （240/340) 具有六边形顶视图。
根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 其中所述第一导电类型的缓冲区 （215/315) 的惨杂浓度比所述第一 导电类型的漂移区 （214/314) 的惨杂浓度高， 所述第一导电类型的 缓冲区 （215/315) 的长度比所述第一导电类型的漂移区 （214/314) 的长度短。
根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 其中所述第二导电类型的集电区 （216/316) 具有 1x10 18cm 3到 1x10 21 cm -3的惨杂浓度以及 0.1 μηι与 1 μηι之间的深度。
根据权利要求 1所述的逆导绝缘栅双极型晶体管结构， 其特征在于， 其中所述第一导电类型的阴极区 （217/317) 具有 1x10 19 cm -3到 1x10 21 cm -3的惨杂浓度。
一种制造 RC-IGBT结构的方法， 其特征在于， 其包括有如下步骤： 以衬底晶圆幵始，
在所述晶圆的正面形成多个元胞结构，
使用硬掩模 （232) 在所述晶圆的背面形成一个以上沟槽 （240/340) 并且同吋形成第一导电类型的漂移区 （214/314) ，
在每个沟槽 （240/340) 的顶部形成第一导电类型的缓冲区 （215/315
) 并且在每个沟槽的侧壁形成第一导电类型的阴极区 （217/317) ， 在所述第一导电类型的缓冲区 （215/315) 下形成第二导电类型的集 电区 （216/316) ，
移除所述硬掩模 （232) ， 在所述晶圆的所述背面形成集电极 （222/322) ，
在所述晶圆的所述正面形成发射极 （220/320) 。
[权利要求 11] 根据权利要求 10所述的制造方法， 其特征在于， 其中通过扩散同吋形 成所述第一导电类型的缓冲区 （215/315) 和所述第一导电类型的阴 极区 （217/317) 。
[权利要求 12] 根据权利要求 10所述的制造方法， 其特征在于， 其中通过扩散形成所 述第一导电类型的缓冲区 （215/315) ， 且接着通过倾斜离子注入和 退火形成所述第一导电类型的阴极区 （217/317) 。
[权利要求 13] 根据权利要求 10所述的制造方法， 其特征在于， 其中通过扩散形成所 述第一导电类型的阴极区 （217/317) ， 且接着通过硅各向异性蚀刻 和随后扩散来形成所述第一导电类型的缓冲区 （215/315) 。
[权利要求 14] 根据权利要求 10所述的制造方法， 其特征在于， 其中通过淀积金属层 形成所述集电极 （222/320) 。
[权利要求 15] 根据权利要求 10所述的制造方法， 其特征在于， 其中通过淀积金属层 且接着执行平坦化来形成所述集电极 （222/320) 。
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