WO2018008140A1 - Pulse-width correction circuit - Google Patents
Pulse-width correction circuit Download PDFInfo
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- WO2018008140A1 WO2018008140A1 PCT/JP2016/070220 JP2016070220W WO2018008140A1 WO 2018008140 A1 WO2018008140 A1 WO 2018008140A1 JP 2016070220 W JP2016070220 W JP 2016070220W WO 2018008140 A1 WO2018008140 A1 WO 2018008140A1
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- output signal
- time
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- high level
- pulse width
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
Definitions
- the present invention relates to a pulse width correction circuit that corrects the pulse width of an input signal.
- pulse width the pulse period when the pulse level is not specified
- low-level pulse width the low-level pulse period
- high-level pulse period the high-level pulse period
- Patent Document 1 discloses a first divide-by-2 circuit that divides an input signal by two at the rising timing in order to eliminate a decrease in pulse width, and a falling edge of the input signal.
- a second frequency divider that divides the frequency by two at the same timing; a delay element that delays one of the output signal of the first frequency divider and the output signal of the second frequency divider by a predetermined time; The other of the output signal of the first divide-by-2 and the output signal of the second divide-by-2 and the output signal of the delay element are input, and the high-level pulse width or low-level pulse width is the delay element.
- a pulse width correction circuit including a logic circuit that outputs an output signal corrected in a direction that becomes wider by the delay time is described.
- the delay element delays only one of the output signal of the first 1 ⁇ 2 divider and the output signal of the second divide-by-2. For this reason, only one of the high level pulse width and the low level pulse width can be corrected.
- the pulse width correction circuit described in Japanese Patent Application Laid-Open No. 2006-67414 is a correction for widening the pulse width even when the high level pulse width of the input signal is sufficiently long when correcting the high level pulse width. I do. Therefore, there is a problem that the low level period from the end of the high level pulse to the next high level pulse is shortened and the low level period necessary for the operation of the output destination circuit is not satisfied.
- the pulse width correction circuit described in Japanese Patent Application Laid-Open No. 2006-67414 widens the pulse width even when the low level pulse width of the input signal is sufficiently long when correcting the low level pulse width. Make corrections. Therefore, there is a problem that the high level period from the end of the low level pulse to the next low level pulse is shortened and the high level period necessary for the operation of the output destination circuit is not satisfied.
- the present invention has been made to solve the above-described problem, and can correct both the low-level pulse width and the high-level pulse width, and can secure a period from the end of the pulse to the next pulse.
- An object is to provide a circuit.
- the pulse width correction circuit of the present invention is a circuit that generates an output signal by correcting the pulse width of an input signal, and includes a fixed portion and a release portion.
- the fixing unit fixes the output signal to a high level when the input signal changes from a low level to a high level after a state in which the output signal is at a low level has passed for a first time or more, and the output signal is When the input signal changes from the high level to the low level after the first time has elapsed for the high level state, the output signal is fixed to the low level.
- the release unit releases the fixed output signal when a second time has elapsed after the output signal is fixed.
- both high-level and low-level input signal pulses are corrected to output signals having a pulse width of the second time if they have a pulse width of less than the second time. For this reason, it is possible to suppress the disappearance of the pulse in the subsequent circuit. Further, when the input signal has a pulse width of the second time or more, the output signal is generated without correcting the pulse width. For this reason, a period from the end of the pulse to the next pulse can be secured.
- FIG. 1 is a diagram showing a configuration of a pulse width correction circuit according to an embodiment of the present invention.
- the pulse width correction circuit 1 corrects the pulse width of the input signal S_IN and outputs an output signal S_OUT.
- the pulse width correction circuit 1 includes a fixed unit 10 and a release unit 20.
- the fixing unit 10 receives an input signal S_IN and outputs an output signal S_OUT. At this time, the fixing unit 10 sets the output signal S_OUT to the high level when the input signal S_IN changes from the low level to the high level after the state in which the output signal S_OUT is the low level has elapsed for a predetermined time (first time) or longer. To fix. In addition, the fixing unit 10 changes the output signal S_OUT to the low level when the input signal S_IN changes from the high level to the low level after the output signal S_OUT is in the high level for a predetermined time (first time) or more. Fix it.
- the fixing unit 10 fixes the output signal S_OUT to the high level, the fixing unit 10 continues to output the high level output signal S_OUT regardless of the level of the input signal S_IN. Similarly, while the fixing unit 10 fixes the output signal S_OUT to the low level, the fixing unit 10 continues to output the low-level output signal S_OUT regardless of the level of the input signal S_IN.
- the releasing unit 20 releases the fixing of the level of the output signal S_OUT by the fixing unit 10 when a predetermined fixing time (corresponding to the second time) has elapsed since the fixing unit 10 fixed the level of the output signal S_OUT. .
- the fixing unit 10 outputs the output signal S_OUT corresponding to the level of the input signal S_IN. That is, the fixing unit 10 outputs the high-level output signal S_OUT when the input signal S_IN is at the high level at the timing when the output signal S_OUT is unfixed, and the input signal at the timing at which the output signal S_OUT is unfixed.
- S_IN is at a low level
- a low-level output signal S_OUT is output.
- the fixing unit 10 continues to fix the output signal S_OUT for a fixed time, for example, after the input signal S_IN changes from a low level to a high level, the input signal S_IN remains at a high level until the fixed time elapses. Even when the output level changes from low to low, an output signal S_OUT in which the high level continues for a fixed time is output. Similarly, even when the input signal S_IN changes from the low level to the high level after the input signal S_IN changes from the high level to the low level and before the fixed time elapses, the output in which the low level continues for the fixed time. A signal S_OUT is output. That is, when the pulse width of the input signal S_IN is less than the fixed time, the fixing unit 10 generates and outputs an output signal S_OUT in which the pulse width is extended to the fixed time.
- the fixed time is set to the minimum value of the pulse width at which the pulse does not disappear in the subsequent circuit of the pulse width correction circuit 1 or a value larger than the minimum value.
- the fixed time is 1 ⁇ 2 or less of the shortest pulse period (the period from the start of the pulse to the start of the next pulse) according to the specifications of the input signal S_IN.
- the output signal S_OUT subjected to the correction for expanding the pulse width it is possible to ensure 1/2 or more of the pulse period as the period from the end of the pulse to the next pulse.
- the fixing is released after a fixed time has elapsed since the fixing unit 10 started fixing the output signal S_OUT. Therefore, for example, when the input signal S_IN changes from the high level to the low level after a fixed time has elapsed since the input signal S_IN changed from the low level to the high level, the fixing of the output signal S_OUT is released. Changes the level of the output signal S_OUT from the high level to the low level in accordance with the level of the input signal S_IN.
- the fixing unit 10 when the pulse width of the input signal S_IN is equal to or longer than the fixed time, the fixing unit 10 outputs the output signal S_OUT having the same pulse width as the pulse width of the input signal S_IN. Thereby, it is possible to prevent the period from the end of the pulse to the next pulse from being shortened.
- the fixed unit 10 includes an OR circuit 101, an AND circuit 102, and a selector 103.
- the release unit 20 includes a delay element 201.
- OR circuit 101 receives input signal S_IN and output signal S_OUT as inputs, and outputs output signal S 1 to selector 103.
- the AND circuit 102 receives the input signal S_IN and the output signal S_OUT as inputs, and outputs the output signal S2 to the selector 103.
- the selector 103 receives the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 as inputs, and outputs one of the output signals S1 and S2 as the output signal S_OUT. Specifically, the selector 103 receives the output signal S3 of the delay element 201 as a switching signal, and when the switching signal is at a low level, outputs the output signal S1 of the OR circuit 101 as the output signal S_OUT, and the switching signal is high. In the case of the level, the output signal S2 of the AND circuit 102 is output as the output signal S_OUT.
- the delay element 201 is connected to the output terminal of the selector 103, and outputs to the selector 103 an output signal S3 obtained by delaying the output signal S_OUT, which is the output of the selector 103, by the fixed time.
- the delay time (that is, the fixed time) of the delay element 201 is, for example, 7 ⁇ s.
- the operation example 1 is an example in which the input signal S_IN to be input is constantly at a low level. Specifically, an example in which an input signal S_IN having a high level pulse width shorter than the fixed time is input in a state where the low level output signal S_OUT has passed for a predetermined time (same as the fixed time in this embodiment) or more. is there.
- FIG. 2 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 1.
- T represents a fixed time
- W0 represents a pulse width
- P0 represents a pulse period. The same applies to FIGS. 3 to 6.
- the output signal S3 of the delay element 201 is also low level (denoted L in the figure), and the selector 103
- the output signal S1 of the OR circuit 101 is output as the output signal S_OUT. Therefore, at time t1, when the input signal S_IN changes from low level to high level (denoted as H in the figure) and the output signal S1 of the OR circuit 101 changes from low level to high level, the selector 103 outputs the output signal S_OUT. Is changed from low level to high level. At this time, since both the input signal S_IN and the output signal S_OUT change from the low level to the high level, the output signal S2 of the AND circuit 102 also changes from the low level to the high level.
- the input signal S_IN changes from the high level to the low level.
- the output signal S2 of the AND circuit 102 changes from the high level to the low level in accordance with the change of the input signal S_IN, but the output signal S1 of the OR circuit 101 maintains the high level by the high level output signal S_OUT.
- the output signal S3 of the delay element 201 is low. The level is maintained. Therefore, the selector 103 continues to output the high level output signal S1 of the OR circuit 101 as the output signal S_OUT.
- the output signal S3 of the delay element 201 changes from low level to high level.
- the selector 103 outputs the output signal S2 of the AND circuit 102 as the output signal S_OUT.
- the output signal S2 of the AND circuit 102 changes from the high level to the low level in accordance with the change of the input signal S_IN at time t2. Therefore, the selector 103 changes the output signal S_OUT from the high level to the low level at time t3.
- the output signal S1 of the OR circuit 101 also changes from the high level to the low level.
- the output signal S_OUT is fixed to the high level at the time t2, which is the falling timing of the input signal S_IN, and the fixed time T
- the output signal S_OUT falls at time t3 when elapses.
- an output signal S_OUT having a high level pulse width of a fixed time T is output.
- the selector 103 outputs the output signal S1 of the OR circuit 101 as the output signal S_OUT. Since the output signal S1 of the OR circuit 101 changes to the low level at time t3, the selector 103 continues to output the low level output signal S_OUT even after the output signal S3 of the delay element 201 changes. .
- the input signal S_IN changes from the low level to the high level according to the next pulse.
- the fixed time T is set to 1 ⁇ 2 or less of the pulse period P0 (period from time t1 to time t5)
- the period from time t3 to time t5 when the output signal S_OUT changes to the low level is The fixed time T or longer. That is, at time t5, similarly to time t1, the low level output signal S_OUT has passed for a fixed time T or longer, and the output signal S3 of the delay element 201 is also at low level.
- the selector 103 changes the output signal S_OUT from low level to high level. Change. That is, the rise of the pulse of the input signal S_IN can be reflected in the output signal S_OUT.
- the operation example 2 is an example in which the input signal S_IN is constantly at a high level. Specifically, in this example, the input signal S_IN having a low level pulse width shorter than the fixed time is input in a state where the high level output signal S_OUT has passed for a predetermined time (same as the fixed time in this embodiment). .
- FIG. 3 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 2.
- the output signal S ⁇ b> 3 of the delay element 201 is also high level, and the selector 103 outputs the output signal of the AND circuit 102.
- S2 is output as an output signal S_OUT. Therefore, at time t6, when the input signal S_IN changes from high level to low level and the output signal S2 of the AND circuit 102 changes from high level to low level, the selector 103 changes the output signal S_OUT from high level to low level. Change. At this time, since both the input signal S_IN and the output signal S_OUT change from the high level to the low level, the output signal S1 of the OR circuit 101 also changes from the high level to the low level.
- the input signal S_IN changes from the low level to the high level.
- the output signal S1 of the OR circuit 101 changes from the low level to the high level in accordance with the change of the input signal S_IN, but the output signal S2 of the AND circuit 102 maintains the low level by the low level output signal S_OUT.
- the output signal S3 of the delay element 201 is at the high level. Is maintained. Therefore, the selector 103 continues to output the low level output signal S2 of the AND circuit as the output signal S_OUT.
- the output signal S3 of the delay element 201 changes from high level to low level.
- the selector 103 outputs the output signal S1 of the OR circuit 101 as the output signal S_OUT.
- the output signal S1 of the OR circuit 101 changes from the low level to the high level in accordance with the change of the input signal S_IN at time t7. Therefore, the selector 103 changes the output signal S_OUT from the low level to the high level at time t8.
- the output signal S2 of the AND circuit 102 also changes from the low level to the high level.
- the output signal S_OUT is fixed to the low level at the time t7 which is the rising timing of the input signal S_IN, and the fixed time T is The output signal S_OUT rises at the elapsed time t8. As a result, an output signal S_OUT having a low level pulse width for a fixed time T is output.
- the selector 103 outputs the output signal S2 of the AND circuit 102 as the output signal S_OUT. Since the output signal S2 of the AND circuit 102 changes to high level at time t8, the selector 103 continues to output the high level output signal S_OUT even after the output signal S3 of the delay element 201 changes. .
- the input signal S_IN changes from the high level to the low level according to the next pulse.
- the fixed time T is set to 1 ⁇ 2 or less of the pulse period P0 (period from time t6 to time t10)
- the period from time t8 to time t10 when the output signal S_OUT changes to high level is The fixed time T or longer. That is, at time t10, the high level output signal S_OUT is in a state where the fixed time T or more has elapsed, and the output signal S3 of the delay element 201 is also at the high level.
- the selector 103 changes the output signal S_OUT from high level to low level. Change. That is, the falling edge of the pulse of the input signal S_IN can be reflected in the output signal S_OUT.
- the operation example 3 is an example in which an input signal S_IN having a high level pulse width longer than a fixed time is input in a state where a low level output signal S_OUT has passed for a predetermined time (same as the fixed time in the present embodiment).
- FIG. 4 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 3.
- the output signal S3 of the delay element 201 changes from low level to high level.
- the output signal S_OUT which is the output of the selector 103, is switched from the output signal S1 of the OR circuit 101 to the output signal S2 of the AND circuit 102.
- both the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 change from the low level to the high level at time t11 and this state continues at time t12, the output signal at time t12.
- the level of S_OUT does not change and the high level is maintained.
- the input signal S_IN changes from the high level to the low level.
- the output signal S2 of the AND circuit 102 changes from the high level to the low level in accordance with the change of the input signal S_IN.
- the selector 103 changes the output signal S_OUT from the high level to the low level in accordance with the change of the output signal S2.
- the output signal S1 of the OR circuit 101 also changes from the high level to the low level.
- the selector 103 matches the timing of rising and falling with the input signal S_IN and the output signal S_OUT. Therefore, the selector 103 outputs the output signal S_OUT having the same pulse width as the input signal S_IN without correcting the pulse width.
- the operation example 4 is an example in which the input signal S_IN having a low level pulse width longer than the fixed time is input in a state where the high level output signal S_OUT has passed for a predetermined time (same as the fixed time in this embodiment). .
- FIG. 5 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 4.
- the output signal S3 of the delay element 201 changes from high level to low level.
- the output signal S_OUT which is the output of the selector 103 is switched from the output signal S2 of the AND circuit 102 to the output signal S1 of the OR circuit 101.
- the output signal at time t16 since both the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 change from the high level to the low level at time t15, and this state continues at time t16, the output signal at time t16.
- the level of S_OUT does not change and the low level is maintained.
- the input signal S_IN changes from the low level to the high level.
- the selector 103 changes the output signal S_OUT from the low level to the high level.
- the output signal S2 of the AND circuit 102 also changes from the low level to the high level.
- the output signal S3 of the delay element 201 changes from low level to high level.
- the output signal S_OUT which is the output of the selector 103, is switched from the output signal S1 of the OR circuit 101 to the output signal S2 of the AND circuit 102.
- the level of the output signal S_OUT does not change at time t18. High level is maintained.
- the selector 103 matches the timings of falling and rising with the input signal S_IN and the output signal S_OUT. Therefore, the selector 103 outputs the output signal S_OUT having the same pulse width as the input signal S_IN without correcting the pulse width.
- the pulse width correction circuit 1 of the present embodiment has a fixed pulse width when the pulse width W0 is less than the fixed time T regardless of whether the pulse of the input signal S_IN is at a high level or a low level.
- An output signal S_OUT corrected at time T is output. That is, even if the pulse width of the input signal S_IN is less than the fixed time T, the output signal S_OUT corrected to a pulse width that does not disappear in the subsequent circuit is output, so that the disappearance of the pulse in the subsequent circuit is suppressed. it can.
- the pulse width correction circuit 1 When the pulse width of the input signal S_IN is equal to or longer than the fixed time T, the pulse width correction circuit 1 outputs an output signal S_OUT having the same pulse width as that of the input signal S_IN.
- FIG. 6 shows an output signal S_OUT according to the present embodiment when an input signal S_IN having a pulse width equal to or longer than a fixed time T is input, and an output in a comparison form to which the technique described in Japanese Patent Laid-Open No. 2006-67414 is applied. It is a figure which shows the comparison with signal S_OUT.
- the pulse width correction circuit 1 can increase the period from the end of a pulse having a pulse width equal to or longer than the fixed time T to the next pulse as compared with the comparative example, and the operation of the subsequent circuit can be increased. It becomes easy to secure the necessary period.
- Japanese Patent Laid-Open No. 2006-67414 two flip-flops are used to widen the pulse width.
- Japanese Patent Laid-Open No. 2009-253951 Patent Document 2 uses a voltage controlled oscillator for correcting the pulse width.
- the pulse width correction circuit 1 of the present embodiment corrects the pulse width by the OR circuit 101, the AND circuit 102, the selector 103, and the delay element 201 shown in FIG. Therefore, the circuit area of the pulse width correction circuit 1 of the present embodiment can be reduced as compared with Japanese Patent Application Laid-Open Nos. 2006-67414 and 2009-253951.
- the circuit area of the pulse width correction circuit 1 of this embodiment using the delay element 201 with a delay time (fixed time) of 7 ⁇ s is about 633 ⁇ m 2 .
- the circuit area is increased by about 350 ⁇ m 2 . That is, compared with the pulse width correction circuit 1 of this embodiment, the circuit area is 1.5 times in the comparative embodiment.
- the circuit scale of the voltage controlled oscillator described in Japanese Patent Laid-Open No. 2009-253951 is much larger than the circuit area of the pulse width correction circuit 1 of the present embodiment.
- the fixed unit 10 includes the OR circuit 101, the AND circuit 102, and the selector 103.
- the fixed unit 10 may, for example, after the output signal S_OUT is at a low level after a predetermined time has elapsed.
- the input signal S_IN changes from the low level to the high level
- the output signal S_OUT is fixed to the high level
- the input signal S_IN is changed from the high level to the low level after a predetermined time has elapsed after the output signal S_OUT is in the high level state.
- the storage unit stores a program for releasing the fixation of the output signal S_OUT in response to an instruction from the release unit 20, and a processor that executes the program It may be comprised.
- the release unit 20 includes the delay element 201.
- the release unit 20 is connected to the fixed unit 10 after a fixed time has elapsed since the fixing unit 10 started fixing the output signal S_OUT. You may be comprised by the memory
- the predetermined time (first time) during which the output signal S_OUT is kept at the low level or the high level, which is determined as a condition for the fixing unit 10 to fix the output signal S_OUT, is fixed. It was the same as the time (second time). However, when the fixing unit 10 and the releasing unit 20 are configured by a storage unit and a processor that store programs, the predetermined time (first time) and the fixed time (second time) may be different.
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Abstract
A pulse-width correction circuit (1) comprising: a fixing unit (10) that fixes an output signal S_OUT at a high level if, after a state in which the output signal S_OUT is low-level has continued for a first period of time, an input signal S_IN changes from low level to high level, and that fixes the output signal S_OUT at a low level if, after a state in which the output signal S_OUT is high-level has continued for a prescribed period of time, the input signal S_IN changes from high level to low level; and a releasing unit (20) that releases the fixed output signal S_OUT after the output signal S_OUT being fixed has continued for a second period of time.
Description
本発明は、入力された信号のパルス幅を補正するパルス幅補正回路に関する。
The present invention relates to a pulse width correction circuit that corrects the pulse width of an input signal.
信号が回路を通過するとき、入力信号に対する出力信号の立上がりの遅延時間と、入力信号に対する出力信号の立下がりの遅延時間との間でずれが生じることがある。このため、多段に接続された回路を信号が通過した場合、信号のハイレベルまたはローレベルのパルスの期間が徐々に減少し、データの消失が起こりうる。
When the signal passes through the circuit, there may be a difference between the delay time of the rise of the output signal with respect to the input signal and the delay time of the fall of the output signal with respect to the input signal. For this reason, when a signal passes through a circuit connected in multiple stages, the period of high-level or low-level pulse of the signal gradually decreases, and data loss may occur.
なお、以下では、パルスのレベルを特定しない場合のパルスの期間を「パルス幅」とし、ローレベルのパルスの期間を「ローレベルパルス幅」とし、ハイレベルのパルスの期間を「ハイレベルパルス幅」とする。
In the following, the pulse period when the pulse level is not specified is referred to as “pulse width”, the low-level pulse period as “low-level pulse width”, and the high-level pulse period as “high-level pulse width”. "
特開2006-67414号公報(特許文献1)には、パルス幅の減少を解消するために、入力信号を立上がりのタイミングで2分周する第1の2分周器と、入力信号を立下がりのタイミングで2分周する第2の2分周器と、第1の2分周器の出力信号および第2の2分周器の出力信号のうちの一方を所定時間遅延する遅延素子と、第1の2分周器の出力信号および第2の2分周器の出力信号のうちの他方と遅延素子の出力信号とをその入力とし、ハイレベルパルス幅もしくはローレベルパルス幅が、遅延素子の遅延時間の分だけ広くなる方向に補正された出力信号を出力する論理回路とを備えたパルス幅補正回路が記載されている。
Japanese Patent Laid-Open No. 2006-67414 (Patent Document 1) discloses a first divide-by-2 circuit that divides an input signal by two at the rising timing in order to eliminate a decrease in pulse width, and a falling edge of the input signal. A second frequency divider that divides the frequency by two at the same timing; a delay element that delays one of the output signal of the first frequency divider and the output signal of the second frequency divider by a predetermined time; The other of the output signal of the first divide-by-2 and the output signal of the second divide-by-2 and the output signal of the delay element are input, and the high-level pulse width or low-level pulse width is the delay element. A pulse width correction circuit including a logic circuit that outputs an output signal corrected in a direction that becomes wider by the delay time is described.
しかしながら、特開2006-67414号公報に記載の技術では、遅延素子は、第1の2分周器の出力信号および第2の2分周器の出力信号のうちの一方のみを遅延する。そのため、ハイレベルパルス幅およびローレベルパルス幅のいずれか一方しか補正できない。
However, in the technique described in Japanese Patent Laid-Open No. 2006-67414, the delay element delays only one of the output signal of the first ½ divider and the output signal of the second divide-by-2. For this reason, only one of the high level pulse width and the low level pulse width can be corrected.
また、特開2006-67414号公報に記載のパルス幅補正回路は、ハイレベルパルス幅の補正を行う場合、入力信号のハイレベルパルス幅が十分に長いときであっても、パルス幅を広げる補正を行う。そのため、当該ハイレベルのパルス終了から次のハイレベルのパルスまでのローレベルの期間が短くなり、出力先の回路の動作に必要なローレベル期間を満たさなくなるという問題がある。同様に、特開2006-67414号公報に記載のパルス幅補正回路は、ローレベルパルス幅の補正を行う場合、入力信号のローレベルパルス幅が十分に長いときであっても、パルス幅を広げる補正を行う。そのため、当該ローレベルのパルス終了から次のローレベルのパルスまでのハイレベルの期間が短くなり、出力先の回路の動作に必要なハイレベル期間を満たさなくなるという問題がある。
Further, the pulse width correction circuit described in Japanese Patent Application Laid-Open No. 2006-67414 is a correction for widening the pulse width even when the high level pulse width of the input signal is sufficiently long when correcting the high level pulse width. I do. Therefore, there is a problem that the low level period from the end of the high level pulse to the next high level pulse is shortened and the low level period necessary for the operation of the output destination circuit is not satisfied. Similarly, the pulse width correction circuit described in Japanese Patent Application Laid-Open No. 2006-67414 widens the pulse width even when the low level pulse width of the input signal is sufficiently long when correcting the low level pulse width. Make corrections. Therefore, there is a problem that the high level period from the end of the low level pulse to the next low level pulse is shortened and the high level period necessary for the operation of the output destination circuit is not satisfied.
本発明は、上記課題を解決するためになされたものであって、ローレベルパルス幅およびハイレベルパルス幅のいずれも補正でき、かつ、パルス終了から次のパルスまでの期間を確保できるパルス幅補正回路を提供することを目的とする。
The present invention has been made to solve the above-described problem, and can correct both the low-level pulse width and the high-level pulse width, and can secure a period from the end of the pulse to the next pulse. An object is to provide a circuit.
本発明のパルス幅補正回路は、入力信号のパルス幅を補正して出力信号を生成する回路であって、固定部と解除部とを備える。
The pulse width correction circuit of the present invention is a circuit that generates an output signal by correcting the pulse width of an input signal, and includes a fixed portion and a release portion.
固定部は、前記出力信号がローレベルである状態が第1時間以上経過した後に前記入力信号がローレベルからハイレベルに変化した場合に、前記出力信号をハイレベルに固定し、前記出力信号がハイレベルである状態が前記第1時間以上経過した後に前記入力信号がハイレベルからローレベルに変化した場合に、前記出力信号をローレベルに固定する。解除部は、前記出力信号が固定された後に第2時間経過したときに、固定された前記出力信号を解除する。
The fixing unit fixes the output signal to a high level when the input signal changes from a low level to a high level after a state in which the output signal is at a low level has passed for a first time or more, and the output signal is When the input signal changes from the high level to the low level after the first time has elapsed for the high level state, the output signal is fixed to the low level. The release unit releases the fixed output signal when a second time has elapsed after the output signal is fixed.
本発明によれば、ハイレベルおよびローレベルのいずれの入力信号のパルスについても、第2時間未満のパルス幅を有する場合には第2時間のパルス幅の出力信号に補正される。このため、後段の回路におけるパルスの消失を抑制できる。また、入力信号が第2時間以上のパルス幅を有する場合には、パルス幅が補正されることなく出力信号が生成される。このため、パルス終了から次のパルスまでの期間を確保できる。
According to the present invention, both high-level and low-level input signal pulses are corrected to output signals having a pulse width of the second time if they have a pulse width of less than the second time. For this reason, it is possible to suppress the disappearance of the pulse in the subsequent circuit. Further, when the input signal has a pulse width of the second time or more, the output signal is generated without correcting the pulse width. For this reason, a period from the end of the pulse to the next pulse can be secured.
以下、本発明の実施の形態について、図面を参照しながら詳細に説明する。なお、図中同一又は相当部分には同一符号を付してその説明は繰返さない。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
(装置の構成)
図1は、本発明の実施の形態に係るパルス幅補正回路の構成を示す図である。パルス幅補正回路1は、入力信号S_INのパルス幅の補正を行い、出力信号S_OUTを出力する。パルス幅補正回路1は、固定部10と解除部20とを備える。 (Device configuration)
FIG. 1 is a diagram showing a configuration of a pulse width correction circuit according to an embodiment of the present invention. The pulsewidth correction circuit 1 corrects the pulse width of the input signal S_IN and outputs an output signal S_OUT. The pulse width correction circuit 1 includes a fixed unit 10 and a release unit 20.
図1は、本発明の実施の形態に係るパルス幅補正回路の構成を示す図である。パルス幅補正回路1は、入力信号S_INのパルス幅の補正を行い、出力信号S_OUTを出力する。パルス幅補正回路1は、固定部10と解除部20とを備える。 (Device configuration)
FIG. 1 is a diagram showing a configuration of a pulse width correction circuit according to an embodiment of the present invention. The pulse
固定部10は、入力信号S_INの入力を受け付け、出力信号S_OUTを出力する。このとき、固定部10は、出力信号S_OUTがローレベルである状態が所定時間(第1時間)以上経過した後に入力信号S_INがローレベルからハイレベルに変化した場合に、出力信号S_OUTをハイレベルに固定する。また、固定部10は、出力信号S_OUTがハイレベルである状態が所定時間(第1時間)以上経過した後に入力信号S_INがハイレベルからローレベルに変化した場合に、出力信号S_OUTをローレベルに固定する。
The fixing unit 10 receives an input signal S_IN and outputs an output signal S_OUT. At this time, the fixing unit 10 sets the output signal S_OUT to the high level when the input signal S_IN changes from the low level to the high level after the state in which the output signal S_OUT is the low level has elapsed for a predetermined time (first time) or longer. To fix. In addition, the fixing unit 10 changes the output signal S_OUT to the low level when the input signal S_IN changes from the high level to the low level after the output signal S_OUT is in the high level for a predetermined time (first time) or more. Fix it.
固定部10が出力信号S_OUTをハイレベルに固定している間、固定部10は、入力信号S_INのレベルにかかわらず、ハイレベルの出力信号S_OUTを出力し続ける。同様に、固定部10が出力信号S_OUTをローレベルに固定している間、固定部10は、入力信号S_INのレベルにかかわらず、ローレベルの出力信号S_OUTを出力し続ける。
While the fixing unit 10 fixes the output signal S_OUT to the high level, the fixing unit 10 continues to output the high level output signal S_OUT regardless of the level of the input signal S_IN. Similarly, while the fixing unit 10 fixes the output signal S_OUT to the low level, the fixing unit 10 continues to output the low-level output signal S_OUT regardless of the level of the input signal S_IN.
解除部20は、固定部10が出力信号S_OUTのレベルを固定してから所定の固定時間(第2時間に対応する)経過したときに、固定部10による出力信号S_OUTのレベルの固定を解除する。固定部10による出力信号S_OUTのレベルの固定が解除されることにより、固定部10は、入力信号S_INのレベルに応じた出力信号S_OUTを出力する。すなわち、固定部10は、出力信号S_OUTの固定が解除されたタイミングで入力信号S_INがハイレベルの場合にハイレベルの出力信号S_OUTを出力し、出力信号S_OUTの固定が解除されたタイミングで入力信号S_INがローレベルの場合にローレベルの出力信号S_OUTを出力する。
The releasing unit 20 releases the fixing of the level of the output signal S_OUT by the fixing unit 10 when a predetermined fixing time (corresponding to the second time) has elapsed since the fixing unit 10 fixed the level of the output signal S_OUT. . When the fixing of the level of the output signal S_OUT by the fixing unit 10 is released, the fixing unit 10 outputs the output signal S_OUT corresponding to the level of the input signal S_IN. That is, the fixing unit 10 outputs the high-level output signal S_OUT when the input signal S_IN is at the high level at the timing when the output signal S_OUT is unfixed, and the input signal at the timing at which the output signal S_OUT is unfixed. When S_IN is at a low level, a low-level output signal S_OUT is output.
このように、固定部10が固定時間だけ出力信号S_OUTの固定を継続するため、例えば入力信号S_INがローレベルからハイレベルに変化した後、固定時間経過するまでの間に入力信号S_INがハイレベルからローレベルに変化した場合であっても、ハイレベルが固定時間継続した出力信号S_OUTが出力される。同様に入力信号S_INがハイレベルからローレベルに変化した後、固定時間経過するまでの間に入力信号S_INがローレベルからハイレベルに変化した場合であっても、ローレベルが固定時間継続した出力信号S_OUTが出力される。すなわち、入力信号S_INのパルス幅が固定時間未満の場合、固定部10は、パルス幅を固定時間に広げた出力信号S_OUTを生成し出力する。
Thus, since the fixing unit 10 continues to fix the output signal S_OUT for a fixed time, for example, after the input signal S_IN changes from a low level to a high level, the input signal S_IN remains at a high level until the fixed time elapses. Even when the output level changes from low to low, an output signal S_OUT in which the high level continues for a fixed time is output. Similarly, even when the input signal S_IN changes from the low level to the high level after the input signal S_IN changes from the high level to the low level and before the fixed time elapses, the output in which the low level continues for the fixed time. A signal S_OUT is output. That is, when the pulse width of the input signal S_IN is less than the fixed time, the fixing unit 10 generates and outputs an output signal S_OUT in which the pulse width is extended to the fixed time.
ここで、固定時間は、パルス幅補正回路1の後段の回路でパルスが消失しないパルス幅の最小値または当該最小値よりも大きな値が設定される。これにより、入力信号S_INのパルス幅が固定時間未満であったとしても、後段の回路において消失しないパルス幅に補正された出力信号S_OUTが出力されるため、後段の回路でのパルスの消失を抑制できる。
Here, the fixed time is set to the minimum value of the pulse width at which the pulse does not disappear in the subsequent circuit of the pulse width correction circuit 1 or a value larger than the minimum value. As a result, even if the pulse width of the input signal S_IN is less than the fixed time, the output signal S_OUT corrected to a pulse width that does not disappear in the subsequent circuit is output, thereby suppressing the disappearance of the pulse in the subsequent circuit. it can.
さらに、固定時間は、入力信号S_INの仕様上最短のパルス周期(パルスの開始時から次のパルスの開始時までの期間)の1/2以下とすることが好ましい。これにより、パルス幅を広げる補正が行われた出力信号S_OUTにおいて、当該パルス終了から次のパルスまでの期間としてパルス周期の1/2以上を確保することができる。
Furthermore, it is preferable that the fixed time is ½ or less of the shortest pulse period (the period from the start of the pulse to the start of the next pulse) according to the specifications of the input signal S_IN. As a result, in the output signal S_OUT subjected to the correction for expanding the pulse width, it is possible to ensure 1/2 or more of the pulse period as the period from the end of the pulse to the next pulse.
また、上述したように、固定部10が出力信号S_OUTの固定を開始してから固定時間経過後に、当該固定が解除される。そのため、例えば入力信号S_INがローレベルからハイレベルに変化してから固定時間経過後に入力信号S_INがハイレベルからローレベルに変化した場合、出力信号S_OUTの固定が解除されているため、固定部10は、入力信号S_INのレベルに応じて、出力信号S_OUTのレベルもハイレベルからローレベルに変化させる。
Also, as described above, the fixing is released after a fixed time has elapsed since the fixing unit 10 started fixing the output signal S_OUT. Therefore, for example, when the input signal S_IN changes from the high level to the low level after a fixed time has elapsed since the input signal S_IN changed from the low level to the high level, the fixing of the output signal S_OUT is released. Changes the level of the output signal S_OUT from the high level to the low level in accordance with the level of the input signal S_IN.
同様に、入力信号S_INがハイレベルからローハイレベルに変化してから固定時間経過後に入力信号S_INがローレベルからハイレベルに変化した場合、出力信号S_OUTの固定が解除されているため、固定部10は、入力信号S_INのレベルに応じて、出力信号S_OUTのレベルもローレベルからハイレベルに変化させる。
Similarly, when the input signal S_IN changes from the low level to the high level after the fixed time has elapsed after the input signal S_IN changes from the high level to the low high level, the fixing of the output signal S_OUT is released. Changes the level of the output signal S_OUT from the low level to the high level in accordance with the level of the input signal S_IN.
このように、入力信号S_INのパルス幅が固定時間以上の場合、固定部10は、入力信号S_INのパルス幅と同じパルス幅を有する出力信号S_OUTを出力する。これにより、パルス終了から次のパルスまでの期間が短くなることを防止できる。
Thus, when the pulse width of the input signal S_IN is equal to or longer than the fixed time, the fixing unit 10 outputs the output signal S_OUT having the same pulse width as the pulse width of the input signal S_IN. Thereby, it is possible to prevent the period from the end of the pulse to the next pulse from being shortened.
次に、固定部10および解除部20の具体的な構成について説明する。図1に示されるように、固定部10は、OR回路101と、AND回路102と、セレクタ103とを備える。また、解除部20は遅延素子201を備える。
Next, specific configurations of the fixing unit 10 and the release unit 20 will be described. As shown in FIG. 1, the fixed unit 10 includes an OR circuit 101, an AND circuit 102, and a selector 103. The release unit 20 includes a delay element 201.
OR回路101は、入力信号S_INおよび出力信号S_OUTを入力として受け、出力信号S1をセレクタ103に出力する。
OR circuit 101 receives input signal S_IN and output signal S_OUT as inputs, and outputs output signal S 1 to selector 103.
AND回路102は、入力信号S_INおよび出力信号S_OUTを入力として受け、出力信号S2をセレクタ103に出力する。
The AND circuit 102 receives the input signal S_IN and the output signal S_OUT as inputs, and outputs the output signal S2 to the selector 103.
セレクタ103は、OR回路101の出力信号S1およびAND回路102の出力信号S2を入力として受け、出力信号S1,S2のいずれかを出力信号S_OUTとして出力する。具体的には、セレクタ103は、遅延素子201の出力信号S3を切替信号として受け、切替信号がローレベルの場合に、OR回路101の出力信号S1を出力信号S_OUTとして出力し、切替信号がハイレベルの場合に、AND回路102の出力信号S2を出力信号S_OUTとして出力する。
The selector 103 receives the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 as inputs, and outputs one of the output signals S1 and S2 as the output signal S_OUT. Specifically, the selector 103 receives the output signal S3 of the delay element 201 as a switching signal, and when the switching signal is at a low level, outputs the output signal S1 of the OR circuit 101 as the output signal S_OUT, and the switching signal is high. In the case of the level, the output signal S2 of the AND circuit 102 is output as the output signal S_OUT.
遅延素子201は、セレクタ103の出力端子に接続され、セレクタ103の出力である出力信号S_OUTを上記の固定時間だけ遅延させた出力信号S3をセレクタ103に出力する。遅延素子201の遅延時間(つまり固定時間)は例えば7μsである。
The delay element 201 is connected to the output terminal of the selector 103, and outputs to the selector 103 an output signal S3 obtained by delaying the output signal S_OUT, which is the output of the selector 103, by the fixed time. The delay time (that is, the fixed time) of the delay element 201 is, for example, 7 μs.
(パルス幅補正回路の動作例1)
次に、パルス幅補正回路1の具体的な動作例1について説明する。動作例1は、入力される入力信号S_INが定常的にローレベルの例である。具体的には、ローレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間よりも短いハイレベルパルス幅を有する入力信号S_INが入力された例である。 (Operation example 1 of pulse width correction circuit)
Next, a specific operation example 1 of the pulsewidth correction circuit 1 will be described. The operation example 1 is an example in which the input signal S_IN to be input is constantly at a low level. Specifically, an example in which an input signal S_IN having a high level pulse width shorter than the fixed time is input in a state where the low level output signal S_OUT has passed for a predetermined time (same as the fixed time in this embodiment) or more. is there.
次に、パルス幅補正回路1の具体的な動作例1について説明する。動作例1は、入力される入力信号S_INが定常的にローレベルの例である。具体的には、ローレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間よりも短いハイレベルパルス幅を有する入力信号S_INが入力された例である。 (Operation example 1 of pulse width correction circuit)
Next, a specific operation example 1 of the pulse
図2は、動作例1における、入力信号S_IN、OR回路の出力信号S1、AND回路の出力信号S2、出力信号S_OUTおよび遅延素子201の出力信号S3のタイミングチャートである。図2において、Tは固定時間、W0はパルス幅、P0はパルス周期を示している。なお、図3から図6においても同様である。
FIG. 2 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 1. In FIG. 2, T represents a fixed time, W0 represents a pulse width, and P0 represents a pulse period. The same applies to FIGS. 3 to 6.
図2に示されるように、ローレベルの出力信号S_OUTが固定時間T以上経過した状態の時刻t1では、遅延素子201の出力信号S3もローレベル(図中Lと記す)であり、セレクタ103は、OR回路101の出力信号S1を出力信号S_OUTとして出力する。そのため、時刻t1において、入力信号S_INがローレベルからハイレベル(図中Hと記す)に変化し、OR回路101の出力信号S1がローレベルからハイレベルに変化すると、セレクタ103は、出力信号S_OUTをローレベルからハイレベルに変化させる。このとき、入力信号S_INおよび出力信号S_OUTの両方がローレベルからハイレベルに変化するため、AND回路102の出力信号S2もローレベルからハイレベルに変化する。
As shown in FIG. 2, at time t1 when the low level output signal S_OUT has passed for a fixed time T or longer, the output signal S3 of the delay element 201 is also low level (denoted L in the figure), and the selector 103 The output signal S1 of the OR circuit 101 is output as the output signal S_OUT. Therefore, at time t1, when the input signal S_IN changes from low level to high level (denoted as H in the figure) and the output signal S1 of the OR circuit 101 changes from low level to high level, the selector 103 outputs the output signal S_OUT. Is changed from low level to high level. At this time, since both the input signal S_IN and the output signal S_OUT change from the low level to the high level, the output signal S2 of the AND circuit 102 also changes from the low level to the high level.
次に、固定時間Tよりも短いパルス幅W0だけ経過した時刻t2において、入力信号S_INがハイレベルからローレベルに変化する。このとき、入力信号S_INの変化に合わせて、AND回路102の出力信号S2がハイレベルからローレベルに変化するが、OR回路101の出力信号S1は、ハイレベルの出力信号S_OUTによりハイレベルを維持する。また、時刻t2では、出力信号S_OUTがローレベルからハイレベルに変化した時刻t1より固定時間T(つまり、遅延素子201の遅延時間)が経過していないため、遅延素子201の出力信号S3はローレベルを維持している。そのため、セレクタ103は、OR回路101のハイレベルの出力信号S1を出力信号S_OUTとして出力し続ける。
Next, at time t2 when a pulse width W0 shorter than the fixed time T has elapsed, the input signal S_IN changes from the high level to the low level. At this time, the output signal S2 of the AND circuit 102 changes from the high level to the low level in accordance with the change of the input signal S_IN, but the output signal S1 of the OR circuit 101 maintains the high level by the high level output signal S_OUT. To do. At time t2, since the fixed time T (that is, the delay time of the delay element 201) has not elapsed from time t1 when the output signal S_OUT changes from the low level to the high level, the output signal S3 of the delay element 201 is low. The level is maintained. Therefore, the selector 103 continues to output the high level output signal S1 of the OR circuit 101 as the output signal S_OUT.
次に、時刻t1から固定時間Tだけ経過した時刻t3では、遅延素子201の出力信号S3がローレベルからハイレベルに変化する。この結果、セレクタ103は、AND回路102の出力信号S2を出力信号S_OUTとして出力する。AND回路102の出力信号S2は、時刻t2において、入力信号S_INの変化に合わせてハイレベルからローレベルへと変化している。そのため、セレクタ103は、時刻t3において、出力信号S_OUTをハイレベルからローレベルに変化させる。このとき、入力信号S_INおよび出力信号S_OUTの両方がローレベルとなるため、OR回路101の出力信号S1もハイレベルからローレベルへと変化する。
Next, at time t3 when the fixed time T has elapsed from time t1, the output signal S3 of the delay element 201 changes from low level to high level. As a result, the selector 103 outputs the output signal S2 of the AND circuit 102 as the output signal S_OUT. The output signal S2 of the AND circuit 102 changes from the high level to the low level in accordance with the change of the input signal S_IN at time t2. Therefore, the selector 103 changes the output signal S_OUT from the high level to the low level at time t3. At this time, since both the input signal S_IN and the output signal S_OUT are at the low level, the output signal S1 of the OR circuit 101 also changes from the high level to the low level.
このように、固定時間Tよりも短いパルス幅W0の入力信号S_INが入力された場合、入力信号S_INの立下がりのタイミングである時刻t2では、出力信号S_OUTがハイレベルに固定され、固定時間Tが経過した時刻t3に出力信号S_OUTが立下がる。これにより、固定時間Tのハイレベルパルス幅を有する出力信号S_OUTが出力される。
As described above, when the input signal S_IN having the pulse width W0 shorter than the fixed time T is input, the output signal S_OUT is fixed to the high level at the time t2, which is the falling timing of the input signal S_IN, and the fixed time T The output signal S_OUT falls at time t3 when elapses. As a result, an output signal S_OUT having a high level pulse width of a fixed time T is output.
次に、時刻t3から固定時間Tが経過した時刻t4では、遅延素子201の出力信号S3がハイレベルからローレベルに変化する。この結果、セレクタ103は、OR回路101の出力信号S1を出力信号S_OUTとして出力する。OR回路101の出力信号S1は、時刻t3においてローレベルに変化しているため、セレクタ103は、遅延素子201の出力信号S3の変化後も、ローレベルの出力信号S_OUTを出力し続けることになる。
Next, at time t4 when the fixed time T has elapsed from time t3, the output signal S3 of the delay element 201 changes from high level to low level. As a result, the selector 103 outputs the output signal S1 of the OR circuit 101 as the output signal S_OUT. Since the output signal S1 of the OR circuit 101 changes to the low level at time t3, the selector 103 continues to output the low level output signal S_OUT even after the output signal S3 of the delay element 201 changes. .
その後、時刻t5において、次のパルスに応じて入力信号S_INがローレベルからハイレベルに変化する。ここで、固定時間Tがパルス周期P0(時刻t1から時刻t5までの期間)の1/2以下に設定されているため、出力信号S_OUTがローレベルに変化した時刻t3から時刻t5までの期間は固定時間T以上となる。すなわち、時刻t5は、時刻t1と同様に、ローレベルの出力信号S_OUTが固定時間T以上経過した状態であり、遅延素子201の出力信号S3もローレベルである。そのため、時刻t5において、入力信号S_INがローレベルからハイレベルに変化し、OR回路101の出力信号S1がローレベルからハイレベルに変化すると、セレクタ103は、出力信号S_OUTをローレベルからハイレベルに変化させる。つまり、入力信号S_INのパルスの立上がりを出力信号S_OUTに反映させることができる。
Thereafter, at time t5, the input signal S_IN changes from the low level to the high level according to the next pulse. Here, since the fixed time T is set to ½ or less of the pulse period P0 (period from time t1 to time t5), the period from time t3 to time t5 when the output signal S_OUT changes to the low level is The fixed time T or longer. That is, at time t5, similarly to time t1, the low level output signal S_OUT has passed for a fixed time T or longer, and the output signal S3 of the delay element 201 is also at low level. Therefore, at time t5, when the input signal S_IN changes from low level to high level and the output signal S1 of the OR circuit 101 changes from low level to high level, the selector 103 changes the output signal S_OUT from low level to high level. Change. That is, the rise of the pulse of the input signal S_IN can be reflected in the output signal S_OUT.
(パルス幅補正回路の動作例2)
次に、パルス幅補正回路1の具体的な動作例2について説明する。動作例2は、入力信号S_INが定常的にハイレベルの例である。具体的には、ハイレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間よりも短いローレベルパルス幅の入力信号S_INが入力された例である。 (Operation example 2 of pulse width correction circuit)
Next, a specific operation example 2 of the pulsewidth correction circuit 1 will be described. The operation example 2 is an example in which the input signal S_IN is constantly at a high level. Specifically, in this example, the input signal S_IN having a low level pulse width shorter than the fixed time is input in a state where the high level output signal S_OUT has passed for a predetermined time (same as the fixed time in this embodiment). .
次に、パルス幅補正回路1の具体的な動作例2について説明する。動作例2は、入力信号S_INが定常的にハイレベルの例である。具体的には、ハイレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間よりも短いローレベルパルス幅の入力信号S_INが入力された例である。 (Operation example 2 of pulse width correction circuit)
Next, a specific operation example 2 of the pulse
図3は、動作例2における、入力信号S_IN、OR回路の出力信号S1、AND回路の出力信号S2、出力信号S_OUTおよび遅延素子201の出力信号S3のタイミングチャートである。
FIG. 3 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 2.
図3に示されるように、ハイレベルの出力信号S_OUTが固定時間T以上経過した状態の時刻t6では、遅延素子201の出力信号S3もハイレベルであり、セレクタ103は、AND回路102の出力信号S2を出力信号S_OUTとして出力する。そのため、時刻t6において、入力信号S_INがハイレベルからローレベルに変化し、AND回路102の出力信号S2がハイレベルからローレベルに変化すると、セレクタ103は、出力信号S_OUTをハイレベルからローレベルに変化させる。このとき、入力信号S_INおよび出力信号S_OUTの両方がハイレベルからローレベルに変化するため、OR回路101の出力信号S1もハイレベルからローレベルに変化する。
As shown in FIG. 3, at time t <b> 6 when the high level output signal S_OUT has passed the fixed time T or longer, the output signal S <b> 3 of the delay element 201 is also high level, and the selector 103 outputs the output signal of the AND circuit 102. S2 is output as an output signal S_OUT. Therefore, at time t6, when the input signal S_IN changes from high level to low level and the output signal S2 of the AND circuit 102 changes from high level to low level, the selector 103 changes the output signal S_OUT from high level to low level. Change. At this time, since both the input signal S_IN and the output signal S_OUT change from the high level to the low level, the output signal S1 of the OR circuit 101 also changes from the high level to the low level.
次に、固定時間Tよりも短いパルス幅W0だけ経過した時刻t7において、入力信号S_INがローレベルからハイレベルに変化する。このとき、入力信号S_INの変化に合わせて、OR回路101の出力信号S1がローレベルからハイレベルに変化するが、AND回路102の出力信号S2は、ローレベルの出力信号S_OUTによりローレベルを維持する。また、時刻t7では、出力信号S_OUTがハイレベルからローレベルに変化した時刻t6より固定時間T(つまり、遅延素子201の遅延時間)経過していないため、遅延素子201の出力信号S3はハイレベルを維持している。そのため、セレクタ103は、AND回路のローレベルの出力信号S2を出力信号S_OUTとして出力し続ける。
Next, at time t7 when the pulse width W0 shorter than the fixed time T has elapsed, the input signal S_IN changes from the low level to the high level. At this time, the output signal S1 of the OR circuit 101 changes from the low level to the high level in accordance with the change of the input signal S_IN, but the output signal S2 of the AND circuit 102 maintains the low level by the low level output signal S_OUT. To do. At time t7, since the fixed time T (that is, the delay time of the delay element 201) has not elapsed since time t6 when the output signal S_OUT changed from the high level to the low level, the output signal S3 of the delay element 201 is at the high level. Is maintained. Therefore, the selector 103 continues to output the low level output signal S2 of the AND circuit as the output signal S_OUT.
次に、時刻t6から固定時間Tだけ経過した時刻t8では、遅延素子201の出力信号S3がハイレベルからローレベルに変化する。この結果、セレクタ103は、OR回路101の出力信号S1を出力信号S_OUTとして出力する。OR回路101の出力信号S1は、時刻t7において、入力信号S_INの変化に合わせてローレベルからハイレベルへと変化している。そのため、セレクタ103は、時刻t8において、出力信号S_OUTをローレベルからハイレベルに変化させる。このとき、入力信号S_INおよび出力信号S_OUTの両方がハイレベルとなるため、AND回路102の出力信号S2もローレベルからハイレベルへと変化する。
Next, at time t8 when a fixed time T has elapsed from time t6, the output signal S3 of the delay element 201 changes from high level to low level. As a result, the selector 103 outputs the output signal S1 of the OR circuit 101 as the output signal S_OUT. The output signal S1 of the OR circuit 101 changes from the low level to the high level in accordance with the change of the input signal S_IN at time t7. Therefore, the selector 103 changes the output signal S_OUT from the low level to the high level at time t8. At this time, since both the input signal S_IN and the output signal S_OUT are at the high level, the output signal S2 of the AND circuit 102 also changes from the low level to the high level.
このように、固定時間Tよりも短いパルス幅W0の入力信号S_INが入力された場合、入力信号S_INの立上がりのタイミングである時刻t7では、出力信号S_OUTがローレベルに固定され、固定時間Tが経過した時刻t8に出力信号S_OUTが立上がる。これにより、固定時間Tのローレベルのパルス幅を有する出力信号S_OUTが出力される。
As described above, when the input signal S_IN having the pulse width W0 shorter than the fixed time T is input, the output signal S_OUT is fixed to the low level at the time t7 which is the rising timing of the input signal S_IN, and the fixed time T is The output signal S_OUT rises at the elapsed time t8. As a result, an output signal S_OUT having a low level pulse width for a fixed time T is output.
次に、時刻t8から固定時間Tが経過した時刻t9では、遅延素子201の出力信号S3がローレベルからハイレベルに変化する。この結果、セレクタ103は、AND回路102の出力信号S2を出力信号S_OUTとして出力する。AND回路102の出力信号S2は、時刻t8においてハイレベルに変化しているため、セレクタ103は、遅延素子201の出力信号S3の変化後も、ハイレベルの出力信号S_OUTを出力し続けることになる。
Next, at time t9 when the fixed time T has elapsed from time t8, the output signal S3 of the delay element 201 changes from low level to high level. As a result, the selector 103 outputs the output signal S2 of the AND circuit 102 as the output signal S_OUT. Since the output signal S2 of the AND circuit 102 changes to high level at time t8, the selector 103 continues to output the high level output signal S_OUT even after the output signal S3 of the delay element 201 changes. .
その後、時刻t10において、次のパルスに応じて入力信号S_INがハイレベルからローレベルに変化する。ここで、固定時間Tがパルス周期P0(時刻t6から時刻t10までの期間)の1/2以下に設定されているため、出力信号S_OUTがハイレベルに変化した時刻t8から時刻t10までの期間は固定時間T以上となる。すなわち、時刻t10は、ハイレベルの出力信号S_OUTが固定時間T以上経過した状態であり、遅延素子201の出力信号S3もハイレベルである。そのため、時刻t10において、入力信号S_INがハイレベルからローレベルに変化し、AND回路102の出力信号S2がハイレベルからローレベルに変化すると、セレクタ103は、出力信号S_OUTをハイレベルからローレベルに変化させる。つまり、入力信号S_INのパルスの立下がりを出力信号S_OUTに反映させることができる。
Thereafter, at time t10, the input signal S_IN changes from the high level to the low level according to the next pulse. Here, since the fixed time T is set to ½ or less of the pulse period P0 (period from time t6 to time t10), the period from time t8 to time t10 when the output signal S_OUT changes to high level is The fixed time T or longer. That is, at time t10, the high level output signal S_OUT is in a state where the fixed time T or more has elapsed, and the output signal S3 of the delay element 201 is also at the high level. Therefore, at time t10, when the input signal S_IN changes from high level to low level and the output signal S2 of the AND circuit 102 changes from high level to low level, the selector 103 changes the output signal S_OUT from high level to low level. Change. That is, the falling edge of the pulse of the input signal S_IN can be reflected in the output signal S_OUT.
(パルス幅補正回路の動作例3)
次に、パルス幅補正回路1の具体的な動作例3について説明する。動作例3は、ローレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間以上のハイレベルパルス幅の入力信号S_INが入力された例である。 (Operation example 3 of pulse width correction circuit)
Next, a specific operation example 3 of the pulsewidth correction circuit 1 will be described. The operation example 3 is an example in which an input signal S_IN having a high level pulse width longer than a fixed time is input in a state where a low level output signal S_OUT has passed for a predetermined time (same as the fixed time in the present embodiment).
次に、パルス幅補正回路1の具体的な動作例3について説明する。動作例3は、ローレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間以上のハイレベルパルス幅の入力信号S_INが入力された例である。 (Operation example 3 of pulse width correction circuit)
Next, a specific operation example 3 of the pulse
図4は、動作例3における、入力信号S_IN、OR回路の出力信号S1、AND回路の出力信号S2、出力信号S_OUTおよび遅延素子201の出力信号S3のタイミングチャートである。
FIG. 4 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 3.
図4に示されるように、時刻t11において、入力信号S_INがローレベルからハイレベルに変化すると、図2の時刻t1と同様に、OR回路101の出力信号S1がローレベルからハイレベルに、出力信号S_OUTがローレベルからハイレベルに、AND回路102の出力信号S2がローレベルからハイレベルに変化する。
As shown in FIG. 4, when the input signal S_IN changes from the low level to the high level at time t11, the output signal S1 of the OR circuit 101 is output from the low level to the high level, similarly to time t1 in FIG. The signal S_OUT changes from low level to high level, and the output signal S2 of the AND circuit 102 changes from low level to high level.
次に、時刻t11から固定時間Tだけ経過した時刻t12では、遅延素子201の出力信号S3がローレベルからハイレベルに変化する。この結果、セレクタ103の出力である出力信号S_OUTは、OR回路101の出力信号S1からAND回路102の出力信号S2に切り替わる。しかしながら、時刻t11においてOR回路101の出力信号S1およびAND回路102の出力信号S2のいずれもローレベルからハイレベルに変化し、この状態が時刻t12でも継続しているため、時刻t12において、出力信号S_OUTのレベルは変化せず、ハイレベルが維持される。
Next, at time t12 when a fixed time T has elapsed from time t11, the output signal S3 of the delay element 201 changes from low level to high level. As a result, the output signal S_OUT, which is the output of the selector 103, is switched from the output signal S1 of the OR circuit 101 to the output signal S2 of the AND circuit 102. However, since both the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 change from the low level to the high level at time t11 and this state continues at time t12, the output signal at time t12. The level of S_OUT does not change and the high level is maintained.
次に、時刻t13において、入力信号S_INがハイレベルからローレベルに変化する。このとき、入力信号S_INの変化に合わせて、AND回路102の出力信号S2がハイレベルからローレベルに変化する。セレクタ103は、出力信号S2の変化に合わせて、出力信号S_OUTをハイレベルからローレベルに変化させる。このとき、入力信号S_INおよび出力信号S_OUTの両方がローレベルとなるため、OR回路101の出力信号S1もハイレベルからローレベルへと変化する。
Next, at time t13, the input signal S_IN changes from the high level to the low level. At this time, the output signal S2 of the AND circuit 102 changes from the high level to the low level in accordance with the change of the input signal S_IN. The selector 103 changes the output signal S_OUT from the high level to the low level in accordance with the change of the output signal S2. At this time, since both the input signal S_IN and the output signal S_OUT are at the low level, the output signal S1 of the OR circuit 101 also changes from the high level to the low level.
なお、時刻t13から固定時間Tが経過した時刻t14では、遅延素子201の出力信号S3がハイレベルからローレベルに変化する。この結果、セレクタ103の出力である出力信号S_OUTは、AND回路102の出力信号S2からOR回路101の出力信号S1に切り替わる。しかしながら、時刻t13において、OR回路101の出力信号S1およびAND回路102の出力信号S2のいずれもハイレベルからローレベルに変化しているため、時刻t14において、出力信号S_OUTのレベルは変化せず、ローレベルが維持される。
Note that at time t14 when the fixed time T has elapsed from time t13, the output signal S3 of the delay element 201 changes from high level to low level. As a result, the output signal S_OUT which is the output of the selector 103 is switched from the output signal S2 of the AND circuit 102 to the output signal S1 of the OR circuit 101. However, since both the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 change from the high level to the low level at time t13, the level of the output signal S_OUT does not change at time t14. Low level is maintained.
このように、固定時間Tより長いハイレベルパルス幅の入力信号S_INが入力された場合、セレクタ103は、入力信号S_INと出力信号S_OUTとで、立上がりおよび立下がりのそれぞれのタイミングを合わせる。そのため、セレクタ103は、パルス幅の補正を行うことなく、入力信号S_INのパルス幅と同一のパルス幅を有する出力信号S_OUTを出力する。
As described above, when the input signal S_IN having a high level pulse width longer than the fixed time T is input, the selector 103 matches the timing of rising and falling with the input signal S_IN and the output signal S_OUT. Therefore, the selector 103 outputs the output signal S_OUT having the same pulse width as the input signal S_IN without correcting the pulse width.
(パルス幅補正回路の動作例4)
次に、パルス幅補正回路1の具体的な動作例4について説明する。動作例4は、ハイレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間以上のローレベルのパルス幅の入力信号S_INが入力された例である。 (Operation example 4 of pulse width correction circuit)
Next, a specific operation example 4 of the pulsewidth correction circuit 1 will be described. The operation example 4 is an example in which the input signal S_IN having a low level pulse width longer than the fixed time is input in a state where the high level output signal S_OUT has passed for a predetermined time (same as the fixed time in this embodiment). .
次に、パルス幅補正回路1の具体的な動作例4について説明する。動作例4は、ハイレベルの出力信号S_OUTが所定時間(本実施形態では固定時間と同一)以上経過した状態で、固定時間以上のローレベルのパルス幅の入力信号S_INが入力された例である。 (Operation example 4 of pulse width correction circuit)
Next, a specific operation example 4 of the pulse
図5は、動作例4における、入力信号S_IN、OR回路の出力信号S1、AND回路の出力信号S2、出力信号S_OUTおよび遅延素子201の出力信号S3のタイミングチャートである。
FIG. 5 is a timing chart of the input signal S_IN, the output signal S1 of the OR circuit, the output signal S2 of the AND circuit, the output signal S_OUT, and the output signal S3 of the delay element 201 in the operation example 4.
図5に示されるように、時刻t15において、入力信号S_INがハイレベルからローレベルに変化すると、図3の時刻t6と同様に、AND回路102の出力信号S2がハイレベルからローレベルに、出力信号S_OUTがハイレベルからローレベルに、OR回路101の出力信号S1がハイレベルからローレベルに変化する。
As shown in FIG. 5, when the input signal S_IN changes from the high level to the low level at time t15, the output signal S2 of the AND circuit 102 is output from the high level to the low level, similarly to time t6 in FIG. The signal S_OUT changes from high level to low level, and the output signal S1 of the OR circuit 101 changes from high level to low level.
次に、時刻t15から固定時間Tだけ経過した時刻t16では、遅延素子201の出力信号S3がハイレベルからローレベルに変化する。この結果、セレクタ103の出力である出力信号S_OUTは、AND回路102の出力信号S2からOR回路101の出力信号S1に切り替わる。しかしながら、時刻t15においてOR回路101の出力信号S1およびAND回路102の出力信号S2のいずれもハイレベルからローレベルに変化し、この状態が時刻t16でも継続しているため、時刻t16において、出力信号S_OUTのレベルは変化せず、ローレベルが維持される。
Next, at time t16 when the fixed time T has elapsed from time t15, the output signal S3 of the delay element 201 changes from high level to low level. As a result, the output signal S_OUT which is the output of the selector 103 is switched from the output signal S2 of the AND circuit 102 to the output signal S1 of the OR circuit 101. However, since both the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 change from the high level to the low level at time t15, and this state continues at time t16, the output signal at time t16. The level of S_OUT does not change and the low level is maintained.
次に、時刻t17において、入力信号S_INがローレベルからハイレベルに変化する。このとき、入力信号S_INの変化に合わせて、OR回路101の出力信号S1がローレベルからハイレベルに変化することを受けて、セレクタ103は、出力信号S_OUTをローレベルからハイレベルに変化させる。このとき、入力信号S_INおよび出力信号S_OUTの両方がハイレベルとなるため、AND回路102の出力信号S2もローレベルからハイレベルへと変化する。
Next, at time t17, the input signal S_IN changes from the low level to the high level. At this time, in response to the change of the output signal S1 of the OR circuit 101 from the low level to the high level in accordance with the change of the input signal S_IN, the selector 103 changes the output signal S_OUT from the low level to the high level. At this time, since both the input signal S_IN and the output signal S_OUT are at the high level, the output signal S2 of the AND circuit 102 also changes from the low level to the high level.
なお、時刻t17から固定時間Tが経過した時刻t18では、遅延素子201の出力信号S3がローレベルからハイレベルに変化する。この結果、セレクタ103の出力である出力信号S_OUTは、OR回路101の出力信号S1からAND回路102の出力信号S2に切り替わる。しかしながら、時刻t17において、OR回路101の出力信号S1およびAND回路102の出力信号S2のいずれもローレベルからハイレベルに変化しているため、時刻t18において、出力信号S_OUTのレベルは変化せず、ハイレベルが維持される。
Note that at time t18 when the fixed time T has elapsed from time t17, the output signal S3 of the delay element 201 changes from low level to high level. As a result, the output signal S_OUT, which is the output of the selector 103, is switched from the output signal S1 of the OR circuit 101 to the output signal S2 of the AND circuit 102. However, since both the output signal S1 of the OR circuit 101 and the output signal S2 of the AND circuit 102 change from the low level to the high level at time t17, the level of the output signal S_OUT does not change at time t18. High level is maintained.
このように、固定時間Tより長いローレベルパルス幅の入力信号S_INが入力された場合、セレクタ103は、入力信号S_INと出力信号S_OUTとで、立下がりおよび立上がりのそれぞれのタイミングを合わせる。そのため、セレクタ103は、パルス幅の補正を行うことなく、入力信号S_INのパルス幅と同一のパルス幅を有する出力信号S_OUTを出力する。
As described above, when the input signal S_IN having a low level pulse width longer than the fixed time T is input, the selector 103 matches the timings of falling and rising with the input signal S_IN and the output signal S_OUT. Therefore, the selector 103 outputs the output signal S_OUT having the same pulse width as the input signal S_IN without correcting the pulse width.
(パルス幅補正回路の効果)
上記のように、本実施形態のパルス幅補正回路1は、入力信号S_INのパルスがハイレベルおよびローレベルのいずれであっても、当該パルス幅W0が固定時間T未満の場合、パルス幅が固定時間Tに補正された出力信号S_OUTを出力する。すなわち、入力信号S_INのパルス幅が固定時間T未満であったとしても、後段の回路において消失しないパルス幅に補正された出力信号S_OUTが出力されるため、後段の回路でのパルスの消失を抑制できる。 (Effect of pulse width correction circuit)
As described above, the pulsewidth correction circuit 1 of the present embodiment has a fixed pulse width when the pulse width W0 is less than the fixed time T regardless of whether the pulse of the input signal S_IN is at a high level or a low level. An output signal S_OUT corrected at time T is output. That is, even if the pulse width of the input signal S_IN is less than the fixed time T, the output signal S_OUT corrected to a pulse width that does not disappear in the subsequent circuit is output, so that the disappearance of the pulse in the subsequent circuit is suppressed. it can.
上記のように、本実施形態のパルス幅補正回路1は、入力信号S_INのパルスがハイレベルおよびローレベルのいずれであっても、当該パルス幅W0が固定時間T未満の場合、パルス幅が固定時間Tに補正された出力信号S_OUTを出力する。すなわち、入力信号S_INのパルス幅が固定時間T未満であったとしても、後段の回路において消失しないパルス幅に補正された出力信号S_OUTが出力されるため、後段の回路でのパルスの消失を抑制できる。 (Effect of pulse width correction circuit)
As described above, the pulse
また、入力信号S_INのパルス幅が固定時間T以上の場合、パルス幅補正回路1は、入力信号S_INのパルス幅と同じパルス幅を有する出力信号S_OUTを出力する。
When the pulse width of the input signal S_IN is equal to or longer than the fixed time T, the pulse width correction circuit 1 outputs an output signal S_OUT having the same pulse width as that of the input signal S_IN.
図6は、パルス幅が固定時間T以上の入力信号S_INが入力された場合の、本実施形態の出力信号S_OUTと、特開2006-67414号公報に記載された技術を適用した比較形態の出力信号S_OUTとの比較を示す図である。
FIG. 6 shows an output signal S_OUT according to the present embodiment when an input signal S_IN having a pulse width equal to or longer than a fixed time T is input, and an output in a comparison form to which the technique described in Japanese Patent Laid-Open No. 2006-67414 is applied. It is a figure which shows the comparison with signal S_OUT.
図6に示されるように、比較形態では、パルス幅の長さにかかわらず、一定量だけパルス幅を広げる補正が行われる。そのため、入力信号S_INのパルス幅W0に対して、出力信号S_OUTのパルス幅W1が長くなっている。そのため、パルス終了から次のパルスまでの期間は、入力信号S_INでは(パルス周期P0-補正前のパルス幅W0)であるのに対し、(パルス周期P0-補正後のパルス幅W1)と短くなってしまう。一方、本実施形態では、パルス終了から次のパルスまでの期間は、入力信号S_INと出力信号S_OUTとでは変化がない。そのため、本実施形態のパルス幅補正回路1は、比較形態に比べて、固定時間T以上のパルス幅を有するパルス終了から次のパルスまでの期間を長くすることができ、後段の回路の動作に必要な期間を確保しやすくなる。
As shown in FIG. 6, in the comparative form, correction for expanding the pulse width by a certain amount is performed regardless of the length of the pulse width. Therefore, the pulse width W1 of the output signal S_OUT is longer than the pulse width W0 of the input signal S_IN. Therefore, the period from the end of the pulse to the next pulse is as short as (pulse period P0−pulse width W1 after correction) in the input signal S_IN (pulse period P0−pulse width W0 before correction). End up. On the other hand, in the present embodiment, there is no change between the input signal S_IN and the output signal S_OUT in the period from the end of the pulse to the next pulse. Therefore, the pulse width correction circuit 1 according to the present embodiment can increase the period from the end of a pulse having a pulse width equal to or longer than the fixed time T to the next pulse as compared with the comparative example, and the operation of the subsequent circuit can be increased. It becomes easy to secure the necessary period.
また、特開2006-67414号公報では、パルス幅を広くするために2つのフリップフロップを用いている。また、特開2009-253951号公報(特許文献2)では、パルス幅の補正のために電圧制御発振器を用いている。これに対し、本実施形態のパルス幅補正回路1は、図1に示すOR回路101、AND回路102、セレクタ103および遅延素子201によりパルス幅の補正を行う。そのため、本実施形態のパルス幅補正回路1は、特開2006-67414号公報および特開2009-253951号公報と比較して、回路面積を小さくすることができる。
In Japanese Patent Laid-Open No. 2006-67414, two flip-flops are used to widen the pulse width. Japanese Patent Laid-Open No. 2009-253951 (Patent Document 2) uses a voltage controlled oscillator for correcting the pulse width. In contrast, the pulse width correction circuit 1 of the present embodiment corrects the pulse width by the OR circuit 101, the AND circuit 102, the selector 103, and the delay element 201 shown in FIG. Therefore, the circuit area of the pulse width correction circuit 1 of the present embodiment can be reduced as compared with Japanese Patent Application Laid-Open Nos. 2006-67414 and 2009-253951.
例えば、遅延時間(固定時間)が7μsの遅延素子201を用いた本実施形態のパルス幅補正回路1の回路面積は約633μm2である。これに対し、特開2006-67414号公報のように2個のフリップフロップを用いた比較形態に係るパルス幅補正回路では、約350μm2だけ回路面積が大きくなる。つまり、本実施形態のパルス幅補正回路1に比べて、比較形態では回路面積が1.5倍となる。また、特開2009-253951号公報に記載されている電圧制御発振器の回路規模は、本実施形態のパルス幅補正回路1の回路面積に比べて格段に大きい。
For example, the circuit area of the pulse width correction circuit 1 of this embodiment using the delay element 201 with a delay time (fixed time) of 7 μs is about 633 μm 2 . On the other hand, in the pulse width correction circuit according to the comparative example using two flip-flops as in JP-A-2006-67414, the circuit area is increased by about 350 μm 2 . That is, compared with the pulse width correction circuit 1 of this embodiment, the circuit area is 1.5 times in the comparative embodiment. Further, the circuit scale of the voltage controlled oscillator described in Japanese Patent Laid-Open No. 2009-253951 is much larger than the circuit area of the pulse width correction circuit 1 of the present embodiment.
(変形例)
上記の説明では、固定部10がOR回路101とAND回路102とセレクタ103とを備える形態としたが、固定部10は、例えば、出力信号S_OUTがローレベルである状態が所定時間経過した後において入力信号S_INがローレベルからハイレベルに変化した場合に、出力信号S_OUTをハイレベルに固定し、出力信号S_OUTがハイレベルである状態が所定時間経過した後において入力信号S_INがハイレベルからローレベルに変化した場合に、出力信号S_OUTをローレベルに固定するとともに、解除部20からの指示に応じて出力信号S_OUTの固定を解除するプログラムが記憶された記憶部と、当該プログラムを実行するプロセッサとで構成されていてもよい。 (Modification)
In the above description, the fixedunit 10 includes the OR circuit 101, the AND circuit 102, and the selector 103. However, the fixed unit 10 may, for example, after the output signal S_OUT is at a low level after a predetermined time has elapsed. When the input signal S_IN changes from the low level to the high level, the output signal S_OUT is fixed to the high level, and the input signal S_IN is changed from the high level to the low level after a predetermined time has elapsed after the output signal S_OUT is in the high level state. When the output signal S_OUT is fixed to a low level, the storage unit stores a program for releasing the fixation of the output signal S_OUT in response to an instruction from the release unit 20, and a processor that executes the program It may be comprised.
上記の説明では、固定部10がOR回路101とAND回路102とセレクタ103とを備える形態としたが、固定部10は、例えば、出力信号S_OUTがローレベルである状態が所定時間経過した後において入力信号S_INがローレベルからハイレベルに変化した場合に、出力信号S_OUTをハイレベルに固定し、出力信号S_OUTがハイレベルである状態が所定時間経過した後において入力信号S_INがハイレベルからローレベルに変化した場合に、出力信号S_OUTをローレベルに固定するとともに、解除部20からの指示に応じて出力信号S_OUTの固定を解除するプログラムが記憶された記憶部と、当該プログラムを実行するプロセッサとで構成されていてもよい。 (Modification)
In the above description, the fixed
また、上記の説明では、解除部20が遅延素子201を備える形態としたが、解除部20は、固定部10による出力信号S_OUTの固定が開始されてから固定時間経過後に固定部10に対して当該固定の解除指示を出力するプログラムが記憶された記憶部と、当該プログラムを実行するプロセッサとで構成されていてもよい。
In the above description, the release unit 20 includes the delay element 201. However, the release unit 20 is connected to the fixed unit 10 after a fixed time has elapsed since the fixing unit 10 started fixing the output signal S_OUT. You may be comprised by the memory | storage part in which the program which outputs the said fixed cancellation | release instruction | indication was memorize | stored, and the processor which performs the said program.
なお、上記の説明では、固定部10が出力信号S_OUTの固定を行う条件として定められている、出力信号S_OUTがローレベルまたはハイレベルの状態を継続している所定時間(第1時間)を固定時間(第2時間)と同一とした。しかしながら、固定部10および解除部20を、プログラムを記憶した記憶部およびプロセッサで構成する場合、当該所定時間(第1時間)と固定時間(第2時間)とを異ならせてもよい。
In the above description, the predetermined time (first time) during which the output signal S_OUT is kept at the low level or the high level, which is determined as a condition for the fixing unit 10 to fix the output signal S_OUT, is fixed. It was the same as the time (second time). However, when the fixing unit 10 and the releasing unit 20 are configured by a storage unit and a processor that store programs, the predetermined time (first time) and the fixed time (second time) may be different.
今回開示された実施の形態は、すべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施の形態の説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.
1 パルス幅補正回路、10 固定部、20 解除部、101 OR回路、102 AND回路、103 セレクタ、201 遅延素子。
1 pulse width correction circuit, 10 fixed part, 20 release part, 101 OR circuit, 102 AND circuit, 103 selector, 201 delay element.
Claims (3)
- 入力信号のパルス幅を補正して出力信号を生成するパルス幅補正回路であって、
前記出力信号がローレベルである状態が第1時間経過した後に前記入力信号がローレベルからハイレベルに変化した場合に、前記出力信号をハイレベルに固定し、前記出力信号がハイレベルである状態が前記第1時間経過した後に前記入力信号がハイレベルからローレベルに変化した場合に、前記出力信号をローレベルに固定する固定部と、
前記出力信号が固定されてから第2時間経過したときに、固定された前記出力信号を解除する解除部とを備える、パルス幅補正回路。 A pulse width correction circuit that generates an output signal by correcting a pulse width of an input signal,
A state in which the output signal is fixed to a high level and the output signal is at a high level when the input signal changes from a low level to a high level after a lapse of a first time when the output signal is at a low level. When the input signal changes from a high level to a low level after elapse of the first time, a fixing unit that fixes the output signal to a low level;
A pulse width correction circuit comprising: a release unit that releases the fixed output signal when a second time has elapsed since the output signal was fixed. - 前記固定部は、
前記入力信号および前記出力信号を受けるOR回路と、
前記入力信号および前記出力信号を受けるAND回路と、
前記OR回路および前記AND回路のいずれか一方の出力を前記出力信号として出力するセレクタとを備え、
前記解除部は、前記出力信号を前記第2時間遅延させる遅延素子を備え、
前記セレクタは、前記遅延素子の出力がローレベルの場合に前記OR回路の出力を前記出力信号として出力し、前記遅延素子の出力がハイレベルの場合に前記AND回路の出力を前記出力信号として出力する、請求項1に記載のパルス幅補正回路。 The fixing part is
An OR circuit for receiving the input signal and the output signal;
An AND circuit that receives the input signal and the output signal;
A selector that outputs an output of one of the OR circuit and the AND circuit as the output signal;
The release unit includes a delay element that delays the output signal for the second time,
The selector outputs the output of the OR circuit as the output signal when the output of the delay element is low level, and outputs the output of the AND circuit as the output signal when the output of the delay element is high level The pulse width correction circuit according to claim 1. - 前記第2時間は、前記入力信号のパルス周期の1/2以下である、請求項1または2に記載のパルス幅補正回路。 The pulse width correction circuit according to claim 1 or 2, wherein the second time period is ½ or less of a pulse period of the input signal.
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS524835Y1 (en) * | 1970-12-02 | 1977-02-01 | ||
JPH01202916A (en) * | 1988-02-09 | 1989-08-15 | Nec Corp | Pulse width adjusting circuit |
JPH11205100A (en) * | 1998-01-17 | 1999-07-30 | Nec Corp | Semi conductor integrated circuit |
JP2009253951A (en) * | 2008-04-11 | 2009-10-29 | Mitsubishi Electric Corp | Pulsewidth correcting apparatus, and pulsewidth correcting method |
US20090322390A1 (en) * | 2008-06-30 | 2009-12-31 | Hynix Semiconductor, Inc. | Duty cycle correction circuit and delay locked loop circuit including the same |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2006067414A (en) * | 2004-08-30 | 2006-03-09 | Kawasaki Microelectronics Kk | Pulse width correction circuit |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS524835Y1 (en) * | 1970-12-02 | 1977-02-01 | ||
JPH01202916A (en) * | 1988-02-09 | 1989-08-15 | Nec Corp | Pulse width adjusting circuit |
JPH11205100A (en) * | 1998-01-17 | 1999-07-30 | Nec Corp | Semi conductor integrated circuit |
JP2009253951A (en) * | 2008-04-11 | 2009-10-29 | Mitsubishi Electric Corp | Pulsewidth correcting apparatus, and pulsewidth correcting method |
US20090322390A1 (en) * | 2008-06-30 | 2009-12-31 | Hynix Semiconductor, Inc. | Duty cycle correction circuit and delay locked loop circuit including the same |
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