USRE45604E1 - DLL circuit adapted to semiconductor device - Google Patents
DLL circuit adapted to semiconductor device Download PDFInfo
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- USRE45604E1 USRE45604E1 US14/020,445 US201314020445A USRE45604E US RE45604 E1 USRE45604 E1 US RE45604E1 US 201314020445 A US201314020445 A US 201314020445A US RE45604 E USRE45604 E US RE45604E
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- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000001514 detection method Methods 0.000 claims description 224
- 230000004044 response Effects 0.000 claims description 23
- 239000000872 buffer Substances 0.000 claims description 20
- 230000004913 activation Effects 0.000 claims description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 5
- 230000003213 activating effect Effects 0.000 claims 2
- 230000003139 buffering effect Effects 0.000 claims 1
- 230000008034 disappearance Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000010485 coping Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
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- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
Definitions
- the present invention relates to delay-locked loop (DLL) circuits adapted to semiconductor devices.
- DLL delay-locked loop
- FIG. 9 shows an example of a DLL circuit in which a clock signal CK and an inverse clock signal /CK (where a slash or bar “/” indicates logical inversion) from an external device (not shown) are supplied to an initial circuit 11 and are then subjected to duty adjustment and delay adjustment, thus producing a DLL clock signal.
- the DLL clock signal is supplied to a DQ replica circuit 15 , from which a DQ replica output signal is supplied to a phase detection circuit 16 and subjected to phase comparison with the clock signal CK and the inverse clock signal /CK.
- the phase comparison result is fed back to a delay control circuit 13 .
- the delay control circuit 13 Based on the phase comparison result output from the phase detection circuit 16 , the delay control circuit 13 outputs a delay signal to a delay circuit 12 so as to adjust a delay element of the delay circuit 12 .
- the DLL clock signal is supplied to a duty detection circuit 21 and subjected to detection as to whether a duty thereof is above or below 50%.
- the duty detection result is fed back to a duty control circuit 22 .
- the duty control circuit 22 Based on the duty detection result output from the duty detection circuit 21 , the duty control circuit 22 outputs a control signal (i.e. a duty signal) to a duty adjustment circuit 23 .
- the duty adjustment circuit 23 adjusts the duty of a clock signal output from the initial circuit 11 based on the clock signal CK and the inverse clock signal /CK in accordance with the duty signal output from the duty control circuit 22 .
- the delay circuit 12 performs delay adjustment so as to cancel out timing skew between the DQ replica output signal and the clock signal CK (or the inverse clock signal /CK).
- the duty adjustment circuit 23 performs duty adjustment such that the duty of the DLL clock signal becomes equal to or close to 50%.
- the clock signal output from the initial circuit 11 is subjected to a frequency dividing process by a counter clock generation circuit 17 , which thus outputs a counter clock signal to a DLL cycle counter 18 .
- the DLL cycle counter 18 Based on the counter clock signal, the DLL cycle counter 18 generates an update clock signal for a prescribed duration, thus outputting it to the delay control circuit 13 and the duty control circuit 22 .
- the delay control circuit 13 and the duty control circuit 22 update their operations in response to the update clock signal.
- each pulse width of the input clock signal varies greatly due to delay adjustment during the locked-control operation, thus causing the DLL clock signal to disappear temporarily.
- phase detection circuit 16 and the duty detection circuit 21 trigger their operations in response to the DLL clock signal, it is very difficult to precisely detect the phase in the period in which the DLL clock signal disappears.
- Patent Document 1 teaches a clock generation circuit which cancels out deviations of the duty of an output clock signal (causing some problems in phase control) by additionally using a simple circuit, thus achieving high-precision phase control. Specifically, a variable delay circuit is followed by a clock duty adjustment circuit and is controlled in the delay time thereof at the leading edge of a clock pulse, wherein the clock duty adjustment circuit performs adjustment at the trailing edge when the phase of the output clock signal at its leading edge matches the phase of a reference clock signal, thus identifying the duty of the output clock signal with the duty of the reference clock signal.
- Patent Document 1 is not designed to solve the above problem regarding the delay-locked control in which the DLL circuit fails to precisely perform phase adjustment due to erroneous detection during the disappearance period of the DLL clock signal, thus increasing the number of cycles adapted to the delay-locked control.
- each pulse width of the input clock signal varies greatly due to delay adjustment during the delay-locked control so as to cause the disappearance period of the DLL clock signal, which makes it very difficult to precisely perform the phase detection and the duty detection.
- the invention seeks to solve the above problem, or to improve upon the problem at least in part.
- the present invention is directed to a DLL circuit which generates and monitors a DLL clock signal based on an input clock signal and which prevents a delay time and a duty from being updated based on the phase detection result and the duty detection result erroneously produced due to disappearance of the DLL clock signal, thus executing the delay-locked control with a small number of cycles in a stable manner.
- a DLL circuit for adjusting the phase of an input clock signal is constituted of delay control circuit for producing a delay signal so as to control a delay time applied to the input clock signal, a delay circuit for applying the delay time to the input clock signal based on the delay signal, thus producing a DLL clock signal, and a DLL clock detection circuit for detecting either a clocking state or a non-clocking state with respect to the DLL clock signal, wherein the DLL clock detection circuit controls the delay control circuit to stop updating the delay time in the delay circuit in the non-clocking state of the DLL clock signal.
- a DLL circuit for adjusting the duty of an input clock signal is constituted of a duty control circuit for producing a duty signal so as to control the duty of the input clock signal, a duty adjustment circuit for adjusting the duty of the input clock signal based on the duty signal, thus producing a DLL clock signal, and a DLL clock detection circuit for detecting either a clocking state or a non-clocking state with respect to the DLL clock signal, wherein the DLL clock detection circuit controls the duty control circuit to stop updating the duty in the duty adjustment circuit in the non-clocking state of the DLL clock signal.
- FIG. 1 is a block diagram showing the constitution of a DLL circuit according to a first embodiment of the present invention
- FIG. 2 is a block diagram showing the constitution of a DLL circuit according to a second embodiment of the present invention.
- FIG. 3 is a block diagram showing the constitution of a DLL circuit according to a third embodiment of the present invention.
- FIG. 4 is a block diagram showing the constitution of a DLL clock detection circuit shown in FIGS. 1 to 3 ;
- FIG. 5A shows the waveform of a counter clock signal output from a counter clock generation circuit shown in FIGS. 1 to 3 ;
- FIG. 5C shows the waveform of a fractional clock signal generated by the DLL cycle counter based on the counter clock signal of FIG. 5A ;
- FIG. 5D shows the waveform of a DLL clock signal output from a delay circuit shown in FIGS. 1 and 3 ;
- FIG. 5E shows the waveform of a DLL clock detection result produced by a DLL clock detection circuit shown in FIGS. 1 to 3 with respect to the DLL clock signal;
- FIG. 5F shows the waveform of an update clock signal output from the DLL cycle counter
- FIG. 6A shows the waveform of the DLL clock detection enable signal in a clocking state of the DLL clock signal
- FIG. 6B shows the waveform of the DLL clock signal in the clocking state
- FIG. 6C shows the waveform of the DLL clock detection result in the clocking state of the DLL clock signal
- FIG. 6D shows the waveform of an update enable/disable signal in the clocking state of the DLL clock signal
- FIG. 6E shows the waveform of the update clock signal in the clocking state of the DLL clock signal
- FIG. 6F shows the waveform of the DLL clock detection enable signal in a non-clocking state of the DLL clock signal
- FIG. 6G shows the waveform of the DLL clock signal in the non-clocking state of the DLL clock signal
- FIG. 6H shows the waveform of the DLL clock detection result in the non-clocking state of the DLL clock signal
- FIG. 7 is a circuit diagram showing the constitution of a delay control circuit shown in FIGS. 1 and 3 ;
- FIG. 9 is a block diagram showing the constitution of the foregoing DLL circuit.
- the counter clock generation circuit 17 divides the frequency of the clock signal so as to generate and output a counter clock signal (see FIG. 5A ) to the DLL cycle counter 18 .
- the DLL circuit of FIG. 1 additionally includes a DLL clock detection circuit 31 , which is activated upon reception of a DLL clock detection enable signal output from the DLL cycle counter 18 and which makes determination as to whether or not the DLL clock signal is disappeared (or whether or not the DLL clock signal is placed in a clocking state), thus executing or stopping the duty/delay control.
- a DLL clock detection circuit 31 which is activated upon reception of a DLL clock detection enable signal output from the DLL cycle counter 18 and which makes determination as to whether or not the DLL clock signal is disappeared (or whether or not the DLL clock signal is placed in a clocking state), thus executing or stopping the duty/delay control.
- the DLL clock signal output from the delay circuit 12 is also supplied to the DQ replica circuit 15 which has the same PVT dependency as the DQ buffer 14 . Since the DQ replica circuit 15 serves as a buffer circuit having the same PVT dependency as the DQ buffer 14 , the DQ replica output signal is output at the same timing as the DQ buffer 14 outputting the DQ output signal.
- the DQ replica output signal is supplied to the phase detection circuit 16 and subjected to phase comparison with the clock signals CK and /CK.
- the phase detection result output from the phase detection circuit 16 is supplied to the delay control circuit 13 , so that the delay circuit 12 adjusts the delay time based on the delay signal output from the delay control circuit 13 .
- the DLL clock detection circuit 31 receives the DLL clock detection enable signal (output from the DLL cycle counter 18 ) and the DLL clock signal (output from the delay circuit 12 ), wherein the DLL clock detection circuit 31 is periodically activated by the DLL clock detection enable signal.
- the period of the DLL clock detection enable signal is identical to the update period for updating the delay time.
- the DLL circuit of FIG. 1 is designed to periodically activate the DLL clock detection circuit 31 in response to the DLL clock detection enable signal output from the DLL cycle counter 18 . It can be redesigned to normally activate the DLL clock detection circuit 31 .
- FIG. 2 shows a DLL circuit according to a second embodiment of the present invention, which is designed to perform the duty control only, wherein parts identical to those shown in FIGS. 1 and 9 are designated by the same reference numerals.
- the initial circuit 11 converts a differential input signal (corresponding to the clock signals CK and /CK) into a clock signal for use in the DLL circuit.
- the clock signal output from the initial circuit 11 is supplied to the counter clock generation circuit 17 and the duty adjustment circuit 23 .
- the duty detection circuit 21 performs detection as to whether the duty of the DLL clock signal is above or below 50%. Based on the duty detection result output from the duty detection circuit 21 , the duty control circuit 22 performs the duty control on the update clock signal from the DLL cycle counter 18 . Based on the duty signal output from the duty control circuit 22 , the duty adjustment circuit 23 adjusts the duty of the clock signal output from the initial circuit 11 , thus outputting the DLL clock signal.
- the DLL cycle counter 18 counts the number of pulses included in the counter clock signal so as to generate the update clock signal for updating the duty control.
- the DLL clock detection circuit 31 detects whether or not the DLL clock signal disappears (or whether or not the DLL clock signal is placed in a clocking state), thus generating the DLL clock detection result (or the update enable/disable signals) for executing or stopping updating the duty control. The details of the DLL clock detection circuit 31 will be described later.
- the DLL clock signal output from the duty adjustment circuit 23 is supplied to the duty detection circuit 21 and subjected to duty detection.
- the duty detection result output from the duty detection circuit 21 is supplied to the duty control circuit 22 .
- the duty control circuit 22 Based on the duty detection result, the duty control circuit 22 generates the duty signal for controlling the duty adjustment performed by the duty adjustment circuit 23 .
- the duty adjustment circuit 23 Based on the duty signal, the duty adjustment circuit 23 adjusts the duty of the clock signal output from the initial circuit 11 .
- the details of the duty detection circuit 21 will be described later.
- the DLL clock detection circuit 31 receives the DLL clock detection enable signal (from the DLL cycle counter 18 ) and the DLL clock signal (from the duty adjustment circuit 23 ), wherein the DLL clock detection circuit 31 is periodically activated by the DLL clock detection enable signal.
- the period of the DLL clock detection enable signal is identical to the update period for updating the duty.
- the DLL clock detection circuit 31 detects either a clocking state or a non-clocking state with respect to the DLL clock signal, thus outputting the DLL clock detection result (or the update enable/disable signals) to the DLL cycle counter 18 and the duty detection circuit 21 .
- the DLL clock detection circuit 31 controls the DLL cycle counter 18 to output or stop the update clock signal while also controlling the duty adjustment circuit 23 to execute or stop the duty control.
- the second embodiment is designed such that the DLL clock detection result, which is produced by the DLL clock detection circuit 31 detecting either the clocking state or the non-clocking state with respect to the DLL clock signal, is fed back to the duty detection circuit 21 for producing the duty detection result, wherein the DLL clock signal is restored by means of the duty detection circuit 21 and the duty control circuit 22 .
- the constitution and operation of the duty detection circuit 21 will be described later in detail.
- the DLL circuit of FIG. 2 is designed such that the DLL clock detection circuit 31 is periodically activated in response to the DLL clock detection enable signal output from the DLL cycle counter 18 . It can be redesigned to normally activate the DLL clock detection circuit 31 .
- FIG. 3 shows a DLL circuit according to a third embodiment of the present invention, wherein parts identical to those shown in FIGS. 1 , 2 , and 9 are designated by the same reference numerals.
- the DLL circuit of FIG. 3 is designed to perform both the phase control and the duty control, wherein it is a combination of the DLL circuit of FIG. 1 achieving the phase control and the DLL circuit of FIG. 2 achieving the duty control.
- the DLL clock signal is supplied to the DQ replica circuit 15 having the same PVT dependency as the DQ buffer 14 . Since the DQ replica circuit 15 serves as a buffer circuit having the same dependency of process, voltage, and temperature as the DQ buffer 14 , the DQ replica output signal is output at the same timing as the DQ output signal.
- the DQ replica output signal of the DQ replica circuit 15 is supplied to the phase detection circuit 16 and subjected to phase comparison with the clock signals CK and /CK.
- the phase detection result output from the phase detection circuit 16 is supplied to the delay control circuit 13 , thus adjusting the delay time by way of the delay circuit 12 .
- the DDL clock signal is supplied to the duty detection circuit 21 and subjected to duty detection, so that the duty detection result is supplied to the duty control circuit 22 , thus adjusting the duty by way of the duty adjustment circuit 23 .
- the DLL clock detection circuit 31 is periodically activated by the DLL clock detection enable signal, wherein the period of the DLL clock detection enable signal is identical to the period for updating the delay time and duty.
- the DLL clock detection circuit 31 detects either the clocking state or the non-clocking state with respect to the DLL clock signal, thus generating the DLL clock detection result (or the update enable/disable signals).
- the DLL clock detection result is supplied to the delay control circuit 13 , the DLL cycle counter 18 , and the duty detection circuit 21 .
- the DLL cycle counter 18 outputs or stops the update clock signal while the delay control circuit 13 executes or stops updating the delay time.
- the duty detection circuit 21 , the duty control circuit 22 , and the duty adjustment circuit 23 collaborate to execute or stop updating the duty in accordance with the DLL clock detection result.
- the third embodiment is designed such that the DLL clock detection circuit 31 detects either the clocking state or the non-clocking state with respect to the DLL clock signal, and then the DLL clock detection result is supplied to the delay control circuit 13 , the DLL cycle counter 18 , and the duty control circuit 22 , thus inhibiting the delay control and the duty control in the non-clocking state of the DLL clock signal.
- the third embodiment is designed such that the DLL clock detection result, which is produced by the DLL clock detection circuit 31 detecting either the clocking state or the non-clocking state with respect to the DLL clock signal, is fed back to the duty detection circuit 21 producing the duty detection result, wherein the DLL clock signal is restored by way of the duty detection circuit 21 and the duty control circuit 22 .
- the constitution and operation of the duty detection circuit 21 will be described later in detail.
- the delay-locked control of the DLL circuit of the third embodiment it is possible to prevent the delay time and the duty from being updated based on the phase detection result and the duty detection result which are erroneously produced in the disappearance period of the DLL clock signal.
- the DLL circuit of FIG. 3 is designed such that the DLL clock detection circuit 31 is periodically activated in response to the DLL clock detection enable signal output from the DLL cycle counter 18 . It can be redesigned to normally activate the DLL clock detection circuit 31 .
- FIG. 4 shows the detailed constitution of the DLL clock detection circuit 31 .
- the DLL clock detection enable signal from the DLL cycle counter 18 is supplied to an inverter 101 of the DLL clock detection circuit 31 .
- the output signal of the inverter 101 is supplied to reset terminals R of D-type latch circuits 105 and 106 (having data terminals D, output terminals Q, and clock terminals C) as well as a first input terminal “a” of an RS-type latch circuit 104 including NAND circuits 102 and 103 .
- the first input terminal “a” corresponds to one input terminal of the NAND circuit 102
- a second input terminal “b” corresponds to one input terminal of the NAND circuit 103
- the NAND circuits 102 and 103 are coupled together such that an output terminal “c” of the NAND circuit 102 is connected to another input terminal of the NAND circuit 103 whose output terminal is connected to another input terminal of the NAND circuit 102 .
- the DLL clock detection circuit 31 includes a plurality of D-type latch circuits wherein the D-type latch circuit 105 is an uppermost one and is followed by the D-type latch circuit 106 .
- the date terminal D of the first D-type latch circuit 105 is connected to a power-supply voltage Vcc (at a high level) while an output terminal Q thereof is connected to the data terminal D of the second D-type latch circuit 106 .
- the D-type latch circuits 105 and 106 are followed by a NAND circuit 107 having three input terminals a 1 , a 2 , and a 3 such that the output terminal Q of the first D-type latch circuit 105 is connected to the first input terminal a 1 while the output terminal Q of the second D-type latch circuit 106 is connected to the second input terminal a 2 .
- Both the clock terminals C of the D-type latch circuits 105 and 106 receive the DLL clock signal subjected to detection.
- FIG. 4 shows the two D-type latch circuits 105 and 106 , whereas it is possible to incorporate three or more D-type latch circuits; hence, the output terminal Q of the third D-type latch circuit (not shown) is connected to the third input terminal a 2 of the NAND circuit 107 , wherein the data terminal D thereof is connected to the output terminal Q of the second D-type latch circuit 106 .
- fourth and other D-type latch circuits can be incorporated into the DLL clock detection circuit 31 .
- the DLL clock detection enable signal becomes high so as to activate the DLL clock detection circuit 31 , wherein a low-level output signal of the inverter 101 is supplied to the reset terminals R of the D-type latch circuits 105 and 106 so as to release the reset states of the D-type latch circuits 105 and 106 , so that the output terminals Q of the D-type latch circuits 105 and 106 are each turned to a low level.
- the input terminals a 1 and a 2 of the NAND circuit 107 are each set at a low level, so that the output signal of the NAND circuit 107 is at a high level which is applied to the second input terminal b of the RS-type latch circuit 104 . Since the low-level output signal of the inverter 101 is supplied to the first input terminal a 1 (corresponding to one input terminal of the NAND circuit 102 ), the output terminal c of the NAND circuit 102 becomes high, so that the output signal OUT (corresponding to the output terminal of the NAND circuit 103 ) becomes low. That is, just after the DLL clock detection circuit 31 is activated, the RS-type latch circuit 104 outputs the low-level output signal OUT serving as the update disable signal declaring the non-clocking state of the DLL clock signal.
- the output terminal Q of the D-type latch circuit 105 becomes high while the output terminal Q of the D-type latch circuit 106 remains low.
- FIG. 5A shows the counter clock signal, which is generated by the counter clock generation circuit 17 based on the clock signal of the initial circuit 11 and supplied to the DLL cycle counter 18 .
- FIG. 5B shows the DLL clock detection enable signal including pulses C 1 and C 2 , which is generated by the DLL cycle counter 18 and is supplied to the DLL clock detection circuit 31 .
- FIG. 5C shows a fractional clock signal including pulses B 1 and B 2 , the frequency of which is a fraction of the frequency of the counter clock signal subjected to frequency dividing in the DLL cycle counter 18 .
- FIG. 5D shows the DLL clock signal output from the delay circuit 12 .
- FIG. 5E shows the DLL clock detection result produced by the DLL clock detection circuit 31 , wherein the DLL clock detection result becomes high to serve as the update enable signal or becomes low to serve as the update disable signal.
- FIG. 5F shows the update clock signal including a pulse K 1 output from the DLL cycle counter 18 .
- the DLL clock signal Due to the non-clocking state of the DLL clock signal occurring at the timing when the DLL clock detection circuit 31 starts detecting either the clocking state or the non-clocking state of the DLL clock signal in response to the pulse C 2 of the DLL clock detection enable signal of FIG. 5B , the DLL clock signal is stacked to a low level so that the DLL clock detection result of FIG. 5E becomes low, wherein the DLL cycle counter 18 stops generating a pulse of the update clock signal of FIG. 5F .
- the delay circuit 12 and the delay control circuit 13 stop updating the delay time, while the duty control circuit 22 and the duty adjustment circuit 23 stop updating the duty.
- FIGS. 6A to 6J show waveforms of signals based on simulation of the DLL clock detection circuit 31 . Specifically, FIGS. 6A to 6E show the waveforms of signals in the clocking state of the DLL clock signal, while FIGS. 6F to 6J show the waveforms of signals which are temporarily varied due to disappearance of pulses in the DLL clock signal.
- the waveforms of signals shown in FIGS. 6A to 6J are drafted in connection with the DLL clock detection circuit 31 of FIG. 4 including the two D-type latch circuits 105 and 106 , wherein a high-level period of a pulse of the DLL clock detection enable signal corresponds to two cycles of pulses of the DLL clock signal.
- the DLL clock detection result of FIG. 6C becomes high time t 2 in synchronization with the leading edge of a pulse C 1 which is a second pulse of the DLL clock signal of FIG. 6B counted after time t 1 when the DLL clock detection enable signal of FIG. 6A becomes high.
- the update enable/disable signal of FIG. 6D becomes high (declaring the update enable state) and is supplied to the delay control circuit 13 , the DLL cycle counter 18 , and the duty detection circuit 21 .
- the update clock signal of FIG. 6E becomes high at time t 4 so as to activate the delay control circuit 13 and the duty control circuit 22 .
- the delay control circuit 13 controls the delay circuit 12 to adjust the delay time applied to the DLL clock signal.
- the duty control circuit 22 controls the duty adjustment circuit 23 to adjust the duty of the DLL clock signal, which is thus set to 50%.
- the DLL clock detection circuit 31 starts detecting either the clocking state or the non-clocking state of the DLL clock signal.
- the DLL clock detection result of FIG. 6H becomes low at time t 1
- the update enable/disable signal of FIG. 6I becomes low (declaring the update disable state) at time t 3 . That is, the update disable signal is supplied to the delay control circuit 13 , the DLL cycle counter 18 , and the duty detection circuit 21 .
- the DLL cycle counter 18 does not generate a pulse of the update clock signal shown in FIG. 6J , thus stopping updating the delay control circuit 13 and the duty detection circuit 21 . Therefore, the duty detection circuit 21 and the duty control circuit 22 stop updating the duty of the DLL clock signal, while the delay circuit 12 and the delay control circuit 13 stop updating the delay time applied to the DLL clock signal. For this reason, the previous duty and the previous delay time are maintained with respect to the DLL clock signal.
- FIG. 7 shows the detailed constitution of the delay control circuit 13 , which is designed to determine the delay time of the delay circuit 12 based on the phase detection result produced by the phase detection circuit 16 .
- the delay control circuit 13 is constituted of an adder 201 , D-type latch circuits 202 , 203 , and 204 (having data terminals D, output terminals Q, and clock terminals C), and an AND circuit 205 . All the output terminals Q of the D-type latch circuits 202 , 203 , and 204 are connected to the adder 201 , which also receives the phase detection result (representing a count-up signal UP and a count-down signal DOWN) output from the phase detection circuit 16 .
- the adder 201 outputs three output signals to the date terminals D of the D-type latch circuits 202 , 203 , and 204 respectively.
- a first input terminal of the AND circuit 205 receives the update clock signal from the DLL cycle counter 18 , while a second input terminal thereof receives the DLL clock detection result (i.e. the update enable/disable signals) from the DLL clock detection circuit 31 .
- the output terminal of the AND circuit 205 is connected to the clock terminals C of the D-type latch circuits 202 , 203 , and 204 respectively.
- the D-type latch circuits 202 , 203 , and 204 latch respective delay times, which are supplied to the adder 201 .
- the adder 201 Upon reception the phase detection signal (representing either the counter-up signal UP or the count-down signal DOWN), the adder 201 update the present delay time by increasing or decreasing.
- the output signal of the adder 201 (representing the updated delay time) is latched by the D-type latch circuits 202 to 204 , from which it is supplied to the delay circuit 12 .
- the output signal of the AND circuit 205 becomes low so that the updated delay time of the adder 201 is not latched by the D-type latch circuits 202 to 204 .
- the D-type latch circuits 202 to 204 are not updated so as to still retain the previous delay time.
- FIG. 7 shows the three D-type latch circuits 202 to 204 , whereas the number of D-type latch circuits included in the delay control circuit 13 can be increased to four or more as necessary.
- the duty detection circuit 21 is designed to detect the duty of the DLL clock signal compared to the reference duty ratio of 50%.
- an inverter 301 receives the DLL clock detection result (i.e. the update enable/disable signals) from the DLL clock detection circuit 31 so as to provide an output signal thereof to an inverter 302 and an ON/OFF control terminal S of a selector 306 .
- the DLL clock detection result i.e. the update enable/disable signals
- the DLL clock signal is supplied to a duty detector 303 and a data terminal D of a D-type latch circuit 304 .
- the output signal of the duty detector 303 is supplied to a first input terminal “a” of the selector 306 .
- the output signal of the D-type latch circuit 304 at its output terminal Q is inverted in logic level by an inverter 305 and is then supplied to a second input terminal “b” of the selector 306 .
- the duty detector 303 detects whether the duty (i.e. the high-level period of a pulse of the DLL clock signal) is greater or less than 50%, thus producing the duty detection result. In the case of FIG. 8B in which the duty is greater than 50%, the duty detector 303 outputs a duty decrease signal (i.e. a low-level signal) to the first input terminal “a” of the selector 306 . In the case of FIG. 8C in which the duty is less than 50%, the duty detector 303 outputs a duty increase signal (i.e. a high-level signal) to the first input terminal “a” of the selector 306 .
- a duty decrease signal i.e. a low-level signal
- the selector 306 switches over to the first input terminal “a” so as to select the duty detection result of the duty detector 303 , which is then output to the duty control circuit 22 .
- the selector 306 switches over to the second input terminal “b” so as to select the output signal of the inverter 305 , which is then output to the duty control circuit 22 .
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Abstract
Description
- Patent Document 1: Japanese Unexamined Patent Application Publication No. 2002-42469
Claims (20)
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US14/020,445 USRE45604E1 (en) | 2008-05-16 | 2013-09-06 | DLL circuit adapted to semiconductor device |
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JP2008-129638 | 2008-05-16 | ||
JP2008129638A JP2009278528A (en) | 2008-05-16 | 2008-05-16 | Dll circuit, and semiconductor device |
US12/465,355 US8013645B2 (en) | 2008-05-16 | 2009-05-13 | DLL circuit adapted to semiconductor device |
US14/020,445 USRE45604E1 (en) | 2008-05-16 | 2013-09-06 | DLL circuit adapted to semiconductor device |
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US12/465,355 Reissue US8013645B2 (en) | 2008-05-16 | 2009-05-13 | DLL circuit adapted to semiconductor device |
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US14/020,445 Active USRE45604E1 (en) | 2008-05-16 | 2013-09-06 | DLL circuit adapted to semiconductor device |
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KR100930416B1 (en) * | 2008-08-11 | 2009-12-08 | 주식회사 하이닉스반도체 | Semiconductor integrated circuit and method of controlling the same |
KR101008990B1 (en) | 2008-12-05 | 2011-01-17 | 주식회사 하이닉스반도체 | Buffer enable signal generating circuit and input circuit using the same |
JP2011142566A (en) * | 2010-01-08 | 2011-07-21 | Elpida Memory Inc | Semiconductor device |
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US20090284290A1 (en) | 2009-11-19 |
US8013645B2 (en) | 2011-09-06 |
JP2009278528A (en) | 2009-11-26 |
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