WO2018004242A1 - Electrical overload protection device - Google Patents

Electrical overload protection device Download PDF

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Publication number
WO2018004242A1
WO2018004242A1 PCT/KR2017/006799 KR2017006799W WO2018004242A1 WO 2018004242 A1 WO2018004242 A1 WO 2018004242A1 KR 2017006799 W KR2017006799 W KR 2017006799W WO 2018004242 A1 WO2018004242 A1 WO 2018004242A1
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WO
WIPO (PCT)
Prior art keywords
package
electrodes
input
sheet layer
electrode
Prior art date
Application number
PCT/KR2017/006799
Other languages
French (fr)
Korean (ko)
Inventor
이재욱
류재수
황윤호
문지우
구유경
구자윤
Original Assignee
주식회사 아모텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020160081860A external-priority patent/KR102063669B1/en
Priority claimed from KR1020170071609A external-priority patent/KR102044408B1/en
Application filed by 주식회사 아모텍 filed Critical 주식회사 아모텍
Publication of WO2018004242A1 publication Critical patent/WO2018004242A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/14—Protection against electric or thermal overload
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/06—Frequency selective two-port networks including resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/09—Filters comprising mutual inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields

Definitions

  • the present invention relates to an electrical overload protection device, and more particularly, to an electrical overload protection device that can simultaneously implement a low capacitance and a protection against static electricity and electrical overload to be suitable for high-speed signal lines.
  • EOS electric overstress
  • Such an electrical overload is a relatively low voltage compared to electrostatic discharge (ESD), but is applied for a relatively long time, which may cause breakdown of the insulating layer of the internal circuit, thereby preventing inflow into the internal circuit. It is necessary to do
  • TVS transient voltage suppressor
  • varistors are used to protect the electrical overload occurring in the main circuit.
  • TVS transient voltage suppressor
  • varistors are used to protect the electrical overload occurring in the main circuit.
  • these devices have high capacitance, they are adversely affected when used in high-speed signal lines.
  • the band of the filter for the conventional ESD or EOS blocking may block the ESD and EOS, but can attenuate high-speed transmission data similar in frequency band. Therefore, there is a need for provision of an electrostatic discharge protection measure corresponding to an increase in data transmission speed.
  • the present invention has been made in view of the above, and an object thereof is to provide an electrical overload protection device having a low capacitance to be suitable for use in a high-speed signal line as well as a protection against electrical overload and static electricity.
  • another object of the present invention is to provide an electrical overload protection device capable of blocking ESD and EOS as well as preventing attenuation of a transmission signal by applying a series capacitor to a high-speed signal line.
  • the present invention includes a first package including one or both of a filter unit for filtering a high-speed signal, and a protection unit having a protection function against electrical overload and static electricity; A second package including a forward diode connected in series to the protection unit, the second package being flip-chip bonded and stacked on the first package; And a molding part for molding the second package.
  • the first package may include the filter unit, and the second package may include the protection unit.
  • the second package may be configured as a single package of the forward diode.
  • the protection unit may be a varistor
  • the first package may include at least one of the filter unit and the varistor.
  • the protection unit may be a zener diode, and the second package may include the zener diode and the forward diode.
  • the first package a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sheet layers; A first electrode spaced at a predetermined interval between the pair of ground electrodes on the first sheet layer on the top; A plurality of second electrodes disposed on the second sheet layer below the first sheet layer to partially overlap the first electrode and connected to any one of the plurality of input / output electrodes; And a plurality of resistors connected to any one of the plurality of input / output electrodes in the plurality of sheet layers below the second sheet layer, wherein the resistors provided on adjacent sheet layers are connected through via holes and face each other. It can be connected to the input and output electrode.
  • the first package may include a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sequentially stacked sheet layers; And a plurality of coil patterns connected to any one of the plurality of input / output electrodes in the plurality of sheet layers, wherein the coil patterns provided on the sheet layers that are cross-laminated among the plurality of sheet layers are connected through via holes. It may be connected to input and output electrodes facing each other.
  • the first package a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sheet layers; And a plurality of capacitor electrodes connected to any one of the plurality of input / output electrodes in the plurality of sheet layers, wherein the capacitor electrodes provided on the sheet layers stacked in the plurality of sheet layers overlap each other.
  • the first package a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sheet layers; A first electrode spaced at a predetermined interval between the pair of ground electrodes on the first sheet layer on the top; And a plurality of second electrodes disposed on the second sheet layer below the first sheet layer to partially overlap with the first electrode, and connected to input / output electrodes facing each other among the plurality of input / output electrodes. .
  • the second package may include a pair of drawing electrodes provided on both sides in one direction from a lower surface thereof; And a plurality of diode electrodes provided on at least one side of the other direction perpendicular to the pair of lead electrodes.
  • the high speed signal may be a signal of any one of low voltage differential signaling (LVDS), high definition multimedia interface (HDMI), universal serial bus (USB), V by 1, and USB 3.0 / 3.1.
  • LVDS low voltage differential signaling
  • HDMI high definition multimedia interface
  • USB universal serial bus
  • the present invention is a plurality of sheet layer; A ground electrode formed on the first sheet layer; An inner electrode formed on the second sheet layer stacked on the first sheet layer and connected to the first outer electrode; And a resistor formed on the third sheet layer stacked on the second sheet layer and connected to the second external electrode.
  • the ground electrode, the inner electrode, the inner electrode, and the resistor are disposed to face each other.
  • the present invention by connecting the forward diode in series with the protection function to reduce the total capacitance, it is possible to perform the electrical overvoltage protection and the electrostatic protection while suppressing the attenuation of the high-speed data signal.
  • the present invention can package a filter according to the type of high-speed signal line and flip-chip bonded and stacked a forward diode on the package, so that a single package can be easily implemented and manufacturing efficiency can be improved.
  • the present invention can configure a high pass filter by applying a series capacitor to the high-speed signal line, it is possible to block the ESD and EOS without attenuation of the high-speed data signal.
  • FIG. 1 is a perspective view showing an electrical overload device according to a first embodiment of the present invention
  • FIG. 2 is a perspective view of the protective part of FIG.
  • FIG. 3 is an exploded perspective view of the protective part of FIG.
  • FIG. 4 is an equivalent circuit diagram of FIG. 1;
  • FIG. 5 is a perspective view showing an electrical overload device according to a second embodiment of the present invention.
  • FIG. 6 is a perspective view of the protective part of FIG.
  • FIG. 7 is an exploded perspective view of the protection unit of FIG. 6, FIG.
  • FIG. 8 is a bottom perspective view of the second package of FIG. 5;
  • FIG. 9 is an equivalent circuit diagram of a second package of FIG. 8.
  • FIG. 10 is an equivalent circuit diagram of FIG. 5;
  • FIG. 11 is a perspective view showing an electrical overload device according to a third embodiment of the present invention.
  • FIG. 12 is an exploded perspective view of the protection unit of FIG. 11;
  • FIG. 13 is an equivalent circuit diagram of FIG.
  • FIG. 14 is a perspective view showing an electrical overload device according to a fourth embodiment of the present invention.
  • FIG. 15 is an exploded perspective view of the protection unit of FIG. 14,
  • FIG. 16 is an equivalent circuit diagram of FIG. 14;
  • FIG. 17 is a cross-sectional view showing an electrical overload device according to a fifth embodiment of the present invention.
  • FIG. 18 is an equivalent circuit diagram of FIG. 17;
  • FIG. 19 is a characteristic graph of a resistance applied in FIG. 18,
  • FIG. 22 is an equivalent circuit diagram including an inductor in FIG. 18;
  • FIG. 24 is an equivalent circuit diagram including a bypass resistor in FIG. 18;
  • FIG. 25 is a test result table of clamp voltages according to resistance values of resistors and bypass resistors applicable to FIG. 24, and
  • FIG. 26 is a characteristic graph of the bypass resistance applied in FIG. 24.
  • Electrical overload protection device 100, 200, 300, 400 according to the present invention, as shown in Figures 1, 5, 11 and 14, the first package (110, 210, 310, 410), the second package (120, 220, 320, 420) and the molding unit (130, 230, 330, 430) do.
  • the electrical overload protection devices 100, 200, 300, and 400 are protection devices for high-speed signal lines, and include low voltage differential signaling (LVDS), high definition multimedia interface (HDMI), universal serial bus (USB), V by 1, and USB 3.0 / 3.1. It may be a protection element for any one signal line.
  • LVDS low voltage differential signaling
  • HDMI high definition multimedia interface
  • USB universal serial bus
  • V by 1, and USB 3.0 / 3.1 It may be a protection element for any one signal line.
  • the electrical overload protection device (100, 200, 300, 400) has a function to protect against electrical overload (EOS) and static electricity (ESD), is disposed on the signal line as described above, is connected to the ground of the circuit board. Accordingly, the electrical overload protection device (100, 200, 300, 400) bypasses the electrical overload (EOS) and electrostatic discharge (ESD) to the ground to block the electrical overload (EOS) and static electricity (ESD) to enter the internal circuit to protect the internal circuit can do.
  • EOS electrical overload
  • ESD electrostatic discharge
  • the first packages 110 and 410 include a filter unit for filtering a high speed signal and a protection unit having a protection function against electrical overload and static electricity, and the second packages 120 and 420 include a forward diode connected in series to the protection unit.
  • the protection part includes a varistor or a zener diode, has a high capacitance, and the forward diode is made of a separate package and has a low capacitance.
  • the high capacitance protection part is connected in series with the low capacitance forward diode so that the total capacitance between the signal output terminal and ground becomes smaller than the capacitance of the forward diode.
  • an electrical overload (EOS) and an electrostatic (ESD) protection function can be performed while suppressing attenuation of a high speed data signal.
  • the forward diode is flip-chip bonded and stacked on the first packages 110 and 410. That is, since the forward diode is a package of a single component, the forward diode is flip-chip bonded and laminated on the first packages 110 and 410, whereby the electrical overload protection devices 100 and 400 can be easily implemented in a single package, and at the same time, manufacturing efficiency is achieved. Can improve.
  • the filter unit may be a filter implemented according to the type of the high speed signal line, and may be a high pass filter.
  • the filter unit may be formed of a capacitor, a resistor, a transformer, or a capacitor.
  • the protection unit may be implemented in the second packages 220 and 320. That is, the first packages 210 and 310 include only the filter unit, and the second packages 220 and 320 include the protection unit together with the forward diode.
  • the protection unit may be a zener diode. That is, the second packages 220 and 320 may be a single package consisting of the forward diode and the zener diode.
  • the second packages 220 and 320 may be flip chip bonded to the first packages 210 and 310 so that electrodes may be disposed on the bottom surface of the package so as to be stacked.
  • the first packages 210 and 310 are manufactured using the existing filter manufacturing process, and the second packages 220 and 320 are manufactured using the diode manufacturing process, thereby easily implementing a single package of the electrical overload protection device 200 and 300.
  • the second package (220,320) to the outer periphery can improve the manufacturing efficiency.
  • the molding parts 130, 230, 330, and 430 are molded to cover top surfaces of the first packages 110, 210, 310, 410 and the second packages 120, 220, 320, and 420 stacked on the second packages 120, 220, 320, and 420. That is, the molding parts 130, 230, 330, and 430 mold the forward diode.
  • Electrical overload protection device 100 is a protection device for LVDS or HDMI signal line, as shown in Figure 1, the first package 110, the second package 120, and The molding part 130 is included.
  • the first package 110 may include a protection unit and a filter unit
  • the second package 120 may include a forward diode made of a single package. That is, the first package 110 may be a package in the form of a protection device, and the second package 120 may be a package composed of a single component.
  • the protection part may be a varistor
  • the filter part may be a high pass filter including a resistor and a capacitor.
  • the first package 110 includes a plurality of sheet layers 111-1 to 111-7, a pair of ground electrodes 112a and 112b, a pair of input / output electrodes 113a and 113b, a first electrode 114, A plurality of second electrodes 115a and 115b and a plurality of resistors 116a to 119a and 116b to 119b may be included.
  • the plurality of sheet layers 111-1 to 111-7 may be body bodies.
  • the first sheet layer 111-1 and the second sheet layer 111-2 correspond to the protection part
  • the third sheet layer 111-3 is a buffer layer for distinguishing the protection part and the filter part.
  • the remaining sheet layers 111-4 to 111-7 correspond to the filter portion (see FIG. 3).
  • the plurality of sheet layers 111-1 to 111-7 may include a varistor material layer and a dielectric.
  • the pair of ground electrodes 112a and 112b may be provided in a 'c' shape on both sides of one direction of the first package 110. That is, each of the pair of ground electrodes 112a and 112b may be formed over a portion of the side, top and bottom surfaces of the first package 110 (see FIG. 2).
  • the ground electrodes 112a and 112b are connected to the ground of the circuit board when the electrical overload protection device 100 is disposed on the high speed signal line.
  • the plurality of input / output electrodes 113a and 113b may be provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes 112a and 112b. That is, each of the plurality of input / output electrodes 113a and 113b may be formed over a part of the side surface, the upper surface, and the lower surface of the first package 110 (see FIG. 2).
  • the input / output electrodes 113a and 113b are connected to a high speed signal line.
  • the first electrode 114 is spaced at a predetermined interval between the pair of ground electrodes 112a and 112b on the first sheet layer 111-1 disposed at the top of the plurality of sheet layers 111-1 to 111-7. May be arranged (see FIG. 2).
  • the first electrode 114 is an electrode for connecting to the forward diode as one side of the varistor.
  • the plurality of second electrodes 115a and 115b may be partially overlapped with the first electrode 114 on the second sheet layer 111-2 below the first sheet layer 111-1 (FIG. 3).
  • the second electrodes 115a and 115b may be connected to one of the plurality of input / output electrodes 113a and 113b as the other electrode of the varistor, respectively.
  • the plurality of resistors 116a to 119a and 116b to 119b may be disposed on the plurality of sheet layers 111-4 to 111-7 below the second sheet layer 111-2 (see FIG. 3). In this case, the plurality of resistors 116a to 119a and 116b to 119b may be connected to one of the plurality of input / output electrodes 113a and 113b, respectively.
  • the resistors 116a and 116b are disposed on the fourth sheet layer 111-4 and disposed at one edge of the fourth sheet layer 111-4 so that one side thereof is connected to the input / output electrode 113b.
  • the side is disposed in the central portion, and may extend in a spiral shape therebetween.
  • the resistors 117a and 117b are disposed on the fifth sheet layer 111-5, and the other side of the fifth sheet layer 111-5 so that one side thereof is connected to the input / output electrode 113a opposite to the input / output electrode 113b. It is disposed on the edge, and the other side is disposed in the center portion, and may extend in a predetermined shape therebetween.
  • the resistors 116a and 117a provided in the adjacent sheet layers are connected through the via holes 116a-1 and 117a-1 at the center portion, and the resistors 116b and the resistor 117b are via holes 116b at the center portion. -1,117b-1) may be connected.
  • the resistors 118a and 118b are disposed on the sixth sheet layer 111-6 and disposed at one edge of the sixth sheet layer 111-6 so that one side thereof is connected to the input / output electrode 113a.
  • the other side is disposed in the central portion, and may extend in a predetermined shape therebetween.
  • the resistors 119a and 119b are disposed on the seventh sheet layer 111-7 and the other side of the seventh sheet layer 111-7 so that one side thereof is connected to the input / output electrode 113b opposite to the input / output electrode 113a. It is disposed at the edge, the other side is disposed in the central portion, and may extend in a spiral shape therebetween.
  • the resistors 118a and 119a provided in the adjacent sheet layers are connected through the via holes 118a-1 and 119a-1 at the center portion, and the resistors 118b and the resistor 119b are via holes 118b at the center portion. -1, 119b-1) can be connected.
  • the resistors 116a to 119a and 116b to 119b are not limited to the shapes described above, but may have various forms.
  • the second package 120 may be a forward diode composed of one single component.
  • the electrical overload protection device 100 may include two second packages 120. That is, the electrical overload protection device 100 may include two forward diodes.
  • Each second package 120 may be disposed between the first electrode 114 and the pair of ground electrodes 112a and 112b.
  • the second package 120 may be stacked by flip chip bonding on the first electrode 114 and the ground electrode 112a or on the first electrode 114 and the ground electrode 112b.
  • the forward diode may be connected in series with the protection unit between the input / output electrodes 113a and 113b and the ground electrodes 112a and 112b.
  • the molding part 130 is molded to cover the top surfaces of the second package 120 and the first package 110.
  • the electrical overload protection device 100 may form a plurality of individual packages into one package.
  • the electrical overload protection device 100 configured as described above is equivalent to a resistor and a pair of varistors between the input / output electrodes c to j and a forward diode connected to the ground electrodes a and b. It can be represented by a circuit.
  • the varistor and the forward diode are connected in series between the input / output electrodes c to j and the ground electrodes a and b, so that the total capacitance between the input and output electrodes c to j and the ground electrodes a and b is increased. It is possible to form smaller capacitances than forward diodes with lower capacitance.
  • a high pass filter may be formed by a capacitance between the input / output electrodes c to j and the ground electrodes a and b and a resistance between the input and output electrodes c to j.
  • the electrical overload protection device 100 may provide a protection function of the electrical overload (EOS) and the static electricity (ESD) while minimizing the attenuation of the signal with respect to the high speed signal.
  • the electrical overload protection device 200 is a protection device for any one of the signal lines of LVDS, HDMI, and USB, and includes a first package 210 and a first package. 2 package 220, and the molding unit 230.
  • the first package 210 may include only the filter unit, and the second package 220 may include a protection unit and a plurality of forward diodes.
  • the protection unit may be a zener diode
  • the filter unit may be a high pass filter made of a transformer.
  • the first package 210 may be a filter-type package
  • the second package 220 may be a package including a plurality of forward diodes and one zener diode as a single component.
  • the first package 210 includes a plurality of sheet layers 211-1 to 211-5, a pair of ground electrodes 212a and 212b, a pair of input / output electrodes 213a and 213b, and a plurality of coil patterns 215a. ⁇ 217a, 215b-217b).
  • the plurality of sheet layers 211-1 to 211-5 may be a body.
  • the first sheet layer 211-1 is a protective layer as the uppermost layer, and the remaining sheet layers 211-2 to 211-5 correspond to the filter portion (see FIG. 7).
  • the plurality of sheet layers 211-1 to 211-5 may include magnetic materials.
  • pair of ground electrodes 212a and 212b and the plurality of input / output electrodes 213a and 213b are the same as those of the pair of ground electrodes 112a and 112b and the plurality of input / output electrodes 113a and 113b of the first embodiment. Detailed description thereof will be omitted here (see FIG. 6).
  • the plurality of coil patterns 214a to 217a and 214b to 217b may be disposed on the plurality of sheet layers 211-2 to 211-5 below the first sheet layer 211-1 (see FIG. 7). In this case, the plurality of coil patterns 214a to 217a and 214b to 217b may be connected to one of the plurality of input / output electrodes 213a and 213b, respectively.
  • the coil patterns 214a and 214b are disposed on the second sheet layer 211-2, and disposed at one edge of the second sheet layer 211-2 so that one side thereof is connected to the input / output electrode 213b.
  • the other side is disposed in the center portion, and may extend in a spiral shape therebetween.
  • the coil patterns 215a and 215b are disposed on the third sheet layer 211-3 and disposed at the other edge of the third sheet layer 211-3 so that one side is connected to the input / output electrode 213b. It is disposed in the center portion, and may extend in a spiral shape therebetween.
  • the coil patterns 216a and 216b are disposed on the fourth sheet layer 211-4, and the fourth sheet layer 211 is connected to the input / output electrode 213a opposite to the input / output electrode 213b. It is disposed on one side edge of -4), the other side is disposed in the center portion, and may extend in a spiral shape therebetween.
  • the coil patterns 217a and 217b are disposed on the fifth sheet layer 211-5, and one side of the fifth sheet layer 211-5 is connected to the input / output electrode 213a opposite to the input / output electrode 213b. It is disposed on the other edge, the other side is disposed in the central portion, and may extend in a spiral shape therebetween.
  • the coil patterns 214a and the coil patterns 216a provided in the sheet layers that are cross-laminated among the plurality of sheet layers 211-2 to 211-5 are provided with via holes 214a-1 and 216a-1 at the center thereof, and between them. It is connected through the through hole 215a-2 of the sheet layer 211-3 disposed of the coil pattern 214b and the coil pattern 216b at the center portion of the via holes 214b-1 and 216b-1 and the sheet layer ( It may be connected through the through hole 215b-2 of 211-3.
  • the coil pattern 215a and the coil pattern 217a are formed through the through holes 216a-2 of the sheet layers 211-4 and the via holes 215a-1 and 217a-1 disposed therebetween at the center portion.
  • the coil pattern 215b and the coil pattern 217b may be connected through the via holes 215b-1 and 217b-1 and the through hole 216b-2 of the sheet layer 211-4 at the center portion.
  • the coil patterns 214a to 217a and 214b to 217b are not limited to the shapes described above, but may have various forms.
  • the second package 220 includes a plurality of forward diodes and one zener diode.
  • the cathode of each of the plurality of forward diodes may be connected to the cathode of the zener diode
  • the anode of each of the plurality of forward diodes may be connected to the diode electrode 223b
  • the anode of the zener diode may be connected to the extraction electrodes 222a and 222b. (See FIG. 9).
  • the forward diode is shown and described as being connected to only one diode electrode 223b of the second package 220, but is not limited thereto and may be provided to be connected to both diode electrodes 223a and 223b.
  • the second package 220 is connected to the ground electrodes 212a and 212b and the input / output electrodes 213a and 213b provided on the upper surface of the first package 210 so that the second package 220 may be flip-chip bonded and stacked on the first package 210.
  • a corresponding pair of lead electrodes 222a and 222b and a plurality of diode electrodes 223a and 223b are provided on the bottom surface.
  • the pair of lead electrodes 222a and 222b may be provided at both sides of one direction of the second package 220, and the plurality of diode electrodes 223a and 223b may be perpendicular to the lead electrodes 222a and 222b. It may be provided on at least one side of the.
  • the second package 220 is flip-chip bonded and stacked on the first package 210 so that each forward diode is connected to the input / output electrodes 213a and 213b through the diode electrodes 223a and 223b, and the zener It may be connected to the ground electrodes 212a and 212b through the lead electrodes 222a and 222b via the diode. Therefore, each of the forward diodes may be connected in series with a zener diode as a protection part between the input / output electrodes 213a and 213b and the ground electrodes 212a and 212b.
  • the molding part 230 is molded to cover the top surfaces of the second package 220 and the first package 210.
  • the electrical overload protection device 200 may form a plurality of individual packages into one package.
  • the electrical overload protection device 200 configured as described above is represented by an equivalent circuit of a forward diode and a zener diode connected to the transformer and the ground electrodes a and b between the input / output electrodes c1 to j1 as shown in FIG. 10. Can be.
  • the Zener diode and the forward diode are connected in series between the input / output electrodes c1 to j1 and the ground electrodes a1 and b1, respectively, so that the total capacitance between the input / output electrodes c1 to j1 and the ground electrodes a1 and b1 is reduced.
  • a high pass filter may be formed by a capacitance between the input / output electrodes c1 to j1 and the ground electrodes a1 and b1 and a transformer between the input and output electrodes c1 to j1.
  • the electrical overload protection device 200 may provide a protection function of the electrical overload (EOS) and the static electricity (ESD) while minimizing the attenuation of the signal with respect to the high speed signal.
  • Electrical overload protection device 300 is a protection device for the V by 1 or USB 3.0 / 3.1 signal line, as shown in Figure 11, the first package 310, the second package 320 and the molding part 330.
  • the first package 310 may include only the filter unit, and the second package 320 may include a protection unit and a plurality of forward diodes.
  • the protection unit may be a zener diode
  • the filter unit may be a high pass filter made of a capacitor.
  • the first package 310 may be a package in the form of a filter
  • the second package 320 may be a package in which a plurality of forward diodes and one zener diode are composed of a single component.
  • the first package 310 includes a plurality of sheet layers 311-1 to 311-5, a pair of ground electrodes 312a and 312b, a pair of input / output electrodes 313a and 313b, and a plurality of capacitor electrodes 314a. , 315a, 314b, 315b).
  • the plurality of sheet layers 311-1 to 311-5 may be a body.
  • the first sheet layer 311-1 is a protective layer as the uppermost layer, and the remaining sheet layers 311-2 to 311-5 correspond to the filter portion (see FIG. 12).
  • the plurality of sheet layers 311-1 to 311-5 may include a dielectric.
  • pair of ground electrodes 312a and 312b and the plurality of input / output electrodes 313a and 313b are the same as those of the pair of ground electrodes 112a and 112b and the plurality of input / output electrodes 113a and 113b of the first embodiment. Detailed description is omitted here (see FIG. 11).
  • the plurality of capacitor electrodes 314a, 315a, 314b, and 315b may be disposed in the plurality of sheet layers 311-2 to 311-5 below the first sheet layer 311-1 (see FIG. 12). In this case, the plurality of capacitor electrodes 314a, 315a, 314b, and 315b may be connected to one of the plurality of input / output electrodes 313a and 313b, respectively.
  • the capacitor electrode 314a is disposed on the second sheet layer 311-2, and is disposed at one edge of the second sheet layer 311-2 so that one side is connected to the input / output electrode 313b, and the other side is It is disposed in the center portion, and may extend in a straight shape between.
  • the capacitor electrode 314b is disposed on the third sheet layer 311-3 and one edge of the third sheet layer 311-3 so that one side thereof is connected to the input / output electrode 313a opposite to the input / output electrode 313b.
  • the other side is disposed in the center portion, and may extend in a straight line therebetween.
  • the capacitor electrode 315a is disposed on the fourth sheet layer 311-4, and is disposed at one side edge of the fourth sheet layer 311-4 so that one side thereof is connected to the input / output electrode 313b.
  • the other side is disposed in the center portion, and may extend in a straight line between them.
  • the capacitor electrode 315b is disposed on the fifth sheet layer 311-5, and one side edge of the fifth sheet layer 311-5 is connected so that one side thereof is connected to the input / output electrode 313a opposite to the input / output electrode 313b.
  • the other side is disposed in the center portion, and may extend in a straight line therebetween.
  • the capacitor electrode 314a and the capacitor electrode 315a provided in the sheet layers stacked in a stack among the plurality of sheet layers 311-2 to 311-5 may be disposed to overlap each other.
  • the second package 320 includes a plurality of forward diodes and one zener diode.
  • the second package 320 is the same as the configuration of the second package 220 of the second embodiment, a detailed description thereof will be omitted.
  • the molding part 330 is molded to cover the top surfaces of the second package 320 and the first package 310.
  • the electrical overload protection device 300 may form a plurality of individual packages into one package.
  • the electrical overload protection device 300 configured as described above is represented by an equivalent circuit of a forward diode and a zener diode connected to the capacitor and the ground electrodes a2 and b2 between the input / output electrodes c2 ⁇ j2. Can be.
  • the Zener diode and the forward diode are connected in series between the input / output electrodes c2 ⁇ j2 and the ground electrodes a2 and b2, respectively, so that the total capacitance between the input and output electrodes c2 ⁇ j2 and the ground electrodes a2 and b2. Can form a smaller capacitance than the forward diode with lower capacitance.
  • a high pass filter may be formed by a capacitance between the input / output electrodes c2 ⁇ j2 and the ground electrodes a2 and b2 and a capacitor between the input / output electrodes c2 ⁇ j2.
  • the electrical overload protection device 300 may provide a protection function of the electrical overload (EOS) and the static electricity (ESD) while minimizing the attenuation of the signal with respect to the high speed signal.
  • Electrical overload protection device 400 is a protection device for the V by 1 or USB 3.0 / 3.1 signal line, as shown in Figure 14, the first package 410, the second package 420, and the molding unit 430.
  • the first package 410 may include a protection unit and a filter unit
  • the second package 420 may include a forward diode made of a single package. That is, the first package 410 may be a package in the form of a protection device, and the second package 420 may be a package composed of a single component.
  • the protection part may be a varistor
  • the filter part may be a high pass filter including a capacitor formed by the varistor and the forward diode.
  • the first package 410 includes a plurality of sheet layers 411-1 to 411-2, a pair of ground electrodes 412a and 412b, a pair of input / output electrodes 413a and 413b, a first electrode 414, And a plurality of second electrodes 415.
  • the plurality of sheet layers 411-1 to 111-2 may be a body.
  • the plurality of sheet layers 411-1 to 411-2 may include varistor material layers (see FIG. 15).
  • the pair of ground electrodes 412a and 412b, the plurality of input / output electrodes 413a and 413b, and the first electrode 414 are the pair of ground electrodes 112a and 112b and the plurality of input / output electrodes 113a of the first embodiment. 113b and the first electrode 114, the detailed description thereof is omitted here (see FIG. 14).
  • the plurality of second electrodes 415 may be partially overlapped with the first electrodes 414 on the second sheet layer 411-2 below the first sheet layer 411-1 (see FIG. 15). ).
  • the second electrode 415 may be connected to the plurality of input / output electrodes 413a and 413b as the other electrode of the varistor facing the first electrode 414, respectively. That is, the plurality of second electrodes 415 may be provided in a straight line connected to both edges of the second sheet layer 411-2.
  • the second package 420 may be a forward diode composed of one single component.
  • the second package 420 is the same as the configuration of the second package 120 of the first embodiment, a detailed description thereof will be omitted.
  • the second package 420 is flip-chip bonded and stacked on the first package 410 so that the forward diode is connected in series with the protection unit between the input / output electrodes 413a and 413b and the ground electrodes 412a and 412b. Can be connected.
  • the molding part 430 is molded to cover the top surfaces of the second package 420 and the first package 410.
  • the electrical overload protection device 400 may form a plurality of individual packages into one package.
  • the electrical overload protection device 400 configured as described above may be represented by an equivalent circuit of a varistor and a forward diode connected in series between the input / output electrodes c3 to j3 and the ground electrodes a3 and b3. .
  • the varistor and the forward diode are connected in series between the input / output electrodes c3 to j3 and the ground electrodes a3 and b3, so that the total capacitance between the input and output electrodes c3 to j3 and the ground electrodes a3 and b3 is reduced. It is possible to form smaller capacitances than forward diodes with lower capacitance.
  • a high pass filter may be formed by a capacitance between the input / output electrodes c3 ⁇ j3 and the ground electrodes a3 and b3.
  • EOS electrical overload
  • ESD static electricity
  • the electrical overload protection device 500 includes a plurality of sheet layers 541, 543, 545, 547, a ground electrode 542, an internal electrode 542, and a resistor 546. It includes.
  • the plurality of sheet layers 541, 543, 545, 547 may include a first sheet layer 541 having a ground electrode 542 and a second sheet layer 543 formed on the first sheet layer 541 with an internal electrode 544 formed thereon. And a third sheet layer 545 formed on the second sheet layer 543 and a fourth sheet layer 547 stacked on top of the third sheet layer 545. can do.
  • the first external electrode 548 electrically connected to the internal electrode 542 and the second external electrode 549 electrically connected to the resistor 546 may be formed on side surfaces of the first to fourth sheet layers 541, 143, 145 and 147. ) Is omitted and is omitted in the drawing, but further includes an external electrode connected to the ground electrode 542.
  • the external electrode connected to the ground electrode 542 may be located on the front or rear surface of the stack structure of the first to fourth sheet layers 541, 143, 145, and 147, or both the front and rear surfaces thereof.
  • the ground electrode 542 may be disposed in the center of the first sheet layer 541 so as not to be connected to both the first external electrode 548 and the second external electrode 549.
  • One end of the inner electrode 544 may be connected to the first outer electrode 548, and the other end thereof may be disposed to face the ground electrode 542.
  • One end of the resistor 546 is connected to the second external electrode 549, and the other end thereof is disposed to face the internal electrode 544, and may have a spiral structure having a plurality of bent portions on a plane.
  • the electrical overload protection device 500 includes a protection unit 510 having a protection function against electrical overload and static electricity, a capacitor 520 connected to one end of the protection unit 510, and It may be an RC circuit including a resistor 530 connected to the other end of the capacitor 520.
  • the resistor 546 corresponds to the resistor 530
  • the internal electrode 544 forms a contact point between the capacitor 520 and the protection unit 510 to correspond to one electrode of the capacitor 520 or the protection unit 510. do.
  • the capacitor 520 is defined as an overlapping region of the resistor 556 and the internal electrode 542 positioned with the third sheet layer 545 therebetween.
  • the third sheet layer 545 may be a dielectric having a predetermined dielectric constant.
  • the ground electrode 542 and the internal electrode 544 correspond to the protection unit 510.
  • the ground electrode 542 and the internal electrode 544 may be a gap or a discharge material filled in part or all of the gap. That is, the second sheet layer 543 may include a discharge material.
  • the protection unit 510 may be a suppressor or a varistor.
  • the capacitance of the capacitor 520 is lowered in the RC circuit, the value of the clamp voltage for confirming the ESD attenuation performance is also lowered, and the ESD operating voltage may be lowered.
  • the high-speed signal may not be transmitted normally due to the increase in the cutoff frequency.
  • the capacitor 520 and the resistor 530 each have an attenuation effect of ESD or EOS.
  • the attenuation effect can be increased by using the capacitor 520 and the resistor 530 composite device.
  • the electrical overload protection device 500 is illustrated and described as a composite device having a stacked structure in the present embodiment, the protection unit 510, the capacitor 520, and the resistor 530 are implemented as individual elements, respectively, in a block type. It can be implemented in a combined structure, it can also be implemented using a semiconductor manufacturing technology.
  • the electrical overload protection device 500 should be implemented as a high pass filter. Therefore, the capacitance of the capacitor 520 is preferably in the range of 10 to 1000 nF and the resistance 530 is in the range of 2 to 5 ⁇ .
  • the series resistance has a high pass characteristic regardless of the resistance value.
  • the high pass characteristic refers to a feature in which the attenuation is reduced above the cutoff frequency.
  • the larger the resistance value the higher the attenuation ratio in the 4GHz band, so that the high-speed signal can be attenuated. Therefore, as described above, it is preferable to use the resistor 530 having a resistance value of 2 to 5 ⁇ .
  • the high pass characteristic is very small at less than 2 ⁇ , and the attenuation ratio is large when exceeding 5 ⁇ , thereby increasing the probability of data loss due to attenuation during high-speed data transmission.
  • the series capacitance has the effect of a bandpass filter in various frequency bands, but has a low attenuation rate around 4 to 6 GHz for high-speed signals, and a high attenuation rate above 6 GHz.
  • Branches use a capacitor 520 of 10 to 1000 nF.
  • the high pass filter using the capacitor 520 and the resistor 530 composite element is effective for ESD and EOS protection while reducing the attenuation of the high speed signal.
  • the resistance value of the resistor 530 is fixed to 2 ⁇ , and the ESD protection test results for the two samples including a capacitor 520 having a capacitance of 10 nF and a capacitor 520 having a capacitance of 100 nF, respectively. 21 is shown.
  • the test was performed by increasing the ESD voltage from 2kV to 0.5kV. For each sample, a clamp voltage (Vp) indicating the ESD operating voltage and the ESD attenuation performance was measured, and the sample in which the suppressor was used alone as the protection unit 510 was used. Compared with.
  • the ESD operating voltage of the sample using only the suppressor was 3.5kV and the clamp voltage (Vp) was measured at 86V.
  • the ESD operating voltage is 2 to 2.5 kV and the clamp voltage Vp is 61 to. You can see that it is significantly lowered to 70V.
  • the inductor 550 may be further included in the equivalent circuit diagram of FIG. 18.
  • the RLC filter of FIG. 22 is a high pass filter and may transmit a high frequency signal of 4 GHz or more without attenuation.
  • the role of the inductor 550 is to provide a differential impedance.
  • the electrical overload protection device 500 when the electrical overload protection device 500 is applied to an electronic device using the USB 3.0 method, it is preferable to use the inductor 550 of 40 to 48 ⁇ H.
  • a bypass resistor 560 may be further added to the equivalent circuit diagram of FIG. 18.
  • bypass resistor 560 connects the contact of the capacitor 520 and the resistor 530 with the ground, and serves to bypass the overcurrent to the ground.
  • the clamping voltage increases as the value of the bypass resistor 560 increases.
  • the clamping voltages are 6.63 V, 22.59 V, and 30.81 V. , 46.0V.
  • the clamping voltage becomes lower.
  • the clamping voltages are 7.42V, 6.63V, 6.0V, You can see that it drops to 4.02V.
  • bypass resistor 560 When the bypass resistor 560 is added, it is necessary to change the value of the resistor 530 in consideration of the attenuation of the high speed signal and the clamping voltage, and the resistance value of the bypass resistor 560 is preferably 900 ⁇ to 1k ⁇ . Can be used.
  • the bypass resistor 560 preferably uses 900 ⁇ to 1 k ⁇ .
  • Electrical overload protection device (100, 200, 300, 400, 500) according to an embodiment of the present invention as described above is located in the signal transmission line between the signal input terminal and the internal circuit.
  • the internal circuit includes an integrated chip and is installed on an internal substrate of the electronic device.
  • the signal transmission line interconnects the signal input terminal and the internal circuit so that data input through the signal input terminal can be input to the internal circuit and processed.
  • the receiving line Rx and the transmission line Tx It can be understood as a concept that includes.
  • the signal transmission line may be a conductor patterned on an internal substrate or a conductor directly connecting the signal input terminal to an internal circuit.

Abstract

An electrical overload protection device is provided. An electrical overload protection device according to an embodiment of the present invention comprises: a filter part for filtering a high-frequency signal; a protection part having a protection function with respect to electrical overload and static electricity; a forward-biased diode connected to the protection part in series; and a moulding part for moulding the forward-biased diode. Wherein, a first package includes the filter part, a second package includes the forward-biased diode and is flip-chip laminated onto the first package, and either of the first package and the second package includes the protection part.

Description

전기적 과부하 보호소자Electrical overload protection device
본 발명은 전기적 과부하 보호소자에 관한 것으로, 더욱 상세하게는 고속 신호라인에 적합하도록 낮은 커패시턴스 및 정전기 및 전기적 과부하에 대한 보호기능을 동시에 구현할 수 있는 전기적 과부하 보호소자에 관한 것이다.The present invention relates to an electrical overload protection device, and more particularly, to an electrical overload protection device that can simultaneously implement a low capacitance and a protection against static electricity and electrical overload to be suitable for high-speed signal lines.
일반적으로, 전기적 과부하(EOS; electric overstress)는 예를 들면, 충전, 변압 및 모터 구동 회로 등 다양한 환경에서, 돌입 전류, 또는 기동 전류 형태로 발생한다. 이때, 비정상적인 전압의 증가로 인해 시스템에 스파크(spark)가 발생하여 구성 요소와 부품, 시스템에 손상을 초래한다. In general, electric overstress (EOS) occurs in the form of inrush current, or starting current, in various environments, such as, for example, charging, transformer, and motor drive circuitry. At this time, an abnormal increase in voltage causes sparks in the system, causing damage to components, components, and the system.
이와 같은 전기적 과부하는 정전기 방전(ESD; Electro Static Discharge)에 비하여 상대적으로 낮은 전압이지만, 상대적으로 긴 시간 동안 인가되는 것으로, 내부회로의 절연층의 파괴를 야기할 수 있어 내부회로로의 유입을 차단하는 것이 필요하다. Such an electrical overload is a relatively low voltage compared to electrostatic discharge (ESD), but is applied for a relatively long time, which may cause breakdown of the insulating layer of the internal circuit, thereby preventing inflow into the internal circuit. It is necessary to do
이와 같이 주요 회로에서 발생하는 전기적 과부하에 대한 보호를 위해 TVS(transient voltage suppressor)나 바리스터와 같은 소자를 이용하고 있으나, 이러한 소자들은 높은 커패시턴스를 갖기 때문에, 고속 신호라인에서 사용하는 경우, 신호에 악영향을 미친다. As such, devices such as TVS (transient voltage suppressor) and varistors are used to protect the electrical overload occurring in the main circuit. However, since these devices have high capacitance, they are adversely affected when used in high-speed signal lines. Crazy
따라서, 전기적 과부하 또는 정전기에 대한 보호기능과 함께 낮은 커패시턴스를 갖는 소자의 개발이 절실한 실정이다. Therefore, there is an urgent need to develop a device having a low capacitance along with a protection against electric overload or static electricity.
한편, 종래 ESD 또는 EOS 차단을 위한 필터의 대역은 ESD 및 EOS를 차단할 수는 있으나, 주파수 대역이 유사한 고속 전송 데이터를 감쇠시킬 수 있다. 따라서 데이터 전송 속도의 증가에 부합하는 정전방전 보호 대책의 마련이 요구되고 있다.On the other hand, the band of the filter for the conventional ESD or EOS blocking may block the ESD and EOS, but can attenuate high-speed transmission data similar in frequency band. Therefore, there is a need for provision of an electrostatic discharge protection measure corresponding to an increase in data transmission speed.
본 발명은 상기와 같은 점을 감안하여 안출한 것으로, 전기적 과부하 및 정전기에 대한 보호기능은 물론 고속 신호라인에서 사용이 적합하도록 낮은 커패시턴스를 갖는 전기적 과부하 보호소자를 제공하는데 그 목적이 있다.The present invention has been made in view of the above, and an object thereof is to provide an electrical overload protection device having a low capacitance to be suitable for use in a high-speed signal line as well as a protection against electrical overload and static electricity.
또한, 본 발명은 고속신호라인에 직렬 커패시터를 적용하여 전송 신호의 감쇠를 방지함과 아울러 ESD 및 EOS를 차단할 수 있는 전기적 과부하 보호소자를 제공하는데 다른 목적이 있다.In addition, another object of the present invention is to provide an electrical overload protection device capable of blocking ESD and EOS as well as preventing attenuation of a transmission signal by applying a series capacitor to a high-speed signal line.
상술한 과제를 해결하기 위하여 본 발명은 고속신호를 필터링하는 필터부, 및 전기적 과부하 및 정전기에 대한 보호기능을 갖는 보호부 중 하나 또는 둘 다를 포함하는 제1패키지; 상기 보호부에 직렬 연결되는 순방향 다이오드를 포함하며, 상기 제1패키지에 플립칩 본딩되어 적층되는 제2패키지; 및 상기 제2패키지를 몰딩하는 몰딩부;를 포함하는 전기적 과부하 보호소자를 제공한다. In order to solve the above problems, the present invention includes a first package including one or both of a filter unit for filtering a high-speed signal, and a protection unit having a protection function against electrical overload and static electricity; A second package including a forward diode connected in series to the protection unit, the second package being flip-chip bonded and stacked on the first package; And a molding part for molding the second package.
본 발명의 바람직한 실시예에 의하면, 상기 제1패키지가 상기 필터부를 포함하고, 상기 제2패키지가 상기 보호부를 포함할 수 있다. According to a preferred embodiment of the present invention, the first package may include the filter unit, and the second package may include the protection unit.
또한, 상기 제2패키지는 상기 순방향 다이오드가 단일 패키지로 구성될 수 있다.In addition, the second package may be configured as a single package of the forward diode.
또한, 상기 보호부는 바리스터이고, 상기 제1패키지는 상기 필터부 및 상기 바리스터 중 적어도 하나를 포함할 수 있다.The protection unit may be a varistor, and the first package may include at least one of the filter unit and the varistor.
또한, 상기 보호부는 제너다이오드이고, 상기 제2패키지는 상기 제너다이오드와 상기 순방향 다이오드를 포함할 수 있다.The protection unit may be a zener diode, and the second package may include the zener diode and the forward diode.
또한, 상기 제1패키지는, 일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; 상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; 복수 개의 시트층을 포함하는 소체; 최상위의 제1시트층 상에서 상기 한 쌍의 접지전극 사이에 일정간격 이격배치되는 제1전극; 상기 제1시트층 아래의 제2시트층 상에 상기 제1전극과 일부 중첩되게 배치되고, 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 제2전극; 및 상기 제2시트층 아래의 복수 개의 시트층에서 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 저항체;를 포함하고, 서로 인접한 시트층 상에 구비되는 저항체는 비아홀을 통하여 연결되며, 서로 대향하는 입출력전극에 연결될 수 있다. In addition, the first package, a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sheet layers; A first electrode spaced at a predetermined interval between the pair of ground electrodes on the first sheet layer on the top; A plurality of second electrodes disposed on the second sheet layer below the first sheet layer to partially overlap the first electrode and connected to any one of the plurality of input / output electrodes; And a plurality of resistors connected to any one of the plurality of input / output electrodes in the plurality of sheet layers below the second sheet layer, wherein the resistors provided on adjacent sheet layers are connected through via holes and face each other. It can be connected to the input and output electrode.
또한, 상기 제1패키지는 일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; 상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; 복수 개의 순차 적층되는 시트층을 포함하는 소체; 및 상기 복수 개의 시트층에서 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 코일패턴;을 포함하고, 상기 복수 개의 시트층 중 교차 적층되는 시트층 상에 구비되는 코일패턴은 비아홀을 통하여 연결되며, 서로 대향하는 입출력전극에 연결될 수 있다.The first package may include a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sequentially stacked sheet layers; And a plurality of coil patterns connected to any one of the plurality of input / output electrodes in the plurality of sheet layers, wherein the coil patterns provided on the sheet layers that are cross-laminated among the plurality of sheet layers are connected through via holes. It may be connected to input and output electrodes facing each other.
또한, 상기 제1패키지는, 일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; 상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; 복수 개의 시트층을 포함하는 소체; 및 상기 복수 개의 시트층에서 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 커패시터전극;을 포함하고, 상기 복수 개의 시트층 중 교차 적층되는 시트층 상에 구비되는 커패시터전극은 서로 중첩되도록 배치될 수 있다. In addition, the first package, a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sheet layers; And a plurality of capacitor electrodes connected to any one of the plurality of input / output electrodes in the plurality of sheet layers, wherein the capacitor electrodes provided on the sheet layers stacked in the plurality of sheet layers overlap each other. Can be.
또한, 상기 제1패키지는, 일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; 상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; 복수 개의 시트층을 포함하는 소체; 최상위의 제1시트층 상에서 상기 한 쌍의 접지전극 사이에 일정간격 이격배치되는 제1전극; 및 상기 제1시트층 아래의 제2시트층 상에 상기 제1전극과 일부 중첩되게 배치되고, 상기 복수 개의 입출력전극 중 서로 대향하는 입출력전극에 연결되는 복수 개의 제2전극;을 포함할 수 있다. In addition, the first package, a pair of ground electrodes provided in a 'c' shape on both sides of one direction; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes; A body comprising a plurality of sheet layers; A first electrode spaced at a predetermined interval between the pair of ground electrodes on the first sheet layer on the top; And a plurality of second electrodes disposed on the second sheet layer below the first sheet layer to partially overlap with the first electrode, and connected to input / output electrodes facing each other among the plurality of input / output electrodes. .
또한, 상기 제2패키지는, 하면에서 일방향의 양측에 구비되는 한 쌍 인출전극; 및 상기 한 쌍의 인출전극과 직각을 이루는 타방향의 적어도 일측에 구비되는 복수 개의 다이오드전극을 포함할 수 있다. In addition, the second package may include a pair of drawing electrodes provided on both sides in one direction from a lower surface thereof; And a plurality of diode electrodes provided on at least one side of the other direction perpendicular to the pair of lead electrodes.
또한, 상기 고속신호는 LVDS(Low voltage differential signaling), HDMI(High Definition Multimedia Interface), USB(Universal Serial Bus), V by 1, 및 USB 3.0/3.1 중 어느 하나의 신호라인의 신호일 수 있다. The high speed signal may be a signal of any one of low voltage differential signaling (LVDS), high definition multimedia interface (HDMI), universal serial bus (USB), V by 1, and USB 3.0 / 3.1.
한편, 본 발명은 복수 개의 시트층; 제1시트층에 형성되는 접지전극; 상기 제1시트층 상에 적층된 제2시트층 상에 형성되어 제1외부전극에 연결되는 내부전극; 및 상기 제2시트층 상에 적층된 제3시트층 상에 형성되어 제2외부전극에 연결되는 저항체;를 포함하는 전기적 과부하 보호소자를 제공한다. 여기서, 상기 접지전극과 상기 내부전극 및 상기 내부전극과 상기 저항체는 서로 대향하여 배치된다.On the other hand, the present invention is a plurality of sheet layer; A ground electrode formed on the first sheet layer; An inner electrode formed on the second sheet layer stacked on the first sheet layer and connected to the first outer electrode; And a resistor formed on the third sheet layer stacked on the second sheet layer and connected to the second external electrode. The ground electrode, the inner electrode, the inner electrode, and the resistor are disposed to face each other.
본 발명에 의하면, 보호기능부와 직렬로 순방향 다이오드를 연결하여 전체 커패시턴스를 감소시킴으로써 고속 데이터 신호의 감쇠를 억제하면서도 전기적 과전압 보호 및 정전기 보호 기능을 수행할 수 있다. According to the present invention, by connecting the forward diode in series with the protection function to reduce the total capacitance, it is possible to perform the electrical overvoltage protection and the electrostatic protection while suppressing the attenuation of the high-speed data signal.
또한, 본 발명은 고속 신호라인의 종류에 따른 필터를 패키지화하고 패키지 상에 순방향 다이오드를 플립칩 본딩하여 적층함으로써, 단일 패키지를 용이하게 구현할 수 있는 동시에 제조 효율을 향상시킬 수 있다. In addition, the present invention can package a filter according to the type of high-speed signal line and flip-chip bonded and stacked a forward diode on the package, so that a single package can be easily implemented and manufacturing efficiency can be improved.
또한, 본 발명은 고속신호라인에 직렬 커패시터를 적용하여, 하이패스 필터를 구성함으로써, 고속 데이터 신호의 감쇠 없이 ESD와 EOS를 차단할 수 있다.In addition, the present invention can configure a high pass filter by applying a series capacitor to the high-speed signal line, it is possible to block the ESD and EOS without attenuation of the high-speed data signal.
도 1은 본 발명의 제1실시예에 따른 전기적 과부하 소자를 나타낸 사시도, 1 is a perspective view showing an electrical overload device according to a first embodiment of the present invention;
도 2는 도 1의 보호부의 사시도,2 is a perspective view of the protective part of FIG.
도 3은 도 2의 보호부의 분해사시도,3 is an exploded perspective view of the protective part of FIG.
도 4는 도 1의 등가회로도, 4 is an equivalent circuit diagram of FIG. 1;
도 5는 본 발명의 제2실시예에 따른 전기적 과부하 소자를 나타낸 사시도, 5 is a perspective view showing an electrical overload device according to a second embodiment of the present invention;
도 6은 도 5의 보호부의 사시도,6 is a perspective view of the protective part of FIG.
도 7은 도 6의 보호부의 분해사시도,7 is an exploded perspective view of the protection unit of FIG. 6, FIG.
도 8은 도 5의 제2패키지의 저면사시도, 8 is a bottom perspective view of the second package of FIG. 5;
도 9는 도 8의 제2패키지의 등가회로도,9 is an equivalent circuit diagram of a second package of FIG. 8;
도 10은 도 5의 등가회로도,10 is an equivalent circuit diagram of FIG. 5;
도 11은 본 발명의 제3실시예에 따른 전기적 과부하 소자를 나타낸 사시도, 11 is a perspective view showing an electrical overload device according to a third embodiment of the present invention;
도 12는 도 11의 보호부의 분해사시도, 12 is an exploded perspective view of the protection unit of FIG. 11;
도 13은 도 11의 등가회로도, 13 is an equivalent circuit diagram of FIG.
도 14는 본 발명의 제4실시예에 따른 전기적 과부하 소자를 나타낸 사시도, 14 is a perspective view showing an electrical overload device according to a fourth embodiment of the present invention;
도 15는 도 14의 보호부의 분해사시도, 15 is an exploded perspective view of the protection unit of FIG. 14,
도 16은 도 14의 등가회로도,16 is an equivalent circuit diagram of FIG. 14;
도 17은 본 발명의 제5실시예에 따른 전기적 과부하 소자를 나타낸 단면도,17 is a cross-sectional view showing an electrical overload device according to a fifth embodiment of the present invention;
도 18은 도 17의 등가회로도,18 is an equivalent circuit diagram of FIG. 17;
도 19는 도 18에서 적용되는 저항의 특성 그래프,19 is a characteristic graph of a resistance applied in FIG. 18,
도 20은 도 18에서 적용되는 커패시터의 특성 그래프,20 is a characteristic graph of a capacitor applied in FIG. 18,
도 21은 도 18에서 정전용량에 따른 ESD 특성 테스트 결과표,21 is an ESD characteristic test result table according to capacitance in FIG. 18,
도 22는 도 18에서 인덕터를 포함하는 등가회로도,FIG. 22 is an equivalent circuit diagram including an inductor in FIG. 18;
도 23은 도 22에서 적용되는 인덕터의 특성 그래프,23 is a characteristic graph of the inductor applied in FIG. 22,
도 24는 도 18에서 바이패스 저항을 포함하는 등가회로도, 24 is an equivalent circuit diagram including a bypass resistor in FIG. 18;
도 25는 도 24에서 적용될 수 있는 저항과 바이패스 저항의 저항값에 따른 클램프 전압의 테스트 결과표, 그리고FIG. 25 is a test result table of clamp voltages according to resistance values of resistors and bypass resistors applicable to FIG. 24, and
도 26은 도 24에서 적용되는 바이패스 저항의 특성 그래프이다.FIG. 26 is a characteristic graph of the bypass resistance applied in FIG. 24.
이하, 첨부한 도면을 참고로 하여 본 발명의 실시예에 대하여 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다. 도면에서 본 발명을 명확하게 설명하기 위해서 설명과 관계없는 부분은 생략하였으며, 명세서 전체를 통하여 동일 또는 유사한 구성요소에 대해서는 동일한 참조부호를 부가한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. The drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.
본 발명에 따른 전기적 과부하 보호소자(100,200,300,400)는 도 1, 도 5, 도 11 및 도 14에 도시된 바와 같이, 제1패키지(110,210,310,410), 제2패키지(120,220,320,420) 및 몰딩부(130,230,330,430)를 포함한다. Electrical overload protection device (100, 200, 300, 400) according to the present invention, as shown in Figures 1, 5, 11 and 14, the first package (110, 210, 310, 410), the second package (120, 220, 320, 420) and the molding unit (130, 230, 330, 430) do.
상기 전기적 과부하 보호소자(100,200,300,400)는 고속 신호라인용 보호소자로서, LVDS(Low voltage differential signaling), HDMI(High Definition Multimedia Interface), USB(Universal Serial Bus), V by 1, 및 USB 3.0/3.1 중 어느 하나의 신호라인용 보호소자일 수 있다. The electrical overload protection devices 100, 200, 300, and 400 are protection devices for high-speed signal lines, and include low voltage differential signaling (LVDS), high definition multimedia interface (HDMI), universal serial bus (USB), V by 1, and USB 3.0 / 3.1. It may be a protection element for any one signal line.
여기서, 상기 전기적 과부하 보호소자(100,200,300,400)는 전기적 과부하(EOS) 및 정전기(ESD)에 대한 보호기능을 가지며, 상술한 바와 같은 신호라인 상에 배치되며, 회로기판의 접지에 연결된다. 이에 의해, 전기적 과부하 보호소자(100,200,300,400)는 전기적 과부하(EOS) 및 정전기(ESD)를 접지로 바이패스함으로써 전기적 과부하(EOS) 및 정전기(ESD)가 내부회로로 유입되는 것을 차단하여 내부회로를 보호할 수 있다. Here, the electrical overload protection device (100, 200, 300, 400) has a function to protect against electrical overload (EOS) and static electricity (ESD), is disposed on the signal line as described above, is connected to the ground of the circuit board. Accordingly, the electrical overload protection device (100, 200, 300, 400) bypasses the electrical overload (EOS) and electrostatic discharge (ESD) to the ground to block the electrical overload (EOS) and static electricity (ESD) to enter the internal circuit to protect the internal circuit can do.
제1패키지(110,410)는 고속신호를 필터링하는 필터부 및 전기적 과부하 및 정전기에 대한 보호기능을 갖는 보호부를 포함하고, 제2패키지(120,420)는 보호부에 직렬 연결되는 순방향 다이오드를 포함한다. The first packages 110 and 410 include a filter unit for filtering a high speed signal and a protection unit having a protection function against electrical overload and static electricity, and the second packages 120 and 420 include a forward diode connected in series to the protection unit.
여기서, 상기 보호부는 바리스터 또는 제너다이오드를 포함하며, 높은 커패시턴스를 갖고, 상기 순방향 다이오드는 별도의 패키지로 이루어지며, 낮은 커패시턴스를 갖는다. Here, the protection part includes a varistor or a zener diode, has a high capacitance, and the forward diode is made of a separate package and has a low capacitance.
이와 같이, 높은 커패시턴스의 보호부가 낮은 커패시턴스의 순방향 다이오드와 직렬 연결됨으로써, 신호출력단과 접지 사이의 전체 커패시턴스는 상기 순방향 다이오드의 커패시턴스보다 작게 된다. In this way, the high capacitance protection part is connected in series with the low capacitance forward diode so that the total capacitance between the signal output terminal and ground becomes smaller than the capacitance of the forward diode.
이에 의해, 높은 커패시턴스를 갖는 보호부를 사용하면서도, 고속 신호라인에 적합한 낮은 커패시턴스를 구현함으로써, 고속 데이터 신호의 감쇠를 억제하면서도 전기적 과부하(EOS) 및 정전기(ESD) 보호 기능을 수행할 수 있다.As a result, by using a high capacitance protection unit and implementing a low capacitance suitable for a high speed signal line, an electrical overload (EOS) and an electrostatic (ESD) protection function can be performed while suppressing attenuation of a high speed data signal.
이때, 상기 순방향 다이오드는 제1패키지(110,410) 상에 플립칩 본딩되어 적층된다. 즉, 상기 순방향 다이오드는 단일 부품의 패키지이므로, 상기 순방향 다이오드를 제1패키지(110,410) 상에 플립칩 본딩하여 적층함으로써, 전기적 과부하 보호소자(100,400)를 단일 패키지로 용이하게 구현할 수 있는 동시에 제조 효율을 향상시킬 수 있다. In this case, the forward diode is flip-chip bonded and stacked on the first packages 110 and 410. That is, since the forward diode is a package of a single component, the forward diode is flip-chip bonded and laminated on the first packages 110 and 410, whereby the electrical overload protection devices 100 and 400 can be easily implemented in a single package, and at the same time, manufacturing efficiency is achieved. Can improve.
상기 필터부는 고속 신호라인의 종류에 따라 구현되는 필터이며, 하이패스필터일 수 있다. 여기서, 상기 필터부는 커패시터와 저항, 트랜스포머, 또는 커패시터로 이루어질 수 있다. The filter unit may be a filter implemented according to the type of the high speed signal line, and may be a high pass filter. The filter unit may be formed of a capacitor, a resistor, a transformer, or a capacitor.
대안적으로, 상기 보호부는 제2패키지(220,320)에 구현될 수 있다. 즉, 제1패키지(210,310)는 상기 필터부만을 포함하고, 제2패키지(220,320)는 상기 순방향 다이오드와 함께 상기 보호부를 포함한다. Alternatively, the protection unit may be implemented in the second packages 220 and 320. That is, the first packages 210 and 310 include only the filter unit, and the second packages 220 and 320 include the protection unit together with the forward diode.
이때, 상기 보호부는 제너다이오드일 수 있다. 즉, 제2패키지(220,320)는 상기 순방향 다이오드와 제너다이오드로 이루어진 단일 패키지일 수 있다. 여기서, 제2패키지(220,320)는 제1패키지(210,310)에 플립칩 본딩되어 적층 가능하도록 전극이 패키지의 하면에 배치될 수 있다.In this case, the protection unit may be a zener diode. That is, the second packages 220 and 320 may be a single package consisting of the forward diode and the zener diode. Here, the second packages 220 and 320 may be flip chip bonded to the first packages 210 and 310 so that electrodes may be disposed on the bottom surface of the package so as to be stacked.
이에 의해, 제1패키지(210,310)는 기존의 필터 제조 공정을 이용하고, 제2패키지(220,320)는 다이오드 제조 공정을 이용하여 제조함으로써, 전기적 과부하 보호소자(200,300)의 단일 패키지를 용이하게 구현할 수 있는 동시에, 제2패키지(220,320)를 별도로 외주 제작함으로써 제조효율을 향상시킬 수 있다.  As a result, the first packages 210 and 310 are manufactured using the existing filter manufacturing process, and the second packages 220 and 320 are manufactured using the diode manufacturing process, thereby easily implementing a single package of the electrical overload protection device 200 and 300. At the same time, by manufacturing the second package (220,320) to the outer periphery can improve the manufacturing efficiency.
몰딩부(130,230,330,430)는 제2패키지(120,220,320,420) 상에 적층되는 제1패키지(110,210,310,410) 및 제2패키지(120,220,320,420)의 상면을 덮도록 몰딩된다. 즉, 몰딩부(130,230,330,430)는 상기 순방향 다이오드를 몰딩한다. The molding parts 130, 230, 330, and 430 are molded to cover top surfaces of the first packages 110, 210, 310, 410 and the second packages 120, 220, 320, and 420 stacked on the second packages 120, 220, 320, and 420. That is, the molding parts 130, 230, 330, and 430 mold the forward diode.
이하, 전기적 과부하 보호소자(100,200,300,400)가 적용되는 고속 신호라인의 종류에 따른 실시예를 보다 상세하게 설명한다. Hereinafter, embodiments of the high speed signal line to which the electrical overload protection devices 100, 200, 300, and 400 are applied will be described in more detail.
본 발명의 제1실시예에 따른 전기적 과부하 보호소자(100)는 LVDS 또는 HDMI 신호라인용 보호소자로서, 도 1에 도시된 바와 같이, 제1패키지(110), 제2패키지(120), 및 몰딩부(130)를 포함한다. Electrical overload protection device 100 according to the first embodiment of the present invention is a protection device for LVDS or HDMI signal line, as shown in Figure 1, the first package 110, the second package 120, and The molding part 130 is included.
여기서, 제1패키지(110)는 보호부 및 필터부를 포함하고, 제2패키지(120)는 단일 패키지로 이루어진 순방향 다이오드를 포함할 수 있다. 즉, 제1패키지(110)는 보호소자 형태의 패키지이고, 제2패키지(120)는 단일 부품으로 이루어진 패키지일 수 있다. Here, the first package 110 may include a protection unit and a filter unit, and the second package 120 may include a forward diode made of a single package. That is, the first package 110 may be a package in the form of a protection device, and the second package 120 may be a package composed of a single component.
이때, 상기 보호부는 바리스터일 수 있고, 상기 필터부는 저항과 커패시터로 이루어진 하이패스필터일 수 있다. In this case, the protection part may be a varistor, and the filter part may be a high pass filter including a resistor and a capacitor.
제1패키지(110)는 복수 개의 시트층(111-1~111-7), 한 쌍의 접지전극(112a,112b), 한 쌍의 입출력전극(113a,113b), 제1전극(114), 복수 개의 제2전극(115a,115b), 및 복수 개의 저항체(116a~119a,116b~119b)를 포함할 수 있다. The first package 110 includes a plurality of sheet layers 111-1 to 111-7, a pair of ground electrodes 112a and 112b, a pair of input / output electrodes 113a and 113b, a first electrode 114, A plurality of second electrodes 115a and 115b and a plurality of resistors 116a to 119a and 116b to 119b may be included.
복수 개의 시트층(111-1~111-7)은 소체일 수 있다. 여기서, 제1시트층(111-1) 및 제2시트층(111-2)은 상기 보호부에 대응하고, 제3시트층(111-3)은 보호부와 필터부를 구분하기 위한 버퍼층이며, 나머지 시트층(111-4~111-7)은 필터부에 대응한다(도 3 참조). 여기서, 복수 개의 시트층(111-1~111-7)은 바리스터 물질층 및 유전체를 포함할 수 있다. The plurality of sheet layers 111-1 to 111-7 may be body bodies. Here, the first sheet layer 111-1 and the second sheet layer 111-2 correspond to the protection part, and the third sheet layer 111-3 is a buffer layer for distinguishing the protection part and the filter part. The remaining sheet layers 111-4 to 111-7 correspond to the filter portion (see FIG. 3). Here, the plurality of sheet layers 111-1 to 111-7 may include a varistor material layer and a dielectric.
한 쌍의 접지전극(112a,112b)은 제1패키지(110)의 일방향의 양측에 'ㄷ'자 형상으로 구비될 수 있다. 즉, 한 쌍의 접지전극(112a,112b) 각각은 제1패키지(110)의 측면, 상면 및 하면의 일부에 걸쳐 형성될 수 있다(도 2 참조). 이러한 접지전극(112a,112b)은 전기적 과부하 보호소자(100)가 고속 신호라인 상에 배치되는 경우, 회로기판의 접지에 연결된다. The pair of ground electrodes 112a and 112b may be provided in a 'c' shape on both sides of one direction of the first package 110. That is, each of the pair of ground electrodes 112a and 112b may be formed over a portion of the side, top and bottom surfaces of the first package 110 (see FIG. 2). The ground electrodes 112a and 112b are connected to the ground of the circuit board when the electrical overload protection device 100 is disposed on the high speed signal line.
복수 개의 입출력전극(113a,113b)은 한 쌍의 접지전극(112a,112b)과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비될 수 있다. 즉, 복수 개의 입출력전극(113a,113b) 각각은 제1패키지(110)의 측면, 상면 및 하면의 일부에 걸쳐 형성될 수 있다(도 2 참조). 이러한 입출력전극(113a,113b)은 고속 신호라인에 연결된다. The plurality of input / output electrodes 113a and 113b may be provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes 112a and 112b. That is, each of the plurality of input / output electrodes 113a and 113b may be formed over a part of the side surface, the upper surface, and the lower surface of the first package 110 (see FIG. 2). The input / output electrodes 113a and 113b are connected to a high speed signal line.
제1전극(114)은 복수 개의 시트층(111-1~111-7) 중 최상위에 배치되는 제1시트층(111-1) 상에서 한 쌍의 접지전극(112a,112b) 사이에 일정간격 이격배치될 수 있다(도 2 참조). 이러한 제1전극(114)은 바리스터의 일측 전극으로서 순방향 다이오드와 연결하기 위한 전극이다. The first electrode 114 is spaced at a predetermined interval between the pair of ground electrodes 112a and 112b on the first sheet layer 111-1 disposed at the top of the plurality of sheet layers 111-1 to 111-7. May be arranged (see FIG. 2). The first electrode 114 is an electrode for connecting to the forward diode as one side of the varistor.
복수 개의 제2전극(115a,115b)은 제1시트층(111-1)의 아래의 제2시트층(111-2) 상에 제1전극(114)과 일부 중첩되게 배치될 수 있다(도 3 참조). 이러한 제2전극(115a,115b)은 바리스터의 타측 전극으로서 복수 개의 입출력전극(113a,113b) 중 하나에 각각 연결될 수 있다. The plurality of second electrodes 115a and 115b may be partially overlapped with the first electrode 114 on the second sheet layer 111-2 below the first sheet layer 111-1 (FIG. 3). The second electrodes 115a and 115b may be connected to one of the plurality of input / output electrodes 113a and 113b as the other electrode of the varistor, respectively.
복수 개의 저항체(116a~119a,116b~119b)는 제2시트층(111-2)의 아래의 복수 개의 시트층(111-4~111-7)에 배치될 수 있다(도 3 참조). 이때, 복수 개의 저항체(116a~119a,116b~119b)는 복수 개의 입출력전극(113a,113b) 중 하나에 각각 연결될 수 있다.The plurality of resistors 116a to 119a and 116b to 119b may be disposed on the plurality of sheet layers 111-4 to 111-7 below the second sheet layer 111-2 (see FIG. 3). In this case, the plurality of resistors 116a to 119a and 116b to 119b may be connected to one of the plurality of input / output electrodes 113a and 113b, respectively.
즉, 저항체(116a,116b)는 제4시트층(111-4) 상에 배치되며, 일측이 입출력전극(113b)에 연결되도록 제4시트층(111-4)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 나선 형상으로 연장될 수 있다. That is, the resistors 116a and 116b are disposed on the fourth sheet layer 111-4 and disposed at one edge of the fourth sheet layer 111-4 so that one side thereof is connected to the input / output electrode 113b. The side is disposed in the central portion, and may extend in a spiral shape therebetween.
저항체(117a,117b)는 제5시트층(111-5) 상에 배치되며, 일측이 입출력전극(113b)에 대향하는 입출력전극(113a)에 연결되도록 제5시트층(111-5)의 타측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 일정 형상으로 연장될 수 있다. The resistors 117a and 117b are disposed on the fifth sheet layer 111-5, and the other side of the fifth sheet layer 111-5 so that one side thereof is connected to the input / output electrode 113a opposite to the input / output electrode 113b. It is disposed on the edge, and the other side is disposed in the center portion, and may extend in a predetermined shape therebetween.
여기서, 서로 인접한 시트층에 구비되는 저항체(116a)와 저항체(117a)는 중앙부에서 비아홀(116a-1,117a-1)을 통하여 연결되고, 저항체(116b)와 저항체(117b)는 중앙부에서 비아홀(116b-1,117b-1)을 통하여 연결될 수 있다.Here, the resistors 116a and 117a provided in the adjacent sheet layers are connected through the via holes 116a-1 and 117a-1 at the center portion, and the resistors 116b and the resistor 117b are via holes 116b at the center portion. -1,117b-1) may be connected.
이와 유사하게, 저항체(118a,118b)는 제6시트층(111-6) 상에 배치되며, 일측이 입출력전극(113a)에 연결되도록 제6시트층(111-6)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 일정 형상으로 연장될 수 있다. Similarly, the resistors 118a and 118b are disposed on the sixth sheet layer 111-6 and disposed at one edge of the sixth sheet layer 111-6 so that one side thereof is connected to the input / output electrode 113a. , The other side is disposed in the central portion, and may extend in a predetermined shape therebetween.
저항체(119a,119b)는 제7시트층(111-7) 상에 배치되며, 일측이 입출력전극(113a)에 대향하는 입출력전극(113b)에 연결되도록 제7시트층(111-7)의 타측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 나선 형상으로 연장될 수 있다. The resistors 119a and 119b are disposed on the seventh sheet layer 111-7 and the other side of the seventh sheet layer 111-7 so that one side thereof is connected to the input / output electrode 113b opposite to the input / output electrode 113a. It is disposed at the edge, the other side is disposed in the central portion, and may extend in a spiral shape therebetween.
여기서, 서로 인접한 시트층에 구비되는 저항체(118a)와 저항체(119a)는 중앙부에서 비아홀(118a-1,119a-1)을 통하여 연결되고, 저항체(118b)와 저항체(119b)는 중앙부에서 비아홀(118b-1,119b-1)을 통하여 연결될 수 있다.Here, the resistors 118a and 119a provided in the adjacent sheet layers are connected through the via holes 118a-1 and 119a-1 at the center portion, and the resistors 118b and the resistor 119b are via holes 118b at the center portion. -1, 119b-1) can be connected.
이때, 저항체(116a~119a,116b~119b)는 상술한 바와 같은 형상에 한정되지 않고, 다양한 형태를 가질 수 있다. In this case, the resistors 116a to 119a and 116b to 119b are not limited to the shapes described above, but may have various forms.
제2패키지(120)는 하나의 단일 부품으로 이루어진 순방향 다이오드일 수 있다. 여기서, 전기적 과부하 보호소자(100)는 두 개의 제2패키지(120)를 포함할 수 있다. 즉, 전기적 과부하 보호소자(100)는 두 개의 순방향 다이오드를 포함할 수 있다.The second package 120 may be a forward diode composed of one single component. Here, the electrical overload protection device 100 may include two second packages 120. That is, the electrical overload protection device 100 may include two forward diodes.
각각의 제2패키지(120)는 제1전극(114)과 한 쌍의 접지전극(112a,112b) 사이에 배치될 수 있다. 이때, 제2패키지(120)는 제1전극(114)과 접지전극(112a) 또는 제1전극(114)과 접지전극(112b) 상에 플립칩 본딩되어 적층될 수 있다. Each second package 120 may be disposed between the first electrode 114 and the pair of ground electrodes 112a and 112b. In this case, the second package 120 may be stacked by flip chip bonding on the first electrode 114 and the ground electrode 112a or on the first electrode 114 and the ground electrode 112b.
즉, 상기 순방향 다이오드는 입출력전극(113a,113b)과 접지전극(112a,112b) 사이에서 보호부와 직렬로 연결될 수 있다. That is, the forward diode may be connected in series with the protection unit between the input / output electrodes 113a and 113b and the ground electrodes 112a and 112b.
몰딩부(130)는 제2패키지(120) 및 제1패키지(110)의 상면을 덮도록 몰딩된다. 이에 의해, 전기적 과부하 보호소자(100)는 복수 개의 개별 패키지를 하나의 패키지로 형성할 수 있다.The molding part 130 is molded to cover the top surfaces of the second package 120 and the first package 110. As a result, the electrical overload protection device 100 may form a plurality of individual packages into one package.
이와 같이 구성된 전기적 과부하 보호소자(100)는 도 4에 도시된 바와 같이, 입출력전극(c~j) 사이에 하나의 저항과 바리스터의 쌍 및 접지전극(a,b)에 연결되는 순방향 다이오드의 등가회로로 나타낼 수 있다. As illustrated in FIG. 4, the electrical overload protection device 100 configured as described above is equivalent to a resistor and a pair of varistors between the input / output electrodes c to j and a forward diode connected to the ground electrodes a and b. It can be represented by a circuit.
여기서, 입출력전극(c~j)과 접지전극(a,b) 사이에서, 바리스터와 순방향 다이오드는 각각 직렬 연결됨으로써, 입출력전극(c~j)과 접지전극(a,b) 사이의 전체 커패시턴스는 낮은 커패시턴스를 갖는 순방향 다이오드보다 작은 커패시턴스를 형성할 수 있다. Here, the varistor and the forward diode are connected in series between the input / output electrodes c to j and the ground electrodes a and b, so that the total capacitance between the input and output electrodes c to j and the ground electrodes a and b is increased. It is possible to form smaller capacitances than forward diodes with lower capacitance.
또한, 입출력전극(c~j)과 접지전극(a,b) 사이의 커패시턴스와 입출력전극(c~j) 전극 사이의 저항에 의해 하이패스 필터가 형성될 수 있다. 이에 의해, 전기적 과부하 보호소자(100)는 고속 신호에 대하여 신호의 감쇠를 최소화하는 동시에 전기적 과부하(EOS) 및 정전기(ESD)의 보호기능을 제공할 수 있다.In addition, a high pass filter may be formed by a capacitance between the input / output electrodes c to j and the ground electrodes a and b and a resistance between the input and output electrodes c to j. As a result, the electrical overload protection device 100 may provide a protection function of the electrical overload (EOS) and the static electricity (ESD) while minimizing the attenuation of the signal with respect to the high speed signal.
본 발명의 제2실시예에 따른 전기적 과부하 보호소자(200)는 도 5에 도시된 바와 같이, LVDS, HDMI, 및 USB 중 어느 하나의 신호라인용 보호소자로서, 제1패키지(210), 제2패키지(220), 및 몰딩부(230)를 포함한다. As shown in FIG. 5, the electrical overload protection device 200 according to the second embodiment of the present invention is a protection device for any one of the signal lines of LVDS, HDMI, and USB, and includes a first package 210 and a first package. 2 package 220, and the molding unit 230.
여기서, 제1패키지(210)는 필터부만을 포함하고, 제2패키지(220)는 보호부 및 복수 개의 순방향 다이오드를 포함할 수 있다. 이때, 상기 보호부는 제너다이오드일 수 있고, 상기 필터부는 트랜스포머로 이루어진 하이패스 필터일 수 있다. Here, the first package 210 may include only the filter unit, and the second package 220 may include a protection unit and a plurality of forward diodes. In this case, the protection unit may be a zener diode, and the filter unit may be a high pass filter made of a transformer.
즉, 제1패키지(210)는 필터 형태의 패키지이고, 제2패키지(220)는 복수 개의 순방향 다이오드와 하나의 제너다이오드가 단일 부품으로 이루어진 패키지일 수 있다.That is, the first package 210 may be a filter-type package, and the second package 220 may be a package including a plurality of forward diodes and one zener diode as a single component.
제1패키지(210)는 복수 개의 시트층(211-1~211-5), 한 쌍의 접지전극(212a,212b), 한 쌍의 입출력전극(213a,213b), 및 복수 개의 코일패턴(215a~217a,215b~217b)을 포함할 수 있다. The first package 210 includes a plurality of sheet layers 211-1 to 211-5, a pair of ground electrodes 212a and 212b, a pair of input / output electrodes 213a and 213b, and a plurality of coil patterns 215a. ~ 217a, 215b-217b).
복수 개의 시트층(211-1~211-5)은 소체일 수 있다. 여기서, 제1시트층(211-1)은 최상층으로서 보호층이고, 나머지 시트층(211-2~211-5)은 필터부에 대응한다(도 7 참조). 여기서, 복수 개의 시트층(211-1~211-5)은 자성체를 포함할 수 있다.The plurality of sheet layers 211-1 to 211-5 may be a body. Here, the first sheet layer 211-1 is a protective layer as the uppermost layer, and the remaining sheet layers 211-2 to 211-5 correspond to the filter portion (see FIG. 7). Here, the plurality of sheet layers 211-1 to 211-5 may include magnetic materials.
한 쌍의 접지전극(212a,212b) 및 복수 개의 입출력전극(213a,213b)은 제1실시예의 한 쌍의 접지전극(112a,112b) 및 복수 개의 입출력전극(113a,113b)의 구성과 동일하므로 여기서 구체적인 설명은 생략한다(도 6 참조). Since the pair of ground electrodes 212a and 212b and the plurality of input / output electrodes 213a and 213b are the same as those of the pair of ground electrodes 112a and 112b and the plurality of input / output electrodes 113a and 113b of the first embodiment. Detailed description thereof will be omitted here (see FIG. 6).
복수 개의 코일패턴(214a~217a,214b~217b)은 제1시트층(211-1)의 아래의 복수 개의 시트층(211-2~211-5)에 배치될 수 있다(도 7 참조). 이때, 복수 개의 코일패턴(214a~217a,214b~217b)은 복수 개의 입출력전극(213a,213b) 중 하나에 각각 연결될 수 있다.The plurality of coil patterns 214a to 217a and 214b to 217b may be disposed on the plurality of sheet layers 211-2 to 211-5 below the first sheet layer 211-1 (see FIG. 7). In this case, the plurality of coil patterns 214a to 217a and 214b to 217b may be connected to one of the plurality of input / output electrodes 213a and 213b, respectively.
즉, 코일패턴(214a,214b)은 제2시트층(211-2) 상에 배치되며, 일측이 입출력전극(213b)에 연결되도록 제2시트층(211-2)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 나선 형상으로 연장될 수 있다. That is, the coil patterns 214a and 214b are disposed on the second sheet layer 211-2, and disposed at one edge of the second sheet layer 211-2 so that one side thereof is connected to the input / output electrode 213b. The other side is disposed in the center portion, and may extend in a spiral shape therebetween.
코일패턴(215a,215b)은 제3시트층(211-3) 상에 배치되며, 일측이 입출력전극(213b)에 연결되도록 제3시트층(211-3)의 타측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 나선 형상으로 연장될 수 있다. The coil patterns 215a and 215b are disposed on the third sheet layer 211-3 and disposed at the other edge of the third sheet layer 211-3 so that one side is connected to the input / output electrode 213b. It is disposed in the center portion, and may extend in a spiral shape therebetween.
이와 유사하게, 코일패턴(216a,216b)은 제4시트층(211-4) 상에 배치되며, 일측이 입출력전극(213b)에 대향하는 입출력전극(213a)에 연결되도록 제4시트층(211-4)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 나선 형상으로 연장될 수 있다. Similarly, the coil patterns 216a and 216b are disposed on the fourth sheet layer 211-4, and the fourth sheet layer 211 is connected to the input / output electrode 213a opposite to the input / output electrode 213b. It is disposed on one side edge of -4), the other side is disposed in the center portion, and may extend in a spiral shape therebetween.
코일패턴(217a,217b)은 제5시트층(211-5) 상에 배치되며, 일측이 입출력전극(213b)에 대향하는 입출력전극(213a)에 연결되도록 제5시트층(211-5)의 타측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 나선 형상으로 연장될 수 있다. The coil patterns 217a and 217b are disposed on the fifth sheet layer 211-5, and one side of the fifth sheet layer 211-5 is connected to the input / output electrode 213a opposite to the input / output electrode 213b. It is disposed on the other edge, the other side is disposed in the central portion, and may extend in a spiral shape therebetween.
이때, 복수 개의 시트층(211-2~211-5) 중 교차 적층되는 시트층에 구비되는 코일패턴(214a)과 코일패턴(216a)은 중앙부에서 비아홀(214a-1,216a-1) 및 그 사이의 배치되는 시트층(211-3)의 관통홀(215a-2)을 통하여 연결되고, 코일패턴(214b)과 코일패턴(216b)은 중앙부에서 비아홀(214b-1,216b-1) 및 시트층(211-3)의 관통홀(215b-2)을 통하여 연결될 수 있다.In this case, the coil patterns 214a and the coil patterns 216a provided in the sheet layers that are cross-laminated among the plurality of sheet layers 211-2 to 211-5 are provided with via holes 214a-1 and 216a-1 at the center thereof, and between them. It is connected through the through hole 215a-2 of the sheet layer 211-3 disposed of the coil pattern 214b and the coil pattern 216b at the center portion of the via holes 214b-1 and 216b-1 and the sheet layer ( It may be connected through the through hole 215b-2 of 211-3.
이와 유사하게, 코일패턴(215a)과 코일패턴(217a)은 중앙부에서 비아홀(215a-1,217a-1) 및 그 사이의 배치되는 시트층(211-4)의 관통홀(216a-2)을 통하여 연결되고, 코일패턴(215b)과 코일패턴(217b)은 중앙부에서 비아홀(215b-1,217b-1) 및 시트층(211-4)의 관통홀(216b-2)을 통하여 연결될 수 있다.Similarly, the coil pattern 215a and the coil pattern 217a are formed through the through holes 216a-2 of the sheet layers 211-4 and the via holes 215a-1 and 217a-1 disposed therebetween at the center portion. The coil pattern 215b and the coil pattern 217b may be connected through the via holes 215b-1 and 217b-1 and the through hole 216b-2 of the sheet layer 211-4 at the center portion.
이때, 코일패턴(214a~217a,214b~217b)은 상술한 바와 같은 형상에 한정되지 않고, 다양한 형태를 가질 수 있다. In this case, the coil patterns 214a to 217a and 214b to 217b are not limited to the shapes described above, but may have various forms.
제2패키지(220)는 복수 개의 순방향 다이오드 및 하나의 제너다이오드를 포함한다. 여기서, 복수 개의 순방향 다이오드 각각의 음극은 제너다이오드의 음극에 연결되고, 복수 개의 순방향 다이오드 각각의 양극은 다이오드전극(223b)에 연결되며, 제너다이오드의 양극은 인출전극(222a,222b)에 연결될 수 있다(도 9 참조). The second package 220 includes a plurality of forward diodes and one zener diode. Here, the cathode of each of the plurality of forward diodes may be connected to the cathode of the zener diode, the anode of each of the plurality of forward diodes may be connected to the diode electrode 223b, and the anode of the zener diode may be connected to the extraction electrodes 222a and 222b. (See FIG. 9).
이때, 순방향 다이오드는 제2패키지(220)의 일측 다이오드전극(223b)에만 연결되는 것으로 도시되고 설명되었으나 이에 한정되지 않고 양측 다이오드전극(223a,223b) 모두에 연결되도록 구비될 수 있다. In this case, the forward diode is shown and described as being connected to only one diode electrode 223b of the second package 220, but is not limited thereto and may be provided to be connected to both diode electrodes 223a and 223b.
제2패키지(220)는 제1패키지(210) 상에 플립칩 본딩되어 적층될 수 있도록 제1패키지(210)의 상면에 구비되는 접지전극(212a,212b) 및 입출력전극(213a,213b)에 대응하는 한 쌍의 인출전극(222a,222b) 및 복수 개의 다이오드전극(223a,223b)이 하면에 구비된다. The second package 220 is connected to the ground electrodes 212a and 212b and the input / output electrodes 213a and 213b provided on the upper surface of the first package 210 so that the second package 220 may be flip-chip bonded and stacked on the first package 210. A corresponding pair of lead electrodes 222a and 222b and a plurality of diode electrodes 223a and 223b are provided on the bottom surface.
여기서, 한 쌍의 인출전극(222a,222b)은 제2패키지(220)의 일방향의 양측에 구비되며, 복수 개의 다이오드전극(223a,223b)은 인출전극(222a,222b)과 직각을 이루는 타방향의 적어도 일측에 구비될 수 있다.Here, the pair of lead electrodes 222a and 222b may be provided at both sides of one direction of the second package 220, and the plurality of diode electrodes 223a and 223b may be perpendicular to the lead electrodes 222a and 222b. It may be provided on at least one side of the.
이때, 제1패키지(210) 상에 제2패키지(220)가 플립칩 본딩되어 적층됨으로써, 각각의 순방향 다이오드는 다이오드전극(223a,223b)을 통하여 입출력전극(213a,213b)에 연결되고, 제너다이오드를 경유하여 인출전극(222a,222b)을 통하여 접지전극(212a,212b)에 연결될 수 있다. 따라서, 순방향 다이오드 각각은 입출력전극(213a,213b)과 접지전극(212a,212b) 사이에서 보호부인 제너다이오드와 직렬로 연결될 수 있다. In this case, the second package 220 is flip-chip bonded and stacked on the first package 210 so that each forward diode is connected to the input / output electrodes 213a and 213b through the diode electrodes 223a and 223b, and the zener It may be connected to the ground electrodes 212a and 212b through the lead electrodes 222a and 222b via the diode. Therefore, each of the forward diodes may be connected in series with a zener diode as a protection part between the input / output electrodes 213a and 213b and the ground electrodes 212a and 212b.
몰딩부(230)는 제2패키지(220) 및 제1패키지(210)의 상면을 덮도록 몰딩된다. 이에 의해, 전기적 과부하 보호소자(200)는 복수 개의 개별 패키지를 하나의 패키지로 형성할 수 있다.The molding part 230 is molded to cover the top surfaces of the second package 220 and the first package 210. As a result, the electrical overload protection device 200 may form a plurality of individual packages into one package.
이와 같이 구성된 전기적 과부하 보호소자(200)는 도 10에 도시된 바와 같이, 입출력전극(c1~j1) 사이에 트랜스포머 및 접지전극(a,b)에 연결되는 순방향 다이오드 및 제너다이오드의 등가회로로 나타낼 수 있다. The electrical overload protection device 200 configured as described above is represented by an equivalent circuit of a forward diode and a zener diode connected to the transformer and the ground electrodes a and b between the input / output electrodes c1 to j1 as shown in FIG. 10. Can be.
여기서, 입출력전극(c1~j1)과 접지전극(a1,b1) 사이에서, 제너다이오드와 순방향 다이오드는 각각 직렬 연결됨으로써, 입출력전극(c1~j1)과 접지전극(a1,b1) 사이의 전체 커패시턴스는 낮은 커패시턴스를 갖는 순방향 다이오드보다 작은 커패시턴스를 형성할 수 있다. Here, the Zener diode and the forward diode are connected in series between the input / output electrodes c1 to j1 and the ground electrodes a1 and b1, respectively, so that the total capacitance between the input / output electrodes c1 to j1 and the ground electrodes a1 and b1 is reduced. Can form a smaller capacitance than the forward diode with lower capacitance.
또한, 입출력전극(c1~j1)과 접지전극(a1,b1) 사이의 커패시턴스와 입출력전극(c1~j1) 사이의 트랜스포머에 의해 하이패스 필터가 형성될 수 있다. 이에 의해, 전기적 과부하 보호소자(200)는 고속 신호에 대하여 신호의 감쇠를 최소화하는 동시에 전기적 과부하(EOS) 및 정전기(ESD)의 보호기능을 제공할 수 있다.In addition, a high pass filter may be formed by a capacitance between the input / output electrodes c1 to j1 and the ground electrodes a1 and b1 and a transformer between the input and output electrodes c1 to j1. As a result, the electrical overload protection device 200 may provide a protection function of the electrical overload (EOS) and the static electricity (ESD) while minimizing the attenuation of the signal with respect to the high speed signal.
본 발명의 제3실시예에 따른 전기적 과부하 보호소자(300)는 V by 1 또는 USB 3.0/3.1 신호라인용 보호소자로서, 도 11에 도시된 바와 같이, 제1패키지(310), 제2패키지(320) 및 몰딩부(330)를 포함한다. Electrical overload protection device 300 according to the third embodiment of the present invention is a protection device for the V by 1 or USB 3.0 / 3.1 signal line, as shown in Figure 11, the first package 310, the second package 320 and the molding part 330.
여기서, 제1패키지(310)는 필터부만을 포함하고, 제2패키지(320)는 보호부 및 복수 개의 순방향 다이오드를 포함할 수 있다. 이때, 상기 보호부는 제너다이오드일 수 있고, 상기 필터부는 커패시터로 이루어진 하이패스 필터일 수 있다. Here, the first package 310 may include only the filter unit, and the second package 320 may include a protection unit and a plurality of forward diodes. In this case, the protection unit may be a zener diode, and the filter unit may be a high pass filter made of a capacitor.
즉, 제1패키지(310)는 필터 형태의 패키지이고, 제2패키지(320)는 복수 개의 순방향 다이오드와 하나의 제너다이오드가 단일 부품으로 이루어진 패키지일 수 있다.That is, the first package 310 may be a package in the form of a filter, and the second package 320 may be a package in which a plurality of forward diodes and one zener diode are composed of a single component.
제1패키지(310)는 복수 개의 시트층(311-1~311-5), 한 쌍의 접지전극(312a,312b), 한 쌍의 입출력전극(313a,313b), 및 복수 개의 커패시터전극(314a,315a,314b,315b)을 포함할 수 있다. The first package 310 includes a plurality of sheet layers 311-1 to 311-5, a pair of ground electrodes 312a and 312b, a pair of input / output electrodes 313a and 313b, and a plurality of capacitor electrodes 314a. , 315a, 314b, 315b).
복수 개의 시트층(311-1~311-5)은 소체일 수 있다. 여기서, 제1시트층(311-1)은 최상층으로서 보호층이고, 나머지 시트층(311-2~311-5)은 필터부에 대응한다(도 12 참조). 여기서, 복수 개의 시트층(311-1~311-5)은 유전체를 포함할 수 있다.The plurality of sheet layers 311-1 to 311-5 may be a body. Here, the first sheet layer 311-1 is a protective layer as the uppermost layer, and the remaining sheet layers 311-2 to 311-5 correspond to the filter portion (see FIG. 12). Here, the plurality of sheet layers 311-1 to 311-5 may include a dielectric.
한 쌍의 접지전극(312a,312b) 및 복수 개의 입출력전극(313a,313b)은 제1실시예의 한 쌍의 접지전극(112a,112b) 및 복수 개의 입출력전극(113a,113b)의 구성과 동일하므로 여기서 구체적인 설명은 생략한다(도 11 참조). Since the pair of ground electrodes 312a and 312b and the plurality of input / output electrodes 313a and 313b are the same as those of the pair of ground electrodes 112a and 112b and the plurality of input / output electrodes 113a and 113b of the first embodiment. Detailed description is omitted here (see FIG. 11).
복수 개의 커패시터전극(314a,315a,314b,315b)은 제1시트층(311-1)의 아래의 복수 개의 시트층(311-2~311-5)에 배치될 수 있다(도 12 참조). 이때, 복수 개의 커패시터전극(314a,315a,314b,315b)은 복수 개의 입출력전극(313a,313b) 중 하나에 각각 연결될 수 있다.The plurality of capacitor electrodes 314a, 315a, 314b, and 315b may be disposed in the plurality of sheet layers 311-2 to 311-5 below the first sheet layer 311-1 (see FIG. 12). In this case, the plurality of capacitor electrodes 314a, 315a, 314b, and 315b may be connected to one of the plurality of input / output electrodes 313a and 313b, respectively.
즉, 커패시터전극(314a)은 제2시트층(311-2) 상에 배치되며, 일측이 입출력전극(313b)에 연결되도록 제2시트층(311-2)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 직선 형상으로 연장될 수 있다. That is, the capacitor electrode 314a is disposed on the second sheet layer 311-2, and is disposed at one edge of the second sheet layer 311-2 so that one side is connected to the input / output electrode 313b, and the other side is It is disposed in the center portion, and may extend in a straight shape between.
커패시터전극(314b)은 제3시트층(311-3) 상에 배치되며, 일측이 입출력전극(313b)에 대향하는 입출력전극(313a)에 연결되도록 제3시트층(311-3)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 직선 형상으로 연장될 수 있다. The capacitor electrode 314b is disposed on the third sheet layer 311-3 and one edge of the third sheet layer 311-3 so that one side thereof is connected to the input / output electrode 313a opposite to the input / output electrode 313b. The other side is disposed in the center portion, and may extend in a straight line therebetween.
이와 유사하게, 커패시터전극(315a)은 제4시트층(311-4) 상에 배치되며, 일측이 입출력전극(313b)에 연결되도록 제4시트층(311-4)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 직선 형상으로 연장될 수 있다. Similarly, the capacitor electrode 315a is disposed on the fourth sheet layer 311-4, and is disposed at one side edge of the fourth sheet layer 311-4 so that one side thereof is connected to the input / output electrode 313b. The other side is disposed in the center portion, and may extend in a straight line between them.
커패시터전극(315b)은 제5시트층(311-5) 상에 배치되며, 일측이 입출력전극(313b)에 대향하는 입출력전극(313a)에 연결되도록 제5시트층(311-5)의 일측 가장자리에 배치되고, 타측은 중앙부에 배치되며, 그 사이는 직선 형상으로 연장될 수 있다. The capacitor electrode 315b is disposed on the fifth sheet layer 311-5, and one side edge of the fifth sheet layer 311-5 is connected so that one side thereof is connected to the input / output electrode 313a opposite to the input / output electrode 313b. The other side is disposed in the center portion, and may extend in a straight line therebetween.
이때, 복수 개의 시트층(311-2~311-5) 중 교차 적층되는 시트층에 구비되는 커패시터전극(314a)과 커패시터전극(315a)은 서로 중첩되도록 배치될 수 있다.At this time, the capacitor electrode 314a and the capacitor electrode 315a provided in the sheet layers stacked in a stack among the plurality of sheet layers 311-2 to 311-5 may be disposed to overlap each other.
제2패키지(320)는 복수 개의 순방향 다이오드 및 하나의 제너다이오드를 포함한다. 여기서, 제2패키지(320)는 제2실시예의 제2패키지(220)의 구성과 동일하므로 여기서 구체적인 설명은 생략한다.The second package 320 includes a plurality of forward diodes and one zener diode. Here, since the second package 320 is the same as the configuration of the second package 220 of the second embodiment, a detailed description thereof will be omitted.
몰딩부(330)는 제2패키지(320) 및 제1패키지(310)의 상면을 덮도록 몰딩된다. 이에 의해, 전기적 과부하 보호소자(300)는 복수 개의 개별 패키지를 하나의 패키지로 형성할 수 있다.The molding part 330 is molded to cover the top surfaces of the second package 320 and the first package 310. As a result, the electrical overload protection device 300 may form a plurality of individual packages into one package.
이와 같이 구성된 전기적 과부하 보호소자(300)는 도 13에 도시된 바와 같이, 입출력전극(c2~j2) 사이에 커패시터 및 접지전극(a2,b2)에 연결되는 순방향 다이오드 및 제너다이오드의 등가회로로 나타낼 수 있다. As shown in FIG. 13, the electrical overload protection device 300 configured as described above is represented by an equivalent circuit of a forward diode and a zener diode connected to the capacitor and the ground electrodes a2 and b2 between the input / output electrodes c2 ˜ j2. Can be.
여기서, 입출력전극(c2~j2)과 접지전극(a2,b2) 사이에서, 제너다이오드와 순방향 다이오드는 각각 직렬 연결됨으로써, 입출력전극(c2~j2)과 접지전극(a2,b2) 사이의 전체 커패시턴스는 낮은 커패시턴스를 갖는 순방향 다이오드보다 작은 커패시턴스를 형성할 수 있다. Here, the Zener diode and the forward diode are connected in series between the input / output electrodes c2 ˜ j2 and the ground electrodes a2 and b2, respectively, so that the total capacitance between the input and output electrodes c2 ˜ j2 and the ground electrodes a2 and b2. Can form a smaller capacitance than the forward diode with lower capacitance.
또한, 입출력전극(c2~j2)과 접지전극(a2,b2) 사이의 커패시턴스와 입출력전극(c2~j2) 사이의 커패시터에 의해 하이패스필터가 형성될 수 있다. 이에 의해, 전기적 과부하 보호소자(300)는 고속 신호에 대하여 신호의 감쇠를 최소화하는 동시에 전기적 과부하(EOS) 및 정전기(ESD)의 보호기능을 제공할 수 있다.In addition, a high pass filter may be formed by a capacitance between the input / output electrodes c2 ˜ j2 and the ground electrodes a2 and b2 and a capacitor between the input / output electrodes c2 ˜ j2. As a result, the electrical overload protection device 300 may provide a protection function of the electrical overload (EOS) and the static electricity (ESD) while minimizing the attenuation of the signal with respect to the high speed signal.
본 발명의 제4실시예에 따른 전기적 과부하 보호소자(400)는 V by 1 또는 USB 3.0/3.1 신호라인용 보호소자로서, 도 14에 도시된 바와 같이, 제1패키지(410), 제2패키지(420), 및 몰딩부(430)를 포함한다. Electrical overload protection device 400 according to the fourth embodiment of the present invention is a protection device for the V by 1 or USB 3.0 / 3.1 signal line, as shown in Figure 14, the first package 410, the second package 420, and the molding unit 430.
여기서, 제1패키지(410)는 보호부 및 필터부를 포함하고, 제2패키지(420)는 단일 패키지로 이루어진 순방향 다이오드를 포함할 수 있다. 즉, 제1패키지(410)는 보호소자 형태의 패키지이고, 제2패키지(420)는 단일 부품으로 이루어진 패키지일 수 있다. Here, the first package 410 may include a protection unit and a filter unit, and the second package 420 may include a forward diode made of a single package. That is, the first package 410 may be a package in the form of a protection device, and the second package 420 may be a package composed of a single component.
이때, 상기 보호부는 바리스터일 수 있고, 상기 필터부는 바리스터와 순방향 다이오드에 의해 형성되는 커패시터로 이루어진 하이패스필터일 수 있다. In this case, the protection part may be a varistor, and the filter part may be a high pass filter including a capacitor formed by the varistor and the forward diode.
제1패키지(410)는 복수 개의 시트층(411-1~411-2), 한 쌍의 접지전극(412a,412b), 한 쌍의 입출력전극(413a,413b), 제1전극(414), 및 복수 개의 제2전극(415)을 포함할 수 있다. The first package 410 includes a plurality of sheet layers 411-1 to 411-2, a pair of ground electrodes 412a and 412b, a pair of input / output electrodes 413a and 413b, a first electrode 414, And a plurality of second electrodes 415.
복수 개의 시트층(411-1~111-2)은 소체일 수 있다. 여기서, 복수 개의 시트층(411-1~411-2)은 바리스터 물질층을 포함할 수 있다(도 15 참조). The plurality of sheet layers 411-1 to 111-2 may be a body. Here, the plurality of sheet layers 411-1 to 411-2 may include varistor material layers (see FIG. 15).
한 쌍의 접지전극(412a,412b), 복수 개의 입출력전극(413a,413b), 및 제1전극(414)은 제1실시예의 한 쌍의 접지전극(112a,112b), 복수 개의 입출력전극(113a,113b), 및 제1전극(114)의 구성과 동일하므로 여기서 구체적인 설명은 생략한다(도 14 참조). The pair of ground electrodes 412a and 412b, the plurality of input / output electrodes 413a and 413b, and the first electrode 414 are the pair of ground electrodes 112a and 112b and the plurality of input / output electrodes 113a of the first embodiment. 113b and the first electrode 114, the detailed description thereof is omitted here (see FIG. 14).
복수 개의 제2전극(415)은 제1시트층(411-1)의 아래의 제2시트층(411-2) 상에 제1전극(414)과 일부 중첩되게 배치될 수 있다(도 15 참조). 이러한 제2전극(415)은 제1전극(414)에 대향하는 바리스터의 타측 전극으로서 복수 개의 입출력전극(413a,413b)에 각각 연결될 수 있다. 즉, 복수 개의 제2전극(415)은 제2시트층(411-2)의 양측 가장자리에 연결되는 직선 형상으로 구비될 수 있다.The plurality of second electrodes 415 may be partially overlapped with the first electrodes 414 on the second sheet layer 411-2 below the first sheet layer 411-1 (see FIG. 15). ). The second electrode 415 may be connected to the plurality of input / output electrodes 413a and 413b as the other electrode of the varistor facing the first electrode 414, respectively. That is, the plurality of second electrodes 415 may be provided in a straight line connected to both edges of the second sheet layer 411-2.
제2패키지(420)는 하나의 단일 부품으로 이루어진 순방향 다이오드일 수 있다. 여기서, 제2패키지(420)는 제1실시예의 제2패키지(120)의 구성과 동일하므로 여기서 구체적인 설명은 생략한다.The second package 420 may be a forward diode composed of one single component. Here, since the second package 420 is the same as the configuration of the second package 120 of the first embodiment, a detailed description thereof will be omitted.
이때, 제1패키지(410) 상에 제2패키지(420)가 플립칩 본딩되어 적층됨으로써, 상기 순방향 다이오드는 입출력전극(413a,413b)과 접지전극(412a,412b) 사이에서 보호부와 직렬로 연결될 수 있다. In this case, the second package 420 is flip-chip bonded and stacked on the first package 410 so that the forward diode is connected in series with the protection unit between the input / output electrodes 413a and 413b and the ground electrodes 412a and 412b. Can be connected.
몰딩부(430)는 제2패키지(420) 및 제1패키지(410)의 상면을 덮도록 몰딩된다. 이에 의해, 전기적 과부하 보호소자(400)는 복수 개의 개별 패키지를 하나의 패키지로 형성할 수 있다.The molding part 430 is molded to cover the top surfaces of the second package 420 and the first package 410. As a result, the electrical overload protection device 400 may form a plurality of individual packages into one package.
이와 같이 구성된 전기적 과부하 보호소자(400)는 도 16에 도시된 바와 같이, 입출력전극(c3~j3)과 접지전극(a3,b3) 사이에 직렬 연결되는 바리스터와 순방향 다이오드의 등가회로로 나타낼 수 있다. As illustrated in FIG. 16, the electrical overload protection device 400 configured as described above may be represented by an equivalent circuit of a varistor and a forward diode connected in series between the input / output electrodes c3 to j3 and the ground electrodes a3 and b3. .
여기서, 입출력전극(c3~j3)과 접지전극(a3,b3) 사이에서, 바리스터와 순방향 다이오드는 각각 직렬 연결됨으로써, 입출력전극(c3~j3)과 접지전극(a3,b3) 사이의 전체 커패시턴스는 낮은 커패시턴스를 갖는 순방향 다이오드보다 작은 커패시턴스를 형성할 수 있다. Here, the varistor and the forward diode are connected in series between the input / output electrodes c3 to j3 and the ground electrodes a3 and b3, so that the total capacitance between the input and output electrodes c3 to j3 and the ground electrodes a3 and b3 is reduced. It is possible to form smaller capacitances than forward diodes with lower capacitance.
또한, 입출력전극(c3~j3)과 접지전극(a3,b3) 사이의 커패시턴스에 의해 하이패스 필터가 형성될 수 있다. 이에 의해, 고속 신호에 대하여 신호의 감쇠를 최소화하는 동시에 전기적 과부하(EOS) 및 정전기(ESD)의 보호기능을 제공할 수 있다.In addition, a high pass filter may be formed by a capacitance between the input / output electrodes c3 ˜ j3 and the ground electrodes a3 and b3. As a result, it is possible to minimize the attenuation of the signal with respect to the high-speed signal and to provide a function of protecting the electrical overload (EOS) and the static electricity (ESD).
본 발명의 제5실시예에 따른 전기적 과부하 보호소자(500)는 도 17에 도시된 바와 같이, 복수의 시트층(541,543,545,547), 접지전극(542), 내부전극(542), 및 저항체(546)를 포함한다. As illustrated in FIG. 17, the electrical overload protection device 500 according to the fifth embodiment of the present invention includes a plurality of sheet layers 541, 543, 545, 547, a ground electrode 542, an internal electrode 542, and a resistor 546. It includes.
복수의 시트층(541,543,545,547)은 접지전극(542)이 형성된 제1시트층(541)과, 내부전극(544)이 형성되며 제1시트층(541) 상에 적층된 제2시트층(543)과, 저항체(546)가 형성되며 제2시트층(543) 상에 적층된 제3시트층(545)과, 제3시트층(545)의 상부에 적층된 제4시트층(547)을 포함할 수 있다.The plurality of sheet layers 541, 543, 545, 547 may include a first sheet layer 541 having a ground electrode 542 and a second sheet layer 543 formed on the first sheet layer 541 with an internal electrode 544 formed thereon. And a third sheet layer 545 formed on the second sheet layer 543 and a fourth sheet layer 547 stacked on top of the third sheet layer 545. can do.
여기서, 상기 제1 내지 제4시트층(541,143,145,147)의 측면에는 내부전극(542)에 전기적으로 연결되는 제1외부전극(548)과, 저항체(546)에 전기적으로 연결되는 제2외부전극(549)이 형성되어 있으며, 도면에는 생략되었으나 접지전극(542)에 연결되는 외부전극이 더 포함된다. 접지전극(542)에 연결되는 외부전극은 도면상 상기 제1 내지 제4시트층(541,143,145,147)의 적층구조의 전면 또는 배면에 위치하거나, 전면과 배면에 모두 위치할 수 있다.Here, the first external electrode 548 electrically connected to the internal electrode 542 and the second external electrode 549 electrically connected to the resistor 546 may be formed on side surfaces of the first to fourth sheet layers 541, 143, 145 and 147. ) Is omitted and is omitted in the drawing, but further includes an external electrode connected to the ground electrode 542. The external electrode connected to the ground electrode 542 may be located on the front or rear surface of the stack structure of the first to fourth sheet layers 541, 143, 145, and 147, or both the front and rear surfaces thereof.
접지전극(542)은 제1외부전극(548) 및 제2외부전극(549) 모두와 연결되지 않도록 제1시트층(541)의 중앙에 배치될 수 있다.The ground electrode 542 may be disposed in the center of the first sheet layer 541 so as not to be connected to both the first external electrode 548 and the second external electrode 549.
내부전극(544)은 일단이 제1외부전극(548)에 연결되고, 타단은 접지전극(542)과 대향하도록 배치될 수 있다.One end of the inner electrode 544 may be connected to the first outer electrode 548, and the other end thereof may be disposed to face the ground electrode 542.
저항체(546)는 일단이 제2외부전극(549)에 연결되고, 타단은 내부전극(544)과 대향하도록 배치되며, 평면상에서 다수의 절곡부를 가지는 나선형의 구조일 수 있다. One end of the resistor 546 is connected to the second external electrode 549, and the other end thereof is disposed to face the internal electrode 544, and may have a spiral structure having a plurality of bent portions on a plane.
이러한 전기적 과부하 보호소자(500)는 도 18에 도시된 바와 같이, 전기적 과부하 및 정전기에 대한 보호기능을 갖는 보호부(510), 일단이 보호부(510)의 일단에 연결된 커패시터(520)와, 상기 커패시터(520)의 타단에 연결된 저항(530)을 포함하는 RC회로일 수 있다.As shown in FIG. 18, the electrical overload protection device 500 includes a protection unit 510 having a protection function against electrical overload and static electricity, a capacitor 520 connected to one end of the protection unit 510, and It may be an RC circuit including a resistor 530 connected to the other end of the capacitor 520.
여기서, 저항체(546)는 저항(530)에 대응하며, 내부전극(544)은 커패시터(520)와 보호부(510)의 접점을 이루어 커패시터(520) 또는 보호부(510)의 일측 전극에 대응한다. Here, the resistor 546 corresponds to the resistor 530, and the internal electrode 544 forms a contact point between the capacitor 520 and the protection unit 510 to correspond to one electrode of the capacitor 520 or the protection unit 510. do.
즉, 커패시터(520)는 제3시트층(545)을 사이에 두고 위치하는 저항체(556)와 내부전극(542)의 중첩 영역으로 정의된다. 이때, 상기 제3시트층(545)은 소정의 유전율을 가지는 유전체일 수 있다.That is, the capacitor 520 is defined as an overlapping region of the resistor 556 and the internal electrode 542 positioned with the third sheet layer 545 therebetween. In this case, the third sheet layer 545 may be a dielectric having a predetermined dielectric constant.
또한, 접지전극(542)과 내부전극(544)은 보호부(510)에 대응한다. 이때 접지전극(542)과 내부전극(544) 사이는 공극이거나, 공극의 일부 또는 전부에 채워진 방전물질일 수 있다. 즉, 제2시트층(543)은 방전물질을 포함할 수 있다. 일례로, 보호부(510)는 써프레서 또는 바리스터일 수 있다. In addition, the ground electrode 542 and the internal electrode 544 correspond to the protection unit 510. At this time, the ground electrode 542 and the internal electrode 544 may be a gap or a discharge material filled in part or all of the gap. That is, the second sheet layer 543 may include a discharge material. In one example, the protection unit 510 may be a suppressor or a varistor.
이때, 상기 RC회로에서 커패시터(520)의 정전용량을 낮출수록 ESD 감쇠 성능을 확인할 수 있는 클램프 전압의 값도 낮아지게 되며, ESD 동작전압도 낮출 수 있다.In this case, as the capacitance of the capacitor 520 is lowered in the RC circuit, the value of the clamp voltage for confirming the ESD attenuation performance is also lowered, and the ESD operating voltage may be lowered.
그러나 커패시터(520)의 정전용량이 일정한 값 이하가 되면, 컷오프 주파수의 증가에 의해 고속 신호가 정상적으로 전송되지 않을 수 있다.However, when the capacitance of the capacitor 520 is less than a predetermined value, the high-speed signal may not be transmitted normally due to the increase in the cutoff frequency.
커패시터(520)와 저항(530)은 각각 ESD 또는 EOS의 감쇠 효과를 가지는 것으로, 본 실시예에서는 커패시터(520)와 저항(530) 복합소자를 사용하여 감쇠 효과를 높일 수 있다.The capacitor 520 and the resistor 530 each have an attenuation effect of ESD or EOS. In this embodiment, the attenuation effect can be increased by using the capacitor 520 and the resistor 530 composite device.
본 실시예에서는 전기적 과부하 보호소자(500)가 적층형 구조의 복합소자로 도시되고 설명되었으나, 보호부(510), 커패시터(520), 및 저항(530)을 각각 개별소자로 구현하고, 블록 타입으로 조합한 구조로 구현될 수 있으며, 또한 반도체 제조 기술을 이용하여 구현될 수 있다.Although the electrical overload protection device 500 is illustrated and described as a composite device having a stacked structure in the present embodiment, the protection unit 510, the capacitor 520, and the resistor 530 are implemented as individual elements, respectively, in a block type. It can be implemented in a combined structure, it can also be implemented using a semiconductor manufacturing technology.
이때, 신호의 손실 없이 ESD 및 EOS를 효과적으로 방호하기 위해서는 전기적 과부하 보호소자(500)는 하이패스필터로 구현되어야 한다. 따라서, 커패시터(520)의 정전용량은 10 내지 1000nF의 범위이고 저항(530)은 2 내지 5Ω의 범위가 되도록 하는 것이 바람직하다.In this case, in order to effectively protect ESD and EOS without losing a signal, the electrical overload protection device 500 should be implemented as a high pass filter. Therefore, the capacitance of the capacitor 520 is preferably in the range of 10 to 1000 nF and the resistance 530 is in the range of 2 to 5 Ω.
도 19를 참조하면, 직렬 저항(Series Resistance)은 저항값에 무관하게 하이패스 특성을 갖는다. 여기서 하이패스 특성이라 함은 컷오프 주파수 이상에서 감쇠가 감소하는 특징을 뜻한다.Referring to FIG. 19, the series resistance has a high pass characteristic regardless of the resistance value. Here, the high pass characteristic refers to a feature in which the attenuation is reduced above the cutoff frequency.
그러나 저항값이 클수록 4GHz 대역에서도 감쇠비가 크기 때문에 고속신호를 감쇠시킬 수 있다. 따라서 앞서 설명한 바와 같이 저항(530)을 2 내지 5Ω의 저항값을 가지는 것을 사용하는 것이 바람직하다. 2Ω 미만에서는 하이패스 특징이 매우 적게 나타나며, 5Ω를 초과하는 경우에는 감쇠비가 커서 고속데이터의 전송시 감쇠에 따른 데이터 손실이 발생할 확률이 높아지게 된다.However, the larger the resistance value, the higher the attenuation ratio in the 4GHz band, so that the high-speed signal can be attenuated. Therefore, as described above, it is preferable to use the resistor 530 having a resistance value of 2 to 5Ω. The high pass characteristic is very small at less than 2Ω, and the attenuation ratio is large when exceeding 5Ω, thereby increasing the probability of data loss due to attenuation during high-speed data transmission.
또한, 도 20을 참조하면, 직렬 커패시턴스(Series Capacitance)는 다양한 전체 주파수 대역에서 밴드패스 필터의 효과를 가지게 되지만, 고속 신호용의 4~6GHz 주변에서는 감쇠율이 낮으며, 6GHz 이상에서는 감쇠율이 높은 특징을 가지는 10 내지 1000nF의 커패시터(520)를 사용한다.Further, referring to FIG. 20, the series capacitance has the effect of a bandpass filter in various frequency bands, but has a low attenuation rate around 4 to 6 GHz for high-speed signals, and a high attenuation rate above 6 GHz. Branches use a capacitor 520 of 10 to 1000 nF.
위와 같이 커패시터(520)와 저항(530) 복합소자를 사용하는 하이패스 필터는 고속신호의 감쇠를 줄이면서 ESD 및 EOS 방호에 효과적인 것을 알 수 있다.As described above, it can be seen that the high pass filter using the capacitor 520 and the resistor 530 composite element is effective for ESD and EOS protection while reducing the attenuation of the high speed signal.
한편, 저항(530)의 저항값을 2Ω으로 고정하고, 10nF의 정전용량을 가지는 커패시터(520)와 100nF의 정전용량을 가지는 커패시터(520)를 각각 포함하는 두 시료에 대한 ESD 보호 테스트 결과를 도 21에 도시하였다.On the other hand, the resistance value of the resistor 530 is fixed to 2Ω, and the ESD protection test results for the two samples including a capacitor 520 having a capacitance of 10 nF and a capacitor 520 having a capacitance of 100 nF, respectively. 21 is shown.
테스트는 ESD 2kV부터 0.5kV씩 증가시키면서 이루어졌으며, 각 시료에 대하여 ESD 동작전압과 ESD 감쇠 성능을 나타내는 클램프 전압(Vp)을 측정하고, 이를 보호부(510)로서 써프레서가 단독으로 사용되는 시료와 비교하였다.The test was performed by increasing the ESD voltage from 2kV to 0.5kV. For each sample, a clamp voltage (Vp) indicating the ESD operating voltage and the ESD attenuation performance was measured, and the sample in which the suppressor was used alone as the protection unit 510 was used. Compared with.
써프레서만 사용한 시료의 ESD 동작전압은 3.5kV이며, 클램프 전압(Vp)은 86V로 측정되었다.The ESD operating voltage of the sample using only the suppressor was 3.5kV and the clamp voltage (Vp) was measured at 86V.
본 실시예와 같이 보호부(510)인 써프레서와 함께 직렬연결되는 커패시터(520)와 저항(530)을 사용하는 경우에는 ESD 동작전압이 2~2.5kV이며, 클램프 전압(Vp)이 61~70V로 현저하게 낮아지는 것을 확인할 수 있다.In the case of using the capacitor 520 and the resistor 530 connected in series with the suppressor 510 as in the present embodiment, the ESD operating voltage is 2 to 2.5 kV and the clamp voltage Vp is 61 to. You can see that it is significantly lowered to 70V.
한편, 상기 하이패스필터의 다른 형태로서, 도 22를 참조하면, 도 18의 등가회로도에서 인덕터(550)를 더 포함하여 구성될 수 있다.Meanwhile, as another form of the high pass filter, referring to FIG. 22, the inductor 550 may be further included in the equivalent circuit diagram of FIG. 18.
상기 인덕터(550)의 일단은 커패시터(520)와 저항(530)의 접점과 접지 사이에 위치하며, RLC 필터를 구성하여 고속신호의 감쇠 없이 ESD 및 EOS를 차단 또는 바이패스시키는 역할을 한다.One end of the inductor 550 is positioned between the contact point of the capacitor 520 and the resistor 530 and the ground, and forms an RLC filter to block or bypass ESD and EOS without attenuating the high speed signal.
도 22의 RLC 필터는 하이패스 필터이며, 4GHz 이상의 고주파 신호를 감쇠 없이 전송할 수 있다. 이때 인덕터(550)의 역할은 차동 임피던스를 제공하는 것이다. 차동 임피던스의 제공에 의하여 전기적 과부하 보호소자(500)를 전자장치에 적용할 때, 회로 정합을 위하여 커패시터(520)의 정전용량을 보완할 필요가 없다.The RLC filter of FIG. 22 is a high pass filter and may transmit a high frequency signal of 4 GHz or more without attenuation. At this time, the role of the inductor 550 is to provide a differential impedance. When the electrical overload protection device 500 is applied to an electronic device by providing a differential impedance, it is not necessary to compensate the capacitance of the capacitor 520 for circuit matching.
테스트 결과로서 USB 3.0 방식을 사용하는 전자장치에 전기적 과부하 보호소자(500)를 적용할 때 40~48μH의 인덕터(550)를 사용하는 것이 바람직하다.As a result of the test, when the electrical overload protection device 500 is applied to an electronic device using the USB 3.0 method, it is preferable to use the inductor 550 of 40 to 48 μH.
도 23을 참조하면 분로 인덕턴스(Shunt Inductance)는 밴드패스의 형태를 나타내며, 고속신호의 데이터의 바이패스를 방지하면서 EOS를 바이패스시키는 역할을 할 수 있다. 도면에 도시되지는 않았으나 5.6 내지 22μH의 시험결과에서처럼 스커트(Skirt)특성은 인덕턱스의 증가에 따라 향상되나 컷오프 주파수가 낮아지게 된다. 컷오프 주파수와 스커트 특성을 고려하여 앞서 언급한 바와 같이 인덕터(550)의 인덕턴스는 40 내지 48μH인 것이 바람직하다. Referring to FIG. 23, the shunt inductance indicates a form of a band pass, and may serve to bypass EOS while preventing the bypass of data of a high speed signal. Although not shown in the drawings, as in the test results of 5.6 to 22 μH, the skirt characteristic is improved with increasing inductance, but the cutoff frequency is lowered. In consideration of the cutoff frequency and the skirt characteristic, as described above, the inductance of the inductor 550 is preferably 40 to 48 mu H.
또한, 상기 하이패스필터의 다른 형태로서, 도 24를 참조하면, 도 18의 등가회로도에서 바이패스 저항(560)을 더 추가하여 구성할 수 있다.As another form of the high pass filter, referring to FIG. 24, a bypass resistor 560 may be further added to the equivalent circuit diagram of FIG. 18.
여기서, 바이패스 저항(560)은 커패시터(520)와 저항(530)의 접점과 접지를 연결하는 것으로, 과전류를 접지로 바이패스 시키는 역할을 한다.Here, the bypass resistor 560 connects the contact of the capacitor 520 and the resistor 530 with the ground, and serves to bypass the overcurrent to the ground.
바이패스 저항(560)의 저항값을 10, 50, 100, 1000Ω으로 하고, 저항(530)의 저항값을 5, 10, 20, 30Ω으로 가변하면서 ESD 테스트를 수행한 결과를 도 25에 도시하였다.25 illustrates the results of performing the ESD test while setting resistance values of the bypass resistor 560 to 10, 50, 100, and 1000 Ω, and changing resistance values of the resistor 530 to 5, 10, 20, and 30 Ω. .
도 25를 참조하면 바이패스 저항(560)의 값이 증가할수록 클램핑 전압은 증가한다. 예를 들어 저항(530)의 저항값을 10Ω으로 고정한 상태에서, 바이패스 저항(560)의 값을 10, 50, 100, 1000Ω으로 단계적으로 증가시키는 경우 클램핑 전압은 6.63V, 22.59V, 30.81V, 46.0V로 증가하게 된다. Referring to FIG. 25, the clamping voltage increases as the value of the bypass resistor 560 increases. For example, when the resistance value of the resistor 530 is fixed to 10 Ω, and the value of the bypass resistor 560 is gradually increased to 10, 50, 100, and 1000 Ω, the clamping voltages are 6.63 V, 22.59 V, and 30.81 V. , 46.0V.
반대로 저항(530)의 저항값이 증가할수록 클램핑 전압은 낮아지게 된다. 예를 들어 바이패스 저항(560)의 저항값을 10Ω으로 고정한 상태에서 저항(530)의 저항값을 5, 10, 20, 30Ω으로 증가시키는 경우, 클램핑 전압은 7.42V, 6.63V, 6.0V, 4.02V로 낮아지는 것을 확인할 수 있다.On the contrary, as the resistance of the resistor 530 increases, the clamping voltage becomes lower. For example, when the resistance value of the resistor 530 is increased to 5, 10, 20, 30Ω while the resistance value of the bypass resistor 560 is fixed to 10Ω, the clamping voltages are 7.42V, 6.63V, 6.0V, You can see that it drops to 4.02V.
상기 바이패스 저항(560)을 부가하였을 때에는 고속신호의 감쇠와 클램핑 전압을 고려하여 상기 저항(530)의 값을 변경할 필요가 있으며, 바이패스 저항(560)의 저항값은 바람직하게 900Ω 내지 1kΩ을 사용할 수 있다.When the bypass resistor 560 is added, it is necessary to change the value of the resistor 530 in consideration of the attenuation of the high speed signal and the clamping voltage, and the resistance value of the bypass resistor 560 is preferably 900Ω to 1kΩ. Can be used.
도 26의 그래프에서 확인할 수 있는 바와 같이 분로 저항은 저항값이 100 내지 10000Ω의 범위 모두 1GHz 이상의 주파수 대역에서는 급격한 감쇠를 보인다. 특히 1000Ω을 초과하는 저항값의 시험결과는 4GHz 이상의 범위에서 감쇠율이 높으며, 820Ω이하에서는 만족스러운 스커트를 얻을 수 없다.As can be seen from the graph of FIG. 26, the shunt resistance shows a rapid attenuation in the frequency band of 1 GHz or more in the range of resistance 100 to 10000 Ω. In particular, test results of resistance values exceeding 1000Ω have high attenuation in the range of 4GHz and above, and satisfactory skirts cannot be obtained below 820Ω.
따라서 바이패스 저항(560)은 900Ω 내지 1kΩ을 사용하는 것이 바람직하다.Therefore, the bypass resistor 560 preferably uses 900 Ω to 1 kΩ.
상술한 바와 같은 본 발명의 일 실시예에 따른 전기적 과부하 보호소자(100,200,300,400,500)는 신호입력단자와 내부회로 사이의 신호 전송라인에 위치한다.Electrical overload protection device (100, 200, 300, 400, 500) according to an embodiment of the present invention as described above is located in the signal transmission line between the signal input terminal and the internal circuit.
여기서, 상기 신호입력단자는 전자장치의 외부에 일부가 노출되어 외부 케이블이 연결될 수 있도록 하는 것으로, USB, HDMI, HML 또는 고속데이터의 전송이 가능한 기타의 전송규격에 만족하는 단자일 수 있다. 바람직하게는 USB 3.0 이상 등 적어도 4Gbps 이상의 속도를 가지는 고속 데이터 전송규격에 만족하는 단자로 한다.In this case, the signal input terminal is exposed to the outside of the electronic device so that an external cable can be connected, and may be a terminal that satisfies USB, HDMI, HML, or other transmission standard capable of high-speed data transmission. Preferably, the terminal satisfies a high-speed data transfer standard having a speed of at least 4 Gbps, such as USB 3.0 or higher.
또한, 상기 내부회로는 집적화된 칩을 포함하며, 상기 전자장치의 내부기판에 설치된다. In addition, the internal circuit includes an integrated chip and is installed on an internal substrate of the electronic device.
이때, 상기 신호 전송라인은 상기 신호입력단자와 내부회로를 상호 연결하여 신호입력단자를 통해 입력된 데이터가 내부회로에 입력되어 처리될 수 있도록 하는 것으로, 수신라인(Rx)과 송신라인(Tx)을 포함하는 개념으로 이해될 수 있다.In this case, the signal transmission line interconnects the signal input terminal and the internal circuit so that data input through the signal input terminal can be input to the internal circuit and processed. The receiving line Rx and the transmission line Tx It can be understood as a concept that includes.
상기 신호 전송라인은 내부기판에 패터닝된 도전체이거나 상기 신호입력단자와 내부회로를 직접 연결하는 도선일 수 있다. The signal transmission line may be a conductor patterned on an internal substrate or a conductor directly connecting the signal input terminal to an internal circuit.
본 발명의 일 실시예에 따른 전기적 과부하 보호소자(100,200,300,400,500)는 상기 신호 전송라인에 직렬로 연결된다. 이때 신호 전송라인은 앞서 설명한 바와 같이 수신라인과 송신라인을 포함할 수 있는 것으로, 전기적 과부하 보호소자(500)는 동일 규격, 동일 소자(또는 복합소자)를 수신라인과 송신라인에 각각 배치한 것일 수 있다.Electrical overload protection device (100, 200, 300, 400, 500) according to an embodiment of the present invention is connected in series to the signal transmission line. In this case, the signal transmission line may include a reception line and a transmission line as described above, and the electrical overload protection device 500 is the same standard and the same device (or a composite device) is disposed on the reception line and the transmission line, respectively. Can be.
이상에서 본 발명의 일 실시예에 대하여 설명하였으나, 본 발명의 사상은 본 명세서에 제시되는 실시 예에 제한되지 아니하며, 본 발명의 사상을 이해하는 당업자는 동일한 사상의 범위 내에서, 구성요소의 부가, 변경, 삭제, 추가 등에 의해서 다른 실시 예를 용이하게 제안할 수 있을 것이나, 이 또한 본 발명의 사상범위 내에 든다고 할 것이다.Although one embodiment of the present invention has been described above, the spirit of the present invention is not limited to the embodiments set forth herein, and those skilled in the art who understand the spirit of the present invention, within the scope of the same idea, the addition of components Other embodiments may be easily proposed by changing, deleting, adding, and the like, but this will also fall within the spirit of the present invention.

Claims (12)

  1. 고속신호를 필터링하는 필터부, 및 전기적 과부하 및 정전기에 대한 보호기능을 갖는 보호부 중 하나 또는 둘 다를 포함하는 제1패키지; A first package including one or both of a filter unit filtering a high speed signal, and a protection unit having a protection function against electric overload and static electricity;
    상기 보호부에 직렬 연결되는 순방향 다이오드를 포함하며, 상기 제1패키지 상에 플립칩 본딩되어 적층되는 제2패키지; 및A second package including a forward diode connected in series to the protection unit, the second package being flip-chip bonded and stacked on the first package; And
    상기 제2패키지를 몰딩하는 몰딩부;를 포함하는 전기적 과부하 보호소자.Electrical overload protection device comprising a; molding unit for molding the second package.
  2. 제1항에 있어서,The method of claim 1,
    상기 제1패키지가 상기 필터부를 포함하고, 상기 제2패키지가 상기 보호부를 포함하는 전기적 과부하 보호소자.And the first package includes the filter unit, and the second package includes the protection unit.
  3. 제1항에 있어서, The method of claim 1,
    상기 제2패키지는 상기 순방향 다이오드가 단일 패키지로 구성되는 전기적 과부하 보호소자.The second package is an electrical overload protection device wherein the forward diode is composed of a single package.
  4. 제1항에 있어서, The method of claim 1,
    상기 보호부는 바리스터이고, The protection part is a varistor,
    상기 제1패키지는 상기 필터부 및 상기 바리스터 중 적어도 하나를 포함하는 전기적 과부하 보호소자.And the first package includes at least one of the filter unit and the varistor.
  5. 제2항에 있어서, The method of claim 2,
    상기 보호부는 제너다이오드이고, The protective part is a zener diode,
    상기 제2패키지는 상기 제너다이오드와 상기 순방향 다이오드를 포함하는 전기적 과부하 보호소자.And the second package includes the zener diode and the forward diode.
  6. 제1항에 있어서, 상기 제1패키지는,The method of claim 1, wherein the first package,
    일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; A pair of ground electrodes provided in a 'c' shape on both sides of one direction;
    상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes;
    복수 개의 시트층을 포함하는 소체; A body comprising a plurality of sheet layers;
    최상위의 제1시트층 상에서 상기 한 쌍의 접지전극 사이에 일정간격 이격배치되는 제1전극; A first electrode spaced at a predetermined interval between the pair of ground electrodes on the first sheet layer on the top;
    상기 제1시트층 아래의 제2시트층 상에 상기 제1전극과 일부 중첩되게 배치되고, 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 제2전극; 및A plurality of second electrodes disposed on the second sheet layer below the first sheet layer to partially overlap the first electrode and connected to any one of the plurality of input / output electrodes; And
    상기 제2시트층 아래의 복수 개의 시트층에서 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 저항체;를 포함하고, And a plurality of resistors connected to any one of the plurality of input / output electrodes in the plurality of sheet layers under the second sheet layer.
    서로 인접한 시트층 상에 구비되는 저항체는 비아홀을 통하여 연결되며, 서로 대향하는 입출력전극에 연결되는 전기적 과부하 보호소자.The resistors provided on the sheet layers adjacent to each other are connected through via holes, and are electrically connected to the input / output electrodes facing each other.
  7. 제2항에 있어서, 상기 제1패키지는, The method of claim 2, wherein the first package,
    일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; A pair of ground electrodes provided in a 'c' shape on both sides of one direction;
    상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes;
    복수 개의 순차 적층되는 시트층을 포함하는 소체; 및A body comprising a plurality of sequentially stacked sheet layers; And
    상기 복수 개의 시트층에서 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 코일패턴;을 포함하고, And a plurality of coil patterns connected to any one of the plurality of input / output electrodes in the plurality of sheet layers.
    상기 복수 개의 시트층 중 교차 적층되는 시트층 상에 구비되는 코일패턴은 비아홀을 통하여 연결되며, 서로 대향하는 입출력전극에 연결되는 전기적 과부하 보호소자.The coil pattern provided on the sheet layer that is cross-laminated among the plurality of sheet layers is connected via a via hole, the electrical overload protection device connected to the input and output electrodes facing each other.
  8. 제2항에 있어서, 상기 제1패키지는, The method of claim 2, wherein the first package,
    일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; A pair of ground electrodes provided in a 'c' shape on both sides of one direction;
    상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes;
    복수 개의 시트층을 포함하는 소체; 및A body comprising a plurality of sheet layers; And
    상기 복수 개의 시트층에서 상기 복수 개의 입출력전극 중 어느 하나에 연결되는 복수 개의 커패시터전극;을 포함하고, And a plurality of capacitor electrodes connected to any one of the plurality of input / output electrodes in the plurality of sheet layers.
    상기 복수 개의 시트층 중 교차 적층되는 시트층 상에 구비되는 커패시터전극은 서로 중첩되도록 배치되는 전기적 과부하 보호소자.Capacitor electrodes provided on the sheet layer that is cross-laminated among the plurality of sheet layers are disposed to overlap each other.
  9. 제1항에 있어서, 상기 제1패키지는, The method of claim 1, wherein the first package,
    일방향의 양측에 'ㄷ'자 형상으로 구비되는 한 쌍의 접지전극; A pair of ground electrodes provided in a 'c' shape on both sides of one direction;
    상기 한 쌍의 접지전극과 직각을 이루는 타방향의 양측에 'ㄷ'자 형상으로 구비되는 복수 개의 입출력전극; A plurality of input / output electrodes provided in a 'c' shape on both sides of the other direction perpendicular to the pair of ground electrodes;
    복수 개의 시트층을 포함하는 소체; A body comprising a plurality of sheet layers;
    최상위의 제1시트층 상에서 상기 한 쌍의 접지전극 사이에 일정간격 이격배치되는 제1전극; 및A first electrode spaced at a predetermined interval between the pair of ground electrodes on the first sheet layer on the top; And
    상기 제1시트층 아래의 제2시트층 상에 상기 제1전극과 일부 중첩되게 배치되고, 상기 복수 개의 입출력전극 중 서로 대향하는 입출력전극에 연결되는 복수 개의 제2전극;을 포함하는 전기적 과부하 보호소자.And a plurality of second electrodes disposed on the second sheet layer below the first sheet layer to partially overlap the first electrode and connected to input / output electrodes facing each other among the plurality of input / output electrodes. device.
  10. 제1항 또는 제3항에 있어서, 상기 제2패키지는, The method of claim 1 or 3, wherein the second package,
    하면에서 일방향의 양측에 구비되는 한 쌍 인출전극; 및A pair of lead-out electrodes provided on both sides of one direction at a lower surface thereof; And
    상기 한 쌍의 인출전극과 직각을 이루는 타방향의 적어도 일측에 구비되는 복수 개의 다이오드전극을 포함하는 전기적 과부하 보호소자.An electrical overload protection device comprising a plurality of diode electrodes provided on at least one side of the other direction perpendicular to the pair of extraction electrodes.
  11. 제1항 또는 제2항에 있어서, The method according to claim 1 or 2,
    상기 고속신호는 LVDS(Low voltage differential signaling), HDMI(High Definition Multimedia Interface), USB(Universal Serial Bus), V by 1, 및 USB 3.0/3.1 중 어느 하나의 신호라인의 신호인 전기적 과부하 보호소자.The high speed signal is an electrical overload protection device which is a signal of any one of low voltage differential signaling (LVDS), high definition multimedia interface (HDMI), universal serial bus (USB), V by 1, and USB 3.0 / 3.1.
  12. 복수 개의 시트층;A plurality of sheet layers;
    제1시트층에 형성되는 접지전극;A ground electrode formed on the first sheet layer;
    상기 제1시트층 상에 적층된 제2시트층 상에 형성되어 제1외부전극에 연결되는 내부전극; 및 An inner electrode formed on the second sheet layer stacked on the first sheet layer and connected to the first outer electrode; And
    상기 제2시트층 상에 적층된 제3시트층 상에 형성되어 제2외부전극에 연결되는 저항체;를 포함하고,  And a resistor formed on the third sheet layer stacked on the second sheet layer and connected to the second external electrode.
    상기 접지전극과 상기 내부전극 및 상기 내부전극과 상기 저항체는 서로 대향하여 배치되는 전기적 과부하 보호소자. And the ground electrode, the inner electrode, the inner electrode, and the resistor are disposed to face each other.
PCT/KR2017/006799 2016-06-29 2017-06-28 Electrical overload protection device WO2018004242A1 (en)

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KR10-2016-0081860 2016-06-29
KR1020160081860A KR102063669B1 (en) 2016-06-29 2016-06-29 Protection device for high speed signal and electronic apparatus with the same
KR10-2017-0071609 2017-06-08
KR1020170071609A KR102044408B1 (en) 2017-06-08 2017-06-08 Electrical overstress protection device

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