WO2018000947A1 - 薄膜晶体管及其制作方法、阵列基板和显示面板 - Google Patents

薄膜晶体管及其制作方法、阵列基板和显示面板 Download PDF

Info

Publication number
WO2018000947A1
WO2018000947A1 PCT/CN2017/083708 CN2017083708W WO2018000947A1 WO 2018000947 A1 WO2018000947 A1 WO 2018000947A1 CN 2017083708 W CN2017083708 W CN 2017083708W WO 2018000947 A1 WO2018000947 A1 WO 2018000947A1
Authority
WO
WIPO (PCT)
Prior art keywords
active layer
layer
amorphous carbon
photoresist
forming
Prior art date
Application number
PCT/CN2017/083708
Other languages
English (en)
French (fr)
Inventor
王珂
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/564,055 priority Critical patent/US10211342B2/en
Publication of WO2018000947A1 publication Critical patent/WO2018000947A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Definitions

  • Embodiments of the present invention relate to a thin film transistor and a method of fabricating the same, an array substrate, and a display panel.
  • the thin film transistor mainly comprises an active layer 1, a gate 2, a source 3 and a drain 4 on a substrate substrate 0, and a gate insulating layer is disposed between the active layer 1 and the gate 2.
  • the layer 5, the source 3 and the drain 4 are disposed in the same layer, and an insulating layer 6 is further disposed between the source 3 and the drain 4 and the gate 2, and the source 3 and the drain 4 are electrically connected to the active layer 2, respectively.
  • a plasma such as H2, NH3, or He.
  • the low doped region P is disposed close to the channel region in the active layer 1 to prevent thermal electron degradation effects.
  • the active layer 1 is mainly treated with a gas having a high hydrogen content such as H2 or NH3, in which case the active layer may be made.
  • a gas having a high hydrogen content such as H2 or NH3
  • the active layer may be made.
  • 1 (especially an active layer formed of a semiconductor oxide) is electrified by the action of hydrogen, thereby destroying the characteristics of the active layer 1.
  • a method of fabricating a thin film transistor includes forming an active layer on a base substrate, the active layer including a channel region, forming an amorphous carbon layer on the non-channel region of the active layer, and on the amorphous carbon layer A source and a drain are formed, and the source and the drain are electrically connected to the active layer through the amorphous carbon layer, respectively.
  • forming an amorphous carbon layer on the non-channel region of the active layer includes: forming an amorphous carbon film over the active layer; and in an oxygen atmosphere, active by dry etching The amorphous carbon film on the channel region of the layer is etched away.
  • forming an active layer on a base substrate and forming an amorphous carbon layer on the non-channel region of the active layer includes: forming a semiconductor film on the base substrate, forming an amorphous film on the semiconductor film a carbon film on which a photoresist is formed; a photoresist is exposed and developed using a two-tone mask to form a photoresist completely removed region, a photoresist remaining region and a photoresist are completely retained a region, a photoresist completely reserved region corresponding to a region where an amorphous carbon layer is to be formed, a photoresist partially reserved region corresponding to a channel region of the active layer, and a photoresist completely removed region corresponding to other regions; using an etching process Removing the amorphous carbon film and the semiconductor film in the completely removed region of the photoresist to form a semiconductor active layer; performing an ashing process to remove the photoresist in the remaining portion of the photoresist and thinning
  • the method further includes annealing the active layer.
  • the temperature at which the active layer is annealed is 230 ° C to 400 ° C.
  • the method further includes forming a gate insulating layer on the channel region of the active layer.
  • a portion of the gate insulating layer that is in direct contact with the active layer is composed of silicon oxide.
  • the gate insulating layer is formed to be higher than the amorphous carbon layer.
  • the method further includes sequentially forming a gate electrode and an insulating layer on the base substrate on which the gate insulating layer is formed, wherein the insulating layer includes a via hole for electrically connecting the source and the drain to the amorphous carbon layer.
  • the material forming the active layer is an oxide semiconductor.
  • a thin film transistor includes: an active layer on a base substrate, the active layer including a channel region; an amorphous carbon layer on the non-channel region of the active layer; and the amorphous carbon layer a source and a drain electrically connected to the active layer through the amorphous carbon layer.
  • the thin film transistor further includes: a gate insulating layer over the channel region of the active layer, a gate over the gate insulating layer, and an insulating layer above the gate, A via hole is disposed in the insulating layer, and the source and the drain are electrically connected to the amorphous carbon layer above the non-communication area of the active layer through via holes in the insulating layer, respectively.
  • a portion of the gate insulating layer that is in contact with the active layer is composed of silicon dioxide.
  • the gate insulating layer is formed to be higher than the amorphous carbon layer.
  • the active layer is formed of an oxide semiconductor.
  • an array substrate including the thin film transistor as described above is provided.
  • a display panel comprising the array substrate as described above.
  • plasma treatment of the active layer can be avoided, thereby avoiding damage of the active layer by the plasma treatment.
  • FIG. 1 is a schematic structural view of a thin film transistor according to a technique
  • FIG. 2 is a schematic flow chart of a method for fabricating a thin film transistor according to an embodiment of the present invention
  • FIG. 3 is a more detailed schematic flowchart of a method for fabricating a thin film transistor according to an embodiment of the present invention
  • FIGS. 4(a)-4(g) are schematic structural views of a method of fabricating a thin film transistor according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, an array substrate, and a display panel, which can avoid plasma processing of an active layer, thereby avoiding plasma processing for active The destruction of the layer.
  • an embodiment of the present invention provides a method for fabricating a thin film transistor, the method comprising:
  • the amorphous carbon layer may be a laminate of graphene, or a layer formed of other carbon structures, and the amorphous carbon layer has electrical conductivity.
  • a method for fabricating a thin film transistor includes forming an active layer on a base substrate, the method further comprising: forming an amorphous carbon layer on a non-channel region of the active layer; A source and a drain are formed on the carbon layer, and the source and the drain are electrically connected to the active layer through the amorphous carbon layer, respectively.
  • the amorphous carbon layer has electrical conductivity and hydrogen absorption.
  • the formation of the amorphous carbon layer on the non-channel region of the active layer enables the hydrogen in the non-channel region of the active layer to be amorphous carbon layer due to hydrogen absorption of the amorphous carbon layer.
  • the amorphous carbon layer due to the conductive action of the amorphous carbon layer, the conductivity of the region of the thin film transistor adjacent to the channel region is increased, and the ohmic contact characteristics of the source and the drain and the semiconductor active layer are improved, thereby improving the thin film transistor. Characteristics. In addition, the formation of an amorphous carbon layer on the non-channel region of the active layer avoids plasma treatment of the active layer, thereby avoiding damage to the active layer by plasma treatment.
  • the thin film transistor fabricated by the above method for fabricating the thin film transistor provided by the embodiment of the present invention is a top gate thin film transistor.
  • an amorphous carbon layer is formed on the non-channel region of the active layer in step S202, including: forming an amorphous carbon film on the active layer; The etching process etches away the amorphous carbon film on the channel region of the active layer.
  • the step of forming an amorphous carbon film on the active layer may be deposited by a magnetron sputtering method or formed by other means, which is not specifically limited herein.
  • the amorphous carbon layer and the active layer can be used in the same patterning process. When formed, it can also be formed separately by two patterning processes, which is not limited herein.
  • the method includes: forming a semiconductor film on the base substrate, forming an amorphous carbon film on the semiconductor film, in the amorphous Forming a photoresist on the carbon film; exposing and developing the photoresist using a two-tone mask (for example, a halftone mask or a gray tone mask) to form a photoresist completely removed region, a photoresist portion remaining region, and The photoresist completely retains the region, the photoresist completely reserved region corresponds to the region where the amorphous carbon layer is to be formed, the photoresist partially reserved region corresponds to the channel region of the active layer, and the photoresist completely removed region corresponds to other regions.
  • a two-tone mask for example, a halftone mask or a gray tone mask
  • the amorphous carbon film and the semiconductor film in the completely removed region of the photoresist are removed by an etching process to form a semiconductor active layer; an ashing process is performed to remove the photoresist in the remaining portion of the photoresist and reduce the light
  • the photoresist is completely preserved in the region; the amorphous carbon film in the remaining portion of the photoresist is removed by an etching process to form an amorphous carbon layer; and the remaining photoresist is removed.
  • the method includes: forming a semiconductor film on the base substrate, etching the semiconductor film with a common mask to form an active layer; An amorphous carbon film is formed on the active layer, and an amorphous carbon film on the channel region of the active layer is etched away by a common mask to form an amorphous carbon layer.
  • the semiconductor film is a semiconductor oxide film.
  • a semiconductor film is formed on a base substrate by a deposition process.
  • the oxide content of the semiconductor oxide film is between 15% and 30%.
  • wet etching is used when etching a semiconductor oxide film.
  • an amorphous carbon film on a channel region of an active layer is etched by an etching process, including: in an oxygen atmosphere, by dry etching The etch etches away the amorphous carbon film on the channel region of the active layer.
  • the method for fabricating the above thin film transistor provided by the embodiment of the present invention, after the amorphous carbon film on the channel region of the active layer is etched by an etching process, and before the source and drain are formed, The method also includes annealing the active layer. Thereby the active layer is made more stable.
  • the active layer is formed of a semiconductor oxide, and the temperature at which the active layer formed of the semiconductor oxide is annealed is 230 ° C to 400 ° C. Thereby the active layer formed by the semiconductor oxide is made more stable.
  • the method further includes: in a channel region of the active layer A gate insulating layer is formed thereon.
  • the material forming the gate insulating layer is silicon dioxide.
  • the material for forming the gate insulating layer is not limited to silicon dioxide, and the gate insulating layer may be formed of silicon nitride and/or silicon oxynitride, which is not specifically limited herein.
  • the gate insulating layer may include a stacked structure of a silicon dioxide layer and a silicon nitride layer, or a stacked structure of a silicon dioxide layer and a silicon oxynitride layer, or a silicon dioxide layer, a silicon nitride layer, and oxynitride.
  • the active layer is formed of a semiconductor oxide
  • the semiconductor oxide is indium gallium zinc oxide and/or indium tin zinc oxide. Both indium gallium zinc oxide and/or indium tin zinc oxide are easily destroyed in the environment of hydrogen or other gases, thereby changing from a semiconductor to a conductor. Therefore, the semiconductor material which is easy to be destroyed in the hydrogen atmosphere is in the protection range of the embodiment of the present invention, and is not specifically limited herein.
  • the gate insulating layer is formed to be higher than the amorphous carbon layer to prevent the gate electrode subsequently formed on the gate insulating layer from coming into contact with the amorphous carbon layer.
  • the method further includes: forming the base substrate on which the gate insulating layer is formed A gate electrode and an insulating layer are sequentially formed thereon, wherein the insulating layer includes a via hole for electrically connecting the source and the drain to the amorphous carbon layer.
  • the gate electrode may be made of any one or more of molybdenum (Mo), aluminum (Al), and copper (Cu), and is not specifically limited herein.
  • a method for fabricating a thin film transistor according to an embodiment of the present invention includes:
  • a semiconductor film 21' and an amorphous carbon film 22' are formed on the base substrate 20 as shown in Fig. 4(a).
  • the thickness of the semiconductor film may be 40-50 nm.
  • the semiconductor film is a semiconductor oxide film, and a semiconductor oxide film can be formed in an environment having an oxygen content of 15% to 30%.
  • the amorphous carbon film may be deposited by magnetron sputtering, and the amorphous carbon film may have a thickness of 200 to 500 nm.
  • a photoresist 23 on the amorphous carbon film 22', and exposing and developing the photoresist 23 by using a two-tone mask to form a photoresist completely removed region, a photoresist portion remaining region and light.
  • the photoresist is completely reserved, the photoresist completely reserved region corresponds to the region where the amorphous carbon layer is to be formed, the photoresist partially reserved region corresponds to the channel region of the active layer, and the photoresist completely removed region corresponds to other regions;
  • the amorphous carbon film 22' and the semiconductor film 21' in the completely removed region of the photoresist are removed by an etching process to form the semiconductor active layer 21 as shown in Fig. 4(b).
  • wet etching may be used for etching the semiconductor film 21', and dry etching may be employed for etching the amorphous carbon film 22'.
  • a portion of the gate insulating layer that is in direct contact with the active layer is composed of a silicon dioxide layer.
  • the gate insulating layer 24 is formed to be higher than the amorphous carbon layer 22.
  • a gate electrode 25 is formed over the gate insulating layer 24, as shown in FIG. 4(e).
  • an insulating layer 26 is formed on the gate electrode 25, and a via hole 261 is formed in the insulating layer as shown in FIG. 4(f).
  • a source 27 and a drain 28 are formed over the insulating layer 26, and the source 27 and the drain 28 are connected to the amorphous carbon layer 22 through the via 261 as shown in FIG. 4(g).
  • the thin film transistor is formed by the above steps, in which the formation of each layer requires a patterning process.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, or may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the hydrogen in the active layer is absorbed by the hydrogen absorption of the amorphous carbon layer, thereby avoiding the destruction of the active layer by hydrogen.
  • an amorphous carbon layer is formed over the non-channel region of the active layer, so that free H in the active layer can be adsorbed, thereby reducing the H content in the active layer, further improving the stability of the thin film transistor.
  • the conductivity of the amorphous carbon layer due to the conductivity of the amorphous carbon layer, the conductivity of the region of the thin film transistor adjacent to the channel region is increased, and the ohmic contact characteristics of the source and the drain and the semiconductor active layer are improved, thereby enhancing the thin film crystal.
  • the characteristics of the tube the formation of an amorphous carbon layer on the non-channel region of the active layer avoids plasma treatment of the active layer, thereby avoiding damage to the active layer by plasma treatment.
  • the embodiment of the present invention further provides a thin film transistor.
  • the active layer 21 on the substrate substrate 20, the amorphous carbon layer 22 on the non-channel region of the active layer 21, and the non-channel are provided.
  • the active layer 21 is formed of a semiconductor oxide such as indium gallium zinc oxide and/or indium tin zinc oxide. Both indium gallium zinc oxide and/or indium tin zinc oxide are easily destroyed in the environment of hydrogen or other gases, thereby changing from a semiconductor to a conductor. Therefore, the semiconductor material which is easy to be destroyed in the hydrogen atmosphere is in the protection range of the embodiment of the present invention, and is not specifically limited herein.
  • a thin film transistor further includes: a gate insulating layer 24 over the channel region of the active layer 21, a gate 25 over the gate insulating layer 24, and a gate electrode.
  • the source 27 and the drain 28 are electrically connected to the amorphous carbon layer above the active layer non-communication area through via holes in the insulating layer, respectively.
  • the material forming the gate insulating layer is silicon dioxide.
  • the hydrogen in the active layer can be absorbed by the hydrogen absorption of the silicon dioxide, thereby further reducing the hydrogen content in the active layer and preventing the active layer from being destroyed by hydrogen. .
  • the material for forming the gate insulating layer is not limited to silicon dioxide, and the gate insulating layer may be formed of silicon nitride and/or silicon oxynitride, which is not specifically limited herein.
  • the gate insulating layer may include a stacked structure of a silicon dioxide layer and a silicon nitride layer, or a stacked structure of a silicon dioxide layer and a silicon oxynitride layer, or a silicon dioxide layer, a silicon nitride layer, and oxynitride.
  • the embodiment of the present invention further provides an array substrate, including any of the above thin film transistors provided by the embodiments of the present invention.
  • the embodiment of the invention further provides a display panel comprising the above array substrate provided by the embodiment of the invention.
  • the embodiments of the present invention provide a thin film transistor, a method for fabricating the same, an array substrate, and a display panel, the method for fabricating the thin film transistor includes forming an active layer on a substrate. The method further includes: forming an amorphous carbon layer on the non-channel region of the active layer; forming a source and a drain on the amorphous carbon layer, the source and the drain respectively passing through the non- The crystalline carbon layer is electrically connected to the active layer.
  • the amorphous carbon layer has electrical conductivity and hydrogen absorption.
  • the formation of the amorphous carbon layer on the non-channel region of the active layer enables the hydrogen in the non-channel region of the active layer to be amorphous carbon layer due to hydrogen absorption of the amorphous carbon layer. Absorption, thereby avoiding the destruction of the characteristics of the semiconductor active layer.
  • the conductivity of the region of the thin film transistor adjacent to the channel region is increased, and the ohmic contact characteristics of the source and the drain and the semiconductor active layer are improved, thereby improving the thin film transistor. Characteristics.
  • the formation of an amorphous carbon layer on the non-channel region of the active layer avoids plasma treatment of the active layer, thereby avoiding damage to the active layer by plasma treatment.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及其制作方法、阵列基板和显示面板。该薄膜晶体管的制作方法包括：在衬底基板（20）上形成有源层（21），该有源层（21）包括沟道区；在所述有源层（21）的非沟道区域上形成非晶碳层（22）；并且在所述非晶碳层（22）上形成源极（27）和漏极（28），该源极（27）和漏极（28）分别通过所述非晶碳层（22）与所述有源层（21）电性连接。可以避免对有源层进行等离子处理，从而避免了等离子体处理对有源层的破坏。

Description

薄膜晶体管及其制作方法、阵列基板和显示面板 技术领域
本发明的实施例涉及一种薄膜晶体管及其制作方法、阵列基板和显示面板。
背景技术
目前，液晶显示器(LCD，Liquid Crystal Display)、电致发光(EL，electroluminescence)显示器以及电子纸等显示装置已为人所熟知。这些显示装置具有控制像素开关的薄膜晶体管(TFT，Thin Film Transistor)。如图1所示，该薄膜晶体管主要包括位于衬底基板0上的有源层1、栅极2、源极3和漏极4，在有源层1与栅极2之间设置有栅绝缘层5，源极3和漏极4同层设置，且源极3和漏极4与栅极2之间还设置有绝缘层6，源极3和漏极4分别与有源层2电性相连。针对图1所示的薄膜晶体管，为了形成低掺杂区域P，一般需要采用H2、NH3、He等等离子体对有源层1进行处理。该低掺杂区域P设置为靠近有源层1中的沟道区，以防止热电子退化效应。
如上所述，在形成低掺杂区域P的等离子体处理的过程中，主要采用H2、NH3等含氢量较高的气体对有源层1进行处理，在此情形下，可能使得有源层1(尤其是半导体氧化物形成的有源层)由于氢的作用而导体化，从而破坏了有源层1的特性。
发明内容
根据本发明的实施例，提供一种薄膜晶体管的制作方法。该方法包括：在衬底基板上形成有源层，该有源层包括沟道区；在所述有源层的非沟道区域上形成非晶碳层；并且在所述非晶碳层上形成源极和漏极，该源极和漏极分别通过所述非晶碳层与所述有源层电性连接。
例如，在所述有源层的非沟道区域上形成非晶碳层，包括：在所述有源层上方形成非晶碳膜；并且在氧气的氛围中，通过干法刻蚀将有源层的沟道区域上的非晶碳膜刻蚀掉。
例如，在衬底基板上形成有源层且在所述有源层的非沟道区域上形成非晶碳层，包括：在衬底基板上形成半导体膜，在所述半导体膜上形成非晶碳膜，在所述非晶碳膜上形成光刻胶；采用双色调掩模板对光刻胶进行曝光和显影以形成光刻胶完全去除区域，光刻胶部分保留区域和光刻胶完全保留区域，光刻胶完全保留区域对应于要形成非晶碳层的区域，光刻胶部分保留区域对应于有源层的沟道区，光刻胶完全去除区域对应于其他区域；采用刻蚀工艺将光刻胶完全去除区域的非晶碳膜和半导体膜去除，以形成半导体有源层；进行灰化工艺，以去除光刻胶部分保留区域的光刻胶并减薄光刻胶完全保留区域的光刻胶；采用刻蚀工艺将光刻胶部分保留区域的非晶碳膜去除，以形成非晶碳层；以及去除剩余的光刻胶。
例如，在形成非晶碳层之后且在形成源极和漏极之前，该方法还包括：对所述有源层进行退火处理。
例如，对所述有源层进行退火处理的温度为230℃-400℃。
例如，在对所述有源层进行退火处理之后且在形成源极和漏极之前，该方法还包括：在所述有源层的沟道区域上形成栅极绝缘层。
例如，所述栅极绝缘层中与所述有源层直接接触的部分由二氧化硅构成。
例如，在所述衬底基板上，所述栅极绝缘层形成为高于所述非晶碳层。
例如，在形成所述栅极绝缘层之后且在形成所述源极和漏极之前，该方法还包括：在形成有所述栅极绝缘层的衬底基板上依次形成栅极和绝缘层，其中所述绝缘层中包括用于使所述源极和漏极与所述非晶碳层电性连接的过孔。
例如，形成所述有源层的材料为氧化物半导体。
根据本发明的实施例，提供一种薄膜晶体管。该薄膜晶体管包括：位于衬底基板上的有源层，该有源层包括沟道区；位于所述有源层的非沟道区域上的非晶碳层；以及位于所述非晶碳层上且通过所述非晶碳层与所述有源层电性连接的源极和漏极。
例如，该薄膜晶体管还包括：位于所述有源层的沟道区域上方的栅极绝缘层、位于所述栅极绝缘层上方的栅极、以及位于所述栅极上方的绝缘层，所述绝缘层中设置有过孔，所述源极和漏极分别通过所述绝缘层中的过孔与有源层非沟通区域上方的非晶碳层电性连接。
例如，所述栅极绝缘层的与所述有源层接触的部分由二氧化硅构成。
例如，在所述衬底基板上，所述栅极绝缘层形成为高于所述非晶碳层。
例如，所述有源层由氧化物半导体形成。
根据本发明的实施例，提供一种阵列基板，该阵列基板包括如上所述的薄膜晶体管。
根据本发明的实施例，提供一种显示面板，该显示面板包括如上所述的阵列基板。
根据本发明的实施例，可以避免对有源层进行等离子处理，从而避免了等离子体处理对有源层的破坏。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述的附图仅仅涉及本发明的一些实施例，而非对本发明实施例的限制。
图1为根据一种技术的薄膜晶体管的结构示意图；
图2为本发明实施例提供的薄膜晶体管的制作方法的流程示意图；
图3为本发明实施例提供的薄膜晶体管的制作方法的更具体的流程示意图；
图4(a)-图4(g)为本发明实施例提供的薄膜晶体管的制作方法的结构示意图；
图5为本发明实施例提供的薄膜晶体管的结构示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的实施例提供了一种薄膜晶体管及其制作方法、阵列基板和显示面板，可以避免对有源层进行等离子处理，从而避免了等离子体处理对有源 层的破坏。
下面结合附图，对本发明实施例提供的薄膜晶体管及其制作方法、阵列基板和显示面板进行详细地说明。
需要说明的是，附图中各膜层的厚度和区域的大小形状不反映薄膜晶体管部件的真实比例，目的只是示意说明本发明实施例的内容。
参见图2，本发明实施例提供了一种薄膜晶体管的制作方法，该方法包括：
S201、在衬底基板上形成有源层，该有源层包括沟道区；
S202、在有源层的非沟道区域上形成非晶碳层；
例如，非晶碳层可以为石墨烯的叠层，或者其他碳结构形成的层，且非晶碳层具有导电性。
S203、在非晶碳层上形成源极和漏极，源极和漏极分别通过非晶碳层与有源层电性连接。
本发明实施例提供的薄膜晶体管的制作方法包括在衬底基板上形成有源层，该方法还包括：在所述有源层的非沟道区域上形成非晶碳层；在所述非晶碳层上形成源极和漏极，所述源极和漏极分别通过所述非晶碳层与所述有源层电性连接。非晶碳层具有导电性和吸氢作用。在本发明实施例中，由于非晶碳层的吸氢作用，在有源层的非沟道区域上形成非晶碳层能够使得有源层的非沟道区域中的氢被非晶碳层吸收，从而避免了半导体有源层的特性被破坏。另外，由于非晶碳层的导电作用，增加了薄膜晶体管的与沟道区紧邻的区域的导电性，并改善了源极和漏极与半导体有源层的欧姆接触特性，从而提升了薄膜晶体管的特性。另外，在有源层的非沟道区域上形成非晶碳层，避免了对有源层进行等离子处理，从而避免了等离子体处理对有源层的破坏。
例如，采用本发明实施例提供的上述薄膜晶体管的制作方法制作的薄膜晶体管为顶栅型薄膜晶体管。
例如，本发明实施例提供的上述薄膜晶体管的制作方法中，步骤S202中在有源层的非沟道区域上形成非晶碳层，包括：在有源层上形成非晶碳膜；采用刻蚀工艺将有源层的沟道区域上的非晶碳膜刻蚀掉。例如，在有源层上形成非晶碳膜的步骤可以采用磁控溅射方法进行沉积，或者采用其他方式形成，在此不做具体限定。例如，非晶碳层与有源层可以采用一次构图工艺同 时形成，也可以采用两次构图工艺分开形成，在此不作限定。
例如，采用一次构图工艺同时形成有源层和非晶碳层的情形下，该方法包括：在衬底基板上形成半导体膜，在所述半导体膜上形成非晶碳膜，在所述非晶碳膜上形成光刻胶；采用双色调掩模板(例如，半色调掩模板或灰色调掩模板)对光刻胶进行曝光和显影以形成光刻胶完全去除区域，光刻胶部分保留区域和光刻胶完全保留区域，光刻胶完全保留区域对应于要形成非晶碳层的区域，光刻胶部分保留区域对应于有源层的沟道区，光刻胶完全去除区域对应于其他区域；采用刻蚀工艺将光刻胶完全去除区域的非晶碳膜和半导体膜去除，以形成半导体有源层；进行灰化工艺，以去除光刻胶部分保留区域的光刻胶并减薄光刻胶完全保留区域的光刻胶；采用刻蚀工艺将光刻胶部分保留区域的非晶碳膜去除，以形成非晶碳层；去除剩余的光刻胶。
例如，采用两次构图工艺形成有源层和非晶碳层的情形下，该方法包括：在衬底基板上形成半导体膜，采用普通掩模板对半导体膜进行刻蚀，形成有源层；在有源层上形成非晶碳膜，采用普通掩模板将有源层的沟道区域上的非晶碳膜刻蚀掉，从而形成非晶碳层。
例如，半导体膜为半导体氧化物膜。例如，通过沉积工艺，在衬底基板上形成半导体膜。例如，沉积半导体氧化物膜时氧气含量在15％-30％之间。例如，对半导体氧化物膜进行刻蚀时采用湿法刻蚀。
例如，本发明实施例提供的上述薄膜晶体管的制作方法中，采用刻蚀工艺将有源层的沟道区域上的非晶碳膜刻蚀掉，包括：在氧气的氛围中，通过干法刻蚀将有源层的沟道区域上的非晶碳膜刻蚀掉。
例如，本发明实施例提供的上述薄膜晶体管的制作方法中，采用刻蚀工艺将有源层的沟道区域上的非晶碳膜刻蚀掉之后，且在形成源极和漏极之前，该方法还包括：对有源层进行退火处理。从而使得有源层更加稳定化。
例如，本发明实施例提供的上述薄膜晶体管的制作方法中，有源层由半导体氧化物形成，对半导体氧化物形成的有源层进行退火处理的温度为230℃-400℃。从而使得半导体氧化物形成的有源层更加稳定化。
例如，本发明实施例提供的上述薄膜晶体管的制作方法中，对有源层进行退火处理之后，且在形成所述源极和漏极之前，该方法还包括：在有源层的沟道区域上形成栅极绝缘层。例如，形成栅极绝缘层的材料为二氧化硅。 采用二样化硅形成栅极绝缘层时，可以通过二氧化硅的吸氢作用，将有源层中的氢气吸收，降低了有源层中的氢含量，避免了有源层被氢破坏。
需要说明的是，本发明实施例中，形成栅极绝缘层的材料不限于二氧化硅，栅极绝缘层还可以由氮化硅和/或氮氧化硅形成，在此不做具体限定。
例如，栅极绝缘层可以包括二氧化硅层和氮化硅层的叠层结构，或者二氧化硅层和氮氧化硅层的叠层结构，或者二氧化硅层、氮化硅层和氮氧化硅层的叠层结构；在此情形下，二氧化硅层与有源层直接接触。
例如，本发明实施例提供的上述薄膜晶体管的制作方法中，有源层由半导体氧化物形成，半导体氧化物为铟镓锌氧化物和/或铟锡锌氧化物。铟镓锌氧化物和/或铟锡锌氧化物均容易在氢气或者其他气体的环境中被破坏，从而从半导体变成导体。因此容易在氢气的环境中被破坏半导体特性的半导体材料均属于本发明实施例的保护范围，在此不做具体限定。
例如，栅极绝缘层形成为高于非晶碳层，以防止后续形成在栅极绝缘层上的栅极与非晶碳层接触。
例如，本发明实施例提供的上述薄膜晶体管的制作方法中，在形成栅极绝缘层之后，且在形成源极和漏极之前，该方法还包括：在形成有栅极绝缘层的衬底基板上依次形成栅极和绝缘层，其中，绝缘层中包括用于使源极和漏极与非晶碳层电性连接的过孔。例如，栅极可以采用钼(Mo)、铝(Al)和铜(Cu)中的任意一种或者多种材料制作，在此不做具体限定。
下面，结合图3和图4(a)至图4(g)，对本发明实施例提供的薄膜晶体管的制作方法进行进一步详细的说明。
参见图3，本发明实施例提供的薄膜晶体管的制作方法包括：
S301、在衬底基板20上形成半导体膜21’和非晶碳膜22’，如图4(a)所示。
例如，半导体膜的厚度可以为40-50nm。例如，半导体膜为半导体氧化物膜，可以在氧气含量为15％-30％的环境中制作半导体氧化物膜。
例如，非晶碳膜可以采用磁控溅射的方式进行沉积，且非晶碳膜的厚度可以为200-500nm。
S302、在非晶碳膜22’上涂覆光刻胶23，并采用双色调掩模板对光刻胶23进行曝光和显影，以形成光刻胶完全去除区域，光刻胶部分保留区域和光 刻胶完全保留区域，光刻胶完全保留区域对应于要形成非晶碳层的区域，光刻胶部分保留区域对应于有源层的沟道区，光刻胶完全去除区域对应于其他区域；采用刻蚀工艺将光刻胶完全去除区域的非晶碳膜22’和半导体膜21’去除，以形成半导体有源层21，如图4(b)所示。
例如，对半导体膜21’进行刻蚀时可以使用湿法刻蚀，对非晶碳膜22’进行刻蚀可以采用干法刻蚀。
S303、进行灰化工艺，以去除光刻胶部分保留区域的光刻胶23并减薄光刻胶完全保留区域的光刻胶23；采用刻蚀工艺将光刻胶部分保留区域的非晶碳膜22’去除，以形成非晶碳层22；去除剩余的光刻胶23，如图4(c)所示。
S304、对有源层21进行退火处理。
S305、在有源层的沟道区域上形成栅极绝缘层24，如图4(d)所示。
例如，栅极绝缘层中与有源层直接接触的部分由二氧化硅层构成。
例如，在衬底基板20上，栅极绝缘层24形成为高于非晶碳层22。
S306、在栅极绝缘层24的上方形成栅极25，如图4(e)所示。
S307、在栅极25上形成绝缘层26，绝缘层中形成有过孔261，如图4(f)所示。
S308、在绝缘层26的上方形成源极27和漏极28，源极27和漏极28通过过孔261连接到非晶碳层22，如图4(g)所示。
通过上述步骤形成薄膜晶体管，其中形成每一层的结构均需要采用构图工艺。构图工艺可以只包括光刻工艺，或者可以包括光刻工艺以及刻蚀步骤，或者还可以包括打印、喷墨等其他用于形成预定图案的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图案的工艺。
在本发明实施例提供的薄膜晶体管的制作方法中，利用非晶碳层的吸氢作用，将有源层中的氢气进行吸收，从而避免了氢气对有源层的破坏。例如，将非晶碳层制作在有源层的非沟道区域上方，因此可以吸附有源层中游离的H，从而降低有源层中的H含量，进一步提升了薄膜晶体管的稳定性。另外，由于非晶碳层的导电性，增加了薄膜晶体管的与沟道区紧邻的区域的导电性，并改善了源极和漏极与半导体有源层的欧姆接触特性，从而提升了薄膜晶体 管的特性。另外，在有源层的非沟道区域上形成非晶碳层，避免了对有源层进行等离子处理，从而避免了等离子体处理对有源层的破坏。
本发明实施例还提供了一种薄膜晶体管，参见图5，包括位于衬底基板20上的有源层21，位于有源层21的非沟道区域上的非晶碳层22，以及位于非晶碳层22的上方且通过非晶碳层22与有源层电性连接的源极27和漏极28。
例如，有源层21由半导体氧化物形成，半导体氧化物例如为铟镓锌氧化物和/或铟锡锌氧化物。铟镓锌氧化物和/或铟锡锌氧化物均容易在氢气或者其他气体的环境中被破坏，从而从半导体变成导体。因此容易在氢气的环境中被破坏半导体特性的半导体材料均属于本发明实施例的保护范围，在此不做具体限定。
例如，本参见图5，根据本发明实施例的薄膜晶体管还包括：位于有源层21的沟道区域上方的栅极绝缘层24、位于栅极绝缘层24上方的栅极25、位于栅极25上方的绝缘层26、以及位于绝缘层26中的过孔。源极27和漏极28分别通过绝缘层中的过孔与有源层非沟通区域上方的非晶碳层电性连接。
例如，形成栅极绝缘层的材料为二氧化硅。采用二样化硅形成栅极绝缘层时，可以通过二氧化硅的吸氢作用，将有源层中的氢气吸收，进一步降低了有源层中的氢含量，避免了有源层被氢破坏。
需要说明的是，本发明实施例中，形成栅极绝缘层的材料不限于二氧化硅，栅极绝缘层还可以由氮化硅和/或氮氧化硅形成，在此不做具体限定。
例如，栅极绝缘层可以包括二氧化硅层和氮化硅层的叠层结构，或者二氧化硅层和氮氧化硅层的叠层结构，或者二氧化硅层、氮化硅层和氮氧化硅层的叠层结构；在此情形下，二氧化硅层与有源层直接接触。
本发明实施例还提供了一种阵列基板，包括本发明实施例提供的上述任一种薄膜晶体管。
本发明实施例还提供了一种显示面板，包括本发明实施例提供的上述阵列基板。
综上所述，本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板和显示面板，所述薄膜晶体管的制作方法包括在衬底基板上形成有源层， 该方法还包括：在所述有源层的非沟道区域上形成非晶碳层；在所述非晶碳层上形成源极和漏极，所述源极和漏极分别通过所述非晶碳层与所述有源层电性连接。非晶碳层具有导电性和吸氢作用。在本发明实施例中，由于非晶碳层的吸氢作用，在有源层的非沟道区域上形成非晶碳层能够使得有源层的非沟道区域中的氢被非晶碳层吸收，从而避免了半导体有源层的特性被破坏。另外，由于非晶碳层的导电作用，增加了薄膜晶体管的与沟道区紧邻的区域的导电性，并改善了源极和漏极与半导体有源层的欧姆接触特性，从而提升了薄膜晶体管的特性。另外，在有源层的非沟道区域上形成非晶碳层，避免了对有源层进行等离子处理，从而避免了等离子体处理对有源层的破坏。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2016年6月28日递交的第201610495890.7号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种薄膜晶体管的制作方法，包括：
    在衬底基板上形成有源层，该有源层包括沟道区；
    在所述有源层的非沟道区域上形成非晶碳层；并且
    在所述非晶碳层上形成源极和漏极，该源极和漏极分别通过所述非晶碳层与所述有源层电性连接。
  2. 根据权利要求1所述的方法，其中，在所述有源层的非沟道区域上形成非晶碳层，包括：
    在所述有源层上方形成非晶碳膜；并且
    在氧气的氛围中，通过干法刻蚀将有源层的沟道区域上的非晶碳膜刻蚀掉。
  3. 根据权利要求1所述的方法，其中，在衬底基板上形成有源层且在所述有源层的非沟道区域上形成非晶碳层，包括：
    在衬底基板上形成半导体膜，在所述半导体膜上形成非晶碳膜，在所述非晶碳膜上形成光刻胶；
    采用双色调掩模板对光刻胶进行曝光和显影以形成光刻胶完全去除区域，光刻胶部分保留区域和光刻胶完全保留区域，光刻胶完全保留区域对应于要形成非晶碳层的区域，光刻胶部分保留区域对应于有源层的沟道区，光刻胶完全去除区域对应于其他区域；
    采用刻蚀工艺将光刻胶完全去除区域的非晶碳膜和半导体膜去除，以形成半导体有源层；
    进行灰化工艺，以去除光刻胶部分保留区域的光刻胶并减薄光刻胶完全保留区域的光刻胶；
    采用刻蚀工艺将光刻胶部分保留区域的非晶碳膜去除，以形成非晶碳层；以及
    去除剩余的光刻胶。
  4. 根据权利要求1所述的方法，其中，在形成非晶碳层之后且在形成源极和漏极之前，该方法还包括：对所述有源层进行退火处理。
  5. 根据权利要求4所述的方法，其中，对所述有源层进行退火处理的温 度为230℃-400℃。
  6. 根据权利要求4所述的方法，其中，在对所述有源层进行退火处理之后且在形成源极和漏极之前，该方法还包括：
    在所述有源层的沟道区域上形成栅极绝缘层。
  7. 根据权利要求6所述的方法，其中，所述栅极绝缘层中与所述有源层直接接触的部分由二氧化硅构成。
  8. 根据权利要求6所述的方法，其中，在所述衬底基板上，所述栅极绝缘层形成为高于所述非晶碳层。
  9. 根据权利要求6所述的方法，其中，在形成所述栅极绝缘层之后且在形成所述源极和漏极之前，该方法还包括：
    在形成有所述栅极绝缘层的衬底基板上依次形成栅极和绝缘层，其中所述绝缘层中包括用于使所述源极和漏极与所述非晶碳层电性连接的过孔。
  10. 根据权利要求1-9任一权项所述的方法，其中，形成所述有源层的材料为氧化物半导体。
  11. 一种薄膜晶体管，包括：
    位于衬底基板上的有源层，该有源层包括沟道区；
    位于所述有源层的非沟道区域上的非晶碳层；以及
    位于所述非晶碳层上且通过所述非晶碳层与所述有源层电性连接的源极和漏极。
  12. 根据权利要求11所述的薄膜晶体管，还包括：位于所述有源层的沟道区域上方的栅极绝缘层、位于所述栅极绝缘层上方的栅极、以及位于所述栅极上方的绝缘层，所述绝缘层中设置有过孔，所述源极和漏极分别通过所述绝缘层中的过孔与有源层非沟通区域上方的非晶碳层电性连接。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述栅极绝缘层的与所述有源层接触的部分由二氧化硅构成。
  14. 根据权利要求12所述的薄膜晶体管，其中，在所述衬底基板上，所述栅极绝缘层形成为高于所述非晶碳层。
  15. 根据权利要求11-14任一项所述的薄膜晶体管，其中，所述有源层由氧化物半导体形成。
  16. 一种阵列基板，包括权利要求11-15任一权项所述的薄膜晶体管。
  17. 一种显示面板，包括权利要求16所述的阵列基板。
PCT/CN2017/083708 2016-06-28 2017-05-10 薄膜晶体管及其制作方法、阵列基板和显示面板 WO2018000947A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/564,055 US10211342B2 (en) 2016-06-28 2017-05-10 Thin film transistor and fabrication method thereof, array substrate, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610495890.7 2016-06-28
CN201610495890.7A CN105977164A (zh) 2016-06-28 2016-06-28 一种薄膜晶体管及其制作方法、阵列基板和显示面板

Publications (1)

Publication Number Publication Date
WO2018000947A1 true WO2018000947A1 (zh) 2018-01-04

Family

ID=57019467

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/083708 WO2018000947A1 (zh) 2016-06-28 2017-05-10 薄膜晶体管及其制作方法、阵列基板和显示面板

Country Status (3)

Country Link
US (1) US10211342B2 (zh)
CN (1) CN105977164A (zh)
WO (1) WO2018000947A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105977164A (zh) 2016-06-28 2016-09-28 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示面板
KR102651544B1 (ko) * 2016-11-21 2024-03-28 삼성전자주식회사 광대역 다기능 광학소자와 그 제조 및 동작방법
CN107170835B (zh) * 2017-07-07 2020-08-21 合肥鑫晟光电科技有限公司 薄膜晶体管及其制备方法和阵列基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199728A (ja) * 1996-01-18 1997-07-31 Toshiba Corp 薄膜トランジスタおよび液晶表示装置
JPH09252141A (ja) * 1996-01-11 1997-09-22 Toshiba Corp 液晶表示素子及びその製造方法並びにスパッタリング装置
CN105575819A (zh) * 2016-02-26 2016-05-11 华南理工大学 一种顶栅结构金属氧化物薄膜晶体管及其制备方法
CN105977164A (zh) * 2016-06-28 2016-09-28 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示面板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101235135B1 (ko) * 2005-12-19 2013-02-20 삼성디스플레이 주식회사 금속 배선, 이의 제조 방법, 이를 구비한 표시 기판 및표시 기판의 제조 방법
JP5213458B2 (ja) * 2008-01-08 2013-06-19 キヤノン株式会社 アモルファス酸化物及び電界効果型トランジスタ
JP2011008882A (ja) 2009-06-26 2011-01-13 Toshiba Storage Device Corp 磁気ヘッドの実効ライトコア幅および実効イレーズコア幅の測定方法
JP5437776B2 (ja) * 2009-11-18 2014-03-12 三井金属鉱業株式会社 酸化物半導体を用いた薄膜トランジスタおよびその製造方法
KR101048987B1 (ko) * 2009-12-10 2011-07-12 삼성모바일디스플레이주식회사 평판 표시 장치 및 그의 제조 방법
KR102199696B1 (ko) 2013-11-25 2021-01-08 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
JP6399801B2 (ja) * 2014-05-13 2018-10-03 株式会社ジャパンディスプレイ 有機エレクトロルミネッセンス表示装置
CN104900533B (zh) * 2015-04-13 2018-12-18 京东方科技集团股份有限公司 薄膜晶体管、阵列基板、制备方法、显示面板和显示装置
CN104779302A (zh) * 2015-05-11 2015-07-15 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置
CN105097548A (zh) * 2015-06-23 2015-11-25 京东方科技集团股份有限公司 氧化物薄膜晶体管、阵列基板及各自制备方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09252141A (ja) * 1996-01-11 1997-09-22 Toshiba Corp 液晶表示素子及びその製造方法並びにスパッタリング装置
JPH09199728A (ja) * 1996-01-18 1997-07-31 Toshiba Corp 薄膜トランジスタおよび液晶表示装置
CN105575819A (zh) * 2016-02-26 2016-05-11 华南理工大学 一种顶栅结构金属氧化物薄膜晶体管及其制备方法
CN105977164A (zh) * 2016-06-28 2016-09-28 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示面板

Also Published As

Publication number Publication date
US10211342B2 (en) 2019-02-19
CN105977164A (zh) 2016-09-28
US20180204949A1 (en) 2018-07-19

Similar Documents

Publication Publication Date Title
US10811434B2 (en) Array substrate and manufacturing method thereof, display panel and display device
US9455324B2 (en) Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device
WO2015100935A1 (zh) 阵列基板及其制造方法、以及显示装置
US10008516B2 (en) LTPS TFT array substrate, its manufacturing method, and display device
US9117915B2 (en) Thin film transistor, pixel structure and method for fabricating the same
CN108550625B (zh) 一种薄膜晶体管及其制作方法
US20160172389A1 (en) Thin film transistor and manufacturing method thereof
US11961848B2 (en) Display substrate and manufacturing method therefor, and display device
US9842915B2 (en) Array substrate for liquid crystal display device and method of manufacturing the same
US7674658B2 (en) Semiconductor device and manufacturing method thereof
US20170170330A1 (en) Thin film transistors (tfts), manufacturing methods of tfts, and display devices
WO2015100894A1 (zh) 显示装置、阵列基板及其制造方法
KR102318054B1 (ko) Tft 기판 및 이의 제조 방법
WO2016070581A1 (zh) 阵列基板制备方法
WO2020154876A1 (zh) 薄膜晶体管及其制造方法、阵列基板和显示装置
US20220020867A1 (en) Manufacturing method of display substrate, display substrate and display device
WO2020232964A1 (zh) 一种薄膜晶体管基板的制备方法
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
WO2017008347A1 (zh) 阵列基板、阵列基板的制造方法及显示装置
WO2018000947A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示面板
WO2015192397A1 (zh) 薄膜晶体管基板的制造方法
KR102224457B1 (ko) 표시장치와 그 제조 방법
WO2020232946A1 (zh) 改善金属氧化物tft特性的结构与其制作方法
WO2021248609A1 (zh) 一种阵列基板及其制备方法以及显示面板
WO2015096239A1 (zh) 一种薄膜电晶体场效应管及其制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15564055

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17818944

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 21.05.2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17818944

Country of ref document: EP

Kind code of ref document: A1