WO2017212693A1 - 固体撮像素子、撮像装置、および、固体撮像素子の制御方法 - Google Patents
固体撮像素子、撮像装置、および、固体撮像素子の制御方法 Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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Definitions
- the present technology relates to a solid-state imaging device, an imaging apparatus, and a control method for the solid-state imaging device.
- the present invention relates to a solid-state imaging device, an imaging apparatus, and a solid-state imaging device control method that share one ADC (Analog-to-Digital-Converter) in a plurality of columns.
- ADC Analog-to-Digital-Converter
- the present technology has been created in view of such a situation, and an object thereof is to reduce the number of wirings in a pixel array in a solid-state imaging device sharing one ADC in a plurality of columns.
- the present technology has been made to solve the above-described problems, and the first side surface thereof is connected to any of a plurality of power supply lines wired in a direction perpendicular to a predetermined direction.
- a plurality of pixel circuits a signal processing unit that processes pixel signals output via signal lines commonly connected to a predetermined number of pixel circuits adjacent in the predetermined direction among the plurality of pixel circuits;
- a solid comprising a power supply path opening / closing section that opens and closes a path between each of the plurality of power supply lines and the power supply, and a signal path opening / closing section that opens and closes a path between each of the plurality of power supply lines and the signal line.
- An imaging device and a control method thereof Thereby, the path between each of the plurality of power supply lines and the power supply and the path between each of the plurality of power supply lines and the signal line are individually opened and closed.
- scanning that performs processing for driving the pixel circuits arranged in the predetermined direction to output the pixel signals and processing for sequentially selecting any one of the predetermined number of pixel circuits.
- a circuit may be further provided. As a result, the pixels arranged in a predetermined direction are driven, and one of a predetermined number of pixel circuits is sequentially selected.
- the power supply path opening / closing unit controls the power supply line connected to the selected pixel circuit among the plurality of power supply lines and the power supply to be closed
- the signal path opening / closing unit may control the path between the power line connected to the selected pixel circuit and the signal line among the plurality of power lines to an open state.
- the plurality of power supply lines, the plurality of pixel circuits, and the signal lines are disposed on a predetermined semiconductor substrate, and the signal processing unit is stacked on the predetermined semiconductor substrate. It may be arranged on a semiconductor substrate. As a result, the pixel signals are processed in the stacked semiconductor substrates.
- the power supply path opening / closing part and the signal path opening / closing part may be arranged on the stacked semiconductor substrates.
- the path between each of the plurality of power supply lines and the power supply and the path between each of the plurality of power supply lines and the signal line are individually opened and closed. .
- the power supply path opening / closing part and the signal path opening / closing part may be arranged on the predetermined semiconductor substrate.
- the path between each of the plurality of power supply lines and the power supply and the path between each of the plurality of power supply lines and the signal line are individually opened and closed. .
- a certain number of adjacent pixel circuits among the plurality of pixel circuits share a floating diffusion layer, and the floating diffusion layer accumulates the photoelectrically converted charge and stores the charge.
- a voltage corresponding to the amount is generated, and the pixel signal may be a signal corresponding to the voltage.
- the pixel signal is generated by the pixel circuit sharing the floating diffusion layer.
- the plurality of pixel circuits include a photoelectric conversion element that converts light into electric charge, a floating diffusion layer that accumulates the electric charge and generates a voltage corresponding to the amount of the electric charge, A reset transistor that initializes the amount of the electric charge accumulated in the floating diffusion layer; and an amplification transistor that outputs a signal corresponding to the voltage as the pixel signal.
- the amplification transistor is connected to the power source, and The reset transistor may be connected to a reset power supply different from the power supply. As a result, a pixel signal is generated by a pixel circuit in which a reset power supply is separately provided.
- the signal processing unit may perform analog-digital conversion on the pixel signal. As a result, the image signal is converted into a digital signal.
- the second aspect of the present technology provides a plurality of pixel circuits each connected to any one of a plurality of power supply lines wired in a direction perpendicular to a predetermined direction, and the predetermined one of the plurality of pixel circuits.
- a signal processing unit that processes a pixel signal output via a signal line commonly connected to a predetermined number of pixel circuits adjacent to each other in a direction, and opens and closes a path between each of the plurality of power supply lines and the power supply
- a power supply path opening / closing section that performs a signal path opening / closing section that opens and closes a path between each of the plurality of power supply lines and the signal line, and a recording section that records image data generated from the processed pixel signal; It is an imaging device which comprises. As a result, the path between each of the plurality of power supply lines and the power supply and the path between each of the plurality of power supply lines and the signal line are individually opened and closed, and the image data is recorded.
- the present technology it is possible to obtain an excellent effect that the number of wirings in the pixel array can be reduced in a solid-state imaging device sharing one ADC in a plurality of columns.
- the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
- FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit and a column selection circuit according to the first embodiment of the present technology.
- FIG. 3 is a circuit diagram illustrating a configuration example of a pixel circuit and a column selection circuit to which wirings are added according to the first embodiment of the present technology.
- FIG. 3 is a circuit diagram illustrating a configuration example of a pixel circuit in which a reset power supply is provided separately from an amplifier power supply according to the first embodiment of the present technology.
- FIG. It is a circuit diagram showing an example of 1 composition of a column selection circuit in a 1st embodiment of this art.
- 3 is a circuit diagram illustrating a configuration example of a pixel circuit and a column selection circuit in which a layout is changed according to the first embodiment of the present technology.
- FIG. 3 is a circuit diagram illustrating a configuration example of a pixel circuit and a column selection circuit to which wirings are added according to the first embodiment of the present technology.
- FIG. 3 is a timing chart illustrating an example of the operation of the scanning circuit according to the first embodiment of the present technology.
- FIG. 1 is a block diagram illustrating a configuration example of the imaging apparatus 100 according to the first embodiment.
- the imaging apparatus 100 is an apparatus that captures image data, and includes an imaging lens 110, a solid-state imaging device 200, an image processing unit 120, an imaging control unit 130, and a recording unit 140.
- an action cam, an in-vehicle camera, or the like is assumed.
- the imaging lens 110 collects light and guides it to the solid-state imaging device 200.
- the solid-state imaging device 200 generates image data according to the control of the imaging control unit 130.
- the solid-state imaging device 200 supplies image data to the image processing unit 120 via the signal line 209.
- the image processing unit 120 performs various image processing such as demosaic processing and white balance processing on the image data.
- the image processing unit 120 supplies the image data after the image processing to the recording unit 140 via the signal line 129.
- the recording unit 140 records image data.
- the image processing unit 120 is disposed outside the solid-state imaging device 200, it may be disposed inside.
- the imaging control unit 130 controls the entire imaging apparatus 100.
- the imaging control unit 130 supplies a vertical synchronization signal indicating imaging timing to the solid-state imaging device 200 via a signal line 139.
- the imaging lens 110, the solid-state imaging device 200, the image processing unit 120, the imaging control unit 130, and the recording unit 140 are arranged in the same device, they can be distributed and arranged in a plurality of devices.
- the imaging lens 110 may be arranged in the lens unit
- the solid-state imaging device 200 or the like may be arranged in the imaging apparatus 100
- the image processing unit 120 or the like may be arranged in the information processing apparatus.
- FIG. 2 is a block diagram illustrating a configuration example of the solid-state imaging device 200 according to the first embodiment.
- the solid-state imaging device 200 includes a scanning circuit 210, a pixel array unit 220, a column selection unit 240, a timing control unit 260, an AD conversion unit 270, and a transfer control circuit 280.
- each of the circuits in the solid-state image sensor 200 is provided on a single semiconductor substrate.
- the pixel array unit 220 is provided with a plurality of pixel circuits in a two-dimensional lattice shape.
- a set of pixel circuits arranged in a predetermined direction (such as a horizontal direction) is referred to as “row”, and a set of pixel circuits arranged in a direction perpendicular to the row is referred to as “column”.
- the scanning circuit 210 drives the pixel circuit to output a pixel signal.
- the scanning circuit 210 selects a row to which a pixel circuit to be read belongs and supplies a row selection signal indicating the row to the pixel array unit 220.
- the scanning circuit 210 selects a column to which the pixel circuit to be read belongs and supplies a column selection signal indicating the column to the column selection unit 240.
- the column selection unit 240 supplies an analog pixel signal from the column indicated by the column selection signal among all the columns to the AD conversion unit 270.
- the timing control unit 260 controls the timing at which each of the scanning circuit 210, the AD conversion unit 270, and the transfer control circuit 280 operates.
- the AD conversion unit 270 performs pixel conversion on the pixel signal from the column selection unit 240 to generate pixel data.
- the transfer control circuit 280 controls the AD conversion unit 270 to transfer pixel data to the image processing unit 120.
- FIG. 3 is a block diagram showing a configuration example of the pixel array unit 220 in the first embodiment.
- pixel circuits 230 are arranged in a two-dimensional lattice pattern.
- the number of rows in the pixel array unit 220 is N (N is an integer of 2 or more), and the number of columns is M (M is an integer of 2 or more).
- M is an integer of 2 or more.
- four horizontal signal lines are wired for each row along the horizontal direction, and one power supply line 229-mv (m is an integer from 0 to M-1) is wired for each column along the vertical direction.
- one is a reset line that transmits a reset signal
- two are transfer lines that transmit a transfer signal
- the other one transmits a row selection signal. Selection line. Details of the reset signal and the transfer signal will be described later.
- one vertical signal line 229-ms is wired in each of the even columns in the vertical direction.
- a reset signal corresponding to n (n is an integer from 0 to N ⁇ 1) rows is RSTn
- a row selection signal corresponding to n rows is SELYn.
- the transfer signal TRG00 is supplied to the left pixel circuit 230 in the 0th row
- the transfer signal TRG01 is supplied to the right pixel circuit 230 in the 0th row.
- the transfer signal TRG10 is supplied to the left pixel circuit 230 in the first row
- the transfer signal TRG11 is supplied to the right pixel circuit 230 in the first row.
- the left side of the second row below is TRG20
- the right side is TRG23, and the row numbers change in order.
- the number of transfer signals TRG depends on the number of columns in the block. For N ⁇ 2, the number is TRGn0 and TRGn1 for each row, and for N ⁇ 3, TRGn0, TRGn1 and TRGn2 are for each row.
- FIG. 4 is a block diagram illustrating a configuration example of the column selection unit 240 and the AD conversion unit 270 according to the first embodiment.
- the column selection unit 240 includes the same number of column selection circuits 250 as the number of vertical signal lines 229-ms. As described above, since the vertical signal line 229-ms is wired only to even columns, the number of column selection circuits 250 is 1 ⁇ 2 of the total number of columns.
- the column selection circuit 250 is connected to different vertical signal lines 229-ms. Further, the column selection unit 240 supplies pixel signals from the odd column and even column indicated by the column selection signal to the AD conversion unit 270.
- the AD converter 270 includes the same number of AD converters 271 as the number of vertical signal lines 229-ms. As described above, since the vertical signal line 229-ms is wired only to even columns, the number of AD converters 271 is 1 ⁇ 2 of the total number of columns. When one AD converter 271 is shared by three or more adjacent S columns, the number of AD converters 271 is 1 / S of the total number of columns.
- the AD converter 271 is connected to different column selection circuits 250.
- the AD converter 271 receives an analog pixel signal from the connected column selection circuit 250 and converts the pixel signal into digital pixel data in synchronization with the clock signal CLK from the timing control unit 260. Then, the AD converter 271 transfers the pixel data to the image processing unit 120 according to the control of the transfer control circuit 280.
- the AD converter 271 performs only AD conversion. However, as long as it is signal processing, the AD converter 271 is not limited to AD conversion, and may perform other processing. For example, the AD converter 271 may further perform a CDS (Correlated Double Sampling) process.
- the AD converter 271 is an example of a signal processing unit described in the claims.
- FIG. 5 is a circuit diagram showing a configuration example of the pixel circuit 230 and the column selection circuit 250 in the first embodiment.
- the pixel circuit 230 includes a photoelectric conversion element 231, a transfer transistor 232, a reset transistor 233, an amplification transistor 234 and a selection transistor 235.
- the column selection circuit 250 includes switches 251, 252, 253, and 254.
- As the transfer transistor 232, the reset transistor 233, the amplification transistor 234, and the selection transistor 235 for example, an N-type MOS (Metal Oxide Semiconductor) transistor is used.
- N-type MOS Metal Oxide Semiconductor
- the photoelectric conversion element 231 generates charges by photoelectrically converting incident light.
- the transfer transistor 232 transfers charges from the photoelectric conversion element 231 to a floating diffusion layer (not shown) in accordance with a transfer signal from the scanning circuit 210.
- the transfer signal is a signal for instructing charge transfer.
- the pixel array unit 220 is divided in units of pixel blocks including N ⁇ 2 pixel circuits 230. In this pixel block, the transfer signal TRG00 is supplied to the left pixel circuit 230 in the 0th row, and the transfer signal TRG01 is supplied to the right pixel circuit 230 in the 0th row.
- the transfer signal TRG10 is supplied to the left pixel circuit 230 in the first row in the pixel block, and the transfer signal TRG11 is supplied to the right pixel circuit 230 in the first row.
- the transfer signal TRGn0 is supplied to the left pixel circuit 230 in the nth row, and the transfer signal TRGn1 is supplied to the right pixel circuit 230 in the nth row.
- the reset transistor 233 initializes the charge amount of the floating diffusion layer in accordance with the reset signal RSTn from the scanning circuit 210.
- the reset signal RSTn is a signal for instructing initialization of the amount of charge accumulated in the floating diffusion layer in the nth row.
- the floating diffusion layer accumulates charges and generates a voltage corresponding to the amount of charges.
- the amplification transistor 234 amplifies the voltage of the floating diffusion layer.
- the amplification transistor 234 outputs a signal corresponding to the voltage of the floating diffusion layer to the selection transistor 235 as a pixel signal.
- the m-th column amplification transistor 234 and reset transistor 233 are connected to the power supply line 229-mv. Thereby, the power supplied to the amplification transistor 234 is also used as a reset power for initializing the floating diffusion layer.
- the selection transistor 235 outputs a pixel signal to the vertical signal line 229-ms in accordance with the row selection signal SELYn.
- the odd-numbered column selection transistors 235 and the even-numbered column selection transistors 235 are commonly connected to the even-numbered column vertical signal line 229-ms.
- the switch 251 opens and closes a path between the power supply line 229-mv (eg, 229-0v) in the odd-numbered column and the power supply of the power supply voltage VDD in accordance with the column selection signal SELXm from the scanning circuit 210. For example, the switch 251 shifts to a closed state when the column selection signal SELYm is at a high level, and shifts to an open state when the column selection signal SELYm is at a low level.
- the switch 252 opens and closes a path between the power supply line 229-mv (such as 229-0v) and the vertical signal line 229-ms (such as 229-1s) in the odd-numbered column in accordance with the column selection signal XSELXm from the scanning circuit 210.
- the column selection signal XSELXm is a signal obtained by inverting the column selection signal SELXm.
- the switch 252 shifts to a closed state when the column selection signal XSELXm is at a high level, and shifts to an open state when the column selection signal XSELXm is at a low level.
- the switch 253 opens and closes a path between the power supply line 229-mv (such as 229-1v) of the even-numbered column and the power supply of the power supply voltage VDD in accordance with the column selection signal SELXm from the scanning circuit 210.
- the switch 254 opens and closes a path between the power supply line 229-mv (such as 229-1v) and the vertical signal line 229-ms (such as 229-1s) in even columns according to the column selection signal XSELXm from the scanning circuit 210. Is.
- the switches 251 and 253 are examples of the power supply path opening / closing unit described in the claims.
- the switches 252 and 254 are examples of the signal path opening / closing unit described in the claims.
- the vertical signal line 229-ms is an example of the signal line described in the claims.
- the scanning circuit 210 can individually drive the pixel circuits 230 by the row selection signal SELYn and the column selection signal SELXm.
- the scanning circuit 210 can drive the pixel circuit 230 of n rows and m columns by supplying a high level row selection signal SELYn and a high level column selection signal SELXm.
- the AD converter 271 is shared by two adjacent columns, two selection lines are wired for each row, and the scanning circuit 210 sequentially selects the columns. Also in this comparative example, the pixel circuits 230 can be driven individually, but since two selection lines are wired for each row, the number of wirings becomes enormous.
- the solid-state imaging device 200 since a column can be selected by the control of the switches 251 to 254, only one selection line is required for each row. Therefore, the number of wirings in the pixel array unit 220 can be reduced as compared with the comparative example. Note that it is necessary to further provide switches 251 to 254 and selection lines to be wired to them. However, since these are wired outside the pixel array unit 220, the number of wirings in the pixel array unit 220 is affected. There is nothing.
- the solid-state imaging device 230 shares the vertical signal line 229-ms in two columns, the number of signal lines is reduced and the degree of freedom in layout is reduced compared to the case where the vertical signal lines are wired for each column. Can be high.
- one AD converter 271 is shared by two adjacent columns, one AD converter 271 may be shared by three or more adjacent columns.
- signal lines for transmitting the column selection signals SELXm and XSELXm are assumed to be wired in the horizontal direction. However, when these signal lines are wired in the horizontal direction, the number of wirings may be limited due to wiring rate limiting. Therefore, it is desirable that signal lines for transmitting the column selection signals SELXm and XSELXm are wired in the vertical direction.
- FIG. 6 is a circuit diagram showing a configuration example of a pixel circuit and a column selection circuit to which wirings are added in the first embodiment.
- vertical signal lines 229-ms such as 229-0s
- the selection transistors 235 of the pixel circuits 230 in the odd columns are commonly connected to the vertical signal lines 229-ms in the columns.
- the odd-numbered vertical signal lines are connected to the adjacent even-numbered vertical signal lines in the pixel array unit 220. Note that the odd-numbered vertical signal lines and the even-numbered vertical signal lines are not connected in the pixel array unit 220 but connected to the outside of the pixel array unit 220 (such as the vicinity of the column selection circuit 250). Also good.
- FIG. 7 is a circuit diagram showing a configuration example of the pixel circuit 230 provided with the reset power supply separately from the amplifier power supply in the first embodiment.
- the power supply (amplifier power supply) to the amplification transistor 234 is also used as a reset power supply for initializing the floating diffusion layer, but a reset power supply is provided separately from the amplifier power supply as illustrated in FIG. May be.
- the amplifier power supply supplies the voltage VDD1, and the reset power supply supplies the power supply voltage VDD2.
- the reset transistor 233 is connected to the reset power supply (VDD2), and the amplification transistor 234 is connected to the amplifier power supply (VDD1) via the power supply line 229-mv.
- FIG. 8 is a circuit diagram showing a configuration example of the column selection circuit 250 in the first embodiment.
- N-type MOS transistors 255, 256, 257, and 258 are used as the switches 251, 252, 253, and 254.
- a P-type MOS transistor may be used instead of the N-type.
- the P type the high level and the low level may be reversed in the column selection signal.
- the N type and the P type may be mixed and arranged.
- the switches 251 and 253 may be N-type and the switches 252 and 254 may be P-type. In this case, the column selection signal SELXm is input to these switches in common.
- FIG. 9 is a circuit diagram showing a configuration example of the pixel circuit 230 and the column selection circuit 250 in which the layout is changed in the first embodiment.
- the switch 251 opens and closes a path between the power supply line 229-0v and the power supply in accordance with the column selection signal SELX0.
- the switch 253 opens and closes a path between the power supply line 229-1v and the power supply according to, for example, the column selection signal SELX1.
- the solid-state imaging device 200 can control for each column whether power is supplied.
- the switch 252 opens and closes the path between the power supply line 229-0v and the vertical signal line 229-1s in accordance with, for example, the column selection signal XSELX0. Further, the switch 254 opens and closes a path between the power supply line 229-1v and the vertical signal line 229-1s in accordance with, for example, the column selection signal XSELX1. With these switches 252 and 254, the solid-state imaging device 200 can short-circuit between the power supply line corresponding to the column and the vertical signal line for each column.
- FIG. 10 is a diagram illustrating an example of a state of the column selection circuit 250 when an odd column is selected in the first embodiment.
- the scanning circuit 210 selects the “0” row and the “0” column, and does not select the “0” row and the “1” column.
- the scanning circuit 210 supplies a high-level row selection signal SELY0 to all the pixel circuits 230 in the “0” row.
- the scanning circuit 210 supplies a high-level column selection signal SELX0 to the switch 251 and supplies a low-level column selection signal XSELX0 to the switch 252.
- the scanning circuit 210 supplies a low-level column selection signal SELX1 to the switch 253, and supplies a high-level column selection signal XSELX1 to the switch 254.
- the switches 251 and 254 shift to the closed state, and the switches 252 and 253 shift to the open state.
- the selection transistors 235 in the “0” row and the “0” column shift to a conductive state (on state).
- the power supply line 229-1v and the vertical signal line 229-ms are short-circuited, the source potential and the drain potential of the selection transistor 235 in the “0” row and the “1” column are approximately the same, and the non-conduction state ( Off state). Accordingly, pixel signals are output from the pixel circuits 230 in the selected “0” row and “0” column, while pixel signals are output from the pixel circuits 230 in the unselected “0” row and “1” column. Not output.
- the potential of the power supply line 229-1v in the non-selected column is in a floating state.
- the high-level row selection signal SELY0 is supplied to the pixel circuit 230 in the non-selected column, the selection transistor 235 in the non-selected column is turned on, and a pixel signal may be output from the non-selected column.
- the source potential and the drain potential of the non-selected selection transistor 235 are controlled to the same level by these switches. The signal output can be stopped.
- FIG. 11 is a timing chart showing an example of the operation of the scanning circuit 210 in the first embodiment.
- the scanning circuit 210 supplies a reset signal RST0. Further, the scanning circuit 210 sets the column selection signal SELX0, the row selection signal SELY0, and the column selection signal XSELX1 to high level.
- the scanning circuit 210 supplies the transfer signal TRG00. By these controls, a pixel signal is read from the pixel circuit 230 in the 0th row and the 0th column.
- the scanning circuit 210 supplies a reset signal RST1.
- the scanning circuit 210 sets the column selection signal SELX1, the row selection signal SELY1, and the column selection signal XSELX0 to a high level.
- the scanning circuit 210 supplies the transfer signal TRG11. By these controls, a pixel signal is read from the pixel circuit 230 in one row and one column.
- the scanning circuit 210 supplies a reset signal RST1. Further, the scanning circuit 210 sets the column selection signal SELX0, the row selection signal SELY1, and the column selection signal XSELX1 to high level. At timing T5, the scanning circuit 210 supplies the transfer signal TRG10. With these controls, a pixel signal is read from the pixel circuit 230 in the 1st row and 0th column.
- the scanning circuit 210 supplies a reset signal RST0. Further, the scanning circuit 210 sets the column selection signal SELX1, the row selection signal SELY0, and the column selection signal XSELX0 to high level. Then, at timing T7, the scanning circuit 210 supplies the transfer signal TRG01. By these controls, a pixel signal is read from the pixel circuit 230 of 0 row and 1 column.
- the solid-state imaging device 200 may read pixel signals from all the pixels in the pixel array unit 220 or may read pixel signals from only a part thereof. For example, when generating low-resolution image data, the solid-state imaging device 200 may read out by thinning out rows and columns.
- the solid-state imaging device 200 may read out pixel signals in a predetermined order or may read them out at random.
- a technique called compressive sensing which restores an object from a small number of observation data on the assumption that it is sparse in an expression space with observation object data (pixel data, etc.), has attracted attention in the medical field and the like.
- the solid-state imaging device 200 randomly reads a part of all pixels (such as 25% of the whole), and the subsequent image processing unit 120 restores the entire image data from the pixel data. Thereby, imaging can be performed at high speed.
- FIG. 12 is a flowchart illustrating an example of the operation of the solid-state imaging device 200 according to the first embodiment. This operation is started, for example, when an operation (such as pressing a shutter button) for capturing an image is performed.
- an operation such as pressing a shutter button
- the scanning circuit 210 selects pixels in n rows and m columns based on the column selection signal SELXm and the row selection signal SELYn, and reads out the pixel signal (step S901). Then, the AD conversion unit 270 performs AD conversion on the pixel signal (step S902).
- the solid-state imaging device 200 determines whether or not all the pixel signals to be read have been read (step S903).
- the pixels to be read may be all of the pixels in the pixel array unit 220 or a part of them.
- step S903 If the reading has not been completed (step S903: No), the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps. On the other hand, when the reading is completed (step S903: Yes), the solid-state imaging device 200 performs image processing (step S904) and ends the operation for imaging.
- the column selection circuit 250 includes a path between the plurality of power supply lines and the power supply, and a path between the power supply lines and the vertical signal line. Therefore, the pixel signal can be output only to the selected column while selecting the entire row by the row selection signal. In this configuration, since one selection line for transmitting a row selection signal may be provided for each row, the number of wirings in the pixel array unit 220 can be reduced.
- Second Embodiment> In the first embodiment described above, all the circuits (the pixel array unit 220, the column selection unit 240, etc.) in the solid-state imaging device 200 are arranged on one semiconductor substrate, but a certain optical size (pixel array) Under the section 220), it is necessary to make the pixels finer in order to improve the resolution.
- This miniaturization increases the number of AD converters, and increases the circuit area other than the pixels, such as the area of the AD converter. That is, the area of the semiconductor substrate increases.
- the solid-state imaging device 200 is stacked on a plurality of semiconductor substrates, the pixel array unit 220 is disposed on one of the substrates, and the other is disposed on another substrate, the area of the semiconductor substrate can be reduced as compared with the case of not stacking. Can be small.
- the solid-state imaging device 200 according to the second embodiment is different from the first embodiment in that the solid-state imaging device 200 has a laminated structure in order to reduce the area of the semiconductor substrate.
- FIG. 13 is an example of a perspective view of the solid-state imaging device 200 according to the second embodiment.
- the solid-state imaging device 200 according to the second embodiment includes a lower semiconductor substrate 202 and an upper semiconductor substrate 201 stacked on the substrate.
- a plurality of pixel units 203 are arranged in a two-dimensional lattice pattern on the upper semiconductor substrate 201.
- a plurality of pixel circuits 230 are arranged in a two-dimensional lattice shape.
- the same number of circuit blocks 204 as the pixel units 203 are arranged in a two-dimensional lattice pattern.
- the pixel unit 203 and the circuit block 204 are connected on a one-to-one basis by through silicon vias (TSV: Through Silicon Via), bumps, or Cu—Cu connection.
- TSV Through Silicon Via
- bumps or Cu—Cu connection.
- a scanning circuit 210, a timing control unit 260, and a transfer control circuit 280 are disposed on the lower semiconductor substrate 202.
- the scanning circuit 210, the timing control unit 260, and the transfer control circuit 280 are omitted.
- FIG. 14 is a block diagram illustrating a configuration example of the pixel unit 203 and the circuit block 204 in the second embodiment.
- pixel circuits 230 of P rows ⁇ Q columns P and Q are integers of 2 or more
- a power supply line 229-qv (q is an integer from 0 to Q-1) is wired to each column.
- a vertical signal line 229- (Q-1) s is wired.
- the vertical signal line 229- (Q-1) s is connected in common to the selection transistors of all the pixel circuits 230 in the pixel unit 203.
- the configuration of the pixel circuit 230 of the second embodiment is the same as that of the first embodiment.
- a column selection circuit 250 and an AD converter 271 are arranged.
- the column selection circuit 250 is provided with switches 251 and 252 for each column.
- the switch 251 opens and closes a path between the power supply line 229-qv and the power supply according to the column selection signal SELXq.
- the switch 252 opens and closes a path between the power supply line 229-qv and the vertical signal line 229- (Q-1) s according to the column selection signal XSELXq.
- the column selection circuit 250 is arranged in the circuit block 204 in the lower semiconductor substrate 202, the column selection circuit 250 may be arranged in the upper semiconductor substrate 201.
- the circuits in the solid-state imaging device 200 may be distributed and arranged in them.
- the circuits in the solid-state imaging device 200 are distributed and arranged on the two stacked semiconductor substrates, the area of the semiconductor substrate is smaller than in the case of not stacking. can do.
- the floating diffusion layer, the reset transistor 233, and the like are provided for each pixel circuit 230.
- the circuit scale per pixel can be reduced from the viewpoint of facilitating pixel miniaturization. desirable.
- the solid-state imaging device 200 of the third embodiment is different from the first embodiment in that the circuit scale of the pixel circuit 230 is reduced.
- FIG. 15 is a circuit diagram showing a configuration example of the pixel circuit 230 and the column selection circuit 250 in the third embodiment.
- the even-numbered pixel circuit 230 includes a photoelectric conversion element 231, a transfer transistor 232, a floating diffusion layer, a reset transistor 233, an amplification transistor 234, and a selection transistor 235.
- the odd-numbered pixel circuit 230 includes only the photoelectric conversion element 236 and the transfer transistor 237. These two adjacent pixel circuits 230 share the floating diffusion layer, the reset transistor 233, the amplification transistor 234, and the selection transistor 235.
- a pair of pixels sharing the left side of the 0th row of the floating diffusion layer of N rows ⁇ 2 columns is a pixel 00a and a pixel 00b, and a pair of pixels sharing the right side of the 0th row is a pixel 01a and a pixel 01b.
- a pair of pixels sharing the left side of the first row of the floating diffusion layer of N rows ⁇ 2 columns is a pixel 10a and a pixel 10b
- a pair of pixels sharing the right side of the first row is a pixel 11a and a pixel 11b.
- Transfer signals TRG00a, TRG00b, TRG01a, TRG01b, TRG10a, TRG10b, TRG11a, and TRG11b are supplied to the pixels 00a, 00b, 01a, 01b, 10a, 10b, 11a, and 11b, respectively. Thereafter, similarly, transfer signals TRGn0a, TRG00b, TRGn1a, and TRGn1b are supplied to the nth row.
- three or more adjacent pixels may share a floating diffusion layer or the like.
- FIG. 16 is a timing chart showing an example of the operation of the vertical scanning circuit in the third embodiment.
- the scanning circuit 210 supplies a reset signal RST0.
- the scanning circuit 210 sets the column selection signal SELX0 and the row selection signal SELY0 to high level.
- the column selection signal XSELXm is omitted.
- the scanning circuit 210 supplies the transfer signal TRG00a. By these controls, the pixel signal of the pixel 00a is read out.
- the scanning circuit 210 supplies a reset signal RST0. In addition, the scanning circuit 210 sets the column selection signal SELX0 and the row selection signal SELY0 to high level. At timing T3, the scanning circuit 210 supplies the transfer signal TRG00b. By these controls, the pixel signal of the pixel 00b is read out.
- the scanning circuit 210 supplies a reset signal RST1. In addition, the scanning circuit 210 sets the column selection signal SELX0 and the row selection signal SELY1 to high level. At timing T5, the scanning circuit 210 supplies the transfer signal TRG10b. By these controls, the pixel signal of the pixel 10b is read out.
- the scanning circuit 210 supplies a reset signal RST0. Further, the scanning circuit 210 sets the column selection signal SELX1 and the row selection signal SELY0 to high level. At timing T7, the scanning circuit 210 supplies the transfer signal TRG01a. By these controls, the pixel signal of the pixel 01a is read out.
- the circuit scale of the pixel circuit 230 can be reduced as compared with a case where the pixel is not shared. Can do.
- this technique can also take the following structures. (1) a plurality of pixel circuits each connected to any of a plurality of power supply lines wired in a direction perpendicular to a predetermined direction; A signal processing unit that processes a pixel signal output via a signal line commonly connected to a predetermined number of pixel circuits adjacent in the predetermined direction among the plurality of pixel circuits; A power supply path opening / closing section that opens and closes a path between each of the plurality of power supply lines and the power supply; A solid-state imaging device comprising: a signal path opening / closing unit that opens and closes a path between each of the plurality of power supply lines and the signal line.
- the scanning circuit further includes a process of driving the pixel circuits arranged in the predetermined direction to output the pixel signal and a process of sequentially selecting any one of the predetermined number of pixel circuits.
- (1) The solid-state image sensor as described.
- (3) The power supply path opening / closing unit controls a path between the power supply line connected to the selected pixel circuit and the power supply among the plurality of power supply lines to be closed,
- the plurality of power supply lines, the plurality of pixel circuits, and the signal lines are disposed on a predetermined semiconductor substrate, The solid-state imaging device according to any one of (1) to (3), wherein the signal processing unit is disposed on a semiconductor substrate stacked on the predetermined semiconductor substrate. (5) The solid-state imaging device according to (4), wherein the power supply path opening / closing unit and the signal path opening / closing unit are disposed on the stacked semiconductor substrates. (6) The solid-state imaging device according to (4), wherein the power supply path opening / closing unit and the signal path opening / closing unit are disposed on the predetermined semiconductor substrate.
- a certain number of adjacent pixel circuits among the plurality of pixel circuits share a floating diffusion layer,
- the floating diffusion layer accumulates photoelectrically converted charges and generates a voltage corresponding to the amount of the charges,
- the solid-state imaging device according to any one of (1) to (6), wherein the pixel signal is a signal corresponding to the voltage.
- the plurality of pixel circuits include: A photoelectric conversion element that converts light into electric charge; A floating diffusion layer that accumulates the charge and generates a voltage according to the amount of the charge; A reset transistor that initializes the amount of the charge accumulated in the floating diffusion layer; An amplification transistor that outputs a signal corresponding to the voltage as the pixel signal;
- the solid-state imaging device according to any one of (1) to (7), wherein the amplification transistor is connected to the power supply, and the reset transistor is connected to a reset power supply different from the power supply.
- a plurality of pixel circuits each connected to any of a plurality of power supply lines wired in a direction perpendicular to a predetermined direction;
- a signal processing unit that processes a pixel signal output via a signal line commonly connected to a predetermined number of pixel circuits adjacent in the predetermined direction among the plurality of pixel circuits;
- a power supply path opening / closing section that opens and closes a path between each of the plurality of power supply lines and the power supply;
- a signal path opening and closing unit for opening and closing a path between each of the plurality of power supply lines and the signal line;
- An imaging apparatus comprising: a recording unit that records image data generated from the processed pixel signal.
- (11) Commonly connected to a predetermined number of pixel circuits adjacent to each other in the predetermined direction among a plurality of pixel circuits each connected to any of a plurality of power supply lines wired in a direction perpendicular to the predetermined direction.
- a control method for a solid-state imaging device comprising: a signal path opening / closing procedure for opening / closing a path between each of the plurality of power supply lines and the signal line.
- Imaging device 110 Imaging lens 120 Image processing part 130 Imaging control part 140 Recording part 200 Solid-state image sensor 201 Upper semiconductor substrate 202 Lower semiconductor substrate 203 Pixel unit 204 Circuit block 210 Scan circuit 220 Pixel array part 230 Pixel circuit 231 and 236 Photoelectric Conversion element 232, 237 Transfer transistor 233 Reset transistor 234 Amplification transistor 235 Selection transistor 240 Column selection unit 250 Column selection circuit 251, 252, 253, 254 Switch 255, 256, 257, 258 MOS transistor 260 Timing control unit 270 AD conversion unit 271 AD converter 280 Transfer control circuit
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Abstract
Description
1.第1の実施の形態(電源経路と信号経路とを開閉する例)
2.第2の実施の形態(積層構造の固体撮像素子において電源経路と信号経路とを開閉する例)
3.第3の実施の形態(浮遊拡散層を2画素で共有し、電源経路と信号経路とを開閉する例)
[撮像装置の構成例]
図1は、第1の実施の形態における撮像装置100の一構成例を示すブロック図である。この撮像装置100は、画像データを撮像する装置であり、撮像レンズ110、固体撮像素子200、画像処理部120、撮像制御部130および記録部140を備える。撮像装置100としては、アクションカムや車載カメラなどが想定される。
図2は、第1の実施の形態における固体撮像素子200の一構成例を示すブロック図である。この固体撮像素子200は、走査回路210、画素アレイ部220、列選択部240、タイミング制御部260、AD変換部270および転送制御回路280を備える。また、固体撮像素子200内の回路のそれぞれは、単一の半導体基板に設けられている。
図3は、第1の実施の形態における画素アレイ部220の一構成例を示すブロック図である。この画素アレイ部220には、二次元格子状に画素回路230が配列される。画素アレイ部220内の行数をN(Nは2以上の整数)とし、列数をM(Mは2以上の整数)とする。また、水平方向に沿って行ごとに4本の水平信号線が配線され、垂直方向に沿って列ごとに1本の電源線229-mv(mは0乃至M-1の整数)が配線される。行に対応する4本の水平信号線のうち1本は、リセット信号を伝送するリセット線であり、2本は転送信号を伝送する転送線であり、残りの1本は行選択信号を伝送する選択線である。リセット信号および転送信号の詳細については後述する。また、偶数列のそれぞれには、垂直方向に1本の垂直信号線229-msが配線される。
図5は、第1の実施の形態における画素回路230および列選択回路250の一構成例を示す回路図である。画素回路230は、光電変換素子231、転送トランジスタ232、リセットトランジスタ233、増幅トランジスタ234および選択トランジスタ235を備える。また、列選択回路250は、スイッチ251、252、253および254を備える。転送トランジスタ232、リセットトランジスタ233、増幅トランジスタ234および選択トランジスタ235として、例えば、N型のMOS(Metal Oxide Semiconductor)トランジスタが用いられる。
図12は、第1の実施の形態における固体撮像素子200の動作の一例を示すフローチャートである。この動作は、例えば、画像を撮像させるための操作(シャッターボタンの押下など)が行われたときに開始される。
上述の第1の実施の形態では、1つの半導体基板に固体撮像素子200内の回路(画素アレイ部220や列選択部240など)の全てを配置していたが、一定の光学サイズ(画素アレイ部220)の下で、解像度を向上させるには画素を微細化する必要が生じる。この微細化により、AD変換器の数が増え、AD変換器の面積など、画素以外の回路面積が増加する。つまり半導体基板の面積が増大する。そこで、固体撮像素子200を複数の半導体基板に積層化し、いずれかの基板に画素アレイ部220を配置して、それ以外を別の基板に配置すれば、積層しない場合よりも半導体基板の面積を小さくすることができる。この第2の実施の形態の固体撮像素子200は、半導体基板の面積を小さくするために、固体撮像素子200を積層構造にした点において第1の実施の形態と異なる。
上述の第1の実施の形態では、画素回路230ごとに浮遊拡散層やリセットトランジスタ233などを設けていたが、画素の微細化を容易にする観点から、画素あたりの回路規模を削減することが望ましい。この第3の実施の形態の固体撮像素子200は、画素回路230の回路規模を削減した点において第1の実施の形態と異なる。
(1)所定の方向に垂直な方向に配線された複数の電源線のいずれかに各々が接続された複数の画素回路と、
前記複数の画素回路のうち前記所定の方向において隣接する所定数の画素回路に共通に接続された信号線を介して出力された画素信号を処理する信号処理部と、
前記複数の電源線のそれぞれと電源との間の経路を開閉する電源経路開閉部と、
前記複数の電源線のそれぞれと前記信号線との間の経路を開閉する信号経路開閉部と
を具備する固体撮像素子。
(2)前記所定の方向に配列された前記画素回路を駆動して前記画素信号を出力させる処理と前記所定数の画素回路のいずれかを順に選択する処理とを行う走査回路をさらに具備する
前記(1)記載の固体撮像素子。
(3)前記電源経路開閉部は、前記複数の電源線のうち前記選択された画素回路に接続された電源線と前記電源との間の経路を閉状態に制御し、
前記信号経路開閉部は、前記複数の電源線のうち前記選択された画素回路に接続された電源線と前記信号線との間の経路を開状態に制御する
前記(2)記載の固体撮像素子。
(4)前記複数の電源線と前記複数の画素回路と前記信号線とは、所定の半導体基板に配置され、
前記信号処理部は、前記所定の半導体基板に積層された半導体基板に配置される
前記(1)から(3)のいずれかに記載の固体撮像素子。
(5)前記電源経路開閉部および前記信号経路開閉部は、前記積層された半導体基板に配置される
前記(4)記載の固体撮像素子。
(6)前記電源経路開閉部および前記信号経路開閉部は、前記所定の半導体基板に配置される
前記(4)記載の固体撮像素子。
(7)前記複数の画素回路のうち隣接する一定数の画素回路は、浮遊拡散層を共有し、
前記浮遊拡散層は、光電変換された電荷を蓄積して当該電荷の量に応じた電圧を生成し、
前記画素信号は、前記電圧に応じた信号である
前記(1)から(6)のいずれかに記載の固体撮像素子。
(8)前記複数の画素回路は、
光を電荷に変換する光電変換素子と、
前記電荷を蓄積して当該電荷の量に応じた電圧を生成する浮遊拡散層と、
前記浮遊拡散層に蓄積された前記電荷の量を初期化するリセットトランジスタと、
前記電圧に応じた信号を前記画素信号として出力する増幅トランジスタと
を備え、
前記増幅トランジスタは、前記電源に接続され、前記リセットトランジスタは前記電源と異なるリセット電源に接続される
前記(1)から(7)のいずれかに記載の固体撮像素子。
(9)前記信号処理部は、前記画素信号に対してアナログデジタル変換を行う
前記(1)から(8)のいずれかに記載の固体撮像素子。
(10)所定の方向に垂直な方向に配線された複数の電源線のいずれかに各々が接続された複数の画素回路と、
前記複数の画素回路のうち前記所定の方向において隣接する所定数の画素回路に共通に接続された信号線を介して出力された画素信号を処理する信号処理部と、
前記複数の電源線のそれぞれと電源との間の経路を開閉する電源経路開閉部と、
前記複数の電源線のそれぞれと前記信号線との間の経路を開閉する信号経路開閉部と、
前記処理された画素信号から生成された画像データを記録する記録部と
を具備する撮像装置。
(11)所定の方向に垂直な方向に配線された複数の電源線のいずれかに各々が接続された複数の画素回路のうち前記所定の方向において隣接する所定数の画素回路に共通に接続された信号線を介して出力された画素信号を処理する信号処理手順と、
前記複数の電源線のそれぞれと電源との間の経路を開閉する電源経路開閉手順と、
前記複数の電源線のそれぞれと前記信号線との間の経路を開閉する信号経路開閉手順と
を具備する固体撮像素子の制御方法。
110 撮像レンズ
120 画像処理部
130 撮像制御部
140 記録部
200 固体撮像素子
201 上側半導体基板
202 下側半導体基板
203 画素ユニット
204 回路ブロック
210 走査回路
220 画素アレイ部
230 画素回路
231、236 光電変換素子
232、237 転送トランジスタ
233 リセットトランジスタ
234 増幅トランジスタ
235 選択トランジスタ
240 列選択部
250 列選択回路
251、252、253、254 スイッチ
255、256、257、258 MOSトランジスタ
260 タイミング制御部
270 AD変換部
271 AD変換器
280 転送制御回路
Claims (11)
- 所定の方向に垂直な方向に配線された複数の電源線のいずれかに各々が接続された複数の画素回路と、
前記複数の画素回路のうち前記所定の方向において隣接する所定数の画素回路に共通に接続された信号線を介して出力された画素信号を処理する信号処理部と、
前記複数の電源線のそれぞれと電源との間の経路を開閉する電源経路開閉部と、
前記複数の電源線のそれぞれと前記信号線との間の経路を開閉する信号経路開閉部と
を具備する固体撮像素子。 - 前記所定の方向に配列された前記画素回路を駆動して前記画素信号を出力させる処理と前記所定数の画素回路のいずれかを順に選択する処理とを行う走査回路をさらに具備する
請求項1記載の固体撮像素子。 - 前記電源経路開閉部は、前記複数の電源線のうち前記選択された画素回路に接続された電源線と前記電源との間の経路を閉状態に制御し、
前記信号経路開閉部は、前記複数の電源線のうち前記選択された画素回路に接続された電源線と前記信号線との間の経路を開状態に制御する
請求項2記載の固体撮像素子。 - 前記複数の電源線と前記複数の画素回路と前記信号線とは、所定の半導体基板に配置され、
前記信号処理部は、前記所定の半導体基板に積層された半導体基板に配置される
請求項1記載の固体撮像素子。 - 前記電源経路開閉部および前記信号経路開閉部は、前記積層された半導体基板に配置される
請求項4記載の固体撮像素子。 - 前記電源経路開閉部および前記信号経路開閉部は、前記所定の半導体基板に配置される
請求項4記載の固体撮像素子。 - 前記複数の画素回路のうち隣接する一定数の画素回路は、浮遊拡散層を共有し、
前記浮遊拡散層は、光電変換された電荷を蓄積して当該電荷の量に応じた電圧を生成し、
前記画素信号は、前記電圧に応じた信号である
請求項1記載の固体撮像素子。 - 前記複数の画素回路は、
光を電荷に変換する光電変換素子と、
前記電荷を蓄積して当該電荷の量に応じた電圧を生成する浮遊拡散層と、
前記浮遊拡散層に蓄積された前記電荷の量を初期化するリセットトランジスタと、
前記電圧に応じた信号を前記画素信号として出力する増幅トランジスタと
を備え、
前記増幅トランジスタは、前記電源に接続され、前記リセットトランジスタは前記電源と異なるリセット電源に接続される
請求項1記載の固体撮像素子。 - 前記信号処理部は、前記画素信号に対してアナログデジタル変換を行う
請求項1記載の固体撮像素子。 - 所定の方向に垂直な方向に配線された複数の電源線のいずれかに各々が接続された複数の画素回路と、
前記複数の画素回路のうち前記所定の方向において隣接する所定数の画素回路に共通に接続された信号線を介して出力された画素信号を処理する信号処理部と、
前記複数の電源線のそれぞれと電源との間の経路を開閉する電源経路開閉部と、
前記複数の電源線のそれぞれと前記信号線との間の経路を開閉する信号経路開閉部と、
前記処理された画素信号から生成された画像データを記録する記録部と
を具備する撮像装置。 - 所定の方向に垂直な方向に配線された複数の電源線のいずれかに各々が接続された複数の画素回路のうち前記所定の方向において隣接する所定数の画素回路に共通に接続された信号線を介して出力された画素信号を処理する信号処理手順と、
前記複数の電源線のそれぞれと電源との間の経路を開閉する電源経路開閉手順と、
前記複数の電源線のそれぞれと前記信号線との間の経路を開閉する信号経路開閉手順と
を具備する固体撮像素子の制御方法。
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2010171521A (ja) * | 2009-01-20 | 2010-08-05 | Sony Corp | 撮像素子およびその制御方法、並びにカメラ |
JP2010245955A (ja) * | 2009-04-08 | 2010-10-28 | Sony Corp | 固体撮像素子およびカメラシステム |
WO2012144218A1 (ja) * | 2011-04-22 | 2012-10-26 | パナソニック株式会社 | 固体撮像装置および固体撮像装置の駆動方法 |
JP2013232717A (ja) | 2012-04-27 | 2013-11-14 | Nikon Corp | 撮像素子、撮像装置および制御方法 |
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US20050185077A1 (en) | 2004-02-23 | 2005-08-25 | Jps Group Holdings, Ltd. | Cmos image sensor with 1.25 - 1.5 transistor/pixel ratio |
JP2005245955A (ja) | 2004-03-08 | 2005-09-15 | Showa Nishikawa Co Ltd | 寝具展示台及び寝具展示方法 |
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US9979916B2 (en) * | 2014-11-21 | 2018-05-22 | Canon Kabushiki Kaisha | Imaging apparatus and imaging system |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171521A (ja) * | 2009-01-20 | 2010-08-05 | Sony Corp | 撮像素子およびその制御方法、並びにカメラ |
JP2010245955A (ja) * | 2009-04-08 | 2010-10-28 | Sony Corp | 固体撮像素子およびカメラシステム |
WO2012144218A1 (ja) * | 2011-04-22 | 2012-10-26 | パナソニック株式会社 | 固体撮像装置および固体撮像装置の駆動方法 |
JP2013232717A (ja) | 2012-04-27 | 2013-11-14 | Nikon Corp | 撮像素子、撮像装置および制御方法 |
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