WO2017197917A1 - 移位寄存器及其操作方法 - Google Patents

移位寄存器及其操作方法 Download PDF

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Publication number
WO2017197917A1
WO2017197917A1 PCT/CN2017/070865 CN2017070865W WO2017197917A1 WO 2017197917 A1 WO2017197917 A1 WO 2017197917A1 CN 2017070865 W CN2017070865 W CN 2017070865W WO 2017197917 A1 WO2017197917 A1 WO 2017197917A1
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WIPO (PCT)
Prior art keywords
pull
node
output
shift register
transistor
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PCT/CN2017/070865
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English (en)
French (fr)
Inventor
高英强
陈华斌
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/541,893 priority Critical patent/US20180226132A1/en
Publication of WO2017197917A1 publication Critical patent/WO2017197917A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to a shift register and method of operation thereof.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • the driving circuit of the TFT-LCD mainly includes a gate driving circuit and a data driving circuit.
  • the data driving circuit is configured to sequentially latch the input data according to the clock signal timing and convert the latched data into an analog signal and input the data to the data line of the display panel.
  • the gate driving circuit is usually implemented by a shift register that converts a clock signal into an on/off voltage, which are respectively output to respective gate lines of the display panel.
  • a gate line on the display panel is typically docked with a shift register (ie, the stage of the shift register). Progressive scanning of pixels in the display panel is achieved by causing the respective shift registers to sequentially output the turn-on voltage.
  • the GOA technology directly integrates the gate driving circuit of the TFT-LCD on the array substrate, thereby replacing the driving chip made of the silicon chip bonded on the outer edge of the panel. Since the technology can directly drive the driving circuit on the array substrate, there is no need to bond the IC and the wiring around the panel, which reduces the manufacturing process of the panel, reduces the product cost, and improves the integration degree of the TFT-LCD panel, so that the panel can be realized. Narrow borders and high resolution.
  • the present disclosure provides a shift register and method of operation thereof. It can eliminate the noise at the output of the shift register and improve the stability of the work.
  • a shift register comprising:
  • An input module the first end of which is connected to the input end of the shift register for receiving an input signal from the input end, and the second end is connected to the pull-up node;
  • a reset module the first end of which is connected to the reset signal end, the second end is connected to the pull-up node, the third end is connected to the first power supply voltage end, and the fourth end is connected to the output end of the shift register;
  • a pull-down control module the first end of which is connected to the first clock signal end, the second end is connected to the pull-up node, the third end is connected to the pull-down node, and the fourth end is connected to the first power supply voltage end;
  • a pull-down module the first end of which is connected to the pull-down node, the second end is connected to the output end of the shift register, the third end is connected to the pull-up node, and the fourth end is connected to the first power supply voltage end;
  • An output module the first end of which is connected to the pull-up node, the second end is connected to the second clock signal end, and the third end is connected to the output end of the shift register;
  • a noise reduction module is coupled to the pull-down node for reducing noise at the output of the shift register by maintaining the level of the pull-down node.
  • an operation method of a shift register including an input module, a reset module, a pull-down control module, a pull-down module, an output module, and a noise reduction module is disclosed, the method comprising:
  • the noise reduction at the output of the shift register is reduced by the noise reduction module by maintaining the level of the pull-down node.
  • Figure 1 shows a circuit diagram of a conventional shift register
  • Figure 2 is a timing diagram of the signals of the shift register of Figure 1 as it is being scanned;
  • FIG. 3 illustrates a block diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 4 illustrates an example circuit configuration diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 5 illustrates another example circuit configuration diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 6 illustrates still another example circuit configuration diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 7 shows an operational timing diagram of an example circuit of the shift register of FIG. 6.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • the gate one of which is called the drain and the other is called the source.
  • Figure 1 shows a circuit diagram of a conventional shift register.
  • the shift register 100 includes first to tenth transistors M1-M10 and a first capacitor C1.
  • the first transistor M1 serves as the input module 11
  • the third and fourth transistors M3-M4 serve as the reset module 12
  • the fifth to eighth transistors M5-M8 serve as the pull-down control module 13
  • the ninth and tenth transistors M9-M10 serve as The pull-down module 14
  • the second transistor M2 and the first capacitor C1 serve as the output module 15.
  • the first end of the input module 11 is connected to the input terminal INPUT of the shift register for receiving an input signal from the input terminal INPUT, the second end is connected to the pull-up node PU, and the input module 11 is configured to be at the input terminal INPUT When the input signal is at the active input level, the received input signal is passed to the pull-up node PU.
  • the first end of the reset module 12 is connected to the reset signal terminal RESET, the second end is connected to the pull-up node PU, the third end is connected to the first power supply voltage terminal VSS, the fourth end is connected to the output terminal OUTPUT, and the reset module 12 is connected.
  • the first end of the pull-down control module 13 is connected to the first clock signal terminal CLKB, the second end is connected to the pull-up node PU, the third end is connected to the pull-down node PD, and the fourth end is connected to the first power supply voltage terminal VSS, the pull-down The control module 13 is configured to control whether the pull down module 14 is operating. For example, the pull-down control module 13 is in the pull-down section when the pull-up signal at the pull-up node PU is at the effective pull-up level.
  • a pull-down signal at a non-active pull-down level is generated at the PD, and the pull-up signal at the pull-up node PU is at a non-active pull-up level and the first clock signal at the first clock signal terminal CLKB is in an active control state
  • a pull-down signal at the effective pull-down level is typically generated at the pull-down node PD.
  • the first end of the pull-down module 14 is connected to the pull-down node PD, the second end is connected to the output terminal OUTPUT, the third end is connected to the pull-up node PU, the fourth end is connected to the first power supply voltage terminal VSS, and the pull-down module 14 is connected.
  • the output terminal OUTPUT and the pull-up node PU are configured to pull down the supply voltage of the first supply voltage terminal VSS when the pull-down signal at the pull-down node PD is at the active pull-down level.
  • the first end of the output module 15 is connected to the pull-up node PU, the second end is connected to the second clock signal terminal CLK, the third end is connected to the output terminal OUTPUT of the shift register, and the output module 15 is configured to be on The second clock signal of the second clock signal terminal CLK is output to the output terminal OUTPUT when the pull-up signal at the pull node PU is at the effective pull-up level.
  • the first clock signal of the first clock signal terminal CLKB is inverted from the second clock signal of the second clock signal terminal CLK.
  • the first power voltage terminal VSS is a low power voltage terminal.
  • Shown in Figure 2 is a timing diagram of the signals of the shift register of Figure 1 as it is being scanned.
  • the pull-up node PU and the output terminal OUTPUT are in a floating state, which is very likely to cause noise. Affects voltage retention.
  • the second clock signal of the second clock signal terminal CLK is changed from the low level of the reset phase (ie, the third phase P3 in FIG. 2) to the high level due to the gate source of the second transistor M2.
  • the voltage of the pull-up node PU is pulled high, and the second transistor M2 is turned on, so that the second clock signal of the second clock signal terminal CLK recharges the output terminal OUTPUT, causing noise at the output terminal.
  • the present disclosure proposes a new shift register, which can effectively reduce the noise at the output end.
  • FIG. 3 shows a block diagram of a shift register in accordance with an embodiment of the present disclosure.
  • the shift register includes an input module 31, a reset module 32, a pull-down control module 33, a pull-down module 34, an output module 35, and a noise reduction module 36.
  • the first end of the input module 31 is connected to the input terminal INPUT of the shift register for receiving an input signal from the input terminal INPUT, the second end is connected to the pull-up node PU, and the input module 31 is configured to be at the input terminal INPUT When the input signal is at the active input level, the received input signal is passed to the pull-up node PU.
  • the first end of the reset module 32 is connected to the reset signal terminal RESET, the second end is connected to the pull-up node PU, the third end is connected to the first power supply voltage terminal VSS, the fourth end is connected to the output terminal OUTPUT, and the reset module 32 is connected.
  • the first end of the pull-down control module 33 is connected to the first clock signal terminal CLKB, the second end is connected to the pull-up node PU, the third end is connected to the pull-down node PD, and the fourth end is connected to the first power supply voltage terminal VSS.
  • the control module 33 is configured to control whether the pull down module 34 is operating.
  • the pull-down control module 33 generates a pull-down signal at the pull-down node PD at the pull-down node PD when the pull-up signal at the pull-up node PU is at the active pull-up level, while the pull-up signal at the pull-up node PU is at A pull-down signal at an effective pull-down level is generated at the pull-down node PD when the non-active pull-up level and when the first clock signal at the first clock signal terminal CLKB is at the active control level.
  • the first end of the pull-down module 34 is connected to the pull-down node PD, the second end is connected to the output terminal OUTPUT, the third end is connected to the pull-up node PU, the fourth end is connected to the first power supply voltage terminal VSS, and the pull-down module 34 is connected.
  • the output terminal OUTPUT and the pull-up node PU are configured to pull down the supply voltage of the first supply voltage terminal VSS when the pull-down signal at the pull-down node PD is at the active pull-down level.
  • the first end of the output module 35 is connected to the pull-up node PU, the second end is connected to the second clock signal terminal CLK, the third end is connected to the output terminal OUTPUT of the shift register, and the output module 35 is configured to be on The second clock signal of the second clock signal terminal CLK is output to the output terminal OUTPUT when the pull-up signal at the pull node PU is at the effective pull-up level.
  • the noise reduction module 36 is coupled to the pull down node PD, and the noise reduction module 36 is configured to reduce the noise at the output of the shift register by maintaining the level of the pull down node. Further, the noise reduction module 36 is also connected to the first power voltage terminal VSS and/or to the second clock signal terminal CLK.
  • the first clock signal of the first clock signal terminal CLKB is inverted from the second clock signal of the second clock signal terminal CLK.
  • the first power voltage terminal VSS is a low power voltage terminal.
  • FIG. 4 shows an example circuit configuration diagram of a shift register according to an embodiment of the present disclosure.
  • the transistors in FIG. 4 are all N-type transistors that are turned on when the gate input is at a high level.
  • the input module 31 includes an input transistor M1, the gate and the first pole of the input transistor M1 are connected to the input terminal INPUT, and the second pole of the input transistor M1 is connected to the pull-up node PU. connection.
  • the input transistor M1 is turned on, and the input signal of the input terminal INPUT is transmitted to the pull-up node PU.
  • the reset module 32 includes a node reset transistor M3 and an output reset transistor M4.
  • the gate of the node reset transistor M3 is connected to the reset signal terminal RESET, the first pole is connected to the pull-up node PU, and the second pole is connected.
  • the first power supply voltage terminal VSS is connected.
  • the gate of the output reset transistor M4 is connected to the reset signal terminal RESET, the first pole is connected to the output terminal OUTPUT, and the second pole is connected to the first power supply voltage terminal VSS.
  • the node reset transistor M3 When the reset signal at the reset signal terminal RESET is at a high level, the node reset transistor M3 is turned on, pulls up the pull-up signal at the pull-up node PU to the power supply voltage of the first power supply voltage terminal VSS, and the output reset transistor M4 is turned on. The output signal of the output terminal OUTPUT is pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the pull-down control module 33 includes a first pull-down control transistor M5, a second pull-down control transistor M6, a third pull-down control transistor M7, and a fourth pull-down control transistor M8.
  • the gate of the first pull-down control transistor M5 is connected to the pull-down control node PD_CN, the first pole is connected to the first clock signal terminal CLKB, the second pole is connected to the pull-down node PD, and the second pull-down control transistor M6 is gated and pulled up.
  • the node PU is connected, the first pole is connected to the pull-down node PD, the second pole is connected to the first power voltage terminal VSS, and the gate and the first pole of the third pull-down control transistor M7 are connected to the first clock signal terminal CLKB, and the second pole Connected to the pull-down control node PD_CN; the gate of the fourth pull-down control transistor M8 is connected to the pull-up node PU, the first pole is connected to the pull-down control node PD_CN, and the second pole is connected to the first power supply voltage terminal VSS.
  • the pull-down module 34 includes a node pull-down transistor M9 and an output pull-down transistor M10, the gates of the node pull-down transistor M9 and the output pull-down transistor M10 are connected to the pull-down node PD, the node pull-down transistor M9 and the output pull-down transistor M10
  • the second pole is connected to the first power voltage terminal VSS
  • the first pole of the node pull-down transistor M9 is connected to the pull-up node PU
  • the first pole of the output pull-down transistor M10 is connected to the output terminal OUTPUT.
  • the node pull-down transistor M9 and the output pull-down transistor M10 are turned on, respectively pulling the pull-up node PU and the output terminal OUTPUT to the power supply voltage of the first power supply voltage terminal VSS.
  • the output module 35 includes an output transistor M2 and a first capacitor C1.
  • the first terminal of the gate of the output transistor M2 and the first capacitor C1 is connected to the pull-up node PU, and the first pole of the output transistor M2 Connected to the second clock signal terminal CLK, the second terminal of the output transistor M2 and the second terminal of the first capacitor C1 are connected to the output terminal OUTPUT.
  • the pull-up signal at the pull-up node PU is at a high level
  • the output transistor M2 is turned on, and the second clock signal of the second clock signal terminal CLK is output to the output terminal OUTPUT.
  • the noise reduction module 36 includes a second capacitor C2 having a first end coupled to the pull-down node PD and a second end coupled to the first supply voltage terminal VSS.
  • the second capacitor C2 maintains the high level, so that the node pull-down transistor M9 and the output pull-down transistor M10 are always turned on, and the voltage of the pull-up node PU and the output terminal OUTPUT is continuously pulled.
  • FIG. 5 illustrates another example circuit configuration diagram of a shift register according to an embodiment of the present disclosure.
  • the example circuit structure diagram differs from FIG. 4 only in the noise reduction module 36.
  • the noise reduction module 36 includes a third capacitor C3.
  • the first end of the third capacitor C3 is connected to the pull-down node PD, and the second end is connected to the second clock signal terminal CLK.
  • the third capacitor C3 maintains the high level, so that the node pull-down transistor M9 and the output pull-down transistor M10 are always turned on, and the voltage of the pull-up node PU and the output terminal OUTPUT is continuously pulled.
  • FIG. 6 shows still another example circuit configuration diagram of a shift register according to an embodiment of the present disclosure.
  • the example circuit structure diagram differs from FIG. 4 only in the noise reduction module 36.
  • the noise reduction module 36 includes a second capacitor C2 and a third capacitor C3.
  • the first end of the second capacitor C2 is connected to the pull-down node PD, and the second end is connected to the first power supply voltage terminal VSS.
  • the first end of the third capacitor C3 is connected to the pull-down node PD, and the second end and the second clock
  • the signal terminal CLK is connected.
  • the second capacitor C2 and the third capacitor C3 maintain the high level, so that the node pull-down transistor M9 and the output pull-down transistor M10 are always turned on, and continue to pull up the node PU and output.
  • the voltage of the terminal OUTPUT is pulled low, thereby lowering the high level of the second clock signal terminal CLK, and affecting the voltage of the pull-up node PU and the output terminal OUTPUT through the gate-source capacitance Cgs of the output transistor M2, reducing the pull-up node PU and the output terminal OUTPUT noise.
  • FIG. 7 shows an operational timing diagram of an example circuit of the shift register of FIG. 6. The operation method of the shift register in Fig. 6 will be described below with reference to Figs. 6 and 7.
  • the input terminal INPUT is at a high level
  • the input transistor T1 is turned on
  • the high level of the input terminal INPUT is transmitted to the pull-up node PU
  • the pull-up node PU is at the first high voltage.
  • the output transistor M2 is turned on, and the output terminal OUTPUT outputs a low level because the second clock signal of the second clock signal terminal CLK is at a low level.
  • the second pull-down control transistor M6 and the fourth pull-down control transistor M8 are turned on, so that the pull-down node PD is at a low level, correspondingly the node pull-down transistor M9 and the output The pull-down transistor M10 is turned off. Further, in this stage, the reset signal of the reset signal terminal RESET is at a low level, and the node reset transistor M3 is turned off.
  • the input terminal INPUT is at a low level
  • the input transistor M1 is turned off
  • the reset signal terminal RESET is at a low level
  • the node reset transistor M3 is kept off
  • the pull-up node PU continues to turn on the output transistor M2.
  • the second clock signal of the second clock signal terminal CLK is at a high level
  • the output terminal OUTPUT outputs a high level. Due to the voltage coupling of the first capacitor C1, the pull-up node PU is raised from the first high voltage to the first Two high voltages.
  • the input terminal INPUT is at a low level
  • the input transistor M1 is kept off
  • the reset signal of the reset signal terminal RESET is at a high level
  • the node reset transistor M3 and the output reset transistor M4 are turned on, respectively
  • the pull-up signal at the pull-up node PU and the output signal of the output terminal OUTPUT are pulled down to the power supply voltage of the first power supply voltage terminal VSS.
  • the pull-up node PU since the pull-up node PU is at a low level, the second pull-down control transistor M6 and the fourth pull-down control transistor M8 are both turned off, because the first clock signal of the first clock signal terminal CLKB is at The high level, the first pull-down control transistor M5 and the third pull-down control transistor M7 are both turned on, so that the pull-down node PD transitions from a low level to a high level, and accordingly the node pull-down transistor M9 and the output pull-down transistor M10 are both turned on. Pulling up the pull-up signal at the pull-up node PU and the output signal of the output terminal OUTPUT to the power supply voltage of the first power supply voltage terminal VSS. Since the pull-down node PD is at a high level, the second capacitor C2 and the third capacitor C3 are charged at this time.
  • the first clock signal of the first clock signal terminal CLKB is at a low level, and the first pull-down control transistor M5 and the third pull-down control transistor M7 are both turned off, since the pull-up node PU is at a low level.
  • the level, the second pull-down control transistor M6 and the fourth pull-down control transistor M8 are both kept off.
  • the second capacitor C2 and the third capacitor C3 simultaneously maintain the voltage of the pull-down node PD to keep it at a high level, and accordingly the node pull-down transistor M9 and the output pull-down transistor M10 are both turned on, and the pull-up node PU and the output terminal OUTPUT are maintained.
  • the first power supply voltage terminal VSS is a low power supply voltage terminal.
  • the pull-up node PU is always at a low level
  • the pull-down node PD is always at a high level
  • the node pull-down transistor M9 and the output pull-down transistor M10 are always in an on state, and the node PU and the output can be continuously pulled up.
  • the terminal OUTPUT performs noise reduction, and ensures the stability of the low-voltage signal output of the output terminal OUTPUT.
  • the shift register re-executes the first stage after receiving the high level signal of the input terminal INPUT.
  • the first clock signal of the first clock signal terminal CLKB is inverted with the second clock signal of the second clock signal terminal CLK.
  • the shift register includes an input module 31, a reset module 32, a pull-down control module 33, a pull-down module 34, an output module 35, and a noise reduction module 36.
  • the operation method of the shift register includes:
  • the power supply voltage of the pull-up node PU is pulled down to the power supply voltage of the first power supply voltage terminal VSS and the output signal of the output terminal OUTPUT of the shift register is pulled down to the power supply voltage of the first power supply voltage terminal VSS by the reset module 32;
  • the noise of the output terminal OUTPUT of the shift register is reduced by the noise reduction module 36 by maintaining the level of the pull-down node PD.
  • the first power voltage terminal VSS is a low power voltage terminal
  • the first clock signal of the first clock signal terminal CLKB is inverted with the second clock signal of the second clock signal terminal CLK.

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  • Crystallography & Structural Chemistry (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

一种移位寄存器及其操作方法。该移位寄存器包括：输入模块（31），连接该移位寄存器的输入端（INPUT）、上拉节点（PU）；复位模块（32），连接复位信号端（RESET）、上拉节点（PU）、第一电源电压端（VSS）和该移位寄存器的输出端（OUTPUT）；下拉控制模块（33），连接第一时钟信号端（CLKB）、上拉节点（PU）、下拉节点（PD）和第一电源电压端（VSS）；下拉模块（34），连接下拉节点（PD）、该移位寄存器的输出端（OUTPUT）、上拉节点（PU）和第一电源电压端（VSS）；输出模块（35），连接上拉节点（PU）、第二时钟信号端（CLK）和该移位寄存器的输出端（OUTPUT）；以及降噪模块（36），连接下拉节点（PD），可以有效降低输出端（OUTPUT）噪声。

Description

移位寄存器及其操作方法 技术领域
本公开涉及一种移位寄存器及其操作方法。
背景技术
薄膜晶体管液晶显示器(TFT-LCD)广泛应用于生产生活的各个领域，其采用M*N点排列的逐行扫描矩阵显示。在进行显示时，TFT-LCD通过驱动电路来驱动显示面板中的各个像素进行显示。TFT-LCD的驱动电路主要包含栅极驱动电路和数据驱动电路。其中，数据驱动电路用于依据时钟信号定时将输入的数据顺序锁存并将锁存的数据转换成模拟信号后输入到显示面板的数据线。栅极驱动电路通常用移位寄存器来实现，所述移位寄存器将时钟信号转换成开启/断开电压，分别输出到显示面板的各条栅线上。显示面板上的一条栅线通常与一个移位寄存器(即移位寄存器的一级)对接。通过使得各个移位寄存器依序轮流输出开启电压，实现对显示面板中像素的逐行扫描。
另一方面，随着平板显示的发展，高分辨率、窄边框成为发展的趋势。针对这一趋势，出现了阵列基板栅极驱动(Gate Driver on Array，GOA)技术。GOA技术直接将TFT-LCD的栅极驱动电路集成制作在阵列基板上，由此来代替在面板外沿粘接的、由硅芯片制作的驱动芯片。由于该技术可以将驱动电路直接做在阵列基板上，面板周围无需再粘接IC和布线，减少了面板的制作程序，降低了产品成本，同时提高了TFT-LCD面板的集成度，使面板实现窄边框和高分辨率。
发明内容
本公开提供了一种移位寄存器及其操作方法。可以消除移位寄存器输出端的噪声，提高工作的稳定性。
根据本公开的一方面，公开了一种移位寄存器，包含：
输入模块，其第一端与该移位寄存器的输入端连接用于从该输入端接收输入信号，第二端与上拉节点连接；
复位模块，其第一端与复位信号端连接，第二端与上拉节点连接，第三端与第一电源电压端连接，第四端与该移位寄存器的输出端连接；
下拉控制模块，其第一端与第一时钟信号端连接，第二端与上拉节点连接，第三端与下拉节点连接，第四端与第一电源电压端连接；
下拉模块，其第一端与下拉节点连接，第二端与该移位寄存器的输出端连接，第三端与上拉节点连接，第四端与第一电源电压端连接；
输出模块，其第一端与上拉节点连接，第二端与第二时钟信号端连接，第三端与该移位寄存器的输出端连接；以及
降噪模块，与下拉节点连接，用于通过维持下拉节点的电平来降低该移位寄存器的输出端的噪声。
根据本公开的又一方面，公开了移位寄存器的操作方法，该移位寄存器包含输入模块、复位模块、下拉控制模块、下拉模块、输出模块和降噪模块，该方法包含：
由输入模块将所接收的输入信号传递到上拉节点；
由复位模块将上拉节点处的上拉信号下拉至第一电源电压端的电源电压以及将该移位寄存器的输出端的输出信号下拉至第一电源电压端的电源电压；
由下拉控制模块控制下拉模块是否进行操作；
由下拉模块将所述移位寄存器的输出端和所述上拉节点下拉至所述第一电源电压端的电源电压；
由输出模块将第二时钟信号端的第二时钟信号输出到该移位寄存器的输出端；
由降噪模块通过维持下拉节点的电平来降低该移位寄存器的输出端的噪声。
附图说明
图1示出了传统的移位寄存器的电路图；
图2中所示的是图1中的移位寄存器在进行扫描时各信号的时序图；
图3示出了根据本公开实施例的移位寄存器的框图；
图4示出了根据本公开实施例的移位寄存器的一种示例电路结构图；
图5示出了根据本公开实施例的移位寄存器的另一种示例电路结构图；
图6示出了根据本公开实施例的移位寄存器的再一种示例电路结构图；
图7示出了图6中的移位寄存器的示例电路的操作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，仅仅是为了区分晶体管除栅极之外的两极，而将其中一极称为漏极，另一极称为源极。
图1示出了传统的移位寄存器的电路图。如图1所示，该移位寄存器100包含第一至第十晶体管M1-M10以及第一电容C1。其中，第一晶体管M1作为输入模块11，第三、第四晶体管M3-M4作为复位模块12，第五至第八晶体管M5-M8作为下拉控制模块13，第九、第十晶体管M9-M10作为下拉模块14，第二晶体管M2和第一电容C1作为输出模块15。
输入模块11的第一端与该移位寄存器的输入端INPUT连接用于从该输入端INPUT接收输入信号，第二端与上拉节点PU连接，并且该输入模块11被配置为在输入端INPUT的输入信号处于有效输入电平时，将所接收的输入信号传递到上拉节点PU。
复位模块12的第一端与复位信号端RESET连接，第二端与上拉节点PU连接，第三端与第一电源电压端VSS连接，第四端与输出端OUTPUT连接，并且该复位模块12被配置来在复位信号端RESET的复位信号处于有效控制电平时将上拉节点PU处的上拉信号下拉至第一电源电压端VSS的电源电压以及将输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。
下拉控制模块13的第一端与第一时钟信号端CLKB连接，第二端与上拉节点PU连接，第三端与下拉节点PD连接，第四端与第一电源电压端VSS连接，该下拉控制模块13被配置为控制下拉模块14是否进行操作。例如，下拉控制模块13在上拉节点PU处的上拉信号处于有效上拉电平时在下拉节 点PD处产生处于非有效下拉电平的下拉信号，而在上拉节点PU处的上拉信号处于非有效上拉电平时并且在第一时钟信号端CLKB处的第一时钟信号处于有效控制电平时在下拉节点PD处产生处于有效下拉电平的下拉信号。下拉模块14的第一端与下拉节点PD连接，第二端与输出端OUTPUT连接，第三端与上拉节点PU连接，第四端与第一电源电压端VSS连接，并且该下拉模块14被配置来在下拉节点PD处的下拉信号处于有效下拉电平时将所述输出端OUTPUT和所述上拉节点PU下拉至所述第一电源电压端VSS的电源电压。
输出模块15的第一端与上拉节点PU连接，第二端与第二时钟信号端CLK连接，第三端与该移位寄存器的输出端OUTPUT连接，并且该输出模块15被配置来在上拉节点PU处的上拉信号处于有效上拉电平时将第二时钟信号端CLK的第二时钟信号输出到输出端OUTPUT。
其中，所述第一时钟信号端CLKB的第一时钟信号与第二时钟信号端CLK的第二时钟信号反相。
其中，第一电源电压端VSS是低电源电压端。
下面以上述晶体管均为N型晶体管为例进行说明。
图2中所示的是图1中的移位寄存器在进行扫描时各信号的时序图。如图2所示，对于该传统的移位寄存器，当其处于保持阶段(即，图2中的第四阶段P4)时，上拉节点PU和输出端OUTPUT处于悬空状态，非常容易引起噪音，影响电压保持。
例如，在保持阶段，第二时钟信号端CLK的第二时钟信号由复位阶段(即，图2中的第三阶段P3)的低电平变成高电平，由于第二晶体管M2的栅源电容Cgs的存在，上拉节点PU的电压被拉高，第二晶体管M2导通，从而第二时钟信号端CLK的第二时钟信号对输出端OUTPUT进行再充电，引起输出端噪声。
针对上述问题，本公开提出一种新的移位寄存器，可以有效降低输出端噪声。
图3示出了根据本公开实施例的移位寄存器的框图。如图3所示，在一个实施例中，该移位寄存器包括输入模块31、复位模块32、下拉控制模块33、下拉模块34、输出模块35和降噪模块36。
输入模块31的第一端与该移位寄存器的输入端INPUT连接用于从该输入端INPUT接收输入信号，第二端与上拉节点PU连接，并且该输入模块31被配置为在输入端INPUT的输入信号处于有效输入电平时，将所接收的输入信号传递到上拉节点PU。
复位模块32的第一端与复位信号端RESET连接，第二端与上拉节点PU连接，第三端与第一电源电压端VSS连接，第四端与输出端OUTPUT连接，并且该复位模块32被配置来在复位信号端RESET的复位信号处于有效控制电平时将上拉节点PU处的上拉信号下拉至第一电源电压端VSS的电源电压以及将输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。
下拉控制模块33的第一端与第一时钟信号端CLKB连接，第二端与上拉节点PU连接，第三端与下拉节点PD连接，第四端与第一电源电压端VSS连接，该下拉控制模块33被配置为控制下拉模块34是否进行操作。例如，下拉控制模块33在上拉节点PU处的上拉信号处于有效上拉电平时在下拉节点PD处产生处于非有效下拉电平的下拉信号，而在上拉节点PU处的上拉信号处于非有效上拉电平时并且在第一时钟信号端CLKB处的第一时钟信号处于有效控制电平时在下拉节点PD处产生处于有效下拉电平的下拉信号。
下拉模块34的第一端与下拉节点PD连接，第二端与输出端OUTPUT连接，第三端与上拉节点PU连接，第四端与第一电源电压端VSS连接，并且该下拉模块34被配置来在下拉节点PD处的下拉信号处于有效下拉电平时将所述输出端OUTPUT和所述上拉节点PU下拉至所述第一电源电压端VSS的电源电压。
输出模块35的第一端与上拉节点PU连接，第二端与第二时钟信号端CLK连接，第三端与该移位寄存器的输出端OUTPUT连接，并且该输出模块35被配置来在上拉节点PU处的上拉信号处于有效上拉电平时将第二时钟信号端CLK的第二时钟信号输出到输出端OUTPUT。
降噪模块36与下拉节点PD连接，并且降噪模块36被配置为通过维持下拉节点的电平来降低该移位寄存器的输出端的噪声。进一步地，降噪模块36还与第一电源电压端VSS连接和/或与第二时钟信号端CLK连接。
其中，所述第一时钟信号端CLKB的第一时钟信号与第二时钟信号端CLK的第二时钟信号反相。
其中，第一电源电压端VSS是低电源电压端。
图4示出了根据本公开实施例的移位寄存器的一种示例电路结构图。下面以图4中的晶体管均为在栅极输入高电平时导通的N型晶体管为例进行说明。
如图4所示，在一个实施例中，例如，输入模块31包括输入晶体管M1，输入晶体管M1的栅极和第一极与输入端INPUT连接，输入晶体管M1的第二极与上拉节点PU连接。在输入端INPUT的输入信号处于高电平时，输入晶体管M1导通，将输入端INPUT的输入信号传递到上拉节点PU。
在一个实施例中，例如，复位模块32包括节点复位晶体管M3和输出复位晶体管M4，节点复位晶体管M3的栅极与复位信号端RESET连接，第一极与上拉节点PU连接，第二极与第一电源电压端VSS连接。输出复位晶体管M4的栅极与所述复位信号端RESET连接，第一极与所述输出端OUTPUT连接，第二极与所述第一电源电压端VSS连接。在复位信号端RESET处的复位信号处于高电平时，节点复位晶体管M3导通，将上拉节点PU处的上拉信号下拉至第一电源电压端VSS的电源电压，并且输出复位晶体管M4导通，将输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。
在一个实施例中，例如，下拉控制模块33包括第一下拉控制晶体管M5、第二下拉控制晶体管M6、第三下拉控制晶体管M7和第四下拉控制晶体管M8。第一下拉控制晶体管M5的栅极和下拉控制节点PD_CN连接，第一极与第一时钟信号端CLKB连接，第二极与下拉节点PD连接；第二下拉控制晶体管M6的栅极与上拉节点PU连接，第一极与下拉节点PD连接，第二极与第一电源电压端VSS连接；第三下拉控制晶体管M7的栅极和第一极与第一时钟信号端CLKB连接，第二极与下拉控制节点PD_CN连接；第四下拉控制晶体管M8的栅极与上拉节点PU连接，第一极与下拉控制节点PD_CN连接，第二极与第一电源电压端VSS连接。
在一个实施例中，例如，下拉模块34包括节点下拉晶体管M9和输出下拉晶体管M10，节点下拉晶体管M9和输出下拉晶体管M10的栅极与下拉节点PD连接，节点下拉晶体管M9和输出下拉晶体管M10的第二极与第一电源电压端VSS连接，节点下拉晶体管M9的第一极与上拉节点PU连接，输出下拉晶体管M10的第一极与输出端OUTPUT连接。在下拉节点PD处的 下拉信号处于高电平时，节点下拉晶体管M9和输出下拉晶体管M10导通，分别将上拉节点PU和输出端OUTPUT下拉至第一电源电压端VSS的电源电压。
在一个实施例中，例如，输出模块35包括输出晶体管M2和第一电容C1，输出晶体管M2的栅极和第一电容C1的第一端与上拉节点PU连接，输出晶体管M2的第一极与第二时钟信号端CLK连接，输出晶体管M2的第二极和第一电容C1的第二端与输出端OUTPUT连接。在上拉节点PU处的上拉信号处于高电平时，输出晶体管M2导通，将第二时钟信号端CLK的第二时钟信号输出到输出端OUTPUT。
在一个实施例中，例如，降噪模块36包括第二电容C2，第二电容C2的第一端与下拉节点PD连接，第二端与第一电源电压端VSS连接。在下拉节点PD处的下拉信号处于高电平时，第二电容C2维持该高电平，使得节点下拉晶体管M9和输出下拉晶体管M10一直导通，继续把上拉节点PU和输出端OUTPUT的电压拉低，从而降低第二时钟信号端CLK的高电平通过输出晶体管M2的栅源电容Cgs对上拉节点PU和输出端OUTPUT的电压的影响，降低上拉节点PU和输出端OUTPUT的噪声。
图5示出了根据本公开实施例的移位寄存器的另一种示例电路结构图。
如图5所示，该示例电路结构图与图4的区别仅在于降噪模块36。在一个实施例中，例如，如图5所示，降噪模块36包括第三电容C3，第三电容C3的第一端与下拉节点PD连接，第二端与第二时钟信号端CLK连接。在下拉节点PD处的下拉信号处于高电平时，第三电容C3维持该高电平，使得节点下拉晶体管M9和输出下拉晶体管M10一直导通，继续把上拉节点PU和输出端OUTPUT的电压拉低，从而降低第二时钟信号端CLK的高电平通过输出晶体管M2的栅源电容Cgs对上拉节点PU和输出端OUTPUT的电压的影响，降低上拉节点PU和输出端OUTPUT的噪声。
图6示出了根据本公开实施例的移位寄存器的再一种示例电路结构图。
如图6所示，该示例电路结构图与图4的区别仅在于降噪模块36。在一个实施例中，例如，如图6所示，降噪模块36包括第二电容C2和第三电容C3。第二电容C2的第一端与下拉节点PD连接，第二端与第一电源电压端VSS连接。第三电容C3的第一端与下拉节点PD连接，第二端与第二时钟 信号端CLK连接。在下拉节点PD处的下拉信号处于高电平时，第二电容C2和第三电容C3维持该高电平，使得节点下拉晶体管M9和输出下拉晶体管M10一直导通，继续把上拉节点PU和输出端OUTPUT的电压拉低，从而降低第二时钟信号端CLK的高电平通过输出晶体管M2的栅源电容Cgs对上拉节点PU和输出端OUTPUT的电压的影响，降低上拉节点PU和输出端OUTPUT的噪声。
图7示出了图6中的移位寄存器的示例电路的操作时序图。下面结合图6和图7对图6中的移位寄存器的操作方法进行说明。
在第一阶段1(输入阶段)，输入端INPUT处于高电平，输入晶体管T1导通，将输入端INPUT的高电平传递到上拉节点PU，此时上拉节点PU处于第一高电压，使得输出晶体管M2导通，由于第二时钟信号端CLK的第二时钟信号处于低电平，输出端OUTPUT输出低电平。此外，在该阶段中，由于上拉节点PU处于高电平，第二下拉控制晶体管M6和第四下拉控制晶体管M8导通，使得下拉节点PD处于低电平，相应地节点下拉晶体管M9和输出下拉晶体管M10均截止。此外，在该阶段中，复位信号端RESET的复位信号处于低电平，节点复位晶体管M3截止。
在第二阶段2(输出阶段)，输入端INPUT处于低电平，输入晶体管M1截止，复位信号端RESET处于低电平，节点复位晶体管M3保持截止，上拉节点PU继续使得输出晶体管M2导通，第二时钟信号端CLK的第二时钟信号处于高电平，输出端OUTPUT输出高电平，由于第一电容C1的电压耦合作用，此时上拉节点PU被从第一高电压抬升到第二高电压。此外，在该阶段中，由于上拉节点PU仍处于高电平，第二下拉控制晶体管M6和第四下拉控制晶体管M8保持导通，下拉节点PD仍处于低电平，相应地节点下拉晶体管M9和输出下拉晶体管M10均保持截止。
在第三阶段3(复位阶段)，输入端INPUT处于低电平，输入晶体管M1保持截止，复位信号端RESET的复位信号处于高电平，节点复位晶体管M3和输出复位晶体管M4导通，分别将上拉节点PU处的上拉信号和输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。此外，在该阶段中，由于上拉节点PU处于低电平，第二下拉控制晶体管M6和第四下拉控制晶体管M8均截止，由于第一时钟信号端CLKB的第一时钟信号处于 高电平，第一下拉控制晶体管M5和第三下拉控制晶体管M7均导通，使得下拉节点PD从低电平跳变至高电平，相应地节点下拉晶体管M9和输出下拉晶体管M10均导通，将上拉节点PU处的上拉信号和输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压。由于下拉节点PD处于高电平，此时对第二电容C2和第三电容C3充电。
在第四阶段4(保持阶段)，第一时钟信号端CLKB的第一时钟信号处于低电平，第一下拉控制晶体管M5和第三下拉控制晶体管M7均截止，由于上拉节点PU处于低电平，第二下拉控制晶体管M6和第四下拉控制晶体管M8均保持截止。第二电容C2和第三电容C3同时维持下拉节点PD的电压，使其保持处于高电平，相应地节点下拉晶体管M9和输出下拉晶体管M10均导通，将上拉节点PU和输出端OUTPUT保持下拉至第一电源电压端VSS的电源电压，从而降低第二时钟信号端CLK的高电平通过输出晶体管M2的栅源电容Cgs对上拉节点PU和输出端OUTPUT的电压的影响，降低上拉节点PU和输出端OUTPUT的噪声。
第一电源电压端VSS是低电源电压端。
此后，在下一帧到来之前，上拉节点PU一直处于低电平，下拉节点PD一直处于高电平，节点下拉晶体管M9和输出下拉晶体管M10一直处于导通状态，可以持续地上拉节点PU和输出端OUTPUT进行降噪，而保证输出端OUTPUT的低压信号输出的稳定性。直至下一帧到来，所述移位寄存器接收到输入端INPUT的高电平信号后，重新执行上述第一阶段。
由图7可以看出，第一时钟信号端CLKB的第一时钟信号与第二时钟信号端CLK的第二时钟信号反相。
本公开还提供了一种上述移位寄存器的操作方法。下面结合图3和图7对该方法进行说明。在一个实施例中，例如，如图3所示，移位寄存器包含输入模块31、复位模块32、下拉控制模块33、下拉模块34、输出模块35和降噪模块36。该移位寄存器的操作方法包含：
由输入模块31将所接收的输入信号传递到上拉节点PU；
由复位模块32将上拉节点PU处的上拉信号下拉至第一电源电压端VSS的电源电压以及将该移位寄存器的输出端OUTPUT的输出信号下拉至第一电源电压端VSS的电源电压；
由下拉控制模块33控制下拉模块34是否进行操作；
由下拉模块34将所述移位寄存器的输出端OUTPUT和所述上拉节点PU下拉至所述第一电源电压端VSS的电源电压；
由输出模块35将第二时钟信号端CLK的第二时钟信号输出到该移位寄存器的输出端OUTPUT；
由降噪模块36通过维持下拉节点PD的电平来降低该移位寄存器的输出端OUTPUT的噪声。
其中，第一电源电压端VSS是低电源电压端，第一时钟信号端CLKB的第一时钟信号与第二时钟信号端CLK的第二时钟信号反相。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年5月16日递交的中国专利申请第201610323870.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种移位寄存器，包含：
    输入模块，其第一端与该移位寄存器的输入端连接用于从该输入端接收输入信号，第二端与上拉节点连接；
    复位模块，其第一端与复位信号端连接，第二端与上拉节点连接，第三端与第一电源电压端连接，第四端与该移位寄存器的输出端连接；
    下拉控制模块，其第一端与第一时钟信号端连接，第二端与上拉节点连接，第三端与下拉节点连接，第四端与第一电源电压端连接；
    下拉模块，其第一端与下拉节点连接，第二端与该移位寄存器的输出端连接，第三端与上拉节点连接，第四端与第一电源电压端连接；
    输出模块，其第一端与上拉节点连接，第二端与第二时钟信号端连接，第三端与该移位寄存器的输出端连接；以及
    降噪模块，与下拉节点连接，用于通过维持下拉节点的电平来降低该移位寄存器的输出端的噪声。
  2. 根据权利要求1所述的移位寄存器，其中，输入模块包括输入晶体管，输入晶体管的栅极和第一极与输入端连接，输入晶体管的第二极与上拉节点连接。
  3. 根据权利要求1-2任一项所述的移位寄存器，其中，输出模块包括输出晶体管和第一电容，输出晶体管的栅极和第一电容的第一端与上拉节点连接，输出晶体管的第一极与第二时钟信号端连接，输出晶体管的第二极和第一电容的第二端与输出端连接。
  4. 根据权利要求1-3任一项所述的移位寄存器，其中，复位模块包括：
    节点复位晶体管，其栅极与所述复位信号端连接，第一极与上拉节点连接，第二极与第一电源电压端连接；以及
    输出复位晶体管，其栅极与所述复位信号端连接，第一极与所述输出端连接，第二极与所述第一电源电压端连接。
  5. 根据权利要求1-4任一项所述的移位寄存器，其中，下拉控制模块包括：
    第一下拉控制晶体管，其栅极和下拉控制节点连接，第一极与第一时钟 信号端连接，第二极与下拉节点连接；
    第二下拉控制晶体管，其栅极与上拉节点连接，第一极与下拉节点连接，第二极与第一电源电压端连接；
    第三下拉控制晶体管，其栅极和第一极与第一时钟信号端连接，第二极与下拉控制节点连接；以及
    第四下拉控制晶体管，其栅极与上拉节点连接，第一极与下拉控制节点连接，第二极与第一电源电压端连接。
  6. 根据权利要求1-5任一项所述的移位寄存器，其中，下拉模块包括节点下拉晶体管和输出下拉晶体管，节点下拉晶体管和输出下拉晶体管的栅极与下拉节点连接，节点下拉晶体管和输出下拉晶体管的第二极与第一电源电压端连接，节点下拉晶体管的第一极与上拉节点连接，输出下拉晶体管的第一极与输出端连接。
  7. 根据权利要求1-6任一项所述的移位寄存器，其中，降噪模块包括第二电容，其第一端与下拉节点连接，第二端与第一电源电压端连接。
  8. 根据权利要求1-6任一项所述的移位寄存器，其中，降噪模块包括第三电容，其第一端与下拉节点连接，第二端与第二时钟信号端连接。
  9. 根据权利要求1-6任一项所述的移位寄存器，其中，降噪模块包括：
    第二电容，其第一端与下拉节点连接，第二端与第一电源电压端连接；以及
    第三电容，其第一端与下拉节点连接，第二端与第二时钟信号端连接。
  10. 根据权利要求2-9中任一项所述的移位寄存器，其中，所述晶体管均为N型晶体管。
  11. 根据权利要求1-10中任一项所述的移位寄存器，其中，所述第二时钟信号端的第二时钟信号与第一时钟信号端的第一时钟信号反相。
  12. 根据权利要求1-11中任一项所述的移位寄存器，其中，第一电源电压端是低电源电压端。
  13. 一种移位寄存器的操作方法，该移位寄存器包含输入模块、复位模块、下拉控制模块、下拉模块、输出模块和降噪模块，该方法包含：
    由输入模块将所接收的输入信号传递到上拉节点；
    由复位模块将上拉节点处的上拉信号下拉至第一电源电压端的电源电压 以及将该移位寄存器的输出端的输出信号下拉至第一电源电压端的电源电压；
    由下拉控制模块控制下拉模块是否进行操作；
    由下拉模块将所述移位寄存器的输出端和所述上拉节点下拉至所述第一电源电压端的电源电压；
    由输出模块将第二时钟信号端的第二时钟信号输出到该移位寄存器的输出端；
    由降噪模块通过维持下拉节点的电平来降低该移位寄存器的输出端的噪声。
  14. 根据权利要求13所述的操作方法，其中，第一电源电压端是低电源电压端。
  15. 根据权利要求13或14所述的操作方法，其中，第二时钟信号端的第二时钟信号与第一时钟信号端的第一时钟信号反相。
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