WO2017161936A1 - 一种半导体外延晶片及其制备方法 - Google Patents

一种半导体外延晶片及其制备方法 Download PDF

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WO2017161936A1
WO2017161936A1 PCT/CN2016/111666 CN2016111666W WO2017161936A1 WO 2017161936 A1 WO2017161936 A1 WO 2017161936A1 CN 2016111666 W CN2016111666 W CN 2016111666W WO 2017161936 A1 WO2017161936 A1 WO 2017161936A1
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layer
reflective layer
substrate
epitaxial wafer
epitaxial
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English (en)
French (fr)
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张书豪
陈文志
韦静静
邱智中
张家宏
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厦门市三安光电科技有限公司
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Publication of WO2017161936A1 publication Critical patent/WO2017161936A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Definitions

  • the invention belongs to the field of semiconductors, and in particular relates to a semiconductor epitaxial wafer capable of preventing laser damage to an epitaxial wafer and a preparation method thereof by using a laser to form a burst point from a lower surface of the substrate.
  • the conventional process of LED is as follows: epitaxial layer is grown on a substrate by epitaxial process, then N-electrode and P-electrode are formed by chip process to form a wafer, and finally the wafer is separated into a plurality of crystal grains by laser cutting technology and splitting technology.
  • a laser beam of a translucent wavelength enters from the lower surface of the substrate and is focused inside the substrate to form a burst point.
  • part of the laser is from a plurality of lasers. The direction escapes and is incident on the upper surface of the substrate. Since the explosion point is closer to the epitaxial layer during the stealth cutting, the laser portion is likely to cause burns on the epitaxial layer, thereby affecting the photoelectric performance of the LED.
  • the invention provides a semiconductor epitaxial wafer and a preparation method thereof, wherein a first reflective layer is disposed between a substrate and an epitaxial layer, and when a laser is used to scan a lower surface of the substrate to form a burst point, the first reflective layer reflects and escapes The laser light is incident on the upper surface of the substrate to prevent the laser from burning the epitaxial layer.
  • a semiconductor epitaxial wafer comprising a substrate, a first reflective layer and an epitaxial layer stacked in sequence, wherein the first reflective layer reflects and escapes when a laser is used to scan a lower surface of the substrate to form a burst point And a laser that strikes the upper surface of the substrate.
  • the first reflective layer is a patterned structure composed of a series of equal-sized cells, each cell being equally spaced.
  • the first reflective layer has a reflectance of 80% or more with respect to infrared rays having a wavelength of 1000 to 1300 nm incident from the substrate side.
  • the material of the first reflective layer is SiO 2 and TiO 2 , and the SiO 2 and TiO 2 are periodically alternately laminated to form the first reflective layer by adjusting the SiO 2 layer and the TiO 2 layer.
  • the thickness and the number of cycles are adjusted so that the reflectance of the first reflective layer to infrared rays having a wavelength of 1000 to 1300 nm incident from the substrate side is 80% or more.
  • the thickness of the first reflective layer ranges from 2 to 6 ⁇ m
  • the thickness of the SiO 2 layer in the first reflective layer ranges from 0.1 to 0.3 ⁇ m
  • the thickness of the TiO 2 layer ranges from 0.1 to 0.3 ⁇ m.
  • the number is 10 to 50.
  • the first reflective layer is a single layer or a multilayer film structure, which may be one of a metal film layer, a transparent conductive film layer, a dielectric multilayer film layer or a metal dielectric composite film layer, and may be evaporated. It is produced by a method, a sputtering method, a chemical vapor deposition method, a spray coating method, a vacuum adsorption method or a dipping method.
  • a second reflective layer is further interposed between the first reflective layer and the epitaxial layer, and the second reflective layer reflects light incident from a side of the epitaxial layer when the epitaxial wafer injects current to emit light.
  • the second reflective layer has a reflectance of 90% or more for light incident from the side of the epitaxial layer.
  • the material of the second reflective layer is SiO 2 and Ti 3 O 5 , and the SiO 2 and Ti 3 O 5 are periodically alternately laminated to form the second reflective layer, by adjusting the SiO 2 layer and The thickness of the Ti 3 O 5 layer and the number of cycles adjust the reflectance of the second reflective layer to light incident from the side of the epitaxial layer by 90% or more.
  • the thickness of the second reflective layer ranges from 1 to 3 ⁇ m
  • the thickness of the SiO 2 layer in the second reflective layer ranges from 0.1 to 0.3 ⁇ m
  • the thickness of the Ti 3 O 5 layer ranges from 0.1 to 0.3 ⁇ m.
  • the number of cycles is 20 to 50.
  • the epitaxial layer comprises an AlN buffer layer, an N-type layer, a light-emitting layer and a P-type layer which are sequentially stacked.
  • the present invention further provides a method for fabricating a semiconductor epitaxial wafer, comprising the steps of: providing a substrate; growing an epitaxial layer on the substrate; wherein: before the depositing step of the epitaxial layer Also included is a deposition step of the first reflective layer that reflects the laser light that escapes and strikes the upper surface of the substrate when a laser is used to sweep from the lower surface of the substrate to form a burst.
  • a deposition step of inserting a second reflective layer between the deposition step of the first reflective layer and the epitaxial layer is performed, and when the epitaxial wafer injects current to emit light, the second reflective layer reflects from the side of the epitaxial layer Incident light.
  • the epitaxial layer is formed by: firstly depositing an AlN buffer layer by a PVD method, The N-type layer, the light-emitting layer, and the epitaxial layer are sequentially stacked on the AlN buffer layer by MOCVD.
  • the semiconductor epitaxial wafer uses a laser to scan from the lower surface of the substrate to form a burst point, thereby dividing the semiconductor epitaxial wafer into a plurality of independent units, and when the laser is used to form a burst point. It escapes and strikes the upper surface of the substrate, causing burns to the epitaxial layer deposited on the substrate.
  • the first reflective layer reflects the laser light incident on the epitaxial layer, thereby preventing the laser from burning the epitaxial layer.
  • the present invention also adds a second reflective layer over the first reflective layer.
  • the semiconductor epitaxial wafer injects a current, the second reflective layer reflects the light incident from the side of the epitaxial layer, thereby preventing the portion of the light from entering the substrate. Inside, the loss of light in this part is reduced.
  • FIG. 1 is a schematic side view showing the structure of a semiconductor epitaxial wafer according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic side view showing the structure of a first reflective layer according to Embodiment 1 of the present invention.
  • FIG 3 is a side view showing the structure of a substrate and a first reflective layer according to Embodiment 1 of the present invention.
  • FIG. 4 is a flow chart showing the preparation of a semiconductor epitaxial wafer according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic side view showing the structure of a semiconductor epitaxial wafer according to Embodiment 2 of the present invention.
  • FIG. 6 is a schematic side view showing the structure of a second reflective layer according to Embodiment 2 of the present invention.
  • FIG. 7 is a flow chart of preparing a semiconductor epitaxial wafer according to Embodiment 2 of the present invention.
  • the drawing is labeled: 10. substrate; 11: protrusion; 20. first reflective layer; 21. SiO 2 layer; 22. TiO 2 layer; 30. epitaxial layer; 31. buffer layer; 32. N-type layer; . luminescent layer; 34. P-type layer; 40. second reflective layer; 41. SiO 2 layer; 42. Ti 3 O 5 layer.
  • the present invention provides a semiconductor epitaxial wafer comprising a substrate 10 and a first reflective layer 20 which are sequentially stacked. And an epitaxial layer 30, wherein when a laser is used to sweep from the lower surface of the substrate 10 to form a blast point, the first reflective layer 20 reflects the laser light that escapes and is incident on the upper surface of the substrate 10.
  • the laser light source is infrared light
  • the reflectance of the first reflective layer 20 to infrared rays having a wavelength of 1000 to 1300 nm incident from the substrate 10 side is 80% or more.
  • the first reflective layer 20 may be a single layer or a multilayer film structure, and one of a metal film layer, a transparent conductive film layer, a dielectric multilayer film layer, or a metal dielectric composite film layer may be selected.
  • the material of the first reflective layer 20 is SiO 2 and TiO 2 , and SiO 2 and TiO 2 are periodically alternately laminated; by adjusting the thickness and cycle of the SiO 2 layer 21 and the TiO 2 layer 22 The number further adjusts the reflectance of the infrared rays of the first reflective layer 20.
  • the thickness of the first reflective layer ranges from 2 to 6 ⁇ m, wherein the thickness of the SiO 2 layer ranges from 0.1 to 0.3 ⁇ m, the thickness of the TiO 2 layer ranges from 0.1 to 0.3 ⁇ m, and the number of cycles is from 10 to 50.
  • the reflectance of infrared rays having a wavelength of 1000 to 1300 nm can be made 80% or more.
  • a first reflective layer 20 of a Ta 2 O 5 /SiO 2 multilayer film structure or a ZnS/SiO 2 multilayer film structure may also be selected, and the first reflection is achieved by adjusting the thickness of the film layer and the number of cycles Layer 20 reflects the purpose of the laser.
  • the substrate 10 is a patterned structure or a flat sheet structure. In order to improve the light emission of the substrate 10, the present embodiment preferably patterns the substrate.
  • the epitaxial layer 30 includes an AlN buffer layer 31, an N-type layer 32, a light-emitting layer 33, and a P-type layer 34 which are sequentially stacked.
  • the first reflective layer 20 is a patterned structure consisting of a series of equally large cells, each cell being equally spaced.
  • the substrate 10 is a patterned substrate, the surface of which is periodically distributed with regularly arranged protrusions 11 , and the first reflective layer 20 is deposited on the surface of the substrate 10 between adjacent protrusions 11 .
  • the side surface portion of the bump 11 is exposed to expose the first reflective layer 20 to a patterned structure. Since the patterned first reflective layer 20 deposits only the gap surface with the adjacent bumps 11 to expose the side surface portion of the bump 11, the crystal of the bump 11 is compared to the amorphous state of the first reflective layer 21.
  • the body state and the epitaxial layer crystal state and the lattice constant are closer, so that the subsequent epitaxial layer is preferably deposited on the side surface of the protrusion 11, thereby better solving the problem that the surface of the substrate 10 is completely covered by the first reflective layer 20, so that the subsequent epitaxial layer cannot be The problem of sedimentation.
  • the present invention also provides a manufacturing method, and the manufacturing steps are as follows:
  • a substrate 10 is provided; the substrate 10 has opposite upper and lower surfaces; the substrate 10 is a transparent substrate, and the sapphire lining is preferred in this embodiment due to the advantages of low price, easy availability, and good stability of the sapphire material.
  • the substrate 10 is a flat substrate or a patterned substrate. Since the patterned substrate can improve the light extraction rate of the semiconductor device, the present embodiment preferably forms a patterned sapphire substrate.
  • the step of depositing the patterned first reflective layer 20 is: S21, applying a photoresist on the substrate 10; S22, exposing the substrate 10 between adjacent bumps 11 of the substrate 10 by photolithography and development processes a surface; S23, depositing the first reflective layer 20 by physical deposition; S24, removing the photoresist, exposing the side surface of the bump 11.
  • the epitaxial layer 30 is grown on the first reflective layer 20; the epitaxial layer 30 is grown by the following steps: first, the AlN buffer layer 31 is deposited by a PVD method, and then the N-type layer is sequentially stacked on the AlN buffer layer 31 by MOCVD. 32. A light-emitting layer 33 and a p-type layer 34.
  • the materials of the N-type layer 32 and the P-type layer 34 may be selected from materials such as GaN, GaP or GaAs depending on the color of the LED light.
  • the semiconductor epitaxial wafer further inserts a second reflective layer 40 between the first reflective layer 20 and the epitaxial layer 30, and the current is injected into the epitaxial wafer.
  • the second reflective layer 40 reflects light incident from the side of the epitaxial layer 30.
  • the reflectance of the second reflective layer 40 to the light incident from the epitaxial layer 30 side is 90% or more.
  • the material of the second reflective layer is SiO 2 and Ti 3 O 5 , wherein SiO 2 and Ti 3 O 5 are periodically alternately laminated to form a second reflective layer 40, and the SiO 2 layer 41 and Ti 3 O are adjusted.
  • the thickness of the fifth layer 42 and the number of cycles are adjusted so that the reflectance of the second reflective layer 40 to the light incident from the side of the epitaxial layer 30 is 90% or more.
  • the second reflective layer 40 has a thickness in the range of 1 to 3 ⁇ m, wherein the SiO 2 layer 41 has a thickness in the range of 0.1 to 0.3 ⁇ m, the Ti 3 O 5 layer 42 has a thickness in the range of 0.1 to 0.3 ⁇ m, and the number of cycles is 20 to 50.
  • the epitaxial layer 30 is grown on the second reflective layer 40.
  • the first reflective layer 20 is preferably patterned, and the second reflective layer 40 is also preferably patterned. Both patterned structures are fabricated by photolithography.
  • the second reflective layer 40 reflects the light incident from the side of the epitaxial layer 30 and has a reflectance of 90% or more, thereby preventing a portion of the light incident from the side of the epitaxial layer 30 from entering the substrate 10, Extend the light propagation path, causing light attenuation and loss.

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Abstract

一种半导体外延晶片及其制备方法，通过在蓝宝石衬底（10）和外延层（30）之间增设一第一反射层（20），当采用激光从衬底（10）下表面进行扫射形成爆点时，第一反射层（20）反射逸出并射向衬底（10）上表面的激光，从而防止采用激光对外延晶片分割时，激光对外延片的灼伤。

Description

一种半导体外延晶片及其制备方法 技术领域
本发明属于半导体领域，尤其涉及一种当采用激光从衬底下表面扫射形成爆点，可防止激光对外延晶片灼伤的半导体外延晶片及其制备方法。
背景技术
LED的常规制程为：在一衬底上采用外延工艺生长外延层，然后采用芯片工艺制备N电极和P电极形成晶片，最后采用激光切割技术和裂片技术将晶片分离形成复数个晶粒。
采用激光切割晶片时，尤其是采用隐形切割技术，即将半透明波长的激光束从衬底的下表面进入并聚焦在衬底内部扫射形成爆点，当激光聚焦形成爆点时，部分激光从多个方向逸出并射入衬底上表面，由于隐形切割时爆点距离外延层较近，该部分激光容易对外延层造成灼伤，进而影响LED的光电性能。
技术问题
问题的解决方案
技术解决方案
本发明提供一种半导体外延晶片及其制备方法，通过在衬底和外延层之间设置第一反射层，当采用激光从衬底的下表面扫射形成爆点时，第一反射层反射逸出并射入衬底上表面的激光，从而防止激光对外延层的灼伤。
具体技术方案如下：
一种半导体外延晶片，包括依次堆叠的衬底、第一反射层和外延层，其特征在于：当采用激光从所述衬底下表面进行扫射形成爆点时，所述第一反射层反射逸出并射向衬底上表面的激光。
优选的，所述第一反射层为图案化结构，其由一系列等大的单元构成，每个单元等间距分布。
优选的，所述第一反射层对从所述衬底一侧入射的波长为1000～1300nm的红外线的反射率为80％以上。
优选的，所述第一反射层的材料为SiO2和TiO2，所述SiO2和TiO2周期性循环交替层叠形成所述第一反射层，通过调节所述SiO2层和TiO2层的厚度和循环周期数调节所述第一反射层对从所述衬底一侧入射的波长为1000～1300nm的红外线的反射率为80％以上。
优选的，所述第一反射层的厚度范围为2～6μm，所述第一反射层中SiO2层的厚度范围为0.1～0.3μm，TiO2层的厚度范围为0.1～0.3μm，循环周期数为10～50。
优选的，所述第一反射层为单层或多层膜结构，其可为金属膜层、透明导电膜层、电介质多层膜层或金属电介质复合膜层中的一种，可采用蒸镀法、溅射法、化学气相沉积法、喷涂法、真空吸附法或浸渍法制成。
优选的，所述第一反射层和外延层之间还***一第二反射层，当所述外延晶片注入电流发光时，所述第二反射层反射从外延层一侧入射的光线。
优选的，所述第二反射层对从所述外延层一侧入射的光线的反射率为90％以上。
优选的，所述第二反射层的材料为SiO2和Ti3O5，所述SiO2和Ti3O5周期性循环交替层叠形成所述第二反射层，通过调节所述SiO2层和Ti3O5层的厚度和循环周期数调节所述第二反射层对从所述外延层一侧入射的光线的反射率为90％以上。
优选的，所述第二反射层的厚度范围为1～3μm，所述第二反射层中SiO2层的厚度范围为0.1～0.3μm，Ti3O5层的厚度范围为0.1～0.3μm，循环周期数为20～50。
优选的，所述外延层包括依次层叠的AlN缓冲层、N型层、发光层和P型层。
为制备上述的半导体外延晶片，本发明还提供一种半导体外延晶片的制作方法，包括步骤2提供一衬底；于所述衬底上生长外延层；其中：于所述外延层的沉积步骤之前还包括第一反射层的沉积步骤，当采用激光从所述衬底下表面进行扫射形成爆点时，所述第一反射层反射逸出并射向衬底上表面的激光。
优选的，于所述第一反射层和外延层的沉积步骤之间还***第二反射层的沉积步骤，当所述外延晶片注入电流发光时，所述第二反射层反射从外延层一侧入射的光线。
优选的，所述外延层通过下面步骤形成：首先采用PVD法沉积AlN缓冲层，其 次采用MOCVD法于所述AlN缓冲层依次层叠N型层、发光层和外延层。
发明的有益效果
有益效果
本发明至少具有以下有益效果：现有技术中，半导体外延晶片采用激光从衬底下表面扫射形成爆点，进而将半导体外延晶片分割成多个独立的单元，而采用激光分割时，形成爆点时逸出并射入衬底上表面，从而对沉积于衬底之上的外延层造成灼伤。本发明中通过在衬底和外延层之间增加一第一反射层，第一反射层反射射入外延层的激光，从而防止激光对外延层的灼伤。同时，本发明还在第一反射层之上增加第二反射层，当半导体外延晶片注入电流时，第二反射层反射从外延层一侧射入的光线，从而防止该部分光线射入衬底内，减少了该部分光线的损失。
对附图的简要说明
附图说明
图1为本发明实施例一之半导体外延晶片侧视结构示意图。
图2为本发明实施例一之第一反射层侧视结构示意图。
图3为本发明实施例一之衬底和第一反射层侧视结构示意图。
图4为本发明实施例一之半导体外延晶片的制备流程图。
图5为本发明实施例二之半导体外延晶片侧视结构示意图。
图6为本发明实施例二之第二反射层侧视结构示意图。
图7为本发明实施例二之半导体外延晶片的制备流程图。
附图标注：10.衬底；11：凸起；20.第一反射层；21.SiO2层；22.TiO2层；30.外延层；31.缓冲层；32.N型层；33.发光层；34.P型层；40.第二反射层；41.SiO2层；42.Ti3O5层。
发明实施例
本发明的实施方式
下面将结合示意图对发明进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的 有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
参看附图1和图2，为解决采用激光对半导体外延晶片分割时，激光对外延层的灼伤，本发明提供了一种半导体外延晶片，其包括依次堆叠的衬底10、第一反射层20和外延层30，其中，当采用激光从衬底10下表面进行扫射形成爆点时，第一反射层20反射逸出并射向衬底10上表面的激光。当该激光源为红外线时，第一反射层20对从衬底10一侧入射的波长为1000～1300nm的红外线的反射率为80％以上。第一反射层20可为单层或多层膜结构，其可选用金属膜层、透明导电膜层、电介质多层膜层或金属电介质复合膜层中的一种。本实施例中，优选第一反射层20的材料为SiO2和TiO2，并且SiO2和TiO2周期性循环交替层叠；通过调节所述SiO2层21和TiO2层22的厚度和循环周期数进而调节第一反射层20红外线的反射率。通过软件模拟，当第一反射层的厚度范围为2～6μm，其中SiO2层的厚度范围为0.1～0.3μm，TiO2层的厚度范围为0.1～0.3μm，循环周期数为10～50时，可实现对波长为1000～1300nm的红外线的反射率达80％以上。在其他实施例中，也可选用Ta2O5/SiO2多层膜结构或ZnS/SiO2多层膜结构的第一反射层20，并通过调节膜层厚度以及循环周期数实现第一反射层20反射激光的目的。衬底10为图案化结构或平片结构，为提高衬底10的出光，本实施例优选图案化衬底。外延层30包括依次层叠的AlN缓冲层31、N型层32、发光层33和P型层34。
参看附图3，第一反射层20为图案化结构，其由一系列等大的单元构成，每个单元等间距分布。在其一变形实施例中，衬底10为图案化衬底，其表面周期性分布有规则排列的凸起11，第一反射层20沉积于相邻凸起11之间的衬底10表面，而裸露出凸起11侧表面部分，使第一反射层20呈现出图案化结构。由于图案化的第一反射层20仅沉积与相邻凸起11的间隙面，而裸露出凸起11的侧表面部分，相比于第一反射层21的非晶体态，凸起11的晶体态与外延层晶体态及晶格常数更为接近，故后续外延层优选沉积于凸起11的侧表面，从而较好的解决了衬底10表面全覆盖第一反射层20导致后续外延层无法沉积的难题。
参看附图4，为制备上述的半导体外延晶片，本发明还提供一种制作方法，制作步骤如下：
S1、提供一衬底10；衬底10具有相对的上表面和下表面；衬底10为透明衬底，而由于蓝宝石材料价格低、易获得、稳定性好等优点，本实施例优选蓝宝石衬底；衬底10为平片衬底或图形化衬底，由于图形化衬底可以提高半导体元件的出光率，本实施例优选图形化蓝宝石衬底。
S2、于衬底10上沉积第一反射层20；当采用激光从衬底10下表面进行扫射形成爆点时，第一反射层20反射逸出并射向衬底10上表面的激光。
图案化第一反射层20的沉积步骤为：S21、于衬底10上涂覆光刻胶；S22、采用光刻和显影工艺裸露出衬底10的相邻凸起11之间的衬底10表面；S23、采用物理沉积法沉积第一反射层20；S24、去除光刻胶，裸露出凸起11的侧表面。
S3、于第一反射层20上生长外延层30；外延层30的采用下面的步骤生长：首先采用PVD法沉积AlN缓冲层31，其次采用MOCVD法于所述AlN缓冲层31依次层叠N型层32、发光层33和P型层34。N型层32和P型层34的材料可根据LED发光颜色的不同选用GaN、GaP或GaAs等材料。
实施例2
参看附图5和图6，本实施例与实施例1的区别在于，所述半导体外延晶片在第一反射层20和外延层30之间还***一第二反射层40，当外延晶片注入电流发光时，第二反射层40反射从外延层30一侧入射的光线。第二反射层40对从外延层30一侧入射的光线的反射率为90％以上。本实施例中，第二反射层的材料选用SiO2和Ti3O5，其中SiO2和Ti3O5周期性循环交替层叠形成第二反射层40，通过调节SiO2层41和Ti3O5层42的厚度和循环周期数调节第二反射层40对从外延层30一侧入射的光线的反射率为90％以上。第二反射层40的厚度范围为1～3μm，其中SiO2层41的厚度范围为0.1～0.3μm，Ti3O5层42的厚度范围为0.1～0.3μm，循环周期数为20～50。
参看附图7，为制备上述的半导体外延晶片，本发明提供的一种制备方法步骤如下：
S1’、提供一衬底10；
S2’、于衬底10上沉积第一反射层20；
S3’、于第一反射层20上沉积第二反射层40；
S4’、于第二反射层40上生长外延层30。
其中，第一反射层20优选图案化结构，第二反射层40也优选图案化结构，两者的图案化结构均采用光刻工艺制作。当外延晶片注入电流发光时，第二反射层40反射从外延层30一侧入射的光线，且反射率达90％以上，从而防止从外延层30一侧入射的部分光线进入衬底10内，延长光传播路径，造成光衰减和损失。

Claims (11)

  1. 一种半导体外延晶片，包括依次堆叠的衬底、第一反射层和外延层，其特征在于：当采用激光从所述衬底下表面进行扫射形成爆点时，所述第一反射层反射逸出并射向衬底上表面的激光。
  2. 根据权利要求1所述的一种半导体外延晶片，其特征在于：所述第一反射层为图案化结构，其由一系列等大的单元构成，每个单元等间距分布。
  3. 根据权利要求1所述的一种半导体外延晶片，其特征在于：所述第一反射层对从所述衬底一侧入射的波长为1000～1300nm的红外线的反射率为80％以上。
  4. 根据权利要求3所述的一种半导体外延晶片，其特征在于：所述第一反射层的材料为SiO2和TiO2，所述SiO2和TiO2周期性循环交替层叠形成所述第一反射层，通过调节所述SiO2层和TiO2层的厚度和循环周期数调节所述第一反射层对从所述衬底一侧入射的波长为1000～1300nm的红外线的反射率为80％以上。
  5. 根据权利要求1所述的一种半导体外延晶片，其特征在于：所述第一反射层和外延层之间还***一第二反射层，当所述外延晶片注入电流发光时，所述第二反射层反射从外延层一侧入射的光线。
  6. 根据权利要求5所述的一种半导体外延晶片，其特征在于：所述第二反射层对从所述外延层一侧入射的光线的反射率为90％以上。
  7. 根据权利要求6所述的一种半导体外延晶片，其特征在于：所述第二反射层的材料为SiO2和Ti3O5，所述SiO2和Ti3O5周期性循环交替层叠形成所述第二反射层，通过调节所述SiO2层和Ti3O5层的厚度和循环周期数调节所述第二反射层对从所述外延层一侧入射的光线的反射率为90％以上。
  8. 根据权利要求1所述的一种半导体外延晶片，其特征在于：所述外延层包括依次层叠的AlN缓冲层、N型层、发光层和P型层。
  9. 一种半导体外延晶片的制作方法，用于制作权利要求1～8中的半导 体外延晶片，制作方法如下：
    提供一衬底；
    于所述衬底上生长外延层；
    其特征在于：于所述外延层的沉积步骤之前还包括第一反射层的沉积步骤，当采用激光从所述衬底下表面进行扫射形成爆点时，所述第一反射层反射逸出并射向衬底上表面的激光。
  10. 根据权利要求1所述的一种半导体外延晶片的制作方法，其特征在于：于所述第一反射层和外延层的沉积步骤之间还***第二反射层的沉积步骤，当所述外延晶片注入电流发光时，所述第二反射层反射从外延层一侧入射的光线。
  11. 根据权利要求1所述的一种半导体外延晶片的制作方法，其特征在于：所述外延层通过下面步骤形成：首先采用PVD法沉积AlN缓冲层，其次采用MOCVD法于所述AlN缓冲层依次层叠N型层、发光层和P型层。
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