WO2017152553A1 - 栅极驱动电路及其检测方法、阵列基板、显示装置 - Google Patents
栅极驱动电路及其检测方法、阵列基板、显示装置 Download PDFInfo
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- WO2017152553A1 WO2017152553A1 PCT/CN2016/088080 CN2016088080W WO2017152553A1 WO 2017152553 A1 WO2017152553 A1 WO 2017152553A1 CN 2016088080 W CN2016088080 W CN 2016088080W WO 2017152553 A1 WO2017152553 A1 WO 2017152553A1
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Definitions
- the present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a detecting method thereof, an array substrate, and a display device.
- the Gate Driver On Array (GOA) technology is a technology for integrating a liquid crystal display gate driver integrated circuit (Gate Driver Integrated Circuit) on an array (Array) substrate.
- the GOA circuit has a plurality of cascaded GOA units, each of which constitutes a shift register, and the input signal of the GOA unit of the present stage is the output signal of the GOA unit of the previous stage, and the output signal of the GOA unit of the current stage is The reset signal of the first-level GOA unit, the output signals of the GOA units of each stage are sequentially high level, and the progressive scanning of the liquid crystal panel is realized.
- the GOA units of each level are usually connected to the oscilloscope in turn, and whether the GOA units of each level have defects according to whether the waveform of the output signals of the GOA units of each level displayed by the oscilloscope is normal. Therefore, at least the following problems exist: the GOA units of each stage are sequentially connected to the oscilloscope, the operation is troublesome, and the detection efficiency is low.
- Embodiments of the present invention provide a gate driving circuit and a detecting method thereof, an array substrate, and a display device.
- a gate driving circuit including a plurality of cascaded gate driving units, an access unit, a first signal line, and a second signal line, each of the access units is provided Connecting to the corresponding gate driving unit and the corresponding gate driving unit of the next stage of the gate driving unit, wherein the access unit corresponding to the gate driving unit of the odd-numbered stage is The first signal line Connecting the first signal line to detect an output signal of the odd-numbered stage of the gate driving unit by the access unit, and the access unit and the second signal corresponding to the gate driving unit of an even-numbered stage The lines are connected such that the second signal line detects an output signal of the even-numbered stages of the gate driving unit through the access unit.
- the access unit corresponding to the gate driving unit of the odd-numbered stage is configured to: according to an output signal of the corresponding gate driving unit, and the corresponding one of the next stage of the gate driving unit An output signal of the gate driving unit is configured to conduct an output end of the corresponding gate driving unit with the first signal line; an access unit corresponding to the even-numbered gate driving unit is used according to the corresponding An output signal of the gate driving unit and an output signal of the gate driving unit of a corresponding stage of the gate driving unit, and an output end of the corresponding gate driving unit and the first The two signal lines are turned on.
- the access unit includes a first transistor and a second transistor, a gate of the first transistor, a first end of the first transistor, and a first end of the second transistor respectively An output end of the gate driving unit corresponding to the access unit is connected, and a gate of the second transistor and an output of the gate driving unit of a next stage of the gate driving unit corresponding to the access unit End connection, the second end of the first transistor and the second end of the second transistor are respectively connected to the first signal line, or the second end of the first transistor and the second transistor The two ends are respectively connected to the second signal line.
- the gate driving unit includes a plurality of transistors, and leads connecting the plurality of transistors, the access unit is simultaneously fabricated with the plurality of transistors, the first signal line and the second The signal lines are all fabricated simultaneously with the leads.
- the access unit, the first signal line and the second signal line are both disposed at an output end of the gate driving unit.
- one end of the first signal line and one end of the second signal line are each provided with a test terminal, and the test terminal is used for connecting with an oscilloscope.
- the first signal line is provided with one end of the test terminal and the second signal line is provided with one end of the test terminal on the same side of the gate driving circuit.
- an array substrate is provided, the array substrate including the above-described gate driving circuit.
- a display device including the above array substrate is provided.
- a method for detecting a gate driving circuit including:
- Determining the defective gate driving unit according to the change of the high and low levels in the output signal of the first signal line and the output signal of the second signal line.
- an output signal of an odd-numbered gate driving unit is detected by a first signal line, and an output signal of an even-numbered gate driving unit is detected by the second signal line, thereby outputting signals of the gate driving units of each stage It is connected to the first signal line and the second signal line. Therefore, it is only necessary to connect the first signal line and the second signal line to the oscilloscope respectively to determine whether there is a defect in the gate driving unit of each stage, the operation is simple and convenient, and the detection efficiency is greatly improved.
- FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
- FIG. 2 is a schematic diagram of an example of a gate driving circuit according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of a gate driving unit according to an embodiment of the present invention.
- FIG. 4 is a timing diagram of signals in a gate driving unit according to an embodiment of the present invention.
- FIG. 5a is a timing diagram of normal and abnormal pull-up node signals according to an embodiment of the present invention.
- FIG. 5b is a timing diagram of normal and abnormal output signals according to an embodiment of the present invention.
- 6a is a timing diagram of normal first signal lines and second signal line signals according to an embodiment of the present invention.
- 6b is a timing diagram of an abnormal first signal line and a second signal line signal according to an embodiment of the present invention.
- FIG. 7 is a flowchart of a method for detecting a gate driving circuit according to an embodiment of the present invention.
- Embodiments of the present invention provide a gate driving circuit.
- the gate driving circuit includes multiple The cascaded gate drive unit 1 (only three of FIG. 1 are taken as an example), the access unit 2, the first signal line 3, and the second signal line 4.
- Each access unit 2 is respectively connected to a gate drive unit 1 of a corresponding stage of the corresponding gate drive unit 1 and a corresponding gate drive unit 1, wherein the access unit corresponding to the gate drive unit 1 of the odd-numbered stage 2 is connected to the first signal line 3 so that the first signal line 3 detects the output signal of the odd-numbered gate driving unit 1 through the access unit 2; the access unit 2 and the second signal corresponding to the even-numbered gate driving unit 1
- the line 4 is connected so that the second signal line 4 detects the output signal of the even-numbered gate drive unit 1 through the access unit 2.
- the output signal of the odd-numbered gate driving unit is detected by the first signal line, and the output signal of the even-numbered gate driving unit is detected by the second signal line, thereby outputting the output signals of the gate driving units of the respective stages. It is connected to the first signal line and the second signal line. Therefore, it is only necessary to connect the first signal line and the second signal line to the oscilloscope when detecting, respectively, to determine whether the gate driving units of each stage have defects.
- FIG. 2 is a schematic diagram of an example of a gate driving circuit according to an embodiment of the present invention.
- the gate driving circuit includes a plurality of cascaded gate driving units 1 (only three of FIG. 2 are taken as an example), an access unit 2, a first signal line 3, and a second signal line 4.
- Each access unit 2 is respectively connected to a gate drive unit 1 of a corresponding stage of the corresponding gate drive unit 1, the corresponding gate drive unit 1, and an access unit 2 corresponding to the odd-numbered gate drive unit 1 and
- the first signal line 3 is connected such that the first signal line 3 detects the output signal of the odd-numbered gate driving unit 1 through the access unit 2, and the access unit 2 and the second signal line 4 corresponding to the even-numbered gate driving unit 1 Connected so that the second signal line 4 detects the output signal of the even-numbered gate drive unit 1 through the access unit 2.
- a corresponding signal is input to the gate driving unit, including the input signal IN, the forward clock signal CLK, The clock signal CLKB, the reset signal RESET, and the low voltage signal VSS are inverted to cause the gate driving unit to be in an operating state (ie, a lighting state).
- the access unit 2, the first signal line 3, and the second signal line 4 may be disposed at an output end of the gate driving unit 1 to facilitate wiring.
- the access unit 2, the first signal line 3, and the second signal line 4 may be located between the gate driving unit 1 and the display area of the array substrate, and the first signal line and the second signal line are both from the display device.
- One side of the screen extends to the other side.
- one end of the first signal line 3 and one end of the second signal line 4 may be provided with a test terminal for connecting with an oscilloscope.
- the gate driving circuit is usually packaged inside the display device, and the test terminal can be connected to the first signal line and the second signal line for detecting without destroying the display device, thereby avoiding damage to the display device.
- the damage gate driving unit does not affect the normal operation of the display device, saves manpower and material resources, and improves the efficiency and accuracy of the test.
- the first signal line 3 is provided with one end of the test terminal and the second signal line 4 is provided with one end of the test terminal on the same side of the gate drive circuit, so as to conveniently connect the oscilloscope with the first signal line 3 and The two signal lines 4 are connected for detection.
- the test pad is placed on the side of the data pad.
- the data terminal is used to connect a data signal external to the display device to the inside of the display device to control the content displayed by the display device.
- the test terminal and the data terminal are disposed together outside the package of the display device to acquire an electrical signal into the display device without damaging the package of the display device.
- the test terminal and the data terminal are disposed outside the frame seal of the liquid crystal cell, so that the probe of the oscilloscope can be connected to the test terminal without damaging the liquid crystal cell, thereby detecting whether the gate drive unit has a defect.
- the access unit 2 corresponding to the odd-numbered gate driving unit 1 is used according to the output signal of the corresponding gate driving unit 1 and the corresponding gate driving unit 1
- the output signal of the gate driving unit 1 of the next stage turns on the output end of the corresponding gate driving unit 1 and the first signal line 3;
- the access unit 2 corresponding to the even-numbered gate driving unit 1 is used for Outputting the output terminal of the corresponding gate driving unit 1 and the second signal line according to the output signal of the corresponding gate driving unit 1 and the output signal of the gate driving unit 1 of the corresponding stage of the corresponding gate driving unit 1 4 conduction.
- the access unit 2 may include a first transistor M1 and a second transistor M2.
- the gate of the first transistor M1, the first end of the first transistor M1, and the first end of the second transistor M2 are respectively connected to the access unit. 2, the output terminal of the corresponding gate driving unit 1 is connected, the gate of the second transistor M2 is connected to the output end of the gate driving unit 1 of the gate driving unit 1 corresponding to the access unit 2, and the first transistor M1
- the second end of the second transistor M2 and the second end of the second transistor M2 are respectively connected to the first signal line 3, or the second end of the first transistor M1 and the second end of the second transistor M2 are respectively connected to the second signal line 4.
- the gate driving unit 1 corresponding to the access unit 2 is the odd-numbered gate driving unit 1
- the second end of the first transistor M1 and the second end of the second transistor M2 are respectively connected to the first signal line 3 Connection
- the gate driving unit 1 corresponding to the access unit 2 is the even-numbered gate driving unit 1
- the second end of the first transistor M1 and the second end of the second transistor M2 are respectively connected to the second signal line 4.
- the first end is a drain and the second end is a source.
- the first transistor M1 and the second transistor M2 may both be N-type transistors or P-type transistors to accommodate different circuit requirements.
- the access unit 2 corresponding to the odd-numbered gate driving unit 1 is used to pass the first when the corresponding gate driving unit 1 outputs a high level.
- the transistor M1 turns on the output end of the corresponding gate driving unit 1 and the first signal line 3, and passes through the second transistor when the gate driving unit 1 of the lower stage of the corresponding gate driving unit 1 outputs a high level.
- M2 turns on the output end of the corresponding gate driving unit 1 and the first signal line 3; the access unit 2 corresponding to the even-numbered gate driving unit 1 is used when the corresponding gate driving unit 1 outputs a high level.
- the output terminal of the corresponding gate driving unit 1 is turned on by the first transistor M1 and the second signal line 4 is turned on, and when the gate driving unit 1 of the next stage of the corresponding gate driving unit 1 outputs a high level, The output terminal of the corresponding gate driving unit 1 is turned on by the second transistor M2 and the second signal line 4.
- the first transistor M1 when the output signal OUT of the gate driving unit 1 of the current stage is at a high level, the first transistor M1 is turned on, and the gate driving unit 1 of the current stage outputs a high-level output signal OUT through the first transistor M1;
- the output signal of the next-stage gate driving unit 1 of the stage gate driving unit 1 is at a high level (since each stage of the gate driving unit 1 outputs a high level step by step, the output of the gate driving unit 1 of the present stage at this time
- the signal OUT has returned to a low level, the second transistor M2 is turned on, and the gate driving unit 1 of the present stage outputs a low-level output signal OUT through the second transistor M2.
- the high level and the low level are two relative voltages, generally a low level of 0 to 0.25 V and a high level of 3.5 to 5 V.
- each of the first transistor M1 and the second transistor M2 may be a Thin Film Transistor (TFT) for facilitating fabrication by a process of a display device.
- TFT Thin Film Transistor
- the gate driving unit 1 includes a plurality of transistors and leads connecting the plurality of transistors, and the first transistor M1 and the second transistor M2 may be simultaneously fabricated with the plurality of transistors, the first signal line 3 and the second signal line. 4 can be made at the same time as the lead to save process and reduce cost.
- the gate driving unit 1 may include a capacitor C, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; a first terminal of the third transistor M3 and a third transistor M3.
- the gate is connected to the input end of the input signal IN, and the second end of the third transistor M3 is connected to the pull-up section Point PU; the first pole of the capacitor C is connected to the pull-up node PU, the second pole of the capacitor C is connected to the output end of the output signal OUT; the first end of the fourth transistor M4 is connected to the input end of the positive-phase clock signal CLK, the fourth transistor The second end of the M4 is connected to the output end of the output signal OUT, the gate of the fourth transistor M4 is connected to the pull-up node PU; the first end of the fifth transistor M5 is connected to the pull-up node PU, and the second end of the fifth transistor M5 is connected low.
- the input end of the voltage signal VSS, the gate of the fifth transistor M5 is connected to the input end of the reset signal RESET; the first end of the sixth transistor M6 is connected to the output end of the output signal OUT, and the second end of the sixth transistor M6 is connected to the low voltage signal.
- the gate of the sixth transistor M6 is connected to the input terminal of the reset signal RESET.
- the leads include leads connected to the gates of the third to sixth transistors M3-M6.
- the leads connected to the gates of the third to sixth transistors M3-M6 include a connection line of the gate of the third transistor M3 and an input terminal of the input signal IN, and a connection of the gate of the fourth transistor M4 and the pull-up node PU.
- the line, the connection line of the gate of the fifth transistor M5 and the input terminal of the reset signal RESET, and the connection line of the gate of the sixth transistor M6 and the input terminal of the reset signal RESET are used to simplify the fabrication process. Further, the first signal line 3 and the second signal line 4 may be fabricated simultaneously with the gates of the first to sixth transistors M1-M6.
- each of the gate driving units 1 may further include a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10; a first terminal of the seventh transistor M7 and a gate of the seventh transistor M7.
- the second end of the seventh transistor M7 is connected to the pull-down node PD; the first end of the eighth transistor M8 is connected to the pull-down node PD, and the second end of the eighth transistor M8 is connected to the low voltage signal VSS
- the gate of the eighth transistor M8 is connected to the pull-up node PU; the first end of the ninth transistor M9 is connected to the pull-up node PU, and the second end of the ninth transistor M9 is connected to the input end of the low-voltage signal VSS, the ninth transistor
- the gate of M9 is connected to the pull-down node PD; the first end of the tenth transistor M10 is connected to the output end of the output signal OUT,
- each of the third to tenth transistors M3-M10 may be a TFT.
- the third to tenth transistors M3-M10 may be both N-type transistors or P-type transistors.
- FIG. 4 is a timing diagram of signals in the gate driving unit according to an embodiment of the present invention, including an input phase T1, an output phase T2, and a reset phase T3. Stages. It should be noted that the timing chart shown in FIG. 4 takes an example in which each transistor is an N-type transistor. The embodiments of the present invention are not limited thereto.
- the positive phase clock signal CLK is at a low level, the inverted clock signal CLKB is at a high level, the input signal IN is at a high level, and the reset signal RESET is at a low level;
- the input signal IN controls the third transistor M3 to be turned on, and the voltage of the pull-up node PU is pulled high by the input signal IN.
- the fourth transistor M4 is turned off by a transistor having a threshold voltage higher than a high level voltage of the input signal IN, and the output signal OUT is at a low level;
- the inverted clock signal CLKB controls the seventh transistor M7 to be turned on.
- the eighth transistor M8 is turned on under the control of the voltage of the pull-up node PU, the pull-down node PD is at a low level, and the ninth transistor M9 and the tenth transistor M10 are turned off;
- the reset signal RESET is at a low level, and the fifth transistor M5 and the sixth transistor M6 are turned off.
- the positive phase clock signal CLK is at a high level, the inverted clock signal CLKB is at a low level, the input signal IN is at a low level, and the reset signal RESET is at a low level;
- the positive phase clock signal CLK is at a high level. Under the bootstrap action of the equivalent capacitance in the fourth transistor M4, the voltage of the pull-up node PU is further pulled up to reach the threshold voltage of the fourth transistor M4, and the fourth transistor M4 Turned on, the output signal OUT is high;
- the inverted clock signal CLKB is at a low level, and the seventh transistor M7 is turned off.
- the eighth transistor M8 is turned on under the control of the voltage of the pull-up node PU, the pull-down node PD is at a low level, and the ninth transistor M9 and the tenth transistor M10 are turned off;
- the reset signal RESET is at a low level, and the fifth transistor M5 and the sixth transistor M6 are turned off.
- the input signal IN is at a low level, and the third transistor M3 is turned off.
- the positive phase clock signal CLK is at a low level, the inverted clock signal CLKB is at a high level, the input signal IN is at a low level, and the reset signal RESET is at a high level;
- the reset signal RESET is at a high level, and the fifth transistor M5 and the sixth transistor M6 are turned on, and the voltage of the pull-up node PU and the output signal OUT are reset;
- the inverted clock signal CLKB is at a high level, and the seventh transistor M7 is turned on.
- the eighth transistor M8 is turned off under the control of the voltage of the pull-up node PU, the pull-down node PD is at a high level, and the ninth transistor M9 and the tenth transistor M10 are turned on to pull down the voltage of the pull-up node PU and the output signal OUT;
- the input signal IN is at a low level, and the third transistor M3 is turned off.
- the fourth transistor M4 is turned off under the control of the voltage of the pull-up node PU.
- the normal pull-up node PU signal is at a high level in the input phase T1 and the output phase T2, and the high level of the output phase T2 is greater than the high level of the input phase T1, and in the reset phase T3 is Low level, so the normal output signal OUT is high in the output phase T2, and low in the input phase T1 and the reset phase T3, as shown in Figure 5b.
- the abnormal pull-up node PU signal is at a high level in the input phase T1, the output phase T2, and the reset phase T3, and the abnormal output signal OUT is high in the output phase T2 and the reset phase T3. Only in the input phase T1 is low, as shown in Figure 5b.
- the access unit 2 corresponding to the odd-numbered gate driving unit 1 is used for the gate of the next stage of the corresponding gate driving unit 1 when the corresponding gate driving unit 1 outputs a high level.
- the driving unit 1 outputs a high level (when the corresponding gate driving unit 1 outputs a low level)
- the output end of the corresponding gate driving unit 1 is turned on with the first signal line 3, and the first signal line 3 is connected.
- the output signals of the gate driving units 1 corresponding to the respective odd-numbered stages are sequentially one high level and one low level.
- the access unit 2 corresponding to the even-numbered gate driving unit 1 is used for the gate driving unit in the next stage of the corresponding gate driving unit 1 when the corresponding gate driving unit 1 outputs a high level.
- the input signal IN of the gate driving unit is the output signal OUT of the gate driving unit of the upper stage of the gate driving unit
- the output signal of the gate driving unit is the gate of the upper stage of the gate driving unit.
- the reset signal of the drive unit Specifically, at the first moment, the first-stage gate driving unit outputs a high-level output signal OUT (also as an input signal IN of the second-stage gate driving unit), and the signal on the first signal line is at a high level.
- the second stage gate driving unit outputs a high level output signal OUT (along as the input signal IN of the third stage gate driving unit and the reset of the first stage gate driving unit) Signal RESET), the signal on the second signal line is high level, and the first stage gate driving unit outputs the low level output signal OUT, the signal on the first signal line is low level; after the second time At the third moment, the third-stage gate driving unit outputs a high-level output signal OUT (at the same time as the input signal IN of the fourth-stage gate driving unit and the reset signal RESET of the second-stage gate driving unit), first The signal on the signal line is high, and the second stage gate drive unit outputs a low level output signal. OUT, the signal on the second signal line is low level... and so on, so under normal circumstances, the signal on the first signal line and the second signal line is a square wave signal with a constant period (high level and low level alternate Appears) as shown in Figure 6a.
- an abnormality of the output signal of the gate driving unit of a certain level will cause an abnormality of the output signals of the subsequent gate driving units, that is, at all the gates.
- the output signals of the driving unit are output once to one cycle on the first signal line and the second signal line, and the signals on the first signal line and the second signal line are before the point corresponding to the output signal of the gate driving unit.
- the square wave signal, the signal on the first signal line and the second signal line is maintained at a high level after the point corresponding to the output signal of the gate driving unit (including the point of the output signal of the gate driving unit), as shown in the figure Shown in 6b.
- the present invention utilizes the above principle to determine whether a defect exists according to the number of cycles of a continuous square wave signal on the first signal line and the second signal line (ie, the number of high and low levels that alternately appear). And a defective gate drive unit.
- the number of cycles of a continuous square wave signal on the first signal line is three
- the number of cycles of a continuous square wave signal on the second signal line is two
- the defective gate drive unit is The sixth stage gate drive unit.
- the embodiment of the invention provides a method for detecting a gate driving circuit, which is suitable for detecting the gate driving circuit shown in FIG. 1 or FIG. 2 .
- the detecting method includes:
- Step 701 Connect the first signal line and the second signal line to the oscilloscope, respectively.
- Step 702 Display an output signal of the first signal line and an output signal of the second signal line by using an oscilloscope.
- Step 703 Determine a gate driving unit having a defect according to a change of a high level and a low level in an output signal of the first signal line and an output signal of the second signal line.
- the gate driving unit has no defect; when the output signal of the first signal line and the output signal of the second signal line A continuous high level appears in the square wave signal of the same period on at least one of the output signals, and the gate drive has a defect.
- the sum of the number of cycles of a continuous square wave signal on the output signal of the first signal line and the number of cycles of a continuous square wave signal on the output signal of the second signal line is increased to 1, which is a gate with defects
- the number of stages of the drive unit For example, the number of cycles of a continuous square wave signal on the first signal line is three, and the number of cycles of a continuous square wave signal on the second signal line is two, and the gate drive unit having a defect is the sixth stage. Gate drive unit.
- the output signal of the odd-numbered gate driving unit is detected by the first signal line
- the second signal line detects the output signal of the even-numbered gate driving unit, that is, the output signal of the gate driving unit of each stage is connected.
- the first signal line and the second signal line it is only necessary to connect the first signal line and the second signal line to the oscilloscope respectively to determine whether there is a defect in the gate driving unit of each stage, and the operation is simple and convenient, and the detection efficiency is Greatly improve.
- Embodiments of the present invention provide an array substrate including a gate driving circuit as shown in FIG. 1 or FIG.
- the output signal of the odd-numbered gate driving unit is detected by the first signal line
- the second signal line detects the output signal of the even-numbered gate driving unit, that is, the output signal of the gate driving unit of each stage is connected.
- the first signal line and the second signal line it is only necessary to connect the first signal line and the second signal line to the oscilloscope respectively to determine whether there is a defect in the gate driving unit of each stage, and the operation is simple and convenient, and the detection efficiency is Greatly improve.
- Embodiments of the present invention provide a display device including the above array substrate.
- the output signal of the odd-numbered gate driving unit is detected by the first signal line
- the second signal line detects the output signal of the even-numbered gate driving unit, that is, the output signal of the gate driving unit of each stage is connected.
- the first signal line and the second signal line it is only necessary to connect the first signal line and the second signal line to the oscilloscope respectively to determine whether there is a defect in the gate driving unit of each stage, and the operation is simple and convenient, and the detection efficiency is Greatly improve.
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Abstract
Description
Claims (10)
- 一种栅极驱动电路,包括多个级联的栅极驱动单元,其特征在于,所述栅极驱动电路还包括与所述栅极驱动单元一一对应的接入单元、第一信号线和第二信号线,每个所述接入单元分别与对应的所述栅极驱动单元、对应的所述栅极驱动单元的下一级的所述栅极驱动单元连接,其中奇数级的所述栅极驱动单元对应的所述接入单元与所述第一信号线连接以便所述第一信号线通过所述接入单元检测奇数级的所述栅极驱动单元的输出信号;偶数级的所述栅极驱动单元对应的所述接入单元与所述第二信号线连接以便所述第二信号线通过所述接入单元检测偶数级的所述栅极驱动单元的输出信号。
- 根据权利要求1所述的栅极驱动电路,其特征在于,奇数级的所述栅极驱动单元对应的接入单元用于,根据对应的所述栅极驱动单元的输出信号、以及对应的所述栅极驱动单元的下一级的所述栅极驱动单元的输出信号,将对应的所述栅极驱动单元的输出端与所述第一信号线导通;偶数级的所述栅极驱动单元对应的接入单元用于,根据对应的所述栅极驱动单元的输出信号、以及对应的所述栅极驱动单元的下一级的所述栅极驱动单元的输出信号,将对应的所述栅极驱动单元的输出端与所述第二信号线导通。
- 根据权利要求1所述的栅极驱动电路,其特征在于,所述接入单元包括第一晶体管和第二晶体管,所述第一晶体管的栅极、所述第一晶体管的第一端、所述第二晶体管的第一端分别与所述接入单元对应的所述栅极驱动单元的输出端连接,所述第二晶体管的栅极与所述接入单元对应的所述栅极驱动单元的下一级所述栅极驱动单元的输出端连接,所述第一晶体管的第二端和所述第二晶体管的第二端分别与所述第一信号线连接,或者所述第一晶体管的第二端和所述第二晶体管的第二端分别与所述第二信号线连接。
- 根据权利要求3所述的栅极驱动电路,其特征在于,所述栅极驱动单元包括多个晶体管、以及连接所述多个晶体管的引线,所述第一晶体管和所述第二晶体管均与所述多个晶体管同时制作,所述第一信号线和所述第二信号线均与所述引线同时制作。
- 根据权利要求1所述的栅极驱动电路,其特征在于,所述接入单元、所述第一信号线和所述第二信号线均设置在所述栅极驱动单元的输出端。
- 根据权利要求1所述的栅极驱动电路,其特征在于,所述第一信号线的一端和所述第二信号线的一端均设有测试端子,所述测试端子用于与示波器连接。
- 根据权利要求6所述的栅极驱动电路,其特征在于,所述第一信号线设有所述测试端子的一端和所述第二信号线设有所述测试端子的一端位于所述栅极驱动电路的同一侧。
- 一种阵列基板,其特征在于,所述阵列基板包括如权利要求1-7任一项所述的栅极驱动电路。
- 一种显示装置,其特征在于,所述显示装置包括如权利要求8所述的阵列基板。
- 一种如权利要求1-7任一项所述的栅极驱动电路的检测方法,其特征在于,所述检测方法包括:将第一信号线和第二信号线分别与示波器连接;采用示波器显示所述第一信号线的输出信号和所述第二信号线的输出信号;根据所述第一信号线的输出信号和所述第二信号线的输出信号中高低电平的变化情况,确定存在缺陷的栅极驱动单元。
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US10241145B2 (en) | 2019-03-26 |
CN105590607B (zh) | 2018-09-14 |
US20180080973A1 (en) | 2018-03-22 |
CN105590607A (zh) | 2016-05-18 |
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