CN105895639A - 阵列基板及其制备方法、显示器件 - Google Patents

阵列基板及其制备方法、显示器件 Download PDF

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CN105895639A
CN105895639A CN201610499703.2A CN201610499703A CN105895639A CN 105895639 A CN105895639 A CN 105895639A CN 201610499703 A CN201610499703 A CN 201610499703A CN 105895639 A CN105895639 A CN 105895639A
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layer
conductive layer
source
drain electrode
passivation layer
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刘保力
陈皓
谢海征
林雨
朱孝会
关跃征
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to CN201610499703.2A priority Critical patent/CN105895639A/zh
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Priority to US15/568,155 priority patent/US10109653B2/en
Priority to PCT/CN2017/084106 priority patent/WO2018000967A1/zh
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract

本发明公开一种阵列基板及其制备方法、显示器件，涉及液晶显示技术领域，以消除钝化层过孔过刻蚀的隐患，避免由于钝化层过孔过刻蚀而导致的钝化层过孔上下层结构连接不良。所述阵列基板，包括承载基底，在所述承载基底上形成有空间垂直交叉的栅线和数据线，所述栅线和数据线限定出像素区域，所述像素区域内设有薄膜晶体管和像素电极，所述薄膜晶体管的栅极与所述栅线连接、源极与所述数据线连接、漏极与所述像素电极连接，所述源漏电极所在的源漏电极层下方设有导电层、上方设有钝化层过孔，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。本发明提供的阵列基板用于制备液晶显示器件。

Description

阵列基板及其制备方法、显示器件
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种阵列基板及其制备方法、显示器件。
背景技术
随着薄膜场效应晶体管液晶显示(TFT-LCD Display)技术的发展和工业技术的进步，液晶显示器件生产成本降低、制造工艺日益完善，TFT-LCD已经取代了阴极射线管显示成为平板显示领域的主流技术。且由于其本身所具有的优点，在市场和消费者心中成为理想的显示器件。
当前TFT基板(阵列基板)的制造过程通常使用6mask工艺，即需要使用6次掩模板。依次为Gate(栅极层，第1次mask)、active(有源层，第2次mask)、1st ITO(第一层ITO(氧化铟锡)，可作为像素电极或公共电极，第3次mask)、SD(源漏电极层，第4次mask)、VIA(钝化层过孔，包括将外部信号引入源漏电极层的引入过孔；当第一层ITO为公共电极时，还包括连接薄膜晶体管漏极和像素电极的过孔；第5次mask)、2nd ITO(第二层ITO，可作为公共电极或像素电极，第6次mask)。
其中，在进行第5次mask时，使用干法刻蚀制作钝化层过孔。钝化层过孔20周围的结构如图1a和图1b所示，由上至下分别为钝化层23、源漏电极层22和栅绝缘层21。在实际操作中，钝化层过孔刻蚀工艺在保证钝化层完全刻蚀的情况下，通常会有一定的过刻率，这样就会对钝化层23下方的源漏电极层22进行刻蚀。因此，如图2a所示，在理想的状态下，钝化层过孔20的深度应该仅到源漏电极层22。但是在过刻的情况下容易形成图2b所示的情况，使得源漏电极层22被刻掉一部分。严重时还会形成图2c所示的情况，源漏电极层22被全部刻蚀。一旦形成图2c所示的情况，与钝化层上方的结构如第二层ITO连接的就只剩下钝化层过孔侧面的源漏电极层材料，这样钝化层上方的结构与源漏电极层的接触面积减小，容易使得钝化层上方的结构与源漏电极层搭接不上，造成断路。
发明内容
本发明的目的在于提供一种阵列基板及其制备方法、显示器件，用于消除钝化层过孔过刻蚀的隐患，避免由于钝化层过孔过刻蚀而导致的钝化层过孔上下层结构连接不良。
为了实现上述目的，本发明提供如下技术方案：
本发明的第一方面提供一种阵列基板，包括承载基底，在所述承载基底上形成有空间垂直交叉的栅线和数据线，所述栅线和数据线限定出像素区域，所述像素区域内设有薄膜晶体管和像素电极，所述薄膜晶体管的栅极与所述栅线连接、源极与所述数据线连接、漏极与所述像素电极连接，所述源漏电极所在的源漏电极层下方设有导电层、上方设有钝化层过孔，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
在上述阵列基板的一个具体实现方案中，所述源漏电极层的下方还设有像素电极，所述导电层与所述像素电极相互分隔地位于同一层且通过一次构图工艺形成。
在上述阵列基板的另一个具体实现方案中，所述源漏电极层的下方还设有公共电极，所述导电层与所述公共电极相互分隔地位于同一层且通过一次构图工艺形成。
在上述各方案中，所述导电层为经过退火处理的导电层。
基于上述阵列基板的技术方案，本发明的第二方面提供一种阵列基板的制备方法，包括：
步骤11、在承载基底上形成栅线和栅极、栅绝缘层和有源层；
步骤12、在形成有栅线和栅极、栅绝缘层和有源层的所述承载基底上形成相互分隔的导电层以及像素电极；
步骤13、在形成有导电层以及像素电极的所述承载基底上形成源漏电极层、钝化层和钝化层过孔、公共电极，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
在所述步骤12中，所述导电层与所述像素电极通过一次构图工艺形成并位于同一层。
并且，在所述步骤12和步骤13之间，所述方法还包括：对所述导电层进行退火处理。
基于上述阵列基板的技术方案，本发明的第三方面还提供一种阵列基板的制备方法，包括：
步骤21、在承载基底上形成栅线和栅极、栅绝缘层和有源层；
步骤22、在形成有栅线和栅极、栅绝缘层和有源层的所述承载基底上形成相互分隔的导电层以及公共电极；
步骤23、在形成有导电层以及公共电极的所述承载基底上形成源漏电极层、钝化层和钝化层过孔、像素电极，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
在所述步骤22中，所述导电层与所述公共电极通过一次构图工艺形成并位于同一层。
并且，在所述步骤22和步骤23之间，所述方法还包括：对所述导电层进行退火处理。
基于上述阵列基板的技术方案，本发明的第四方面还提供一种显示器件，包括上述任一项技术方案所述的阵列基板。
本发明提供的阵列基板及其制备方法、显示器件中，在源漏电极层下方增设导电层之后，源漏电极层与所述导电层形成电连接。这样，在进行钝化层过孔的刻蚀时，即使由于过刻蚀而将源漏电极层刻穿，仍然存在所述导电层可以通过钝化层过孔与后续工序中形成的结构进行大面积的连接，从而消除钝化层过孔过刻蚀的隐患，避免由于钝化层过孔过刻蚀而导致的钝化层过孔上下层结构连接不良。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1a为现有技术中钝化层过孔周围的平面结构示意图；
图1b为图1a的AA线剖视图；
图2a为现有技术中理想状态下的钝化层过孔示意图；
图2b为现有技术中将源漏电极层刻掉一部分的钝化层过孔示意图；
图2c为现有技术中将源漏电极层刻穿的钝化层过孔示意图；
图3为本发明实施例中钝化层过孔周围结构的剖视图；
图4a为本发明实施例中理想状态下的钝化层过孔示意图；
图4b为本发明实施例中将源漏电极层刻穿的钝化层过孔示意图；
图5为本发明实施例一种阵列基板制备方法的示意图；
图6为本发明实施例另一种阵列基板制备方法的示意图。
附图标记：
20-钝化层过孔 21-栅绝缘层
22-源漏电极层 23-钝化层
30-钝化层过孔 31-栅绝缘层
32-源漏电极层 33-钝化层
34-导电层
具体实施方式
为便于理解，下面结合说明书附图，对本发明实施例提供的阵列基板及其制备方法、显示器件进行详细描述。
本发明实施例提供的阵列基板包括承载基底，在所述承载基底上形成有空间垂直交叉的栅线和数据线，所述栅线和数据线限定出像素区域，所述像素区域内设有薄膜晶体管和像素电极，所述薄膜晶体管的栅极与所述栅线连接、源极与所述数据线连接、漏极与所述像素电极连接。请参阅图3，本实施例提供的阵列基板的特征在于，在所述源漏电极所在的源漏电极层32的下方设有导电层34、上方设有钝化层过孔30，所述导电层34、源漏电极层32、以及钝化层过孔30位置相互对应且由下至上依次排列。
其中，钝化层过孔30位于钝化层33中，漏极位于源漏电极层32中，源漏电极层32的下方为导电层34，导电层34的下方为栅绝缘层31。
本实施例中，在源漏电极层32下方增设导电层34之后，源漏电极层32与所述导电层34形成电连接。这样，在进行钝化层过孔30的刻蚀时，即使由于过刻蚀而将源漏电极层32刻穿，仍然存在所述导电层34可以通过钝化层过孔30与后续工序中形成的结构进行大面积的连接，从而消除钝化层过孔过刻蚀的隐患，避免由于钝化层过孔过刻蚀而导致的钝化层过孔30上下层结构连接不良。如图4a所示，在理想状态下，钝化层过孔30的位置仅到源漏电极层32处。但即使如图4b所示，当源漏电极层32被刻穿时，还可以有导电层34与钝化层33上方的结构形成连接。
虽然图3未显示，但在上述阵列基板的一个具体实现方式中，还可以在所述源漏电极层32的下方设置像素电极。此时，所述导电层34与所述像素电极相互分隔地位于同一层，且通过一次构图工艺形成。
在阵列基板的6mask工艺结构中：可以在制作有源层之后依次制作像素电极和源漏电极，之后再制作钝化层和公共电极，此时像素电极和薄膜晶体管的漏极直接搭接，钝化层过孔的作用是将外部信号引入漏极；也可以制作有源层之后依次制作公共电极和源漏电极，之后再制作钝化层和像素电极，此时钝化层过孔的作用还包括连接像素电极和漏极。
当先制作像素电极后制作公共电极时，所述导电层34可以与像素电极相互分隔地位于同一层且通过一次构图工艺形成，这样仅通过一次mask(掩膜板曝光、显影工艺)就能同时制作出导电层34和像素电极。这样通过一次构图工艺仅仅是对原本制作像素电极的mask进行一些改进，使其同时具备制作导电层34的图案即可，不增加mask的次数，有效地控制了成本。
同样地，虽然图3未显示，但在上述阵列基板的另一个具体实现方式中，所述源漏电极层32的下方还设有公共电极，所述导电层与所述公共电极相互分隔地位于同一层且通过一次构图工艺形成。当先制作公共电极后制作像素电极时，所述导电层34可以与公共电极相互分隔地位于同一层且通过一次构图工艺形成，这样仅通过一次mask就能同时制作出导电层34和公共电极。仅是对原本制作公共电极的mask进行一些改进，使其同时具备制作导电层34的图案即可，不增加mask的次数，有效地控制了成本。
在上述各实施例中，所述导电层34为经过退火处理的导电层。当导电层34与像素电极或公共电极采用同一次构图工艺形成时，由于像素电极或公共电极通常采用氧化铟锡材料(ITO)制成，因此导电层34也可以使用氧化铟锡材料制成。对导电层进行退火之后，氧化铟锡材料可以具有几乎不能被刻蚀的特性。因此即使由于过刻蚀而将源漏电极层32刻穿，导电层34也不会被刻穿，杜绝了源漏电极层32与后续工序中形成的结构搭接不上的隐患。
除上述阵列基板之外，本发明实施例还提供了两种制备阵列基板的方法，该两种制备方法的不同之处在于像素电极和公共电极形成的顺序不同。在下列制备方法的实施例1中是先形成像素电极后形成公共电极，在下列制备方法的实施例2中则是先形成公共电极后形成像素电极。
制备方法的实施例1
本实施例1中，阵列基板的制备方法包括：
步骤11、在承载基底上形成栅线和栅极、栅绝缘层和有源层；
步骤12、在形成有栅线和栅极、栅绝缘层和有源层的所述承载基底上形成相互分隔的导电层以及像素电极；
步骤13、在形成有导电层以及像素电极的所述承载基底上形成源漏电极层、钝化层和钝化层过孔、公共电极，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
该实施例1所涉及的制备步骤11和13与行业内通常的制备步骤相同。所不同的是，在所述步骤12中，所述导电层与所述像素电极通过一次构图工艺形成并位于同一层。
并且，在所述步骤12和步骤13之间，所述方法还包括：对所述导电层进行退火处理。
制备方法的实施例2
本实施例2中，阵列基板的制备方法包括：
步骤21、在承载基底上形成栅线和栅极、栅绝缘层和有源层；
步骤22、在形成有栅线和栅极、栅绝缘层和有源层的所述承载基底上形成相互分隔的导电层以及公共电极；
步骤23、在形成有导电层以及公共电极的所述承载基底上形成源漏电极层、钝化层和钝化层过孔、像素电极，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
该实施例2所涉及的制备步骤21和23与行业内通常的制备步骤相同。所不同的是，在所述步骤22中，所述导电层与所述公共电极通过一次构图工艺形成并位于同一层。
并且，在所述步骤22和步骤23之间，所述方法还包括：对所述导电层进行退火处理。
基于上述阵列基板的实施例，本发明实施例还提供一种显示器件，包括上述实施例中所述的阵列基板。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

1.一种阵列基板，包括承载基底，在所述承载基底上形成有空间垂直交叉的栅线和数据线，所述栅线和数据线限定出像素区域，所述像素区域内设有薄膜晶体管和像素电极，所述薄膜晶体管的栅极与所述栅线连接、源极与所述数据线连接、漏极与所述像素电极连接，其特征在于，所述源漏电极所在的源漏电极层下方设有导电层、上方设有钝化层过孔，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
2.根据权利要求1所述的阵列基板，其特征在于：
所述源漏电极层下方还设有像素电极，所述导电层与所述像素电极相互分隔地位于同一层且通过一次构图工艺形成；或
所述源漏电极层下方还设有公共电极，所述导电层与所述公共电极相互分隔地位于同一层且通过一次构图工艺形成。
3.根据权利要求2所述的阵列基板，其特征在于，所述导电层为经过退火处理的导电层。
4.一种阵列基板的制备方法，其特征在于，包括：
步骤11、在承载基底上形成栅线和栅极、栅绝缘层和有源层；
步骤12、在形成有栅线和栅极、栅绝缘层和有源层的所述承载基底上形成相互分隔的导电层以及像素电极；
步骤13、在形成有导电层以及像素电极的所述承载基底上形成源漏电极层、钝化层和钝化层过孔、公共电极，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
5.根据权利要求4所述的阵列基板的制备方法，其特征在于，在所述步骤12中，所述导电层与所述像素电极通过一次构图工艺形成并位于同一层。
6.根据权利要求5所述的阵列基板的制备方法，其特征在于，在所述步骤12和步骤13之间，所述方法还包括：对所述导电层进行退火处理。
7.一种阵列基板的制备方法，其特征在于，包括：
步骤21、在承载基底上形成栅线和栅极、栅绝缘层和有源层；
步骤22、在形成有栅线和栅极、栅绝缘层和有源层的所述承载基底上形成相互分隔的导电层以及公共电极；
步骤23、在形成有导电层以及公共电极的所述承载基底上形成源漏电极层、钝化层和钝化层过孔、像素电极，所述导电层、源漏电极层、以及钝化层过孔位置相互对应且由下至上依次排列。
8.根据权利要求7所述的阵列基板的制备方法，其特征在于，在所述步骤22中，所述导电层与所述公共电极通过一次构图工艺形成并位于同一层。
9.根据权利要求8所述的阵列基板的制备方法，其特征在于，在所述步骤22和步骤23之间，所述方法还包括：对所述导电层进行退火处理。
10.一种显示器件，包括如权利要求1-3任一项所述的阵列基板。
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