WO2017118034A1 - 电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路、显示装置 - Google Patents

电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2017118034A1
WO2017118034A1 PCT/CN2016/095949 CN2016095949W WO2017118034A1 WO 2017118034 A1 WO2017118034 A1 WO 2017118034A1 CN 2016095949 W CN2016095949 W CN 2016095949W WO 2017118034 A1 WO2017118034 A1 WO 2017118034A1
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Prior art keywords
output
signal
transistor
module
input
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PCT/CN2016/095949
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English (en)
French (fr)
Inventor
张志豪
孙志华
马伟超
张旭
苏国火
汪建明
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/519,984 priority Critical patent/US10229634B2/en
Publication of WO2017118034A1 publication Critical patent/WO2017118034A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present disclosure belongs to the field of display technologies, and in particular, to a level shifting unit, a level shifting circuit, a driving method thereof, a gate driving circuit, and a display device.
  • the display area of the flat panel display device includes a plurality of pixel regions surrounded by intersecting gate lines and data lines, and a thin film transistor (TFT) for controlling display is provided in each of the pixel driving.
  • TFT thin film transistor
  • the thin film transistor realizes image display of pixel dots by driving of a driving unit located in a non-display area.
  • the drive unit includes a gate driver for scanning and opening multi-channel RGB pixel points belonging to the same row in the display screen, and a source driver for providing display data for the opened multi-channel RGB pixel.
  • the clock signal of the gate driver is provided by a level shifting circuit.
  • the level shifting circuit is generally used to convert an input small amplitude level signal into a large value level signal for driving a pixel point (driven by a gate line and a gate of a thin film transistor).
  • the clock signal line is likely to have a line-to-line intersection when wiring. Once the line is crossed with the line, the clock signal will be shorted during display. Due to the large amplitude of the clock signal, the short-circuit current is also large, which causes the current in the gate driver to burn out, thereby causing the display device to be scrapped, and even causing a safety hazard.
  • the technical solution adopted to solve the technical problem of the present disclosure is a level shifting unit, comprising: a logic control module, an output module, an output control module, and a feedback module.
  • the logic control module is connected to the power on, the driving power source, the input signal end, and the output module, configured to generate a control signal opposite to the input signal, and select a polarity corresponding to the polarity of the power source according to the control signal
  • a logic level signal output by the driving power source transmits the logic level signal to the output module.
  • the feedback module, the connection enable signal end, the signal output end, and the output control module are configured to output a feedback signal according to the signal input by the enable signal end and the signal output end, and transmit the feedback signal to the Output control module.
  • the output control module is connected to the output module and the driving power source for controlling whether the driving power source outputs a logic level signal input thereto to the output module according to the feedback signal.
  • the output module is connected to the signal output end for controlling the output of the signal output end under the control of the logic level signal output by the driving power source and the output control module.
  • the logic control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a first inverter.
  • the first transistor and the fourth transistor have a first switching characteristic
  • the second transistor and the third transistor have a second switching characteristic.
  • An input end of the first inverter is connected to the input signal end, and an output end is connected to a control electrode of the first transistor, a control electrode of the second transistor, a control electrode of the third transistor, and the The gate of the four transistors.
  • the first pole of the first transistor is connected to the first end of the output module and the first resistor, and the second pole is connected to the turn-on voltage end of the power-on.
  • the first pole of the second transistor is connected to the second end of the first resistor and the output module, and the second pole is connected to the working ground of the power source.
  • the first pole of the third transistor is connected to a high level signal end of the driving power source, and the second pole is connected to the first end of the first transistor, the first end of the first resistor, and the output module.
  • the first pole of the fourth transistor is connected to the low level signal end of the driving power source, and the second pole is connected to the second end of the first resistor, the first pole of the second transistor, and the output module.
  • the output module includes a fifth transistor and a sixth transistor.
  • the fifth transistor has a first switching characteristic and the sixth transistor has a second switching characteristic.
  • the first pole of the fifth transistor is connected to the signal output end and the first pole of the sixth transistor, the second pole is connected to the output control module, and the control pole is connected to the logic control module.
  • the first pole of the sixth transistor is connected to the signal output end, the second pole is connected to the output control module, and the control pole is connected to the logic control module.
  • the output control module includes a seventh transistor having a first switching characteristic and an eighth transistor having a second switching characteristic.
  • the second pole of the seventh transistor is connected to a high level signal end of the driving power source, and the control pole is connected to the feedback module.
  • the second pole of the eighth transistor is connected to a low level signal end of the driving power source, and the control pole is connected to the feedback module.
  • the feedback module includes a voltage comparator, an OR gate (OR), and a second inverter.
  • the first input end of the voltage comparator is connected to the first reference voltage end, the second input end is connected to the second reference voltage end, the third input end is connected to the signal output end, and the output end is connected with the first input of the OR gate Electrical connection.
  • the second input end of the OR gate is connected to the enable signal end, and the output end is connected to the input end of the second inverter.
  • An input end of the second inverter is connected to the output control module, and an output end is also connected to the output control module.
  • the level shifting unit further includes: an enable signal generating module, configured to output a high level signal at a power-on time, and input the signal to the feedback module through the enable signal end, The feedback module outputs a feedback signal to control the output control module to be turned on.
  • the enable signal generating module includes: a second resistor, a ninth transistor, and a first capacitor.
  • the ninth transistor has a second switching characteristic.
  • the first end of the second resistor is connected to the high-level signal end of the driving power source, and the second end is connected to the enabling signal end.
  • the first pole of the ninth transistor is connected to the enable signal end, the second pole is connected to the low level signal end of the driving power source, and the control pole is connected to the high level signal end of the driving power source.
  • the first end of the first capacitor is connected to the control electrode of the ninth transistor, and the second end is connected to the low level signal end of the driving power source.
  • the technical solution adopted to solve the technical problem of the present disclosure also provides a level shift circuit including a plurality of the above-described level shifting units.
  • the level shifting unit includes a voltage comparator, an OR gate, and a second inverter
  • the level shifting circuit further includes a NOR gate.
  • the input of the NOR gate The terminals are respectively connected to the output terminals of the voltage comparators of each of the feedback modules, and the output terminals of the NOR gates are connected to the first input terminals of the OR gates of the respective feedback modules.
  • the technical solution adopted to solve the technical problem of the present disclosure further provides a driving method of a level shifting circuit, wherein the level shifting circuit is the above-described level shifting circuit, and the driving method includes: An output stage: the enable signal end inputs an enable signal, the feedback module controls the output control module to be turned on according to the enable signal; and the logic control module generates and generates according to the signal input by the input signal end a control signal having an opposite input signal, selecting a logic level signal input by the driving power source corresponding to a polarity of the power source according to the control signal, and outputting the logic level signal through the output module; and feedback Stage: The feedback module controls the output control module to be turned on or off according to a signal output by the signal output end of the level shifting unit to control an output of the output module.
  • the level shifting unit includes a voltage comparator, an OR gate, and a second inverter
  • the level shifting circuit further includes a NOR gate.
  • the feedback phase includes: a voltage comparator in each of the feedback modules of the level shifting unit outputs a first control signal to the NOR gate according to a signal output by the respective signal output end, The NOR gate outputs a second control signal according to the first control signal outputted by the voltage comparators in each of the feedback modules, and controls all of the output control through an OR gate and a second inverter of each of the feedback modules The modules are turned on simultaneously or simultaneously to control the output of the output module.
  • the technical solution adopted to solve the technical problems of the present disclosure also provides a gate driving circuit including the above-described level shifting circuit.
  • the feedback module controls the turning on or off of the output module by the signals input from the enable signal terminal and the signal output terminal, particularly in the level shift circuit. If the signals output by the two level shifting units are short-circuited, the signals output by the two level shifting units will inevitably change, and the feedback module can output the signals according to the signal output terminals received at this time.
  • the size is compared with a preset potential to determine whether a short circuit occurs.
  • the output feedback signal controls the output control module of the level shifting circuit to be turned off, so that The output module outputs a high-impedance state to avoid gate drive The burner burned and there was a safety hazard.
  • FIG. 1 is a schematic diagram of a level shifting unit provided by a first embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an enable signal generating module provided by a first embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a level shifting circuit provided by a second embodiment of the present disclosure.
  • FIG. 4 is an operational timing diagram of a level shifting unit provided by a third embodiment of the present disclosure.
  • the transistors employed in various embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices of the same characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are indistinguishable. In various embodiments of the present disclosure, to distinguish the source and drain of a transistor, one of the poles is referred to as a first pole and the other pole is referred to as a second pole, and the gate is referred to as a gate. In addition, the transistors can be classified into N-type and P-type according to the characteristics of the transistors. In the following embodiments, a transistor having a first switching characteristic is a P-type transistor, and a transistor having a second switching characteristic is an N-type transistor.
  • the source of the first very N-type transistor and the drain of the second N-type transistor are turned on when the gate is input to a high level, and the P-type is opposite. It is conceivable that the transistor having the first switching characteristic is an N-type transistor, and the transistor having the second switching characteristic is a P-type transistor. The realization can be easily imagined by those skilled in the art without any creative work, and therefore Within the scope of the protection of the embodiments of the present disclosure.
  • the embodiment provides a level shifting unit, including: a logic control module 1 , an output module 2 , an output control module 3 , and a feedback module 4 .
  • the logic control module 1 is connected to an open power source, a driving power source, an input signal terminal CLK_IN, and an output module 2, configured to generate a control signal opposite to the input signal, and select and correspond to the polarity of the power source according to the control signal.
  • the logic level signal output by the driving power source transmits the logic level signal to the output module 2.
  • the feedback module 4 is connected to the enable signal terminal EN, the signal output terminal CLK_OUT, and the output control module 3, and is configured to output a feedback signal according to the signal input by the enable signal terminal EN and the signal output terminal CLK_OUT.
  • the output control module 3 is connected to the output module 2 and the driving power source for controlling whether the driving power source outputs the logic level signal input thereto to the output control module 3 according to the feedback signal.
  • the output module 2 is connected to the signal output terminal CLK_OUT for controlling the output of the signal output terminal CLK_OUT under the control of the logic level signal output by the driving power source and the output control module 3.
  • the feedback module 4 can enable the signal input from the signal terminal EN and the signal output terminal CLK_OUT to control the turning on or off of the output module 2, especially in the level shifting circuit. If the signals output by the two level shifting units are short-circuited, the signals output by the two level shifting units will inevitably change, so the feedback module 4 can be based on the signal output received at this time.
  • the magnitude of the signal output by CLK_OUT is compared with a preset potential to determine whether a short circuit has occurred.
  • the output feedback signal controls the output control module of the level shifting circuit to be turned off, so that the output module 2 outputs a high-impedance state, thereby preventing the gate driver from being burned and appearing safe. Hidden dangers.
  • the logic control module 1 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first resistor R1, and a first inverter N1.
  • the first transistor T1 and the third transistor T3 have a first switching characteristic
  • the second transistor T2 and the fourth transistor T4 have a second switching characteristic.
  • the present disclosure should not be construed as being limited thereto, and those skilled in the art can design other settings as needed.
  • the first transistor T1 and the third transistor T3 have a second switching characteristic
  • the second transistor T2 and the fourth transistor T4 have a first switching characteristic.
  • the input end of the first inverter N1 is connected to the input signal terminal CLK_IN, and the output terminal is connected to the control electrode of the first transistor T1, the control electrode of the second transistor T2, the control electrode of the third transistor T3, and the fourth The gate of transistor T4.
  • the first pole of the first transistor T1 is connected to the output module 2 and the first end of the resistor, and the second pole is connected to the turn-on voltage end of the power-on.
  • the first pole of the second transistor T2 is connected to the second end of the first resistor R1 and the output module 2, and the second pole is connected to the working ground GND of the power-on.
  • a first pole of the third transistor T3 is connected to the high-level signal terminal VGH of the driving power source, and a second pole is connected to the first end of the first transistor T1, the first end of the first resistor R1, and the Output module 2.
  • the first pole of the fourth transistor T4 is connected to the low-level signal terminal VGL of the driving power source, and the second pole is connected to the second end of the first resistor R1, the first pole of the second transistor T2, and the Output module 2.
  • the first inverter When the signal input by the input signal terminal CLK_IN is 3.3V high level, the first inverter is passed.
  • the control signal output by N1 that is, the potential at point A is 0V.
  • the first transistor T1 and the fourth transistor T4 are turned on, and the second transistor T2 and the third transistor T3 are turned off.
  • the 3.3V voltage input to the working voltage terminal VIO of the power supply is turned through the first transistor T1 to reach the point B.
  • the potential is 3.3V. Since the fourth transistor T4 is turned on, the -8V voltage input from the low-level signal terminal VGL of the driving power source passes through the fourth transistor T4 to reach the point C. Therefore, the potential at point C is -8V, that is, -8V is transmitted to the output module 2 to control the output of the output module 2.
  • the control signal outputted through the first inverter N1 that is, the potential at point A is 3.3V.
  • the first transistor T1 and the fourth transistor T4 are turned off, and the second transistor T2 and the third transistor T3 are turned on.
  • the low side of the working power supply is grounded, and the input 0V voltage reaches the point C through the second transistor T2, and the potential of the point C is 0V.
  • the third transistor T3 Since the third transistor T3 is turned on, the 30V voltage input by the high-level signal terminal of the driving power source reaches the point B through the third transistor T3, so the potential of the point B is 30V, that is, 30V is transmitted to the output module 2 to control Output the output of module 2.
  • point A is the output node of the first inverter N1
  • point B and point C are the connection nodes of the logic control module 1 and the output module 2.
  • the output module 2 includes a fifth transistor T5 and a sixth transistor T6.
  • the fifth transistor T5 has a first switching characteristic
  • the sixth transistor T6 has a second switching characteristic.
  • the present disclosure should not be construed as being limited thereto, and those skilled in the art can design other settings as needed.
  • the fifth transistor T5 has a second switching characteristic
  • the sixth transistor T6 has a first switching characteristic.
  • the first pole of the fifth transistor T5 is connected to the signal output terminal CLK_OUT and the first pole of the sixth transistor T6, the second pole is connected to the output control module 3, and the control pole is connected to the logic control module. 1.
  • the first pole of the sixth transistor T6 is connected to the signal output terminal CLK_OUT, the second pole is connected to the output control module 3, and the control pole is connected to the logic control module 1.
  • the potential at point A is 0V
  • the output point at point B is the operating voltage at which the power source is turned on, that is, the above-mentioned 3.3V.
  • the potential at point C is a signal input from the low-level signal terminal VGL of the driving power source, that is, when the above-mentioned -8V, the fifth transistor T5 is turned on, and the sixth transistor T6 is turned off.
  • the potential at point A is 3.3V above, and the potential at point B is driven.
  • the signal input from the high-level signal terminal VGH of the power supply, that is, the above 30V, the potential at the C point is the working ground potential of the power-on, that is, when the voltage is 0V, the fifth transistor T5 is turned off, and the sixth transistor T6 is turned on.
  • the output control module 3 includes a seventh transistor T7 and an eighth transistor T8.
  • the seventh transistor T7 has a first switching characteristic
  • the eighth transistor T8 has a second switching characteristic.
  • the present disclosure should not be construed as being limited thereto, and those skilled in the art can design other settings as needed.
  • the seventh transistor T7 has a second switching characteristic
  • the eighth transistor T8 has a first switching characteristic.
  • the second pole of the seventh transistor T7 is connected to the high level signal terminal VGH of the driving power source, and the control pole is connected to the feedback module 4.
  • the second electrode of the eighth transistor T8 is connected to the low-level signal terminal VGL of the driving power source, and the control electrode is connected to the feedback module 4.
  • the seventh transistor T7 and the fifth transistor T5 have the same switching characteristics, when both are turned on, the signal input from the high-level signal terminal VGH of the driving power source passes through the seventh transistor T7 and the fifth transistor. After T5, it is output from the signal output terminal CLK_OUT. Since the eighth transistor T8 and the sixth transistor T6 have the same switching characteristics, when both are turned on, the signal input by the low-level signal terminal VGL of the driving power source passes through the eighth transistor T8 and the sixth transistor T6. The signal output terminal CLK_OUT is output.
  • the feedback module 4 includes a voltage comparator, an OR gate OR and a second inverter N2.
  • the first input end of the voltage comparator is connected to the first reference voltage terminal Vref1, the second input terminal is connected to the second reference voltage terminal Vref2, the third input terminal is connected to the signal output terminal CLK_OUT, and the output terminal is connected to the OR gate OR.
  • the first input is electrically connected.
  • the second input terminal of the OR gate OR is connected to the enable signal terminal EN, and the output terminal is connected to the input terminal of the second inverter N2.
  • the input end of the second inverter N2 is connected to the output control module 3, and the output end is also connected to the output control module 3.
  • the enable signal terminal EN inputs a high-level signal
  • the enable signal terminal EN inputs a low-level signal
  • the input signal of the OR gate is input to the high level of the enable signal
  • the other port is the high level or the low level of the input.
  • the high level that is, the potential at point D is high. If the output control module 3 is the output control module 3 including the seventh transistor T7 and the eighth transistor T8 described above, the high potential of the D point controls the eighth transistor T8 to be turned on, and the potential of the D point acts as the second inverse.
  • the voltage comparator in the feedback module 4 acquires the output of the signal output terminal CLK_OUT in real time, and outputs the voltage outputted from the signal output terminal CLK_OUT to the first reference voltage terminal Vref1 and the second reference voltage terminal Vref2.
  • the input first reference voltage and the second reference voltage are compared.
  • the control voltage comparator outputs a logic level signal, for example, outputs a low level signal.
  • the first input terminal of the OR gate is input with a low level, and the second input terminal is connected with the enable signal terminal EN.
  • the eighth transistor T8 is turned off, and the potential at point D becomes a high level through the second inverter N2, and at this time, the seventh transistor T7 is also turned off, thereby causing the output module 2 to output a high impedance state.
  • the control voltage comparator outputs a high level signal, at this time OR gate OR
  • the first input terminal inputs a high level, and the second input terminal is connected to the enable signal terminal EN to input a low level, and at this time, the OR output of the gate is a high level, that is, the potential at the D point is a high level, so the first The eight-transistor T8 is turned on, and the potential at point D becomes a low level through the second inverter N2, and at this time, the seventh transistor T7 is also turned on, so that the signal output terminal CLK_OUT maintains a normal output.
  • the level shifting unit in this embodiment further includes an enable signal generating module 5 for outputting a high level signal at the power-on time, and inputting the high-level signal through the enable signal terminal EN.
  • the feedback module 4 outputs a feedback signal to control the output control module 3 to be turned on.
  • the enable signal generating module 5 may include a second resistor R2, a ninth transistor T9, and a first capacitor C1.
  • the ninth transistor T9 has a second switching characteristic.
  • the first end of the second resistor R2 is connected to the high level signal terminal VGH of the driving power source, and the second end is connected to the enable signal terminal EN.
  • the first pole of the ninth transistor T9 is connected to the enable signal terminal EN, the second pole is connected to the low level signal terminal VGL of the driving power source, and the control pole is connected to the high level signal terminal VGH of the driving power source.
  • the first end of the first capacitor C1 is connected to the control electrode of the ninth transistor T9, The second end is connected to the low level signal terminal VGL of the driving power source.
  • the level shifting unit when the level shifting unit is powered on, since the first capacitor C1 needs to be charged, the potential of the control electrode of the ninth transistor T9 is low, and the ninth transistor T9 is turned off, and the high level signal of the driving power source is turned on.
  • the signal output from the terminal VGH is output from the enable signal terminal EN, that is, the enable signal terminal EN outputs a high level.
  • the potential of the control electrode of the ninth transistor T9 is high, and the ninth transistor T9 is turned on, and the signal output by the low-level signal terminal VGL of the driving power source is output from the enable signal terminal EN, that is, The enable signal terminal EN output goes low.
  • the present embodiment provides a level shift circuit including a plurality of level shifting units described in the first embodiment.
  • the preferred level shift circuit in this embodiment further includes a NOR gate NOR.
  • Each input end of the NOR gate NOR is respectively connected to an output end of a voltage comparator of each of the feedback modules 4, and an output end is connected to a first input end of an OR gate of each feedback module 4.
  • the enable signal terminal EN inputs a high-level signal, and at other times, the enable signal terminal EN inputs a low-level signal.
  • one input terminal (the second input terminal) of the OR gate inputs the enable signal high level, and the other input terminal (the first input terminal) inputs the high level or the low level.
  • Level, at this time, the output of the OR gate is high, that is, the potential of the D point is high. If the output control module 3 is the above-described output control module 3 including the seventh transistor T7 and the eighth transistor T8, the high potential of the D point controls the eighth transistor T8 to be turned on, and the potential of the D point serves as the second inverter.
  • the input signal of N2 at this time, the output of the second inverter N2 is at a low potential, and controls the seventh transistor T7 to be turned on. That is to say, at the time of power-on, the feedback module 4 is used to control the output control module 3 to be turned on. After the power-on time, the output control module 3 selects a signal input by the high-level signal terminal VGH or the low-level signal terminal VGL of the driving power source according to the states of the fifth transistor T5 and the sixth transistor T6 in the output module 2. Output.
  • the voltage comparator in the feedback module 4 acquires the output of the signal output terminal CLK_OUT in real time, and outputs the voltage outputted from the signal output terminal CLK_OUT to the first reference voltage terminal Vref1 and the second reference voltage terminal Vref2.
  • the input first reference voltage and the second reference voltage are compared.
  • the control voltage comparator outputs a logic level signal (ie, the first control signal), for example, outputs a high level signal, and the NOR gate NOR output is low level (ie, the second control signal).
  • the first input of the OR gate of each level shifting unit is connected to the NOR gate NOR, that is, the first input of the OR gate OR is input to the low level, or the second input of the OR gate is connected to the enable signal. End EN.
  • the enable signal terminal EN outputs a high level signal at the time of power-on, and the output signal at all other times is a low level, that is, the second input terminal of the OR gate OR inputs a low level, and the output is output at this time. Then, it is low level, that is, the potential of the D point is low level, so the eighth transistor T8 is turned off, and the potential of the D point is changed to the high level through the second inverter N2, and the seventh transistor T7 is also turned off.
  • the output module 2 of each potential offset circuit outputs a high impedance state.
  • the control voltage comparator outputs a low level signal (ie, the first Control signal), at this time the NOR gate NOR input is low level, and its output is high level (that is, the second control signal). Therefore, the first input terminal connected to each OR gate OR and the NOR gate NOR output terminal inputs a high level, and the second input terminal is connected to the enable signal terminal EN to input a low level, and the output is at a high level.
  • the eighth transistor T8 is turned on, and the potential of the D point is changed to the low level through the second inverter N2, and the seventh transistor T7 is also turned on, thereby making the signal output end CLK_OUT maintains a normal output.
  • the NOR gate NOR is added to the level shift circuit of the embodiment, at this time, as long as the voltage comparator of the feedback module 4 of one of the level shifting units outputs a high level, the output terminal of the NOR gate NOR The output is low, and the output of the NOR gate NOR is connected to the first input of the OR gate of the feedback module 4 of each level shifting unit, and the second input and the enable signal end of each OR gate EN is connected, and the enable signal terminal EN is high level except the signal output at the time of power-on, and the signals output at other times are all low level, that is, the second input of each NAND gate OR is low level.
  • the output terminal of the OR gate OR outputs a low level, and the seventh transistor T7 and the eighth transistor T8 in each level shifting unit are turned off, thereby cutting off the output of each level shifting unit, thereby ensuring the level shift.
  • This embodiment provides a driving method of a level shift circuit.
  • the level shifting circuit comprises a plurality of level shifting units in the first embodiment of the embodiment.
  • the driving method specifically includes the following steps.
  • the power-on output stage if the signal VIO input by the operating voltage terminal VIO of the power supply is turned on, the working ground is grounded.
  • the enable signal terminal EN inputs a high-level signal, and at other times, the enable signal terminal EN inputs a low-level signal. Therefore, at the power-on time, the input OR signal of the OR gate of the OR gate is high, and the other port is high or low regardless of the input. At this time, the output of the OR gate is high, that is, The potential at point D is high. At this time, the high potential of point D controls the eighth transistor T8 to be turned on, and the potential of point D serves as the input signal of the second inverter N2. At this time, the output of the second inverter N2 is Low potential and control the seventh transistor T7 to turn on.
  • the control signal outputted through the first inverter N1 that is, the potential of the point A is 0V, at which time the first transistor T1 and the fourth transistor T4 are turned on.
  • the second transistor T2 and the third transistor T3 are turned off.
  • the 3.3V voltage input to the operating voltage terminal VIO of the power supply through the first transistor T1 reaches the potential of point B at 3.3V.
  • the fourth transistor T4 is turned on, the -8V voltage input from the low-level signal terminal VGL of the driving power source reaches the point C through the fourth transistor T4, so the potential at the point C is -8V.
  • the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the high-level signal input by the high-level signal terminal VGH of the driving power source, that is, the 30V voltage is passed through the seventh transistor T7 and the fifth transistor T5, and the signal output terminal CLK_OUT output.
  • the control signal outputted through the first inverter N1 that is, the potential of the point A is 3.3V, at which time the first transistor T1 and the fourth transistor T4 are turned off.
  • the second transistor T2 and the third transistor T3 are turned on.
  • the low side of the working power supply is grounded, and the input 0V voltage reaches the point C through the second transistor T2, and the potential of the point C is 0V.
  • the third transistor T3 Since the third transistor T3 is turned on, the voltage of 30 V input from the high-level signal terminal VGH of the driving power source reaches the point B through the third transistor T3, so the potential at the point B is 30V.
  • the sixth transistor T6 is turned on, and the fifth transistor T5 is turned off, and the -8V voltage input from the low-level signal terminal VGL of the driving power source is output from the signal output terminal CLK_OUT via the eighth transistor T8 and the sixth transistor T6.
  • the voltage comparator in the feedback module 4 acquires the output of the signal output terminal CLK_OUT in real time, and outputs the voltage outputted from the signal output terminal CLK_OUT with the first reference voltage terminal Vref1 and the first reference voltage terminal Vref2 The reference voltage is compared with the second reference voltage. When the output voltage value is between the two, it indicates that the signal of the signal output terminal CLK_OUT is short-circuited with the output signal of the other level shifting unit, and at this time, the control voltage comparator outputs a logic level signal, such as an output.
  • the low level signal at this time, the first input of the OR gate is input to the low level, and the second input is connected to the enable signal terminal EN, so the low level is also input, and the output of the output of the OR gate is Low level, that is, the potential of the D point is low level, so the eighth transistor T8 is turned off, and the potential of the D point is changed to the high level through the second inverter N2, and the seventh transistor T7 is also turned off, thereby making The signal output terminal CLK_OUT outputs a high impedance state.
  • the control voltage comparator outputs a high level signal, at this time OR gate OR
  • the first input terminal inputs a high level
  • the second input terminal is connected to the enable signal terminal EN to input a low level, and the output is at a high level, that is, the D point potential is a high level, so the eighth transistor T8 When turned on, the potential at point D becomes a low level through the second inverter N2, and at this time, the seventh transistor T7 is also turned on, so that the signal output terminal CLK_OUT maintains a normal output.
  • the driving method of the level shifting circuit provided in this embodiment includes a feedback phase, that is, when the control voltage comparator outputs a logic level signal, for example, outputs a low level signal, at this time, the first input of the OR gate OR Input low level, the second input terminal is connected with the enable signal terminal EN, so the low level is also input.
  • the output of the output terminal of the gate OR is low level, that is, the potential of the D point is low level, so the eighth The transistor T8 is turned off, and the potential of the D point is changed to the high level through the second inverter N2, and the seventh transistor T7 is also turned off to cut off the output of the level shifting unit, thereby ensuring the level shift.
  • the working safety of the circuit is, when the control voltage comparator outputs a logic level signal, for example, outputs a low level signal, at this time, the first input of the OR gate OR Input low level, the second input terminal is connected with the enable signal terminal EN, so the low level is also input.
  • the present embodiment provides a driving method of a level shifting circuit, wherein the level shifting circuit includes a level shifting unit in a plurality of first embodiment of the embodiment, and a NOR gate NOR, and the driving method thereof
  • the third embodiment is substantially the same, with the difference being the feedback phase, so the description will not be repeated for the power-on output stage.
  • the feedback phase specifically includes:
  • the voltage comparator in the feedback module 4 acquires the output of the signal output terminal CLK_OUT in real time, and outputs the voltage outputted from the signal output terminal CLK_OUT to the first reference voltage terminal Vref1 and the second reference voltage terminal Vref2.
  • the input first reference voltage is compared with the second reference voltage.
  • the signal output terminal CLK_OUT is indicated.
  • the signal is short-circuited with the output signal of the other level shifting unit.
  • the control voltage comparator outputs a logic level signal (that is, the first control signal), for example, outputs a high level signal, and the NOR gate at this time
  • the NOR output is low level (that is, the second control signal)
  • the first input end of the OR gate of each level shifting unit is connected to the NOR gate NOR, that is, the input end inputs a low level
  • the two input terminals are connected to the enable signal terminal EN, and therefore also input a low level.
  • the output of the OR gate OR is outputted to a low level, that is, the potential of the D point is a low level, so the eighth transistor T8 is turned off.
  • the potential of the D point becomes a high level through the second inverter N2, and the seventh transistor T7 is also turned off, so that the signal output terminal CLK_OUT of each potential offset circuit outputs a high impedance state.
  • the control voltage comparator outputs a low level signal (ie, the first control) Signal), at this time the NOR input NOR input is low level, and its output is high level (that is, the second control signal), so the first connection of each OR gate OR and NOR NOR output end
  • the input terminal inputs a high level, and the second input terminal connected to the enable signal terminal EN inputs a low level, and the output is at a high level, that is, the potential at the D point is a high level, so the eighth transistor T8 is turned on.
  • the potential at point D goes low through the second inverter N2, at which time the seventh transistor
  • the driving method of the level shift circuit provided in this embodiment is as long as the voltage comparator of the feedback module 4 of one level shifting unit outputs a high level, and the output end of the NOT gate NOR outputs a low level.
  • the output of the NOR gate NOR is connected to the first input terminal of the OR gate of the feedback module 4 of each level shifting unit, and the second input end of each OR gate is connected to the enable signal terminal EN, so that The signal output from the signal terminal EN is high at the time of power-on, and the signals output at other times are all low, that is, the second input of each NAND gate OR is low, so OR gate OR
  • the output terminal outputs a low level, and turns off the seventh transistor T7 and the eighth transistor T8 in each level shifting unit, thereby cutting off the output of each level shifting unit, thereby ensuring the work of the level shifting circuit. safety.
  • This embodiment provides another gate driving circuit including the level shifting circuit in the second embodiment.
  • the gate driving circuit further includes other components such as a shift register, which will not be described one by one.
  • the gate driving circuit of the embodiment includes the above-described level shifting circuit, the performance is better and the security performance is superior.
  • the embodiment also provides a display device comprising any of the gate drive circuits as described above.
  • the display device provided by the sixth embodiment of the present disclosure may be any product or component having a display function such as a notebook computer display screen, a display, a television, a digital photo frame, a mobile phone, a tablet computer, or the like.

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Abstract

一种电平偏移单元包括逻辑控制模块（1）、输出模块（2）、输出控制模块（3）和反馈模块（4）。该逻辑控制模块（1），连接开启电源（VIO）、驱动电源（VGH和VGL）、输入信号端（CLK_IN），以及输出模块（2）。该反馈模块（4），连接使能信号端（EN）、信号输出端（CLK_OUT），以及输出控制模块（3）。该输出控制模块（3），连接输出模块（2）、驱动电源（VGH和VGL）。该输出模块（2），连接信号输出端（CLK_OUT）。该电平偏移单元的反馈模块（4）通过使能信号端（EN）和信号输出端（CLK_OUT）所输出的信号来控制输出模块（2）的开启或关断。如果两个电平偏移单元所输出的信号短路，则反馈模块（4）控制该电平偏移电路的输出控制模块（3）断开，以使输出模块（2）输出高阻态，进而避免栅极驱动器烧毁，出现安全隐患。

Description

电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路、显示装置
相关申请的交叉参考
本申请主张在2016年1月8日在中国提交的中国专利申请号No.201610013117.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本属于显示技术领域，具体涉及一种电平偏移单元、电平偏移电路及其驱动方法、栅极驱动电路、显示装置。
背景技术
目前最常见的平板显示装置包括液晶显示装置(LCD)和有机发光二极管显示装置(OLED)。在平板显示装置的显示区包括由交叉设置的栅线和数据线围成的多个像素区，在每一个像素驱动中均设置有控制显示的薄膜晶体管(TFT)。该薄膜晶体管通过位于非显示区的驱动单元的驱动，实现像素点的图像显示。驱动单元包括栅极驱动器和源极驱动器，其中栅极驱动器用于扫描并打开显示屏中隶属同一行的多通道RGB像素点，源极驱动器用于为打开的多通道RGB像素点提供显示数据。
栅极驱动器的时钟信号由电平偏移电路提供。电平偏移电路一般用于将输入的小幅值电平信号转换成用于驱动像素点(通过栅线与薄膜晶体管的栅极驱动)的大幅值电平信号。实际使用时，由于布线空间的限制，时钟信号线在布线时很可能出现线与线之间的交叉。一旦在线与线交叉的位置发生短接，在进行显示时，时钟信号就会发生短路。由于时钟信号的幅值大，造成的短路电流也较大，则会造成栅极驱动器中电流烧毁，从而使显示装置报废，甚至带来安全隐患的问题。
发明内容
(一)要解决的技术问题
本公开文本所要解决的技术问题在于，针对现有的电平偏移电路存在的 上述问题，提供一种安全性高的电平偏移单元、电平偏移电路及其驱动方法、栅极驱动电路、显示装置。
(二)技术方案
解决本公开文本技术问题所采用的技术方案是一种电平偏移单元，包括：逻辑控制模块、输出模块、输出控制模块和反馈模块。所述逻辑控制模块，连接开启电源、驱动电源、输入信号端，以及所述输出模块，用于生成与输入信号相反的控制信号，并根据所述控制信号选择与所述开启电源极性对应的所述驱动电源所输出的逻辑电平信号，将所述逻辑电平信号传输至所述输出模块。所述反馈模块，连接使能信号端、信号输出端，以及所述输出控制模块，用于根据所述使能信号端和所述信号输出端所输入的信号，输出反馈信号并传输给所述输出控制模块。所述输出控制模块，连接所述输出模块和所述驱动电源，用于根据所述反馈信号，控制所述驱动电源是否将其所输入的逻辑电平信号输出给所述输出模块。所述输出模块，连接所述信号输出端，用于在所述驱动电源所输出的逻辑电平信号和所述输出控制模块的控制下，控制所述信号输出端的输出。
在一个可行的实施例中，所述逻辑控制模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电阻，以及第一反相器。所述第一晶体管和所述第四晶体管具有第一开关特性，所述第二晶体管和所述第三晶体管具有第二开关特性。所述第一反相器的输入端连接所述输入信号端，输出端连接所述第一晶体管的控制极、所述第二晶体管的控制极、所述第三晶体管的控制极、所述第四晶体管的控制极。所述第一晶体管的第一极连接所述输出模块和所述第一电阻的第一端，第二极连接所述开启电源的开启电压端。所述第二晶体管的第一极连接所述第一电阻的第二端和所述输出模块，第二极连接所述开启电源的工作地端。所述第三晶体管的第一极连接所述驱动电源的高电平信号端，第二极连接所述第一晶体管的第一端、所述第一电阻的第一端和所述输出模块。所述第四晶体管的第一极连接所述驱动电源的低电平信号端，第二极连接所述第一电阻的第二端、所述第二晶体管的第一极和所述输出模块。
在一个可行的实施例中，所述输出模块包括第五晶体管和第六晶体管。 所述第五晶体管具有第一开关特性，所述第六晶体管具有第二开关特性。所述第五晶体管的第一极连接所述信号输出端和所述第六晶体管的第一极，第二极连接所述输出控制模块，控制极连接所述逻辑控制模块。所述第六晶体管的第一极连接所述信号输出端，第二极连接所述输出控制模块，控制极连接所述逻辑控制模块。
在一个可行的实施例中，所述输出控制模块包括第七晶体管和第八晶体管，所述第七晶体管具有第一开关特性，所述第八晶体管具有第二开关特性。所述第七晶体管的第二极连接所述驱动电源的高电平信号端，控制极连接所述反馈模块。所述第八晶体管的第二极连接所述驱动电源的低电平信号端，控制极连接所述反馈模块。
在一个可行的实施例中，所述反馈模块包括电压比较器、或门(OR)和第二反相器。所述电压比较器的第一输入端连接第一参考电压端，第二输入端连接第二参考电压端，第三输入端连接所述信号输出端，输出端与所述或门的第一输入端电性连接。所述或门的第二输入端连接所述使能信号端，输出端连接所述第二反相器的输入端。所述第二反相器的输入端连接所述输出控制模块，输出端也连接所述输出控制模块。
在一个可行的实施例中，所述电平偏移单元还包括：使能信号产生模块，用于在上电时刻输出高电平信号，通过所述使能信号端输入至所述反馈模块，所述反馈模块输出反馈信号，控制所述输出控制模块开启。
在一个可行的实施例中，所述使能信号产生模块包括：第二电阻、第九晶体管和第一电容。所述第九晶体管具有第二开关特性。所述第二电阻的第一端连接所述驱动电源的高电平信号端，第二端连接所述使能信号端。所述第九晶体管的第一极连接所述使能信号端，第二极连接所述驱动电源的低电平信号端，控制极连接所述驱动电源的高电平信号端。所述第一电容的第一端连接第九晶体管的控制极，第二端连接所述驱动电源的低电平信号端。
此外，解决本公开文本技术问题所采用的技术方案还提供了一种电平偏移电路，其包括多个上述的电平偏移单元。
在一个可行的实施例中，所述电平偏移单元包括电压比较器、或门和第二反相器，所述电平偏移电路还包括或非门(NOR)。所述或非门的各个输入 端分别连接每一个所述反馈模块的电压比较器的输出端，所述或非门的输出端连接各个所述反馈模块的或门的第一输入端。
此外，解决本公开文本技术问题所采用的技术方案还提供了一种电平偏移电路的驱动方法，所述电平偏移电路为上述的电平偏移电路，所述驱动方法包括：上电输出阶段：所述使能信号端输入使能信号，所述反馈模块根据该使能信号控制所述输出控制模块开启；所述逻辑控制模块根据所述输入信号端所输入的信号，生成与输入信号相反的控制信号，根据所述控制信号选择与开启电源极性对应的所述驱动电源所输入的逻辑电平信号，并将所述逻辑电平信号通过所述输出模块进行输出；以及反馈阶段：所述反馈模块根据所述电平偏移单元的信号输出端所输出的信号，控制所述输出控制模块开启或关断，以控制所述输出模块的输出。
在一个可行的实施例中，所述电平偏移单元包括电压比较器、或门和第二反相器，所述电平偏移电路还包括或非门。所述反馈阶段包括：各个所述电平偏移单元的反馈模块中的电压比较器均根据各自的所述信号输出端所输出的信号，输出第一控制信号给所述或非门，所述或非门根据各个所述反馈模块中的电压比较器输出的第一控制信号，输出第二控制信号，并通过各个所述反馈模块的或门和第二反相器控制所有的所述输出控制模块同时开启或同时关断，以控制所述输出模块的输出。
此外，解决本公开文本技术问题所采用的技术方案还提供了一种栅极驱动路，其包括上述的电平偏移电路。
(三)有益效果
本公开文本实施例至少具有如下有益效果：
在本公开文本所提供的电平偏移单元中，由于反馈模块通过使能信号端和信号输出端所输入的信号来控制输出模块的开启或关断，特别是在电平偏移电路中，假若其中两个电平偏移单元所输出的信号短路，必然会导致这两个电平偏移单元所输出的信号发生变化，反馈模块则可以根据此时所接收的信号输出端所输出的信号的大小与预设的电位进行比较，以判断出是否发生短路，当判断出哪一个电平偏移单元发生短路，则输出反馈信号控制该电平偏移电路的输出控制模块断开，以使输出模块输出高阻态，进而避免栅极驱 动器烧毁，出现安全隐患。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开文本的第一实施例所提供的电平偏移单元的示意图；
图2为本公开文本的第一实施例所提供的使能信号产生模块的示意图；
图3为本公开文本的第二实施例所提供的电平偏移电路的示意图；以及
图4为本公开文本的第三实施例所提供的电平偏移单元的工作时序图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本的专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开文本的各个实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件。由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开文本的各个实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型。以下实施例中是以具有第一开关特性的晶体管为P型晶体管，具有第二开关特性的晶体管为N型晶体管进行说明的。当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，当栅极输入高电平时，源漏极导通，P型相反。可以想到的是，采用具有第一开关特性的晶体管为N型晶体管，具有第二开关特性的晶体管为P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开文本实施例的保护范围内的。
下面将结合附图和实施例，对本公开文本的具体实施方式作进一步详细描述。以下各个实施例用于说明本公开文本，但不用来限制本公开文本的范围。
第一实施例
结合图1所示，本实施例提供一种电平偏移单元，包括：逻辑控制模块1、输出模块2、输出控制模块3和反馈模块4。其中，所述逻辑控制模块1，连接开启电源、驱动电源、输入信号端CLK_IN，以及输出模块2，用于生成与输入信号相反的控制信号，并根据所述控制信号选择与开启电源极性对应的所述驱动电源所输出的逻辑电平信号，将所述逻辑电平信号传输至所述输出模块2。所述反馈模块4，连接使能信号端EN、信号输出端CLK_OUT，以及输出控制模块3，用于根据所述使能信号端EN和所述信号输出端CLK_OUT所输入的信号，输出反馈信号并传输给输出控制模块3。所述输出控制模块3，连接输出模块2、驱动电源，用于根据所述反馈信号，控制所述驱动电源是否将其所输入的逻辑电平信号输出给输出控制模块3。所述输出模块2，连接信号输出端CLK_OUT，用于在所述驱动电源所输出的逻辑电平信号和所述输出控制模块3的控制下，控制所述信号输出端CLK_OUT的输出。
在本实施例的电平偏移单元中，由于反馈模块4能够使能信号端EN和信号输出端CLK_OUT所输入的信号来控制输出模块2的开启或关断，特别是在电平偏移电路中，假若其中两个电平偏移单元所输出的信号短路，必然会导致这两个电平偏移单元所输出的信号发生变化，因此反馈模块4则可以根据此时所接收的信号输出端CLK_OUT所输出的信号的大小与预设的电位进行比较，以判断出是否发生短路。当判断出哪一个电平偏移单元发生短路，则输出反馈信号控制该电平偏移电路的输出控制模块断开，以使输出模块2输出高阻态，进而避免栅极驱动器烧毁，出现安全隐患。
其中，逻辑控制模块1包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电阻R1，以及第一反相器N1。所述第一晶体管T1和所述第三晶体管T3具有第一开关特性，所述第二晶体管T2和所述第四晶体管T4具有第二开关特性。当然，本公开文本并不应该被理解为限制于此，本领域技术人员可以根据需要设计其他设置方式。例如，所述第一晶体管T1和所述第三晶体管T3具有第二开关特性，所述第二晶体管T2和所述第四晶体管T4具有第一开关特性。其中，所述第一反相器N1的输入端连接所述输入信号端CLK_IN，输出端连接第一晶体管T1的控制极、第二晶体管T2的控制极、第三晶体管T3的控制极、第四晶体管T4的控制极。所述第一晶体管T1的第一极连接所述输出模块2和所述电阻的第一端，第二极连接所述开启电源的开启电压端。所述第二晶体管T2的第一极连接所述第一电阻R1的第二端和所述输出模块2，第二极连接所述开启电源的工作地端GND。所述第三晶体管T3的第一极连接所述驱动电源的高电平信号端VGH，第二极连接所述第一晶体管T1的第一端、所述第一电阻R1的第一端和所述输出模块2。所述第四晶体管T4的第一极连接所述驱动电源的低电平信号端VGL，第二极连接所述第一电阻R1的第二端、所述第二晶体管T2的第一极和所述输出模块2。
具体的，假若开启电源的工作电压端VIO所输入的信号VIO＝3.3V，工作地端接地；驱动电源的高电平信号端VGH所输入的信号VGH＝30V，低电平信号端VGL所输入的信号VGL＝-8V。
当输入信号端CLK_IN所输入的信号为3.3V高电平时，经过第一反相器 N1输出的控制信号，即A点的电位为0V。此时第一晶体管T1和第四晶体管T4导通，第二晶体管T2和第三晶体管T3关断，此时开启电源的工作电压端VIO所输入的3.3V电压经过第一晶体管T1到达B点的电位为3.3V。由于第四晶体管T4打开，驱动电源的低电平信号端VGL所输入的-8V电压经过第四晶体管T4到达C点。所以C点的电位为-8V，也就是说将-8V传输给输出模块2，以控制输出模块2的输出。
当输入信号端CLK_IN所输入的信号为0V低电平时，经过第一反相器N1输出的控制信号，即A点的电位为3.3V。此时第一晶体管T1和第四晶体管T4关断，第二晶体管T2和第三晶体管T3导通。此时开启电源的工作低端接地，输入的0V电压经过第二晶体管T2到达C点，C点的电位为0V。由于第三晶体管T3打开，驱动电源的高电平信号端所输入的30V电压经过第三晶体管T3到达B点，所以B点的电位为30V，也就是说将30V传输给输出模块2，以控制输出模块2的输出。
在此需要说明的是，A点为第一反相器N1的输出节点，B点和C点均为逻辑控制模块1与输出模块2的连接节点。
其中，输出模块2包括第五晶体管T5和第六晶体管T6。所述第五晶体管T5具有第一开关特性，所述第六晶体管T6具有第二开关特性。当然，本公开文本并不应该被理解为限制于此，本领域技术人员可以根据需要设计其他设置方式。例如，所述第五晶体管T5具有第二开关特性，所述第六晶体管T6具有第一开关特性。其中，所述第五晶体管T5的第一极连接所述信号输出端CLK_OUT和所述第六晶体管T6的第一极，第二极连接所述输出控制模块3，控制极连接所述逻辑控制模块1。所述第六晶体管T6的第一极连接所述信号输出端CLK_OUT，第二极连接所述输出控制模块3，控制极连接所述逻辑控制模块1。
具体的，当输入信号端CLK_IN输入3.3V高电平时，A点电位为0V，B点输出的为开启电源的工作电压时，也就是上述的3.3V。C点电位为驱动电源的低电平信号端VGL输入的信号，也就是上述的-8V时，第五晶体管T5导通，第六晶体管T6关断。
当输入信号为0V低电平时，A点电位为上述的3.3V，B点的电位为驱 动电源的高电平信号端VGH输入的信号，也就是上述的30V，C点电位为开启电源的工作地端电位，即0V时，第五晶体管T5关断，第六晶体管T6导通。
其中，输出控制模块3包括第七晶体管T7和第八晶体管T8。所述第七晶体管T7具有第一开关特性，所述第八晶体管T8具有第二开关特性。当然，本公开文本并不应该被理解为限制于此，本领域技术人员可以根据需要设计其他设置方式。例如，所述第七晶体管T7具有第二开关特性，所述第八晶体管T8具有第一开关特性。其中，所述第七晶体管T7的第二极连接所述驱动电源的高电平信号端VGH，控制极连接所述反馈模块4。所述第八晶体管T8的第二极连接所述驱动电源的低电平信号端VGL，控制极连接所述反馈模块4。
具体的，由于第七晶体管T7和第五晶体管T5具有相同的开关特性，因此当两者均导通时，驱动电源的高电平信号端VGH所输入的信号通过第七晶体管T7和第五晶体管T5之后从信号输出端CLK_OUT输出。由于第八晶体管T8和第六晶体管T6具有相同的开关特性，因此当两者均导通时，驱动电源的低电平信号端VGL所输入的信号通过第八晶体管T8和第六晶体管T6之后从信号输出端CLK_OUT输出。
其中，反馈模块4包括电压比较器、或门OR和第二反相器N2。所述电压比较器的第一输入端连接第一参考电压端Vref1，第二输入端连接第二参考电压端Vref2，第三输入端连接所述信号输出端CLK_OUT，输出端与所述或门OR的第一输入端电性连接。所述或门OR的第二输入端连接使能信号端EN，输出端连接第二反相器N2的输入端。所述第二反相器N2的输入端连接输出控制模块3，输出端也连接输出控制模块3。
具体的，在上电时刻使能信号端EN输入高电平信号，其它时刻使能信号端EN输入的均是低电平信号。在本实施例中，在上电时刻，或门OR一个输入端输入使能信号高电平，另一个端口无论输入的是高电平还是低电平，此时或门OR的输出端均为高电平，也就是D点的电位为高电位。假若输出控制模块3就是上述的包括第七晶体管T7和第八晶体管T8的输出控制模块3，此时D点的高电位控制第八晶体管T8导通，同时D点的电位作为第二反 相器N2的输入信号，此时第二反相器N2的输出为低电位，并控制第七晶体管T7开启。也就是说在上电时刻反馈模块4用于控制输出控制模块3开启。在上电时刻之后，输出控制模块3则根据输出模块2中第五晶体管T5和第六晶体管T6的状态选择将驱动电源的高电平信号端VGH或者低电平信号端VGL所输入的信号进行输出。在进入正常的输出状态之后，反馈模块4中的电压比较器实时采集信号输出端CLK_OUT的输出，并将信号输出端CLK_OUT所输出的电压与其第一参考电压端Vref1和第二参考电压端Vref2上所输入的第一参考电压和第二参考电压进行比较。当所输出的电压值在两者之间时，则说明信号输出端CLK_OUT的信号与其他电平偏移单元的输出信号发生了短路。此时，控制电压比较器输出一个逻辑电平信号，例如输出低电平信号，此时或门OR的第一输入端，则输入低电平，第二输入端与使能信号端EN连接，也输入低电平，此时输出则为低电平，即D点电位为低电平。因此第八晶体管T8关断，D点电位经过第二反相器N2变为高电平，此时第七晶体管T7也是关断的，从而使得输出模块2输出高阻态。当然，如果信号输出端CLK_OUT的输出信号不在第一参考电压和第二参考电压之间，也就是说信号输出端CLK_OUT输出正常，此时控制电压比较器输出高电平信号，此时或门OR的第一输入端输入高电平，第二输入端与使能信号端EN连接则输入低电平，此时或门OR输出则为高电平，即D点电位为高电平，因此第八晶体管T8导通，D点电位经过第二反相器N2变为低电平，此时第七晶体管T7也是导通的，从而使得信号输出端CLK_OUT保持正常的输出。
如图2所示，其中，本实施例中的电平偏移单元还包括使能信号产生模块5，用于在上电时刻输出高电平信号，通过所述使能信号端EN输入至所述反馈模块4，所述反馈模块4输出反馈信号，控制所述输出控制模块3开启。
例如，如图2所示，使能信号产生模块5可包括：第二电阻R2、第九晶体管T9和第一电容C1。所述第九晶体管T9具有第二开关特性。其中，所述第二电阻R2的第一端连接所述驱动电源的高电平信号端VGH，第二端连接所述使能信号端EN。所述第九晶体管T9的第一极连接所述使能信号端EN，第二极连接所述驱动电源的低电平信号端VGL，控制极连接所述驱动电源的高电平信号端VGH。所述第一电容C1的第一端连接第九晶体管T9的控制极， 第二端连接所述驱动电源的低电平信号端VGL。
具体的，在电平偏移单元上电时，由于第一电容C1需要充电，此时第九晶体管T9的控制极的电位为低电位，第九晶体管T9关断，驱动电源的高电平信号端VGH输出的信号从使能信号端EN输出，即，使能信号端EN输出高电平。待第一电容C1充电完毕，第九晶体管T9的控制极的电位为高电位，第九晶体管T9导通，驱动电源的低电平信号端VGL输出的信号从使能信号端EN输出，即，使能信号端EN输出变为低电平。
第二实施例
如图1和图3所示，本实施例提供一种电平偏移电路，其包括多个第一实施例中所述的电平偏移单元。
其中，当反馈模块4包括电压比较器、或门OR和第二反相器N2时，本实施例中优选的电平偏移电路还包括或非门NOR。其中，所述或非门NOR的各个输入端分别连接每一个所述反馈模块4的电压比较器的输出端，输出端连接各个反馈模块4的或门OR的第一输入端。
具体的，在上电时刻，使能信号端EN输入高电平信号，在其它时刻，使能信号端EN输入的均是低电平信号。在本实施例中，在上电时刻，或门OR一个输入端(第二输入端)输入使能信号高电平，另一个输入端(第一输入端)无论输入的是高电平还是低电平，此时或门OR的输出端均为高电平，也就是D点的电位为高电位。假若输出控制模块3就是上述的包括第七晶体管T7和第八晶体管T8的输出控制模块3，此时D点的高电位控制第八晶体管T8导通，同时D点的电位作为第二反相器N2的输入信号，此时第二反相器N2的输出为低电位，并控制第七晶体管T7导通。也就是说，在上电时刻，反馈模块4用于控制输出控制模块3开启。在上电时刻之后，输出控制模块3则根据输出模块2中第五晶体管T5和第六晶体管T6的状态选择将驱动电源的高电平信号端VGH或者低电平信号端VGL所输入的信号进行输出。在进入正常的输出状态之后，反馈模块4中的电压比较器实时采集信号输出端CLK_OUT的输出，并将信号输出端CLK_OUT所输出的电压与其第一参考电压端Vref1和第二参考电压端Vref2上所输入的第一参考电压和第二参考电压进行比较。当所输出的电压值在两者之间时，则说明信号输出端CLK_OUT 的信号与其他电平偏移单元的输出信号发生了短路。此时，控制电压比较器输出一个逻辑电平信号(也即第一控制信号)，例如输出高电平信号，此时或非门NOR输出为低电平(也即第二控制信号)。每个电平偏移单元的或门OR的第一输入端均与或非门NOR连接，也就是或门OR第一输入端输入低电平，或门OR的第二输入端连接使能信号端EN。而使能信号端EN除上电时刻输出的信号为高电平，其他时刻均输出的信号均为低电平，也就是说，或门OR的第二输入端输入低电平，此时输出则为低电平，即D点电位为低电平，因此第八晶体管T8关断，D点电位经过第二反相器N2变为高电平，此时第七晶体管T7也是关断的，从而使得各个电位偏移电路的输出模块2输出高阻态。当然，如果信号输出端CLK_OUT的输出信号不在第一参考电压和第二参考电压之间，也就是说，信号输出端CLK_OUT输出正常，此时控制电压比较器输出低电平信号(也即第一控制信号)，此时或非门NOR输入端均为低电平，其输出则为高电平(也即第二控制信号)。因此每个或门OR与或非门NOR输出端连接的第一输入端则输入高电平，第二输入端与使能信号端EN连接则输入低电平，此时输出则为高电平，即D点电位为高电平，因此第八晶体管T8导通，D点电位经过第二反相器N2变为低电平，此时第七晶体管T7也是导通的，从而使得信号输出端CLK_OUT保持正常的输出。
由于在本实施例的电平偏移电路中增加了或非门NOR，此时只要其中一个电平偏移单元的反馈模块4的电压比较器输出高电平，或非门NOR的输出端则输出低电平，而或非门NOR的输出端又与各个电平偏移单元的反馈模块4的或门OR的第一输入端连接，而各个或门的第二输入端与使能信号端EN连接，而使能信号端EN除上电时刻输出的信号为高电平，其他时刻均输出的信号均为低电平，也就是说各个或非门OR的第二输入端低电平，因此或门OR的输出端输出低电平，将各个电平偏移单元中的第七晶体管T7和第八晶体管T8关断，从而切断各个电平偏移单元的输出，从而保证了电平偏移电路的工作安全性。
第三实施例
本实施例提供了一种电平偏移电路的驱动方法。其中，电平偏移电路包括实施例多个第一实施例中电平偏移单元。驱动方法具体包括如下步骤。
参照图1和图4所示，上电输出阶段：假若开启电源的工作电压端VIO所输入的信号VIO＝3.3V，工作地端接地。驱动电源的高电平信号端VGH所输入的信号VGH＝30V，低电平信号端VGL所输入的信号VGL＝-8V。
在上电时刻，使能信号端EN输入高电平信号，其它时刻使能信号端EN输入的均是低电平信号。因此上电时刻，或门OR一个输入端输入使能信号高电平，另一个端口无论输入的是高电平还是低电平，此时或门OR的输出端均为高电平，也就是D点的电位为高电位，此时D点的高电位控制第八晶体管T8导通，同时D点的电位作为第二反相器N2的输入信号，此时第二反相器N2的输出为低电位，并控制第七晶体管T7开启。
当输入信号端CLK_IN所输入的信号为3.3V的高电平时，经过第一反相器N1输出的控制信号，即A点的电位为0V，此时第一晶体管T1和第四晶体管T4导通，第二晶体管T2和第三晶体管T3关断。此时开启电源的工作电压端VIO所输入的3.3V电压经过第一晶体管T1到达B点的电位为3.3V。由于第四晶体管T4打开，驱动电源的低电平信号端VGL所输入的-8V电压经过第四晶体管T4到达C点，所以C点的电位为-8V。故第五晶体管T5导通，第六晶体管T6关断，驱动电源的高电平信号端VGH所输入的高点平信号，即30V电压经由第七晶体管T7、第五晶体管T5，从信号输出端CLK_OUT输出。
当输入信号端CLK_IN所输入的信号为0V的低电平时，经过第一反相器N1输出的控制信号，即A点的电位为3.3V，此时第一晶体管T1和第四晶体管T4关断，第二晶体管T2和第三晶体管T3导通。此时开启电源的工作低端接地，输入的0V电压经过第二晶体管T2到达C点，C点的电位为0V。由于第三晶体管T3打开，驱动电源的高电平信号端VGH所输入的30V电压经过第三晶体管T3到达B点，所以B点的电位为30V。此时第六晶体管T6导通，第五晶体管T5关断，驱动电源的低电平信号端VGL所输入的-8V电压经由第八晶体管T8、第六晶体管T6，从信号输出端CLK_OUT输出。
反馈阶段：反馈模块4中的电压比较器实时采集信号输出端CLK_OUT的输出，并将信号输出端CLK_OUT所输出的电压与第一参考电压端Vref1和第二参考电压端Vref2上所输入的第一参考电压和第二参考电压进行比较。 当所输出的电压值在两者之间时，则说明信号输出端CLK_OUT的信号与其他电平偏移单元的输出信号发生了短路，此时，控制电压比较器输出一个逻辑电平信号，例如输出低电平信号，此时或门OR的第一输入端输入低电平，第二输入端与使能信号端EN连接，因此也输入低电平，此时或门OR的输出端的输出则为低电平，即D点电位为低电平，因此第八晶体管T8关断，D点电位经过第二反相器N2变为高电平，此时第七晶体管T7也是关断的，从而使得信号输出端CLK_OUT输出高阻态。当然，如果信号输出端CLK_OUT的输出信号不在第一参考电压和第二参考电压之间，也就是说信号输出端CLK_OUT输出正常，此时控制电压比较器输出高电平信号，此时或门OR的第一输入端输入高电平，第二输入端与使能信号端EN连接则输入低电平，此时输出则为高电平，即D点电位为高电平，因此第八晶体管T8导通，D点电位经过第二反相器N2变为低电平，此时第七晶体管T7也是导通的，从而使得信号输出端CLK_OUT保持正常的输出。
本实施例所提供的电平偏移电路的驱动方法，由于包括反馈阶段，即当控制电压比较器输出一个逻辑电平信号，例如输出低电平信号，此时或门OR的第一输入端输入低电平，第二输入端与使能信号端EN连接，因此也输入低电平，此时门OR的输出端的输出则为低电平，即D点电位为低电平，因此第八晶体管T8关断，D点电位经过第二反相器N2变为高电平，此时第七晶体管T7也是关断的，以切断该电平偏移单元的输出，从而保证了电平偏移电路的工作安全性。
第四实施例
本实施例提供了一种电平偏移电路的驱动方法，其中，电平偏移电路包括实施例多个第一实施例中电平偏移单元，以及一个或非门NOR，其驱动方法与第三实施例大致相同，区别在于反馈阶段，故对于上电输出阶段不再重复描述。其中，反馈阶段具体包括：
参照图3和4所示，反馈模块4中的电压比较器实时采集信号输出端CLK_OUT的输出，并将信号输出端CLK_OUT所输出的电压与其第一参考电压端Vref1和第二参考电压端Vref2上所输入的第一参考电压和第二参考电压进行比较，当所输出的电压值在两者之间时，则说明信号输出端CLK_OUT 的信号与其他电平偏移单元的输出信号发生了短路，此时，控制电压比较器输出一个逻辑电平信号(也即第一控制信号)，例如输出高电平信号，此时或非门NOR输出为低电平(也即第二控制信号)，每个电平偏移单元的或门OR的第一输入端均与或非门NOR连接，也就是该输入端输入低电平，第二输入端与使能信号端EN连接，因此也输入低电平，此时或门OR的输出端则输出则为低电平，即D点电位为低电平，因此第八晶体管T8关断，D点电位经过第二反相器N2变为高电平，此时第七晶体管T7也是关断的，从而使得各个电位偏移电路的信号输出端CLK_OUT输出高阻态。当然，如果信号输出端CLK_OUT的输出信号不在第一参考电压和第二参考电压之间，也就是说信号输出端CLK_OUT输出正常，此时控制电压比较器输出低电平信号(也即第一控制信号)，此时或非门NOR输入端均为低电平，其输出则为高电平(也即第二控制信号)，因此每个或门OR与或非门NOR输出端连接的第一输入端输入高电平，与使能信号端EN连接的第二输入端则输入低电平，此时输出则为高电平，即D点电位为高电平，因此第八晶体管T8导通，D点电位经过第二反相器N2变为低电平，此时第七晶体管T7也是导通的，从而使得信号输出端CLK_OUT保持正常的输出。
本实施例中所提供的电平偏移电路的驱动方法，只要其中一个电平偏移单元的反馈模块4的电压比较器输出高电平，或非门NOR的输出端则输出低电平，而或非门NOR的输出端又与各个电平偏移单元的反馈模块4的或门OR的第一输入端连接，而各个或门的第二输入端与使能信号端EN连接，而使能信号端EN除上电时刻输出的信号为高电平，其他时刻均输出的信号均为低电平，也就是说各个或非门OR的第二输入端低电平，因此或门OR的输出端输出低电平，将各个电平偏移单元中的第七晶体管T7和第八晶体管T8的关断，从而切断各个电平偏移单元的输出，从而保证了电平偏移电路的工作安全性。
第五实施例
本实施例提供了另一种栅极驱动电路，其包括第二实施例中的电平偏移电路，当然该栅极驱动电路还包括移位寄存器等其它部件，在此不再一一描述。
由于本实施例的栅极驱动电路包括上述的电平偏移电路，因此其性能较好，具有较优的安全性能。
第六实施例
本实施例还提供了一种显示装置，其包括如上所述的任一种栅极驱动电路。
本公开文本的第六实施例所提供的显示装置可以是笔记本电脑显示屏、显示器、电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开文本的原理而采用的示例性实施方式，然而本公开文本并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开文本的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开文本的保护范围。

Claims (13)

  1. 一种电平偏移单元，包括：逻辑控制模块、输出模块、输出控制模块和反馈模块；其中，
    所述逻辑控制模块，连接开启电源、驱动电源、输入信号端，以及所述输出模块，用于生成与输入信号相反的控制信号，并根据所述控制信号选择与所述开启电源极性对应的所述驱动电源所输出的逻辑电平信号，将所述逻辑电平信号传输至所述输出模块；
    所述反馈模块，连接使能信号端、信号输出端，以及所述输出控制模块，用于根据所述使能信号端和所述信号输出端所输入的信号，输出反馈信号并传输给所述输出控制模块；
    所述输出控制模块，连接所述输出模块和所述驱动电源，用于根据所述反馈信号，控制所述驱动电源是否将其所输入的逻辑电平信号输出给所述输出模块；并且
    所述输出模块，连接所述信号输出端，用于在所述驱动电源所输出的逻辑电平信号和所述输出控制模块的控制下，控制所述信号输出端的输出。
  2. 根据权利要求1所述的电平偏移单元，其中，所述逻辑控制模块包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电阻，以及第一反相器；所述第一晶体管和所述第四晶体管具有第一开关特性，所述第二晶体管和所述第三晶体管具有第二开关特性；其中，
    所述第一反相器的输入端连接所述输入信号端，输出端连接所述第一晶体管的控制极、所述第二晶体管的控制极、所述第三晶体管的控制极、所述第四晶体管的控制极；
    所述第一晶体管的第一极连接所述输出模块和所述第一电阻的第一端，第二极连接所述开启电源的开启电压端；
    所述第二晶体管的第一极连接所述第一电阻的第二端和所述输出模块，第二极连接所述开启电源的工作地端；
    所述第三晶体管的第一极连接所述驱动电源的高电平信号端，第二极连接所述第一晶体管的第一端、所述第一电阻的第一端和所述输出模块；并且
    所述第四晶体管的第一极连接所述驱动电源的低电平信号端，第二极连接所述第一电阻的第二端、所述第二晶体管的第一极和所述输出模块。
  3. 根据权利要求1或2所述的电平偏移单元，其中，所述输出模块包括第五晶体管和第六晶体管；所述第五晶体管具有第一开关特性，所述第六晶体管具有第二开关特性；其中，
    所述第五晶体管的第一极连接所述信号输出端和所述第六晶体管的第一极，第二极连接所述输出控制模块，控制极连接所述逻辑控制模块；
    所述第六晶体管的第一极连接所述信号输出端，第二极连接所述输出控制模块，控制极连接所述逻辑控制模块。
  4. 根据权利要求1至3中任意一项所述的电平偏移单元，其中，所述输出控制模块包括第七晶体管和第八晶体管，所述第七晶体管具有第一开关特性，所述第八晶体管具有第二开关特性；其中，
    所述第七晶体管的第二极连接所述驱动电源的高电平信号端，控制极连接所述反馈模块；
    所述第八晶体管的第二极连接所述驱动电源的低电平信号端，控制极连接所述反馈模块。
  5. 根据权利要求1至4中任意一项所述的电平偏移单元，其中，所述反馈模块包括电压比较器、或门(OR)和第二反相器；其中，
    所述电压比较器的第一输入端连接第一参考电压端，第二输入端连接第二参考电压端，第三输入端连接所述信号输出端，输出端与所述或门的第一输入端电性连接；
    所述或门的第二输入端连接所述使能信号端，输出端连接所述第二反相器的输入端；
    所述第二反相器的输入端连接所述输出控制模块，输出端也连接所述输出控制模块。
  6. 根据权利要求1至5中任意一项所述的电平偏移单元，其中，所述电平偏移单元还包括：使能信号产生模块，用于在上电时刻输出高电平信号，通过所述使能信号端输入至所述反馈模块，所述反馈模块输出反馈信号，控制所述输出控制模块开启。
  7. 根据权利要求6所述的电平偏移单元，其中，所述使能信号产生模块包括：第二电阻、第九晶体管和第一电容；所述第九晶体管具有第二开关特性，其中，
    所述第二电阻的第一端连接所述驱动电源的高电平信号端，第二端连接所述使能信号端；
    所述第九晶体管的第一极连接所述使能信号端，第二极连接所述驱动电源的低电平信号端，控制极连接所述驱动电源的高电平信号端；并且
    所述第一电容的第一端连接第九晶体管的控制极，第二端连接所述驱动电源的低电平信号端。
  8. 一种电平偏移电路，包括：
    多个根据权利要求1-7中任意一项所述的电平偏移单元。
  9. 根据权利要求8所述的电平偏移电路，其中，所述电平偏移单元为权利要求5所述的电平偏移单元，所述电平偏移电路还包括或非门(NOR)；其中，
    所述或非门的各个输入端分别连接每一个所述反馈模块的电压比较器的输出端，所述或非门的输出端连接各个所述反馈模块的或门的第一输入端。
  10. 一种电平偏移电路的驱动方法，其中，所述电平偏移电路为权利要求8或9所述的电平偏移电路，所述驱动方法包括：
    上电输出阶段：所述使能信号端输入使能信号，所述反馈模块根据该使能信号控制所述输出控制模块开启；所述逻辑控制模块根据所述输入信号端所输入的信号，生成与输入信号相反的控制信号，根据所述控制信号选择与开启电源极性对应的所述驱动电源所输入的逻辑电平信号，并将所述逻辑电平信号通过所述输出模块进行输出；以及
    反馈阶段：所述反馈模块根据所述电平偏移单元的信号输出端所输出的信号，控制所述输出控制模块开启或关断，以控制所述输出模块的输出。
  11. 根据权利要求10所述的电平偏移电路的驱动方法，其中，所述电平偏移电路为权利要求9所述的电平偏移电路，所述反馈阶段包括：
    各个所述电平偏移单元的反馈模块中的电压比较器均根据各自的所述信号输出端所输出的信号，输出第一控制信号给所述或非门，所述或非门根据 各个所述反馈模块中的电压比较器输出的第一控制信号，输出第二控制信号，并通过各个所述反馈模块的或门和第二反相器控制所有的所述输出控制模块同时开启或同时关断，以控制所述输出模块的输出。
  12. 一种栅极驱动电路，包括：
    根据权利要求8或9所述的电平偏移电路。
  13. 一种显示装置，包括：
    根据权利要求12所述的栅极驱动电路。
PCT/CN2016/095949 2016-01-08 2016-08-19 电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路、显示装置 WO2017118034A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962119A (zh) * 2018-08-01 2018-12-07 京东方科技集团股份有限公司 电平转移电路及其驱动方法、显示装置

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105139824B (zh) * 2015-10-16 2018-02-06 重庆京东方光电科技有限公司 栅极驱动器及其配置***和调节配置方法
CN105680845A (zh) * 2016-01-04 2016-06-15 京东方科技集团股份有限公司 一种电平转换电路、电平转换方法及相关装置
CN105632438B (zh) 2016-01-08 2017-12-08 京东方科技集团股份有限公司 电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路
CN106409263B (zh) * 2016-11-29 2020-05-22 海信视像科技股份有限公司 液晶面板及其线路短路保护方法
CN106603096B (zh) * 2016-12-16 2018-12-28 湖南基石通信技术有限公司 一种宽带射频发射控制方法、电路及通信设备
CN107483045B (zh) * 2017-07-20 2020-02-14 深圳市华星光电半导体显示技术有限公司 一种电平位移电路及显示装置
CN111176366B (zh) * 2018-11-13 2022-07-08 合肥格易集成电路有限公司 一种宽压存储器电流镜电路
CN109360520B (zh) 2018-11-29 2020-11-24 惠科股份有限公司 检测电路和扫描驱动电路
CN109640448B (zh) * 2018-12-25 2024-02-13 中山市卓越制品有限公司 一种恒流反馈控制电路
CN110995223B (zh) * 2019-12-10 2023-07-21 华润微集成电路(无锡)有限公司 驱动控制电路
TWI753369B (zh) * 2020-02-26 2022-01-21 盛群半導體股份有限公司 電壓監控裝置
CN112953504B (zh) * 2021-02-01 2024-03-19 南京国微电子有限公司 电平转换电路
CN112947282B (zh) * 2021-03-08 2023-06-20 电子科技大学 一种应用于电源门控fpga结构中的新型隔离单元
CN113707105B (zh) * 2021-08-18 2022-08-23 Tcl华星光电技术有限公司 延迟电路及电压控制芯片
CN113726319B (zh) * 2021-08-27 2024-06-04 上海金脉电子科技有限公司 功率半导体的驱动电路及功率半导体器件
CN114882821A (zh) * 2022-03-24 2022-08-09 Tcl华星光电技术有限公司 驱动电路及显示装置
CN117912507A (zh) * 2022-10-12 2024-04-19 长鑫存储技术有限公司 电源控制电路及存储器

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087852A (en) * 1997-12-19 2000-07-11 Texas Instruments Incorporated Multiplexing a single output node with multiple output circuits with varying output voltages
CN1316827A (zh) * 2000-03-14 2001-10-10 夏普株式会社 电平偏移通过门电路
US20060158421A1 (en) * 2004-12-20 2006-07-20 Kabushiki Kaisha Toshiba Driver circuit of display device and method of driving the same
JP2011181626A (ja) * 2010-02-26 2011-09-15 Sharp Corp ヒューズ制御回路、ヒューズ制御システム、照度センサ、近接センサ、携帯電話、デジタルスチルカメラ、および電源回路
CN102768825A (zh) * 2011-05-03 2012-11-07 瑞鼎科技股份有限公司 显示驱动器及画面闪烁抑制装置
CN104078966A (zh) * 2014-07-14 2014-10-01 余姚市劲仪仪表厂 一种低阻抗限流式抗高压保护电路
CN105632438A (zh) * 2016-01-08 2016-06-01 京东方科技集团股份有限公司 电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI256771B (en) * 2002-03-27 2006-06-11 Ind Tech Res Inst Capacitance coupling acceleration device
GB2397710A (en) * 2003-01-25 2004-07-28 Sharp Kk A shift register for an LCD driver, comprising reset-dominant RS flip-flops
TWI270042B (en) * 2003-10-24 2007-01-01 Au Optronics Corp Clock signal amplifying method and driving stage for LCD driving circuit
US7312636B2 (en) * 2006-02-06 2007-12-25 Mosaid Technologies Incorporated Voltage level shifter circuit
US7804327B2 (en) * 2007-10-12 2010-09-28 Mediatek Inc. Level shifters
US20090206878A1 (en) * 2008-02-14 2009-08-20 Himax Technologies Limited Level shift circuit for a driving circuit
US8598916B2 (en) * 2010-06-18 2013-12-03 Freescale Semiconductor, Inc. Circuit having gate drivers having a level shifter
JP5581957B2 (ja) * 2010-10-08 2014-09-03 ソニー株式会社 レベル変換回路および表示装置、並びに電子機器
KR101350545B1 (ko) * 2012-05-31 2014-01-13 삼성전기주식회사 레벨 변환 회로 및 그를 포함하는 게이트 드라이버 회로
US8975943B2 (en) * 2013-05-29 2015-03-10 Silanna Semiconductor U.S.A., Inc. Compact level shifter

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087852A (en) * 1997-12-19 2000-07-11 Texas Instruments Incorporated Multiplexing a single output node with multiple output circuits with varying output voltages
CN1316827A (zh) * 2000-03-14 2001-10-10 夏普株式会社 电平偏移通过门电路
US20060158421A1 (en) * 2004-12-20 2006-07-20 Kabushiki Kaisha Toshiba Driver circuit of display device and method of driving the same
JP2011181626A (ja) * 2010-02-26 2011-09-15 Sharp Corp ヒューズ制御回路、ヒューズ制御システム、照度センサ、近接センサ、携帯電話、デジタルスチルカメラ、および電源回路
CN102768825A (zh) * 2011-05-03 2012-11-07 瑞鼎科技股份有限公司 显示驱动器及画面闪烁抑制装置
CN104078966A (zh) * 2014-07-14 2014-10-01 余姚市劲仪仪表厂 一种低阻抗限流式抗高压保护电路
CN105632438A (zh) * 2016-01-08 2016-06-01 京东方科技集团股份有限公司 电平偏移单元、电平偏移电路及驱动方法、栅极驱动电路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962119A (zh) * 2018-08-01 2018-12-07 京东方科技集团股份有限公司 电平转移电路及其驱动方法、显示装置

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