WO2017094095A1 - 突入電流防止回路 - Google Patents
突入電流防止回路 Download PDFInfo
- Publication number
- WO2017094095A1 WO2017094095A1 PCT/JP2015/083689 JP2015083689W WO2017094095A1 WO 2017094095 A1 WO2017094095 A1 WO 2017094095A1 JP 2015083689 W JP2015083689 W JP 2015083689W WO 2017094095 A1 WO2017094095 A1 WO 2017094095A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- voltage
- bypass
- inrush current
- prevention circuit
- current prevention
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Definitions
- the present invention relates to an inrush current preventing circuit that suppresses an inrush current that flows when power is supplied to an electronic circuit.
- an inrush current flows transiently to charge the capacitor immediately after that. If an excessive inrush current flows, not only the capacitor and the load but also the power supply may be seriously damaged. Therefore, when the power is turned on, a high resistance element such as a current limiting resistor is inserted in the electric circuit to suppress the inrush current, and after the inrush current has converged, the high resistance element is bypassed by a low resistance bypass element.
- An inrush current prevention circuit that suppresses useless power consumption due to is widely known.
- the inrush current prevention circuit described above if the bypass element is bypassed before the inrush current sufficiently converges, the inrush current will flow again, and therefore it is required to appropriately control the timing of bypassing the high resistance element. .
- the charging voltage of the capacitor may be detected. That is, if the capacitor charging voltage is detected and the bypass operation is performed when the value exceeds a predetermined value, there is no possibility that a large inrush current flows again.
- An inrush current prevention circuit based on such a principle is described in Patent Document 1, for example.
- FIG. 4 shows an inrush current prevention circuit described in Patent Document 1.
- 101 is a DC power supply
- 102 is a connector
- 103 is an FET as a bypass element
- 104 is a charging resistance (current limiting resistance) as a high resistance element
- 105 and 106 are voltage dividing resistors
- 107 and 109 are capacitors
- 108 is a transistor for controlling the gate voltage of the FET 103
- 110 is a control circuit
- 111 is a comparator
- 112 is a reference power supply
- 113 and 114 are voltage dividing resistors for output voltage
- 120 is a load.
- the FET 103 Since the potential difference between both ends of the resistor 104 (the drain-source voltage of the FET 103) when the FET is turned on from the OFF state and bypasses the charging resistor 104 is 1.5 [V], the FET 103 is turned on. It can be said that an excessive inrush current does not occur.
- the charging threshold must be set to about 4.5 [V], so the input voltage is 15 [V], the maximum rated voltage.
- the FET 103 changes from the OFF state to the ON state and bypasses the charging resistor 104, the drain-source voltage of the FET 103 becomes 10.5 [V], and an excessive inrush current flows through the FET 103. There is a problem of end.
- Patent Document 2 in a boost power supply device that boosts and outputs a DC power supply voltage by a converter, when the input voltage is high, the current flowing through the switching element of the boost converter is limited to suppress the inrush current.
- Technology is disclosed.
- Figure 5 is a circuit diagram of a boost power source device disclosed in Patent Document 2, when starting the output voltage V o of the boost converter 150 is below the threshold value V r of the comparator 161 (V o ⁇ V r) is The “Low” level output signal of the comparator 161 is inverted to “High” level by the inversion circuit 162 and input to the start-up circuit 140.
- the starting circuit 140 as the drain voltage V x of the FET151 in boost converter 150 does not exceed the threshold value V th of the comparator 141, to suppress the rush current by controlling the operation of the FET151 through the driving circuit 142.
- V o V r
- V r the “High” level output signal of the comparator 161 is input to the control circuit 164 via the delay circuit 163, so that the control is performed in place of the start-up circuit 140 described above.
- a circuit 164 controls the operation of the FET 151.
- Patent Document 3 describes a load control device that suppresses an inrush current flowing in a solenoid valve for a fuel injection device.
- FIG. 6 is a circuit diagram showing this prior art.
- the processing circuit 180 is used for voltage division control so that the input voltage at the negative input terminal of the comparator 174 is increased during a certain period W1 when starting the electromagnetic valve 190 and decreased during the subsequent holding period W2.
- the switch 173 is controlled and operates so as to turn on the driving switching element 177 over the period W1 to W2.
- Reference numeral 171 denotes a DC power source
- 172 denotes a voltage dividing resistor.
- the output of the load current detection circuit 178 is input to the positive input terminal of the comparator 174, and the comparator 174 outputs an instruction signal corresponding to the magnitude relationship between the voltages of the positive and negative input terminals to the control circuit 175.
- Control circuit 175, in the period W1 of the duty control switching element 176 is turned on, the period in W2 and operates to turn off the switching element 176, a third load current I L in the period W1 of the following first current value the limit current value, the load current I L in the holding period W2, to limit to a second current value which is the minimum necessary to drive the third current value less a solenoid valve 190.
- JP 2009-261166 A paragraphs [0043] to [0049], FIG. 4 etc.
- Japanese Patent Laying-Open No. 2008-79448 paragraphs [0018] to [0029], FIG. 1, FIG. 2, etc.
- Japanese Patent Laying-Open No. 2005-158870 paragraphs [0055] to [0067], FIGS. 1 to 5 etc.
- a problem to be solved by the present invention is to provide an inrush current prevention circuit that can reliably suppress an inrush current at power-on regardless of the rated input voltage range with a relatively simple circuit configuration.
- the invention according to claim 1 is configured such that when a power supply voltage is applied to a power supply input terminal, an inrush current flowing in is suppressed by a high resistance element, and an output voltage to a load exceeds a bypass threshold.
- a bypass threshold setting means for setting the bypass threshold according to the voltage value at the voltage dividing point.
- the bypass threshold value setting means includes a first comparator that compares the output voltage equivalent value to the load with a first threshold value.
- a first switching element that operates according to an output signal of the first comparator when the output voltage equivalent value exceeds the first threshold, and an operation of the first switching element divides the power supply voltage.
- a voltage dividing circuit for pressure and when the output voltage equivalent value exceeds the first threshold value, a voltage value at a voltage dividing point in the voltage dividing circuit is set as the bypass threshold value.
- the invention according to claim 3 is the inrush current prevention circuit according to claim 2, wherein the output voltage equivalent value is a voltage obtained by dividing the output voltage to the load, and the first threshold value is rated. This is set according to the lower limit value of the input voltage range.
- the first threshold value is set lower than a minimum operating voltage of the load.
- the invention according to claim 5 is the inrush current prevention circuit according to any one of claims 2 to 4, wherein the output voltage to the load is compared with the bypass threshold, and the output A second switching element that operates according to an output signal of the second comparator when a voltage exceeds the bypass threshold, and the bypass element is configured to be the high-resistance element by the operation of the second switching element. This current is bypassed.
- the second comparator has a hysteresis characteristic.
- the invention according to claim 7 is the inrush current prevention circuit according to claim 5 or 6, further comprising a delay circuit for delaying the output signal of the second comparator and applying the delayed output signal to the second switching element. Is.
- n (n is a plurality) parallel circuits of the high resistance element and the bypass element are connected in series between the power supply input terminal and the load, and the bypass threshold setting means includes: The voltage at n voltage dividing points in the voltage dividing circuit that divides the power supply voltage is set as the n bypass threshold values, and the n bypass elements are operated when the output voltage exceeds each bypass threshold value. Thus, the current of the high resistance element connected in parallel to the bypass element is bypassed.
- the invention according to claim 9 is the inrush current prevention circuit according to any one of claims 5 to 7, wherein a parallel circuit of the high resistance element and the bypass element is provided between the power input terminal and the load.
- N n is a plurality
- the bypass threshold value setting means uses the n number of second comparators with the voltage at the n voltage dividing points in the voltage dividing circuit as the n number of bypass threshold values.
- each of the n number of second switching elements is turned on to turn on the n number of bypass elements to be connected in parallel to the bypass element. The current of the high resistance element is bypassed.
- the bypass threshold (capacitor charging threshold) that is a timing trigger for bypassing a high-resistance element such as a current limiting resistor is set according to the voltage dividing ratio of the power supply voltage, regardless of the rated input voltage range. An excessive inrush current generated when the high resistance element is bypassed can be prevented.
- FIG. 1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram which shows 2nd Embodiment of this invention. It is a circuit diagram which shows the principal part of 3rd Embodiment of this invention. It is a circuit diagram which shows the prior art described in patent document 1. It is a circuit diagram which shows the prior art described in patent document 2. It is a circuit diagram which shows the prior art described in patent document 3.
- FIG. 1 shows an inrush current prevention circuit according to the first embodiment of the present invention.
- a power source input terminal 1 to which a DC power source (not shown) is connected is connected to one end of a capacitor 3 and a load 4 via a current limiting resistor 2 as a high resistance element.
- Both ends of the current limiting resistor 2 are respectively connected to a source S and a drain D of a P-type MOSFET (hereinafter simply referred to as FET) 5 as a bypass element (bypass switching element).
- FET P-type MOSFET
- a pull-up resistor 6 and a second switching element 7 are connected in series between the power input terminal 1 and the ground point, and the connection point between them is connected to the gate G of the FET 5.
- the switching element 7 is a bipolar transistor, and the output signal of the second comparator 8 is applied to its base. It is applied to one end of the voltage (output voltage) V c of the capacitor 3 to the positive input terminal of the comparator 8.
- an input voltage (power supply voltage) V i pressure minute resistors 9 and 10 is connected in series is a bipolar transistor
- the connection point between the resistors 9 and 10, that is, the voltage dividing point, is connected to the negative input terminal of the comparator 8.
- the output voltage is V c presses the partial resistors 12 and 13 are connected in series, the voltage dividing point of the resistor 12 and 13 are connected to each other (output Voltage equivalent value) V cd is applied to the positive input terminal of the first comparator 14.
- the reference voltage V ref of the reference power supply 15 is applied to the negative input terminal of the comparator 14, and the output signal of the comparator 14 is given to the base of the switching element 11.
- reference numeral 16 denotes bypass threshold setting means comprising resistors 9, 10, 12, 13 for voltage division, switching element 11, comparator 14 and reference power supply 15, and the main part thereof is, for example, a general-purpose IC. It is configurable.
- the bypass threshold setting means 16 in accordance with the magnitude of the output voltage V c, compares the voltage V id of the second input voltage V i by voltage dividing circuit consisting of resistors 9 and 10 divide the voltage dividing point It operates to set as the threshold value (bypass threshold value) of the device 8.
- the second comparator 8 has a “High” level according to a comparison result between the voltage V c of the capacitor 3 and the voltage set by dividing the input voltage V i by the resistors 9 and 10, that is, the bypass threshold V id.
- a “Low” level signal is output to turn on / off the second switching element 7.
- the voltage dividing ratio by the resistors 9 and 10 is arbitrary, from the viewpoint of suppressing the inrush current during the bypass operation by the FET 5, assuming that the resistance values of the resistors 9 and 10 are R 9 and R 10 , respectively, R 10 / (R 9 Each resistance value may be selected so that + R 10 ) is approximately 0.9 (90 [%]).
- the first comparator 14 has a “High” level or a “Low” level according to a comparison result between the output voltage equivalent value V cd obtained by dividing the voltage V c of the capacitor 3 by the resistors 12 and 13 and the reference voltage V ref.
- the first switching element 11 is controlled to be turned on / off.
- the output signal of the comparator 14 becomes “High” level, and the switching element 11 is turned on.
- the collector of the switching element 11 - to-emitter voltage assuming 0 [V]
- the voltage V id dividing point by the resistors 9 and 10 is the resistance value R of the resistors 9 and 10 9, a value determined by R 10.
- the resistance value R 9 1 [kW] when the resistance value R 10 was 9 [kW]
- the voltage V id of 90 [%] of the input voltage V i is the negative input of the comparator 8 as a bypass threshold Applied to the terminal.
- the comparison is performed.
- the output signal of the device 8 becomes “Low” level, and the switching element 7 maintains the OFF state.
- V c exceeds 90 [%] of V i
- the output signal of the comparator 8 is inverted to “High” level, and the switching element 7 is turned on.
- the collector-emitter voltage of the switching element 7 is 0 [V]
- the voltage between the gate G and the source S of the FET 5 is ⁇ V i [V].
- the current limiting resistor 2 is bypassed.
- rated input voltage range is 5 ⁇ 15 [V]
- the bypass threshold value serving as a trigger condition for the bypass operation by the FET 5 can be set according to the voltage dividing ratio of the input voltage V i , so that the bypass operation can be performed even when the rated input voltage range is wide. Inrush current at the time can be reliably suppressed.
- FIG. 2 parts having the same functions as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
- parts different from those in FIG. 1 will be mainly described.
- a resistor 19 is connected between the drain D of the FET 5 and the positive input terminal of the comparator 8, and a resistor 20 is connected between the positive input terminal and the output terminal of the comparator 8.
- These resistors 19 and 20 are for imparting hysteresis characteristics to the comparator 8 according to the ratio of the resistance values.
- a diode 21, a capacitor 22, and resistors 23 and 24 that constitute a delay circuit are connected between the output terminal of the comparator 8 and the switching element 7.
- a Zener diode 18 is connected between the source S and the gate G of the FET 5 with the polarity shown in the figure, and a resistor 17 is connected between the anode and the collector of the switching element 7.
- the Zener diode 18 has a use for protecting the FET 5 against an input overvoltage, and the resistor 17 has a use for protecting the Zener diode 18 when an input overvoltage occurs, both of which are main features of the present invention. It does not affect the circuit operation.
- the bypass threshold value for turning on the FET 5 is determined only by the voltage dividing ratio based on the resistance values R 9 and R 10 of the resistors 9 and 10 , but in this second embodiment, the resistance When the resistance values of 19 and 20 are R 19 and R 20 , respectively, ⁇ R 10 / (R 9 + R 10 ) ⁇ ⁇ ⁇ (R 19 + R 20 ) / R 20 ⁇ is approximately 0.9 (90 [%] )
- the resistors 19 and 20 are selected so as to be approximately.
- the operation of the second embodiment will be described.
- the operation in the period in which the magnitude relationship between the divided value V cd of the voltage V c and the reference voltage V ref is V cd ⁇ V ref is the same as that in the first embodiment, and the comparator 14
- the output signal is “Low” level, and the switching element 11 is in the OFF state.
- the voltage V id of the negative input terminal of the comparator 8 becomes equal to the input voltage V i.
- V cd > V ref the output signal of the comparator 14 becomes “High” level, and the switching element 11 is turned on.
- the voltage V id at the voltage dividing point is a divided value by the resistors 9 and 10, for example, the resistance value R of the resistor 9 9 1 [kW], when the resistance value R 10 of the resistor 10 and 3 [kW], the voltage of 75 [%] of the input voltage V i is applied as a bypass threshold to the negative input terminal of the comparator 8.
- the resistance values R 9 , R 20 are combined with the resistance values R 19 , R 20 of the hysteresis resistors 19 , 20 .
- R 10 may be selected again.
- the voltage V c of the capacitor 3 rises to 90% or more of the input voltage V i, "High output signal of the comparator 8 from the" Low "level
- the capacitor 22 in the delay circuit is charged via the diode 21 and the switching element 7 is turned on.
- the charging resistance of the capacitor 22 is not shown in FIG. 2, when it is desired to further delay the ON operation of the FET 5, a predetermined resistance value is provided between the cathode of the diode 21 and one end of the capacitor 22. Insert a charging resistor.
- the bypass threshold value that serves as a trigger condition for the bypass operation by the FET 5 can be set according to the voltage dividing ratio of the input voltage V i , so that the bypass operation can be performed even when the rated input voltage range is wide. Inrush current at the time can be reliably suppressed.
- the operation when the input voltage V i drops.
- the FET 5 is turned on, so that the magnitude relationship between V i and V c is strictly equal to V i > V c .
- the switching element 11 since the switching element 11 is also in the ON state, within its scope, the voltage V id dividing point is always lower than the voltage V c of the capacitor 3. Therefore, even if the input voltage V i falls within the rated input range, the output signal of the comparator 8 does not invert from the “High” level to the “Low” level, so the FET 5 remains on.
- the minimum operating voltage is generally defined for the component corresponding to the load 4 in FIG. 2, but actually, the load 4 can operate even when a voltage slightly lower than the minimum operating voltage is applied. is there. Therefore, when the voltage V c decreases enough below the rated input range of the load 4, there FET5 despite load 4 is running it is necessary to avoid a situation where it becomes the OFF state, FIG. 2
- the delay circuit is provided in consideration of the above points.
- FIG. 3 is a circuit diagram showing the main part of the third embodiment of the present invention.
- This third embodiment assumes a case where the rated input voltage range is very wide, and the second comparator 8, the second switching element 7, the current limiting resistor 2 and the second embodiment 8 in the first and second embodiments.
- the FET5 provided a plurality of stages, by sequentially turning on the FET5 in accordance with the magnitude of the voltage V c of the capacitor 3 is intended to suppress the inrush current during bypass operation.
- n (n is a plurality) current limiting resistors 2 1 to 2 n are connected in series between the power input terminal 1 and one end of the capacitor 3, and each resistor 2 1 to 2 n has FETs 5 1 to 5 n are connected in parallel.
- the drain D of the FET 5 1 of the capacitor 3 side is connected to the positive input terminal of the n second comparators 8 1 ⁇ 8 n provided in correspondence to the current-limiting resistor 2 1 ⁇ 2 n, comparator
- the negative input terminals 8 1 to 8 n serve as voltage dividing points between the resistors in the series circuit of the resistors 9 1 to 9 n and the resistor 10 connected between the power input terminal 1 and the ground point. Each is connected.
- the output terminals of the second comparators 8 1 to 8 n are connected to the bases of the n second switching elements 7 1 to 7 n , respectively, and the collectors of these switching elements 7 1 to 7 n are resistors. 6 1 to 6 n are connected to the source S of the FET 5 n . The emitters of the switching elements 7 1 to 7 n are all grounded.
- the configuration of the bypass threshold setting means 16A is the same as that of the first and second embodiments except for the series circuit of the resistors 9 1 to 9 n for voltage division, and the description thereof is omitted here.
- the ratio of the combined resistance value of the series circuit of the resistors 9 1 to 9 n and the resistance value of the resistor 10 is 9: 1
- the input voltage V i is 5 [V]
- the resistances 9 n and 10 The voltage V id1 at the connection point is 0.5 [V]
- this voltage V idn is added to the negative input terminal of the comparator 8 n as a bypass threshold.
- the comparator goes, the output signal becomes “High” level in the order of 8 n ⁇ 8 n ⁇ 1 ⁇ ?? ⁇ 8 2 ⁇ 8 1 , and the FET also becomes 5 n ⁇ 5 n ⁇ 1 ⁇ ?? ⁇ 5 2 ⁇ 5 Turns on in the order of 1 .
- the voltage Vid1 at the voltage dividing point is exceeded, all the current limiting resistors 2 1 to 2 n are bypassed. Therefore, if the values of the voltage dividing resistors 9 1 to 9 n and 10 are appropriately selected, the potential difference between both ends of the series circuit of the current limiting resistors 2 1 to 2 n is reduced when all the current limiting resistors are bypassed. Therefore, an excessive inrush current does not flow into the capacitor 3 or the load 4.
- the voltages V id1 to V idn at the voltage dividing point are also increased according to the magnitude of the input voltage V i, but the current limiting resistor 2 is operated by the same operation as when the input voltage V i is small. Since the potential difference between both ends of the 1 to 2 n series circuit becomes a small value, the current flowing through the FETs 5 1 to 5 n can be reduced by the bypass operation to prevent the occurrence of an inrush current.
- the second comparators 8 1 to 8 n may have hysteresis characteristics, and the second comparators 8 1 to 8 n A delay circuit may be inserted between the second switching elements 7 1 to 7 n .
- the present invention has a wide rated input voltage range from a power source, and can be used as various DC power supply devices having a purpose of supplying a DC voltage of a predetermined magnitude to a load.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Direct Current Feeding And Distribution (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
そこで、電源投入時には、電流制限抵抗等の高抵抗素子を電路に挿入して突入電流を抑制し、突入電流が収束した後に高抵抗素子を低抵抗のバイパス素子によりバイパスすることで、高抵抗素子による無用な電力消費を抑えるようにした突入電流防止回路が広く知られている。
突入電流が十分に収束したか否かを判断するためには、コンデンサの充電電圧を検出すれば良い。すなわち、コンデンサの充電電圧を検出してその値が所定値を超えたタイミングでバイパス動作させれば、大きな突入電流が再度流入する恐れはない。
このような原理に基づく突入電流防止回路は、例えば特許文献1に記載されている。
図4において、101は直流電源、102はコネクタ、103はバイパス素子としてのFET、104は高抵抗素子としての充電抵抗(電流制限抵抗)、105,106は分圧抵抗、107,109はコンデンサ、108はFET103のゲート電圧制御用のトランジスタ、110は制御回路、111は比較器、112は基準電源、113,114は出力電圧の分圧抵抗、120は負荷である。
上記の動作により抑制された電流によってコンデンサ109が次第に充電され、分圧抵抗113,114による分圧値が充電閾値(基準電源112による基準電圧)を超えると比較器111の出力が反転し、トランジスタ108及びFET103がオン状態(導通)になって充電抵抗104をバイパスする。
この従来技術は、コンデンサ109の電圧に相当する分圧値が充電閾値を超えることにより、FET103によるバイパス動作を実行する点を特徴としている。
例えば、定格入力電圧範囲が5~6[V]である場合、充電閾値を4.5[V]程度に設定すれば、入力電圧が最大定格電圧の6[V]であったとしても、FET103がオフ状態からオン状態になって充電抵抗104をバイパスする時の同抵抗104の両端電位差(FET103のドレイン-ソース間電圧)は1.5[V]であるため、FET103がオン状態になった際に過大な突入電流が生じることはないと言える。
また、Vo>Vrとなった場合には、比較器161の「High」レベルの出力信号が遅延回路163を介して制御回路164に入力されるため、上述の起動回路140に代えて制御回路164がFET151の動作を制御する。
図6において、処理回路180は、比較器174の負入力端子の入力電圧を、電磁弁190を起動する際の一定期間W1では高くし、その後の保持期間W2では低くするように分圧制御用スイッチ173を制御し、かつ、上記の期間W1~ W2にわたり駆動用スイッチング素子177をオンさせるように動作する。なお、171は直流電源、172は分圧抵抗である。
また、特許文献3に記載された従来技術では、短い期間ではあっても起動時の期間W1に大きな電流(第3の電流値)が流れるので、突入電流の抑制という観点からは未だ改良の余地がある。
図1は、本発明の第1実施形態に係る突入電流防止回路を示している。図1において、直流電源(図示せず)が接続される電源入力端子1には、高抵抗素子としての電流制限抵抗2を介してコンデンサ3及び負荷4の各一端が接続されている。
スイッチング素子7はバイポーラトランジスタであり、そのベースには第2の比較器8の出力信号が加えられている。この比較器8の正入力端子にはコンデンサ3の一端の電圧(出力電圧)Vcが加わっている。
また、コンデンサ3の一端と接地点との間には、出力電圧Vcを分圧する抵抗12,13が直列に接続されており、抵抗12,13同士が接続された分圧点の電圧(出力電圧相当値)Vcdは第1の比較器14の正入力端子に加えられている。なお、比較器14の負入力端子には、基準電源15の基準電圧Vrefが加えられており、この比較器14の出力信号が前記スイッチング素子11のベースに与えられている。
このバイパス閾値設定手段16は、出力電圧Vcの大きさに応じて、抵抗9,10からなる分圧回路により入力電圧Viを分圧してその分圧点の電圧Vidを第2の比較器8の閾値(バイパス閾値)として設定するように動作するものである。
いま、回路に電源が投入されて入力電圧Viが印加されたとすると、電流制限抵抗2により大きさが制限された電流によってコンデンサ3の充電が開始される。充電に伴って徐々に上昇していく出力電圧Vcの分圧値Vcdと基準電圧Vrefとの大小関係が、Vcd≦Vrefである期間は、比較器14の出力信号は「Low」レベルであり、スイッチング素子11はオフ状態を保つ。
このため、比較器8の負入力端子の電圧Vidは抵抗9によって電源入力端子1にプルアップされることになり、入力電圧Viと等しくなる。
この場合、Vcd>Vrefであるから、比較器14の出力信号は「High」レベルとなり、スイッチング素子11がオン状態になる。ここで、理解を容易にするため、スイッチング素子11のコレクタ-エミッタ間電圧を0[V]と仮定すると、抵抗9,10による分圧点の電圧Vidは各抵抗9,10の抵抗値R9,R10によって決まる値となる。例えば、抵抗値R9を1[kΩ]、抵抗値R10を9[kΩ]とした場合には、入力電圧Viの90[%]の電圧Vidがバイパス閾値として比較器8の負入力端子に印加される。
図2において、図1と同一の機能を有する部分については同一の参照符号を付して説明を省略し、以下では図1と異なる部分を中心に説明する。
また、比較器8の出力端子とスイッチング素子7との間には、遅延回路を構成するダイオード21、コンデンサ22及び抵抗23,24が接続されている。
更に、FET5のソースS-ゲートG間にはツェナーダイオード18が図示の極性で接続され、そのアノードとスイッチング素子7のコレクタとの間には抵抗17が接続されている。
なお、ツェナーダイオード18は、入力過電圧に対してFET5を保護する用途を持ち、抵抗17は入力過電圧が生じた際にツェナーダイオード18を保護する用途を持つものであり、何れも本発明の主要な回路動作を左右するものではない。
これらの抵抗19,20によって比較器8にヒステリシス特性を付与することにより、例えば、電圧Vcがノイズなどの影響でバイパス閾値を跨ぐように繰り返し変動したとしても、FET5がオン・オフ動作を繰り返す恐れは少なくなる。
更に、比較器8の出力側に、ダイオード21、コンデンサ22及び抵抗23,24からなる遅延回路を設ければ、例えば、Vcd<Vrefとなるほどに電圧Vcが単調低下した場合に、負荷4が動作を続けている期間はFET5のオン状態を維持して電力を供給することが可能になる。
電源が投入された直後において、電圧Vcの分圧値Vcdと基準電圧Vrefとの大小関係がVcd≦Vrefである期間の動作は第1実施形態と同様であり、比較器14の出力信号は「Low」レベルであってスイッチング素子11はオフ状態である。また、比較器8の負入力端子の電圧Vidは入力電圧Viに等しくなる。
Vcd>Vrefになると比較器14の出力信号は「High」レベルとなり、スイッチング素子11はオン状態となる。第1実施形態と同様にスイッチング素子11のコレクタ-エミッタ間電圧を0[V]と仮定すると、分圧点の電圧Vidは抵抗9,10による分圧値となり、例えば抵抗9の抵抗値R9を1[kΩ]、抵抗10の抵抗値R10を3[kΩ]とすると、入力電圧Viの75[%]の電圧が比較器8の負入力端子にバイパス閾値として印加される。この時、比較器8の出力信号が「Low」レベルから「High」レベルに反転するようであれば、ヒステリシス用の抵抗19,20の抵抗値R19,R20と併せて抵抗値R9,R10を選定し直せば良い。
以上のように、この第2実施形態においても、FET5によるバイパス動作のトリガ条件となるバイパス閾値を、入力電圧Viの分圧比に応じて設定できるため、定格入力電圧範囲が広い場合でもバイパス動作時の突入電流を確実に抑制することができる。
入力電圧Viが定格入力範囲内にある時は、FET5がオン状態になるため、Vi,Vcの大小関係は、厳密にはVi>Vcであるが概ね等しい値となる。この時、スイッチング素子11もまたオン状態にあるため、その範囲内では、分圧点の電圧Vidは常にコンデンサ3の電圧Vcより低くなる。
従って、入力電圧Viが定格入力範囲内において低下したとしても、比較器8の出力信号が「High」レベルから「Low」レベルに反転することはないので、FET5はオン状態を維持する。
前述したごとく、Vi>Vcであるから、比較器8の出力信号は「High」レベルから「Low」レベルに反転するが、遅延回路内のコンデンサ22及び抵抗23,24の値を適宜、設定すれば所望の遅延時間だけFET5のオン状態を保持することができ、負荷4の駆動状態を維持することができる。
この第3実施形態は、定格入力電圧範囲が非常に広い場合を想定したものであり、第1,第2実施形態における第2の比較器8、第2のスイッチング素子7、電流制限抵抗2及びFET5を複数段設け、コンデンサ3の電圧Vcの大きさに応じてFET5を順次オンさせることにより、バイパス動作時の突入電流を抑制するものである。
コンデンサ3側のFET51のドレインDは、電流制限抵抗21~2nに対応して設けられたn個の第2の比較器81~8nの正入力端子にそれぞれ接続され、比較器81~8nの負入力端子は、電源入力端子1と接地点との間に接続された分圧用の抵抗91~9nと抵抗10との直列回路における抵抗相互間の分圧点にそれぞれ接続されている。
なお、バイパス閾値設定手段16Aの構成は、分圧用の抵抗91~9nの直列回路を除けば第1,第2実施形態と同一であるため、ここでは説明を省略する。
例えば、抵抗91~9nの直列回路の合成抵抗値と抵抗10の抵抗値との比を9:1とした場合、入力電圧Viが5[V]の時に抵抗9n,10同士の接続点の電圧Vid1は0.5[V]であり、この電圧Vidnが比較器8nの負入力端子にバイパス閾値として加わる。このため、コンデンサ3の電圧Vcが0.5[V]を超えた時点で比較器8nの出力信号が「High」レベルになり、スイッチング素子7nがオン状態になってFET5nもオン状態になる。この時点で、FET5nのソースS-ドレインD間の電圧は僅かな値である。
すなわち、コンデンサ3の電圧Vcの上昇と共に電流制限抵抗が2n→2n-1→……→22→21という順でバイパスされていき、電圧Vcが抵抗91,92による分圧点の電圧Vid1を超えた時点で、全ての電流制限抵抗21~2nがバイパスされる。
従って、分圧用の抵抗91,~9n,10の値を適切に選定すれば、全ての電流制限抵抗がバイパスされた場合の電流制限抵抗21~2nの直列回路の両端電位差を小さくすることができ、過大な突入電流がコンデンサ3や負荷4に流入することはない。
2,21~2n:電流制限抵抗
3:コンデンサ
4:負荷
5,51~5n:FET
7,71~7n,11:スイッチング素子
6,61~6n,9,91~9n,10,12,13,17,19,20,23,24:抵抗
8,81~8n,14:比較器
15:基準電源
16,16A:バイパス閾値設定手段
18:ツェナーダイオード
21:ダイオード
22:コンデンサ
G:ゲート
S:ソース
D:ドレイン
Claims (9)
- 電源入力端子に電源電圧が印加された時に流入する突入電流を高抵抗素子により抑制し、負荷への出力電圧がバイパス閾値を超えた時に、前記高抵抗素子と並列に接続された低抵抗のバイパス素子を動作させて前記高抵抗素子の電流をバイパスするようにした突入電流防止回路において、
前記出力電圧に応じて、前記電源電圧を分圧してその分圧点の電圧値により前記バイパス閾値を設定するバイパス閾値設定手段を備えたことを特徴とする突入電流防止回路。 - 請求項1に記載した突入電流防止回路において、
前記バイパス閾値設定手段は、
前記負荷への出力電圧相当値と第1の閾値とを比較する第1の比較器と、
前記出力電圧相当値が前記第1の閾値を超えた時の前記第1の比較器の出力信号により動作する第1のスイッチング素子と、
前記第1のスイッチング素子の動作により前記電源電圧を分圧する分圧回路と、を備え、
前記出力電圧相当値が前記第1の閾値を超えた時に、前記分圧回路における分圧点の電圧値を前記バイパス閾値として設定することを特徴とする突入電流防止回路。 - 請求項2に記載した突入電流防止回路において、
前記出力電圧相当値を、前記負荷への出力電圧を分圧した電圧とし、かつ、前記第1の閾値を、定格入電圧範囲の下限値に応じて設定したことを特徴とする突入電流防止回路。 - 請求項2または3に記載した突入電流防止回路において、
前記第1の閾値を、前記負荷の最低動作電圧より低く設定したことを特徴とする突入電流防止回路。 - 請求項2~4の何れか1項に記載した突入電流防止回路において、
前記負荷への出力電圧と前記バイパス閾値とを比較する第2の比較器と、
前記出力電圧が前記バイパス閾値を超えた時の前記第2の比較器の出力信号により動作する第2のスイッチング素子と、を備え、
前記第2のスイッチング素子の動作により、前記バイパス素子が前記高抵抗素子の電流をバイパスすることを特徴とする突入電流防止回路。 - 請求項5に記載した突入電流防止回路において、
前記第2の比較器がヒステリシス特性を有することを特徴とする突入電流防止回路。 - 請求項5または6に記載した突入電流防止回路において、
前記第2の比較器の出力信号を遅延させて前記第2のスイッチング素子に加えるための遅延回路を備えたことを特徴とする突入電流防止回路。 - 請求項1~4の何れか1項に記載した突入電流防止回路において、
前記高抵抗素子と前記バイパス素子との並列回路を前記電源入力端子と前記負荷との間にn(nは複数)個直列に接続し、
前記バイパス閾値設定手段は、前記電源電圧を分圧する分圧回路におけるn個の分圧点の電圧をn個の前記バイパス閾値として設定し、
前記出力電圧が各バイパス閾値を超えた時にn個の前記バイパス素子をそれぞれ動作させて当該バイパス素子に並列接続された前記高抵抗素子の電流をバイパスすることを特徴とする突入電流防止回路。 - 請求項5~7の何れか1項に記載した突入電流防止回路において、
前記高抵抗素子と前記バイパス素子との並列回路を前記電源入力端子と前記負荷との間にn(nは複数)個直列に接続し、
前記バイパス閾値設定手段は、前記分圧回路におけるn個の分圧点の電圧をn個の前記バイパス閾値としてn個の前記第2の比較器にそれぞれ与え、
前記出力電圧が各バイパス閾値を超えた時にn個の前記第2のスイッチング素子をそれぞれオンさせることにより、n個の前記バイパス素子をそれぞれオンさせて当該バイパス素子に並列接続された前記高抵抗素子の電流をバイパスすることを特徴とする突入電流防止回路。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017529402A JP6288379B2 (ja) | 2015-12-01 | 2015-12-01 | 突入電流防止回路 |
PCT/JP2015/083689 WO2017094095A1 (ja) | 2015-12-01 | 2015-12-01 | 突入電流防止回路 |
CN201580065502.5A CN107027334A (zh) | 2015-12-01 | 2015-12-01 | 浪涌电流防止电路 |
DE112015005280.1T DE112015005280T5 (de) | 2015-12-01 | 2015-12-01 | Schaltung zum verhindern eines einschaltstroms |
US15/611,458 US20170271867A1 (en) | 2015-12-01 | 2017-06-01 | Inrush current prevention circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/083689 WO2017094095A1 (ja) | 2015-12-01 | 2015-12-01 | 突入電流防止回路 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/611,458 Continuation US20170271867A1 (en) | 2015-12-01 | 2017-06-01 | Inrush current prevention circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017094095A1 true WO2017094095A1 (ja) | 2017-06-08 |
Family
ID=58796555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2015/083689 WO2017094095A1 (ja) | 2015-12-01 | 2015-12-01 | 突入電流防止回路 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20170271867A1 (ja) |
JP (1) | JP6288379B2 (ja) |
CN (1) | CN107027334A (ja) |
DE (1) | DE112015005280T5 (ja) |
WO (1) | WO2017094095A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021044971A (ja) * | 2019-09-12 | 2021-03-18 | 新電元工業株式会社 | プリチャージ回路、及びモータ制御装置 |
CN116231610A (zh) * | 2023-05-09 | 2023-06-06 | 四川泰瑞创通讯技术股份有限公司 | 前端抑制浪涌装置、控制方法、电子装置及可读存储介质 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3182572B1 (en) * | 2015-12-17 | 2019-11-13 | Grundfos Holding A/S | Electronic circuit and method for operating an electronic circuit |
CN106655272B (zh) * | 2017-01-16 | 2018-12-04 | 湖南大学 | 抑制故障瞬时冲击电流型虚拟同步逆变器及其控制方法 |
CN109728570B (zh) * | 2017-10-27 | 2020-06-12 | 光宝科技股份有限公司 | 用以抑制浪涌电流的电路 |
US10254812B1 (en) * | 2017-12-13 | 2019-04-09 | Cypress Semiconductor Corporation | Low inrush circuit for power up and deep power down exit |
US11114844B2 (en) * | 2018-07-20 | 2021-09-07 | Vertiv Corporation | Inrush current limiter circuits and methods of limiting inrush current in a circuit |
CN113162008B (zh) * | 2020-01-07 | 2024-04-02 | 台达电子工业股份有限公司 | 突波电流抑制电路 |
TWI721748B (zh) * | 2020-01-07 | 2021-03-11 | 台達電子工業股份有限公司 | 突波電流抑制電路與具有該突波電流抑制電路之電源電路 |
TWI729835B (zh) * | 2020-06-03 | 2021-06-01 | 亞源科技股份有限公司 | 遲滯電壓偵測電路 |
CN113612194B (zh) * | 2021-08-20 | 2024-01-12 | 裕太微电子股份有限公司 | 以太网phy芯片的浪涌保护电路 |
CN114094544B (zh) * | 2021-11-11 | 2022-12-02 | 珠海格力电器股份有限公司 | 一种变频器的保护装置、方法和磁悬浮机组 |
CN117691847B (zh) * | 2024-02-01 | 2024-05-03 | 成都新欣神风电子科技有限公司 | 一种基于n沟道mos管的正线冲击电流抑制电路 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003189464A (ja) * | 2001-12-21 | 2003-07-04 | Sanken Electric Co Ltd | 突入電流防止回路 |
JP2005198357A (ja) * | 2003-12-26 | 2005-07-21 | Canon Finetech Inc | 突入電流防止回路 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5677558A (en) * | 1995-03-03 | 1997-10-14 | Analog Devices, Inc. | Low dropout linear regulator |
JP3394389B2 (ja) * | 1995-07-13 | 2003-04-07 | シャープ株式会社 | 直流安定化電源回路 |
US6163712A (en) * | 1998-02-04 | 2000-12-19 | Motorola, Inc. | Inrush current limiter with output voltage detection for control of input current level and activation of current bypass path |
JP3526267B2 (ja) * | 2000-10-27 | 2004-05-10 | シャープ株式会社 | 安定化電源回路 |
US6947272B2 (en) * | 2001-11-20 | 2005-09-20 | Texas Instruments Incorporated | Inrush current control method using a dual current limit power switch |
JP2005158870A (ja) * | 2003-11-21 | 2005-06-16 | Fujitsu Ten Ltd | 負荷制御装置 |
JP2007336739A (ja) * | 2006-06-16 | 2007-12-27 | Yokowo Co Ltd | 保護回路 |
JP4783220B2 (ja) * | 2006-06-20 | 2011-09-28 | 株式会社リコー | 過電圧保護回路、電子装置 |
JP2008035596A (ja) * | 2006-07-27 | 2008-02-14 | Yokowo Co Ltd | 保護回路 |
JP2008079448A (ja) * | 2006-09-22 | 2008-04-03 | Matsushita Electric Ind Co Ltd | 昇圧電源装置 |
JP2009261166A (ja) * | 2008-04-18 | 2009-11-05 | Ricoh Elemex Corp | 突入電流制御回路 |
US8614866B2 (en) * | 2009-09-14 | 2013-12-24 | Electronic Systems Protection, Inc. | Hybrid switch circuit |
JP5279796B2 (ja) * | 2010-10-29 | 2013-09-04 | 三菱電機株式会社 | 電力変換装置 |
JP5368508B2 (ja) * | 2011-05-16 | 2013-12-18 | 三菱電機株式会社 | 車載電子制御装置 |
US9787086B2 (en) * | 2015-02-27 | 2017-10-10 | Electronic Systems Protection, Inc. | Limiting amplitude of electricity delivered to an electrical load |
-
2015
- 2015-12-01 WO PCT/JP2015/083689 patent/WO2017094095A1/ja active Application Filing
- 2015-12-01 JP JP2017529402A patent/JP6288379B2/ja not_active Expired - Fee Related
- 2015-12-01 DE DE112015005280.1T patent/DE112015005280T5/de not_active Withdrawn
- 2015-12-01 CN CN201580065502.5A patent/CN107027334A/zh active Pending
-
2017
- 2017-06-01 US US15/611,458 patent/US20170271867A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003189464A (ja) * | 2001-12-21 | 2003-07-04 | Sanken Electric Co Ltd | 突入電流防止回路 |
JP2005198357A (ja) * | 2003-12-26 | 2005-07-21 | Canon Finetech Inc | 突入電流防止回路 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021044971A (ja) * | 2019-09-12 | 2021-03-18 | 新電元工業株式会社 | プリチャージ回路、及びモータ制御装置 |
JP7292158B2 (ja) | 2019-09-12 | 2023-06-16 | 新電元工業株式会社 | プリチャージ回路、及びモータ制御装置 |
CN116231610A (zh) * | 2023-05-09 | 2023-06-06 | 四川泰瑞创通讯技术股份有限公司 | 前端抑制浪涌装置、控制方法、电子装置及可读存储介质 |
Also Published As
Publication number | Publication date |
---|---|
US20170271867A1 (en) | 2017-09-21 |
JPWO2017094095A1 (ja) | 2017-11-30 |
JP6288379B2 (ja) | 2018-03-07 |
CN107027334A (zh) | 2017-08-08 |
DE112015005280T5 (de) | 2017-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6288379B2 (ja) | 突入電流防止回路 | |
US8031450B2 (en) | Power supply control circuit | |
US10715032B2 (en) | Circuit for charging an electric battery by means of a photovoltaic module | |
US8742741B2 (en) | Apparatus and methods of soft-start in a hysteretic power converter | |
US6807039B2 (en) | Inrush limiter circuit | |
US20140253086A1 (en) | Using Synchronous Converter in Asynchronous Mode to Prevent Current Reversal During Battery Charging | |
US9324530B2 (en) | Circuit for protecting against reverse polarity | |
CN106067684B (zh) | 电池装置 | |
CN213846230U (zh) | 一种过流保护电路 | |
CN113472032A (zh) | 一种充电控制电路、充电控制***与充电器 | |
US20160079748A1 (en) | Over-Current Protection Circuit And Method | |
CN113746076B (zh) | 浪涌电流限制器和包括该浪涌电流限制器的*** | |
CN109478780B (zh) | 极性变换保护电路 | |
US9484801B2 (en) | Start-up regulator for high-input-voltage power converters | |
JPWO2013187269A1 (ja) | スイッチング電源装置 | |
CN108963999B (zh) | 一种浪涌电流抑制器 | |
US10298008B2 (en) | DC to DC boost converter | |
JP2014021634A (ja) | 突入電流抑制回路 | |
JP7247903B2 (ja) | 電気回路及び電源装置 | |
JP2008148380A (ja) | 過電圧保護回路 | |
CN116670615A (zh) | 具有短路保护的三输出dc电压供应 | |
CN110165880B (zh) | 一种稳定开关电路输出电压的电路及方法 | |
US9018925B2 (en) | Load control apparatus | |
CN215835153U (zh) | 一种充电控制电路、充电控制***与充电器 | |
CN208820681U (zh) | 一种电容器放电电路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref document number: 2017529402 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112015005280 Country of ref document: DE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15909725 Country of ref document: EP Kind code of ref document: A1 |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15909725 Country of ref document: EP Kind code of ref document: A1 |