WO2017041116A1 - Optoelectronic device with dielectric layer and method of manufacture - Google Patents
Optoelectronic device with dielectric layer and method of manufacture Download PDFInfo
- Publication number
- WO2017041116A1 WO2017041116A1 PCT/US2016/052939 US2016052939W WO2017041116A1 WO 2017041116 A1 WO2017041116 A1 WO 2017041116A1 US 2016052939 W US2016052939 W US 2016052939W WO 2017041116 A1 WO2017041116 A1 WO 2017041116A1
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- WIPO (PCT)
- Prior art keywords
- dielectric layer
- layer
- optoelectronic device
- dielectric
- metal
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 92
- 239000002184 metal Substances 0.000 claims abstract description 92
- 239000003989 dielectric material Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000002253 acid Substances 0.000 claims abstract description 8
- 150000007513 acids Chemical class 0.000 claims abstract description 8
- 230000008569 process Effects 0.000 claims description 32
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 18
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- 238000007641 inkjet printing Methods 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 11
- 229910052709 silver Inorganic materials 0.000 claims description 11
- 239000004332 silver Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052763 palladium Inorganic materials 0.000 claims description 9
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 229910052804 chromium Inorganic materials 0.000 claims description 8
- 239000011651 chromium Substances 0.000 claims description 8
- 238000001459 lithography Methods 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 238000000608 laser ablation Methods 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- 238000007650 screen-printing Methods 0.000 claims description 6
- 238000000224 chemical solution deposition Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 claims description 4
- -1 arsenic selenide Chemical class 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- UKUVVAMSXXBMRX-UHFFFAOYSA-N 2,4,5-trithia-1,3-diarsabicyclo[1.1.1]pentane Chemical compound S1[As]2S[As]1S2 UKUVVAMSXXBMRX-UHFFFAOYSA-N 0.000 claims description 3
- 229940052288 arsenic trisulfide Drugs 0.000 claims description 3
- 238000005422 blasting Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000003618 dip coating Methods 0.000 claims description 3
- 229920002313 fluoropolymer Polymers 0.000 claims description 3
- 239000004811 fluoropolymer Substances 0.000 claims description 3
- ORUIBWPALBXDOA-UHFFFAOYSA-L magnesium fluoride Chemical compound [F-].[F-].[Mg+2] ORUIBWPALBXDOA-UHFFFAOYSA-L 0.000 claims description 3
- 229910001635 magnesium fluoride Inorganic materials 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 claims description 3
- 229920000515 polycarbonate Polymers 0.000 claims description 3
- 239000004417 polycarbonate Substances 0.000 claims description 3
- 229920000728 polyester Polymers 0.000 claims description 3
- 229920000098 polyolefin Polymers 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 claims description 2
- 229910001634 calcium fluoride Inorganic materials 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 238000007735 ion beam assisted deposition Methods 0.000 claims description 2
- 238000010884 ion-beam technique Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 239000000843 powder Substances 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 221
- 239000000463 material Substances 0.000 description 26
- 229910005540 GaP Inorganic materials 0.000 description 20
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 18
- 238000000151 deposition Methods 0.000 description 17
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 13
- 230000008021 deposition Effects 0.000 description 13
- 229910052738 indium Inorganic materials 0.000 description 11
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 11
- 239000010409 thin film Substances 0.000 description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000002243 precursor Substances 0.000 description 6
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 5
- 238000003892 spreading Methods 0.000 description 4
- 230000007480 spreading Effects 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000000609 electron-beam lithography Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000002310 reflectometry Methods 0.000 description 3
- 238000004901 spalling Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000002202 sandwich sublimation Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- HTDIUWINAKAPER-UHFFFAOYSA-N trimethylarsine Chemical compound C[As](C)C HTDIUWINAKAPER-UHFFFAOYSA-N 0.000 description 2
- DIIIISSCIXVANO-UHFFFAOYSA-N 1,2-Dimethylhydrazine Chemical compound CNNC DIIIISSCIXVANO-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 125000005600 alkyl phosphonate group Chemical group 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910000074 antimony hydride Inorganic materials 0.000 description 1
- 238000000149 argon plasma sintering Methods 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000012707 chemical precursor Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- JMMJWXHSCXIWRF-UHFFFAOYSA-N ethyl(dimethyl)indigane Chemical compound CC[In](C)C JMMJWXHSCXIWRF-UHFFFAOYSA-N 0.000 description 1
- KQTKYCXEDDECIZ-UHFFFAOYSA-N ethylarsenic Chemical compound CC[As] KQTKYCXEDDECIZ-UHFFFAOYSA-N 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000025 interference lithography Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- WJFZPDZHLPHPJO-UHFFFAOYSA-N methyl-di(propan-2-yl)indigane Chemical compound CC(C)[In](C)C(C)C WJFZPDZHLPHPJO-UHFFFAOYSA-N 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- HKOOXMFOFWEVGF-UHFFFAOYSA-N phenylhydrazine Chemical compound NNC1=CC=CC=C1 HKOOXMFOFWEVGF-UHFFFAOYSA-N 0.000 description 1
- 229940067157 phenylhydrazine Drugs 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- YBRBMKDOPFTVDT-UHFFFAOYSA-N tert-butylamine Chemical compound CC(C)(C)N YBRBMKDOPFTVDT-UHFFFAOYSA-N 0.000 description 1
- QTQRGDBFHFYIBH-UHFFFAOYSA-N tert-butylarsenic Chemical compound CC(C)(C)[As] QTQRGDBFHFYIBH-UHFFFAOYSA-N 0.000 description 1
- ZGNPLWZYVAFUNZ-UHFFFAOYSA-N tert-butylphosphane Chemical compound CC(C)(C)P ZGNPLWZYVAFUNZ-UHFFFAOYSA-N 0.000 description 1
- RBEXEKTWBGMBDZ-UHFFFAOYSA-N tri(propan-2-yl)stibane Chemical compound CC(C)[Sb](C(C)C)C(C)C RBEXEKTWBGMBDZ-UHFFFAOYSA-N 0.000 description 1
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- OTRPZROOJRIMKW-UHFFFAOYSA-N triethylindigane Chemical compound CC[In](CC)CC OTRPZROOJRIMKW-UHFFFAOYSA-N 0.000 description 1
- KKOFCVMVBJXDFP-UHFFFAOYSA-N triethylstibane Chemical compound CC[Sb](CC)CC KKOFCVMVBJXDFP-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
- PORFVJURJXKREL-UHFFFAOYSA-N trimethylstibine Chemical compound C[Sb](C)C PORFVJURJXKREL-UHFFFAOYSA-N 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0687—Multiple junction or tandem solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/054—Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
- H01L31/056—Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means the light-reflecting means being of the back surface reflector [BSR] type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0693—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/52—PV systems with concentrators
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
Definitions
- the present invention relates generally to fabrication of optoelectronic devices and more particularly to optoelectronic devices including a dielectric layer.
- the optoelectronic device comprises a p-n structure, a patterned dielectric layer on the p-n structure and a metal layer disposed on the dielectric layer.
- the dielectric layer comprises a dielectric material, wherein the dielectric material is chemically resistant to acids and provides adhesion to the p-n structure and the metal layer.
- the metal layer makes one or more contacts to the p- n structure through one or more openings in the patterned dielectric layer.
- a method for fabricating an optoelectronic device comprises providing an epitaxially grown p-n structure, providing a dielectric layer on the p-n structure and providing a metal layer on the dielectric layer and then lifting the device off the substrate, such that after the lift off the p-n structure is closer than the patterned dielectric layer to a front side of the device; wherein the device comprises the p-n structure, the patterned dielectric layer, and the metal layer.
- the dielectric layer comprises a dielectric material and has a chemical resistance to acids and provides adhesion to the p-n structure and the metal layer.
- the method comprises providing a p-n structure
- the method further includes providing one or more contact between the p-n structure and the metal layer.
- Figure 1 illustrates a flow chart depicting a process for forming an optoelectronic device comprising a dielectric layer according to embodiments described herein.
- Figures 2a-e depict different stages of fabrication of an optoelectronic device comprising a dielectric layer according to an embodiment of the invention.
- Figures 3a-f depict different stages of fabrication of an optoelectronic device comprising a dielectric layer according to another embodiment of the invention.
- Figures 4a-e depict exemplary embodiments of an optoelectronic device comprising a dielectric layer according to the present invention.
- Figure 5 illustrates an optoelectronic device with front metal contacts according to an embodiment of the invention.
- the present invention relates generally to optoelectronic devices and more particularly to an optoelectronic device with a dielectric layer.
- the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
- Embodiments of the inventions generally relate to optoelectronic devices more specifically to optoelectronic semiconductor devices including one or more textured layers and the fabrication processes for forming such optoelectronic devices.
- Embodiments of the invention also relate to the fabrication of thin film devices, such as photovoltaic devices, light-emitting diodes, or other optoelectronic devices, which contain a dielectric layer on the back side.
- a method for forming an optoelectronic device comprising a dielectric layer according to an embodiment of the invention comprises providing a p-n structure deposited on a substrate.
- a dielectric layer is then patterned on the p-n structure thus formed providing one or more openings for electrical contacts.
- a metallic layer is then disposed on the dielectric layer such that the metal layer makes one or more contacts with the p-n structure through the openings provided in the dielectric layer.
- the p-n structure, the dielectric layer and the metal layer are then lifted off the substrate.
- Embodiments may also provide back reflectors which are metallic reflectors or metal-dielectric reflectors.
- Many of the thin film devices described herein generally contain epitaxially grown layers which are formed on a sacrificial layer disposed on or over a support substrate or wafer.
- the thin film devices thus formed may be flexible single crystal devices.
- the thin film devices are subsequently removed from a support substrate or wafer, for example during an epitaxial lift off (ELO) process, a laser lift off (LLO) process, ion
- a layer can be described as being deposited "on or over" one or more other layers. This term indicates that the layer can be deposited directly on top of the other layer(s), or can indicate that one or more additional layers can be deposited between the layer and the other layer(s) in some embodiments. Also, the other layer(s) can be arranged in any order.
- Figure 1 illustrates a flow chart depicting a process for forming an optoelectronic device comprising a dielectric layer according to embodiments described herein.
- the method comprises providing a p-n structure on a substrate via step 02.
- a sacrificial layer may be disposed on the substrate prior to deposition of the p-n structure, for example to enable liftoff of the p-n structure in an epitaxial liftoff (ELO) process.
- the sacrificial layer may comprise AIAs, AIGaAs, AIGalnP, or AllnP, or other layers with high Al content, or
- the p-n structure may be grown on a substrate, for example, a gallium arsenide wafer may be used, with epitaxially grown layers as thin films made of Group lll-V materials.
- a germanium wafer, or an indium phosphide wafer, or a sapphire wafer, or a gallium nitride wafer, or a silicon wafer may be used.
- the p-n structure may be formed by epitaxial growth using various techniques, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), metalorganic vapor phase epitaxy (MOVPE or OMVPE), liquid phase epitaxy (LPE), hydride vapor phase epitaxy (HVPE), etc.
- MOCVD metalorganic chemical vapor deposition
- MBE molecular beam epitaxy
- MOVPE or OMVPE metalorganic vapor phase epitaxy
- LPE liquid phase epitaxy
- HVPE hydride vapor phase epitaxy
- the p-n structure is substantially a single crystal.
- the epitaxially grown layers of Group lll-V materials can be formed using a high growth rate vapor deposition process.
- the high growth rate deposition process allows for growth rates of greater than 5 pm/hr, such as about 10 pm/hr or greater, or as high as about 100 pm/hr or greater.
- the high growth rate process includes heating a wafer to a deposition temperature of about
- the group Mi-containing precursor gas may contain a group III element, such as indium, gallium, or aluminum.
- the group Ill-containing precursor gas may be chosen from the list: trimethyl aluminum, triethyl aluminum, trimethyl gallium, triethyl gallium, trimethyl indium, triethyl indium, di- isopropylmethylindium, ethyldimethylindium.
- the group V-containing precursor gas may contain a group V element, such as nitrogen, phosphorus, arsenic, or antimony.
- the group V-containing precursor gas may be chosen from the list: phenyl hydrazine, dimethylhydrazine, tertiarybutylamine, ammonia, phosphine, tertiarybutyl phosphine, bisphosphinoethane, arsine, tertiarybutyl arsine, monoethyl arsine, trimethyl arsine, trimethyl antimony, triethyl antimony, tri-isopropyl antimony, stibine.
- the deposition processes for depositing or forming Group lll-V materials can be conducted in various types of deposition chambers.
- one continuous feed deposition chamber that may be utilized for growing, depositing, or otherwise forming Group lll-V materials is described in the commonly assigned U.S. Patent Application Nos. 12/475,131 and 12/475,169, both filed on May 29, 2009, which are herein incorporated by reference in their entireties.
- the p-n structure may contain various arsenide, nitride, and phosphide layers, such as but not limited to GaAs, AIGaAs, InGaP, InGaAs, AllnGaP,
- the p-n structure comprises a Group lll-V semiconductor and includes at least one of the group consisting of: gallium, aluminum, indium, phosphorus, nitrogen, and arsenic. In one embodiment the p-n structure comprises gallium arsenide material, and derivatives thereof.
- the p-n structure comprises a p-type aluminum gallium arsenide layer or stack disposed above an n-type gallium arsenide layer or stack.
- the p-type aluminum gallium arsenide stack has a thickness within a range from about 100 nm to about 3,000 nm and the n-type gallium arsenide stack has a thickness within a range from about 100 nm to about 3,000 nm.
- the n-type gallium arsenide stack has a thickness within a range from about 700 nm to about 2500 nm.
- the p-n structure comprises indium gallium phosphide material, and derivatives thereof.
- the indium gallium phosphide material may contain various indium gallium phosphide layers, such as an indium gallium phosphide, aluminum indium gallium phosphide, etc.
- the p-n structure comprises a p-type aluminum indium gallium phosphide layer or stack disposed above an n-type indium gallium phosphide layer or stack.
- the p-type aluminum indium gallium phosphide stack has a thickness within a range from about 100 nm to about 3,000 nm and the n-type indium gallium phosphide stack has a thickness within a range from about 100 nm to about 3,000 nm. In one example, the n-type indium gallium phosphide stack has a thickness within a range from about 400 nm to about 1 ,500 nm.
- the p-n structure comprises indium gallium arsenide phosphide material, and derivatives thereof.
- the indium gallium arsenide phosphide material may contain various indium gallium arsenide phosphide layers, such as an indium gallium phosphide, aluminum indium gallium phosphide, indium gallium arsenide phosphide, aluminum indium gallium arsenide phosphide etc.
- the p-n structure comprises a p-type aluminum indium gallium phosphide layer or stack disposed above an n-type indium gallium arsenide phosphide layer or stack.
- the p-n structure comprises aluminum indium gallium phosphide material, and derivatives thereof.
- the aluminum indium gallium phosphide material may contain various aluminum indium gallium phosphide layers, such as an aluminum indium phosphide, aluminum indium gallium phosphide, etc.
- the p-n structure comprises a p-type aluminum indium phosphide layer or stack disposed above an n-type aluminum indium gallium phosphide layer or stack.
- the p-n structure comprises multiple p-n junctions.
- Each p-n junction may contain various arsenide, nitride, and phosphide layers, such as GaAs, AIGaAs, InGaP, InGaAs, AllnGaP, AllnGaAs, InGaAsP, AllnGaAsP, GaN, InGaN, AIGaN, AllnGaN, GaP, alloys thereof, derivatives thereof and combinations thereof.
- each p-n junction comprises a Group lll-V semiconductor and includes at least one of the group consisting of: gallium, aluminum, indium, phosphorus, nitrogen, and arsenic.
- the junction formed between the two layers can be a heterojunction that is, the N-layer and P-layer could be of different material or a homojunction, that is, both the N-layer and P-layer could be the same material (both layers being GaAs or both layers InGaP, for example) and that would be within the spirit and scope of the present invention.
- the p-n structure could have either doping polarity, with n-type material at the top of the device and p-type material at the bottom, or alternatively with p-type material at the top of the device and n-type material at the bottom.
- the optoelectronic device could be comprised of multiple p-n layers grown in series, for example, to form a multijunction photovoltaic cell.
- the p-n structure may comprise a textured surface. This textured surface can improve the scattering of light at that surface, as well as improve adhesion to both metal and dielectric layers.
- the texturing is achieved during the growth of the materials that comprise the p-n structure. This may be achieved at least in part for by exploiting a lattice mismatch between at least two materials in the p-n structure, for example in a Stranski- Krastanov process or a Volmer-Weber process.
- a layer in or on the p-n structure may act as an etch mask and texturing can be provided by an etching process.
- texturing may be provided by physical abrasion such as sandpaper or sandblasting or particle blasting or similar processes.
- the back side and/or the front side of the p- n structure can be textured to improve light scattering into and/or out of the device.
- a dielectric layer is then patterned on the p-n structure, via step 104 providing one or more openings for electrical contacts.
- a dielectric layer with an array of openings is disposed on a p-n structure, forming a plurality of apertures extending into the p-n structure.
- the openings for electrical contacts may be patterned such that front metal contacts and openings for electrical contact to back metal layer are offset to prevent short circuits.
- the front and back metal contacts may be aligned.
- the dielectric layer is disposed by using various methods such as but not limited to spin coating, dip coating, spray coating, physical vapor deposition (PVD) (including sputtering, evaporation, and electron-beam evaporation, etc.), chemical vapor deposition (CVD) (including metalorganic chemical vapor deposition (MOCVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma- enhanced chemical vapor deposition (PECVD), ion-beam assisted chemical vapor deposition (IBAD CVD), etc.), atomic layer deposition (ALD), powder coating, sol gel, chemical bath deposition (CBD), close space sublimation (CSS), inkjet printing, screen printing and lamination.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- MOCVD metalorganic chemical vapor deposition
- APCVD atmospheric pressure chemical vapor deposition
- LPCVD low pressure chemical vapor deposition
- PECVD plasma- enhanced chemical
- the patterning of the dielectric layer can achieved either directly during the dielectric disposition process, for example in a printing process or by using a shadow mask, or indirectly in a process subsequent to the disposition process by using various techniques comprising wet or dry etching through the dielectric layer, patterning the dielectric layer using photolithography, electron-beam lithography, imprint lithography, and laser ablation etc.
- direct patterning is that the pattern is provided during the dielectric deposition in an additive process, without the need for a subsequent subtractive step to remove significant amounts of dielectric to form the pattern, for example using inkjet printing, shadow masking, or screen printing, etc.
- indirect patterning is that there is a patterning step subsequent to the dielectric deposition step, usually in a subtractive process or combination of processes, such as in wet or dry etching, photolithography, electron-beam
- a dielectric material of specific viscosity and drying properties is used such that the dielectric material is liquid during the application process and becomes solid after optional curing.
- the dielectric material can be cured at elevated temperature or under ultraviolet light if required, or simply at room temperature, for example by evaporation of solvent components in the dielectric material.
- the dielectric material used is photosensitive it may be cured using light and if the dielectric material used is not photosensitive it may be cured using heat. For some dielectric materials a combination of light and heat may be used for curing.
- the dielectric layer may have a thickness within a range from about 10 nm to about 10 pm, preferably, from about 20 nm to about 2000 nm, and more preferably, from about 50 nm to about 1000 nm.
- the thickness of the dielectric layer may differ substantially based on the technique used for deposition of the dielectric layer.
- the thickness of the dielectric layer deposited using screen printing may be different from that deposited using inkjet printing.
- typical film thickness obtained using inkjet printing after curing is in the range of about 10 nm to about 10 pm, more typically in the range of about 100 nm to about 1000 nm, more typically about 500 nm. Thinner layers are generally harder to control as they require better control of the spreading.
- the dielectric layer has openings to provide for electrical connection between layers above and below the dielectric.
- Each opening within the dielectric layer may have a diameter within a range from about 5 ⁇ to about 1000 pm, and preferably from about 20 pm to about 500 pm.
- Typical via width obtained by inkjet printing is in the range of about 10 pm to about 1000 pm, for example 50 pm - 500 pm, and more typically 60 pm - 250 pm. Smaller via width is generally preferred but is generally harder to control.
- the dielectric layer has no openings and an electrical connection is provided by the dielectric layer itself.
- the dielectric layer comprises organic or inorganic dielectric materials that are resistant to etching by acids such as hydrochloric acid, sulfuric acid or hydrofluoric acid, for example during an epitaxial lift off (ELO) process.
- the dielectric materials can also be transparent and provide adhesion to both metal and semiconductor layers.
- the dielectric materials can also be electrically insulating or electrically conducting.
- the organic dielectric materials may comprise any of polyolefin, polycarbonate, polyester, epoxy, fluoropolymer, derivatives thereof and combinations thereof.
- the inorganic dielectric materials may comprise any of arsenic trisulfide, arsenic selenide, a-alumina (sapphire), magnesium fluoride, calcium fluoride, diamond, derivatives thereof and combinations thereof.
- the dielectric layer contains a dielectric material with a refractive index within a range from about 1 to about 3.
- the dielectric layer can be physically or optically textured.
- the physical and/or optical texture may be provided by embedding particles within the dielectric material.
- the dielectric material comprises particles such as alumina, titania, silica or combinations thereof, to scatter light, disposed on a p-n structure.
- the dielectric layer contains a dielectric material whose coefficient of thermal expansion (CTE) is similar to that of the Group lll-V
- the CTE of the dielectric materials in the dielectric layer are dissimilar from that of the Group lll-V semiconductor onto which they are disposed.
- the dielectric layer comprises a textured surface to scatter light and improve adhesion to both metal and semiconductor layers.
- the dielectric layer comprises a surface diffraction grating to disperse light.
- the pitch and facet profile of the surface diffraction grating is chosen such that at the band gap wavelength: 1. Zeroth order diffraction is minimized and 2. First order diffraction angle is higher than the angle of total internal reflection. The diffraction grating with increased angle allows more light to be diffracted into the optoelectronic device.
- Grating of the dielectric surface may be accomplished by mechanical imprinting such as but not limited to imprint lithography, imprint stamping or laser ablation. Alternatively, other techniques such as
- photolithography electron-beam lithography, interference lithography, etc. may be used.
- Adhesion between the p-n structure and the dielectric material can be improved by texturing the p-n structure or the dielectric layer as described above, or chemically, for example with alkylphosphonate monolayers or derivatives thereof.
- the adhesion layer may have a thickness within a range from about a monolayer to about 100 A.
- the dielectric adhesion layer may be deposited by a variety of techniques including, but not limited to, atomic layer deposition (ALD), spincoating, inkjetting, chemical bath deposition (CBD) or dipcoating techniques.
- a metallic layer is then disposed on the dielectric layer.
- the metallic layer makes one or more contacts with the p-n structure through these openings.
- the metallic layer may contain at least one metal, such as silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof.
- the metallic layer may contain silver, copper, or gold.
- the metallic layer may have a thickness within a range from about 1 nm to about 10,000 nm, preferably, from about 10 nm to about 4000 nm.
- the metallic layer may comprise one or more layers made of the same or different metals.
- the metallic layer may comprise an adhesion layer comprising materials such as but not limited to nickel,
- Additional metallic layers may be also deposited, for example to improve the electrical or mechanical properties of the combination of metal layers, and may comprise a back metal with varying thickness.
- metallic contacts may be formed separately from the metallic layer.
- the metal in the apertures in the dielectric may be deposited prior to the dielectric deposition or prior to the metal reflector.
- the metallic layer comprises a metallic reflector layer disposed on or over the dielectric layer, and a plurality of reflector protrusions formed within the dielectric layer extending from the metallic reflector layer and into the p-n structure.
- the metallic reflector layer may be textured.
- the metallic reflector layer thus formed may be on the back side of the optoelectronic device.
- the metallic reflector may contain at least one metal, such as silver, gold, aluminum, nickel, copper, platinum, palladium, alloys thereof, derivatives thereof, and combinations thereof.
- the metallic reflector layer may contain silver, copper, aluminum, platinum, or gold, alloys thereof, derivatives thereof, or combinations thereof.
- the metallic reflector layer may have a thickness within a range from about 1 nm to about 10,000 nm or greater. In some examples, the thickness of the metallic reflector layer may be from about 10 nm to about 4000 nm.
- the reflector protrusions contain at least one metal, such as silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof.
- the reflector protrusions may contain silver, copper, or gold.
- Each protrusion may have a diameter within a range from about 5 ⁇ to about 100 pm, and preferably from about 50 pm to about 500 pm.
- Each protrusion may have a length within a range from about 10 nm to about 10 pm, such as from about 50 nm to about 1000 nm.
- the reflector protrusion diameter or length may be defined by the vias in the dielectric, and the dielectric layer thickness, respectively.
- an adhesion layer comprising materials such as but not limited to nickel, molybdenum, tungsten, titanium, chromium, palladium, alloys thereof, derivatives thereof, or combinations thereof.
- the adhesion layer may have a thickness within a range from about 1 A to about 100 nm.
- the metallic adhesion layer may be deposited by a variety of techniques including, but not limited to, PVD (including evaporation and sputtering for example), electroless plating, electroplating, ALD, or CVD techniques.
- additional layers such as an adhesive, epoxy, or glue layer and above that layer there is a carrier layer such as a plastic.
- a carrier layer such as a plastic.
- This can act as a handle material to hold the p-n structure, dielectric layer, and metal layer after a lift off step such as epitaxial liftoff (ELO).
- ELO epitaxial liftoff
- the mechanical properties of the adhesive and carrier layers may also affect the liftoff process itself, for example by affecting the overall stiffness of the combined handle, adhesive, p-n structure, dielectric layer, and metal layer structure during the liftoff.
- the carrier layer may also be flexible.
- a thin film optoelectronic device is subsequently removed from a support substrate or wafer, for example during an epitaxial lift off (ELO) process, a laser lift off (LLO) process, ion implantation and liftoff, liftoff by etching of a buried oxide layer or a buried porous layer, or a spalling process etc., where the thin film optoelectronic device compromises the p-n structure, the patterned dielectric layer, and the metal layer.
- ELO epitaxial lift off
- LLO laser lift off
- ion implantation and liftoff ion implantation and liftoff
- liftoff by etching of a buried oxide layer or a buried porous layer or a spalling process etc.
- the thin film optoelectronic devices thus formed may be flexible, single crystal devices.
- the optoelectronic device can include a plurality of non- continuous metal contacts that improve the reflectivity and reduce the power losses associated with the configuration of the back surface of the device.
- plasmonic losses at the back contact are reduced, improving the angle-averaged reflectivity of the back contact, which in turn increases the minority carrier density in the device under illumination, improving the external fluorescence of the device and reducing the loss of recycled band edge photons within the device.
- LED light-emitting diode
- a dielectric reflector may increase the open-circuit and operating voltage of the device. Accordingly, described below in conjunction with the accompanying figures are multiple embodiments of an optoelectronic device which utilizes such contacts.
- non-continuous metal contacts it is not necessarily implied that the metal contacts are disconnected.
- the metal contacts could be all connected together, or they could be disconnected.
- the metal contacts may be disconnected in this sense if for example there is an array of separate of contacts between the metal and the p-n structure.
- the metal contacts may be connected in this sense if for example there is a connected "finger" pattern where the metal connects to the p-n structure, such that metal does not contact the entirety of the p-n structure surface.
- the metal may also be connected to each other through the metallic layer itself.
- the front metal contacts may be non-continuous yet connected, in that they do not cover the entire front surface of the device (which would block the incident sunlight in the case of a photovoltaic cell, or the exiting light in the case of an LED), and yet are connected such that power can be input or extracted by making contact to a single point on the top metal of the device (in addition to making connection to the back of the device).
- the non-continuous metal contacts in any of the above mentioned embodiments can be arranged such that there is no alignment (in the sense of an imaginary perpendicular line drawn directly through the device) between the contacts on the top of the device and the plurality of non-continuous metal contacts directly adjacent to the p-n structure material on the back of the device.
- there is no back mirror metal In either case, this can provide an additional advantage in that the chance of a metal-on-metal short, either during device fabrication or after the device has aged, can be greatly reduced. This can improve manufacturing yield and product reliability.
- the degree of alignment between back metal and front metal is substantially unchanged.
- Figures 2a-e depict different stages of fabrication of an optoelectronic device comprising a dielectric layer according to an embodiment of the invention in which the dielectric is patterned directly, for example using an inkjet printing technique.
- a p-n structure 204 is disposed on a substrate 202.
- a dielectric layer 206 is then disposed in a pattern on the p-n structure 204 as shown in Figure 2b, for example using inkjet printing.
- the dielectric layer 206 is then optionally cured, for example using heat, light, and/or time. After curing there are openings 208 through the dielectric layer 206 as shown in Figure 2c.
- the size and shape of the dielectric 206 and the openings 208 may or may not change between patterned deposition and optional curing.
- a metallic layer 210 in then disposed on top of the dielectric layer 206 with metal protrusions forming through openings 208 as shown in Figure 2d.
- the optoelectronic device thus formed is then lifted off the substrate using a lift off technique, for example, ELO.
- ELO lift off technique
- the metallic layer is on the back side of the device, away from the light facing side, as illustrated in Figure 2e, and the metallic layer as well as the metallic protrusions enhance the efficiency of the device by scattering the light passing through the device within the device.
- the dielectric layer 206 comprises inkjet droplets.
- the inkjet droplets may wet the surface immediately on contact, at a wetting angle determined by the surface preparation and the associated surface energy.
- the droplets 206 may start spreading immediately and stop spreading once curing is complete and all the solvent has been driven out of the ink.
- the pitch may be unchanged during the cure but the droplet height may be reduced and droplet width may be increased.
- Defining the via size is a matter of controlling droplet volume, spreading rate (surface condition) and cure rate. In other embodiments involving direct patterning the droplets may be substantially unchanged between the deposition of the dielectric and any curing step.
- the optoelectronic device comprises a dielectric layer wherein the dielectric layer is patterned indirectly by using techniques such as etching or dissolving.
- a p-n structure 204 is disposed on a substrate 202.
- a dielectric layer is then disposed on the p-n structure 204.
- the dielectric layer is then etched or dissolved to provide openings through the dielectric layer.
- a metallic layer is then disposed on top of the dielectric layer with metal protrusions forming through openings.
- Figures 3a-f depict different stages of fabrication of an optoelectronic device comprising a p-n structure where the surface of the p-n structure is textured and a dielectric layer patterned using an indirect patterning technique, such as lithography, according to yet another embodiment of the invention.
- a textured p-n structure 304 is disposed on a substrate 302.
- a dielectric layer 306 is then disposed on the p-n structure 304 as shown in Figure 3c.
- the dielectric layer 306 is etched or dissolved to provide openings 308 through the dielectric layer 306 as shown in Figure 3d.
- the optoelectronic device thus formed is then lifted off the substrate using a lift off technique, for example, ELO.
- ELO lift off technique
- the metallic layer is on the back side of the device, away from the light facing side, as illustrated in Figure 3f, and the metallic layer as well as the metallic protrusions enhance the efficiency of the device by scattering the light passing through the device within the device.
- the optoelectronic device comprises a p-n structure where the surface of the p-n structure is textured and a dielectric layer patterned using a direct patterning technique, such as inkjet printing.
- a textured p-n structure 304 is disposed on a substrate 302.
- a dielectric layer is then disposed in a pattern on the p-n structure 304.
- the dielectric layer is then optionally cured, for example using heat, light, and/or time. After curing there are openings through the dielectric layer. The size and shape of the dielectric and the openings may or may not change between patterned deposition and optional curing.
- a metallic layer in then disposed on top of the dielectric layer with metal protrusions forming through openings.
- Figures 4 a-e depict exemplary embodiments of an optoelectronic device comprising a dielectric layer after it is separated from the substrate according to the present invention.
- Figures 4 a-e generally depict different embodiments comprising a p-n structure 404, a dielectric layer 406 and a metallic layer 410.
- the surface of the p-n structure 404 can be smooth with patterned dielectric layer 406.
- the surface of the p-n structure can be textured.
- the dielectric layer 406 may or may not conform to the surface texture of the p-n structure 404.
- Figures 4a, 4b and 4e illustrate the dielectric layer 406 conforming to the surface texture of the p-n structure 404.
- Figures 4c and 4d illustrate the dielectric layer 406 not conforming to the surface texture of the p-n structure 404.
- the dielectric layer 406 may be patterned indirectly as illustrated in figures 4b, 4d and 4e by a subtractive process such as wet or dry etching, photolithography, electron-beam lithography, imprint lithography, or laser ablation, etc.
- the dielectric layer 406 may be patterned directly as illustrated in figures 4a and 4c by an additive process such as inkjet printing, shadow masking, or screen printing, etc..
- the dielectric layer 406 may inherit the texture of the p-n structure, as shown in figure 4e.
- the dielectric layer may have a different texture from the p-n structure, for example, because of an additional texturing step, or because of a property of the dielectric.
- the dielectric may be smooth, as shown in figure 4b.
- the metallic layer 410 may also be textured (not shown) or smooth. [0066] The metal layer 410 may or may not conform to the structure of the dielectric layer 406.
- the surface of the p-n structure 404 is textured, with the dielectric layer 406 disposed on or over the p-n structure 404, where the dielectric layer 406 may not inherit the surface structure of the p-n structure 404, and a metal layer 410 disposed on or over the dielectric layer 406 with a texture conforming that of the dielectric layer 406.
- the dielectric layer 406 may inherit the surface structure of the p-n structure 404 and a metal layer 410 disposed on or over the dielectric layer 406 with a texture
- Figure 5 illustrates an optoelectronic device with front metal contacts after it is separated from the substrate according to an embodiment of the invention.
- a dielectric layer 506 is disposed on a p-n structure 504.
- the dielectric layer 506 can be patterned either directly or indirectly, as described above, to provide openings 508 through the dielectric layer 506 as shown.
- a metallic layer 510 is then disposed on top of the dielectric layer 506 with metal protrusions forming through openings 508.
- the optoelectronic device is also provided with front metal contacts 512.
- the front metal contacts 512 are arranged such that there is no alignment (in the sense of an imaginary perpendicular line drawn directly through the device) between the front metal contacts 512 on the top of the device and the plurality of non-continuous metal contacts directly adjacent to the p-n structure material on the back of the device as illustrated by metal protrusions formed through openings 508.
- the front and back metal contacts may be aligned.
- an anti-reflection coating (ARC) may be deposited on the optoelectronic device as well (not shown in the figures).
- the front and/or back metal contacts can be deposited on the optoelectronic device before or after the device is separated from the substrate.
- additional layers can be deposited on the optoelectronic device before or after the device is separated from the substrate.
Abstract
An optoelectronic device and a method for fabricating the optoelectronic device are disclosed. The optoelectronic device comprises a p-n structure, a patterned dielectric layer comprising a dielectric material and a metal layer disposed on the dielectric layer. The metal layer makes one or more contact to the p-n structure through the patterned dielectric layer. The dielectric material may be chemically resistant to acids and may provide adhesion to the p-n structure and the metal layer. The method for fabricating an optoelectronic device comprises providing a p-n structure, providing a dielectric layer on the p-n structure and providing a metal layer on the dielectric layer and then lifting the device off the substrate, such that after the lift off the p-n structure is closer than the patterned dielectric layer to a front side of the device; wherein the device comprises the p-n structure, the patterned dielectric layer, and the metal layer.
Description
OPTOELECTRONIC DEVICE WITH DIELECTRIC LAYER AND METHOD OF
MANUFACTURE
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Application No. 14/846,675 entitled OPTOELECTRONIC DEVICE WITH DIELECTRIC LAYER AND METHOD OF MANUFACTURE", filed September 4, 2015. The disclosures of the prior application is hereby incorporated in its entirety by reference.
FIELD OF THE INVENTION
[0002] The present invention relates generally to fabrication of optoelectronic devices and more particularly to optoelectronic devices including a dielectric layer.
BACKGROUND OF THE INVENTION
[0003] It is sometimes desirable to improve the reflectivity of the back surface of an optoelectronic device such as a photovoltaic cell or a light-emitting diode to improve the performance thereof without significantly affecting the cost or adding to overall size of the device. Accordingly, there is a need to provide such an improvement while addressing the above identified issues. The present invention addresses such a need.
SUMMARY OF THE INVENTION
[0004] An optoelectronic device and a method for fabricating the optoelectronic device are disclosed. The optoelectronic device comprises a p-n structure, a patterned dielectric layer on the p-n structure and a metal layer disposed on the dielectric layer. The dielectric layer comprises a dielectric material, wherein the dielectric material is chemically resistant to acids and provides adhesion to the p-n structure and the metal layer. The metal layer makes one or more contacts to the p- n structure through one or more openings in the patterned dielectric layer.
[0005] A method for fabricating an optoelectronic device comprises providing an epitaxially grown p-n structure, providing a dielectric layer on the p-n structure and providing a metal layer on the dielectric layer and then lifting the device off the substrate, such that after the lift off the p-n structure is closer than the patterned dielectric layer to a front side of the device; wherein the device comprises the p-n structure, the patterned dielectric layer, and the metal layer. The dielectric layer comprises a dielectric material and has a chemical resistance to acids and provides adhesion to the p-n structure and the metal layer.
[0006] In an embodiment, the method comprises providing a p-n structure;
directly patterning a dielectric material on the p-n structure; and providing a metal layer on the dielectric material, wherein the dielectric material has a chemical resistance to acids and provides adhesion to the p-n structure and the metal layer. The method further includes providing one or more contact between the p-n structure and the metal layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The appended drawings illustrate only some embodiments and are therefore not to be considered limiting of scope.
[0008] Figure 1 illustrates a flow chart depicting a process for forming an optoelectronic device comprising a dielectric layer according to embodiments described herein.
[0009] Figures 2a-e depict different stages of fabrication of an optoelectronic device comprising a dielectric layer according to an embodiment of the invention.
[0010] Figures 3a-f depict different stages of fabrication of an optoelectronic device comprising a dielectric layer according to another embodiment of the invention.
[0011] Figures 4a-e depict exemplary embodiments of an optoelectronic device comprising a dielectric layer according to the present invention.
[0012] Figure 5 illustrates an optoelectronic device with front metal contacts according to an embodiment of the invention.
DETAILED DESCRIPTION
[0013] The present invention relates generally to optoelectronic devices and more particularly to an optoelectronic device with a dielectric layer. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the
present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
[0014] Embodiments of the inventions generally relate to optoelectronic devices more specifically to optoelectronic semiconductor devices including one or more textured layers and the fabrication processes for forming such optoelectronic devices. Embodiments of the invention also relate to the fabrication of thin film devices, such as photovoltaic devices, light-emitting diodes, or other optoelectronic devices, which contain a dielectric layer on the back side.
[0015] A method for forming an optoelectronic device comprising a dielectric layer according to an embodiment of the invention is described herein. In an embodiment, the method comprises providing a p-n structure deposited on a substrate. A dielectric layer is then patterned on the p-n structure thus formed providing one or more openings for electrical contacts. A metallic layer is then disposed on the dielectric layer such that the metal layer makes one or more contacts with the p-n structure through the openings provided in the dielectric layer. The p-n structure, the dielectric layer and the metal layer are then lifted off the substrate. Embodiments may also provide back reflectors which are metallic reflectors or metal-dielectric reflectors.
[0016] Many of the thin film devices described herein generally contain epitaxially grown layers which are formed on a sacrificial layer disposed on or over a support substrate or wafer. The thin film devices thus formed may be flexible single crystal devices. Once the thin film devices are formed by epitaxy processes, the thin film devices are subsequently removed from a support substrate or wafer, for example
during an epitaxial lift off (ELO) process, a laser lift off (LLO) process, ion
implantation and liftoff, liftoff by etching of a buried oxide layer or a buried porous layer, or a spalling process etc.
[0017] Herein, a layer can be described as being deposited "on or over" one or more other layers. This term indicates that the layer can be deposited directly on top of the other layer(s), or can indicate that one or more additional layers can be deposited between the layer and the other layer(s) in some embodiments. Also, the other layer(s) can be arranged in any order. To describe the features of the present invention in more detail refer now to the following discussion in conjunction with the accompanying figures.
[0018] Figure 1 illustrates a flow chart depicting a process for forming an optoelectronic device comprising a dielectric layer according to embodiments described herein. In an embodiment, the method comprises providing a p-n structure on a substrate via step 02.
[0019] In some embodiments, a sacrificial layer may be disposed on the substrate prior to deposition of the p-n structure, for example to enable liftoff of the p-n structure in an epitaxial liftoff (ELO) process. The sacrificial layer may comprise AIAs, AIGaAs, AIGalnP, or AllnP, or other layers with high Al content, or
combinations thereof and is utilized to form a lattice structure for the layers contained within the cell, and then etched and removed during the ELO process. In other embodiments, alternative liftoff processes such as laser lift off (LLO), ion
implantation and liftoff, liftoff by etching of a buried oxide layer or a buried porous layer, or spalling may be used.
[0020] In an embodiment, the p-n structure may be grown on a substrate, for example, a gallium arsenide wafer may be used, with epitaxially grown layers as thin films made of Group lll-V materials. Alternatively a germanium wafer, or an indium phosphide wafer, or a sapphire wafer, or a gallium nitride wafer, or a silicon wafer may be used. The p-n structure may be formed by epitaxial growth using various techniques, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), metalorganic vapor phase epitaxy (MOVPE or OMVPE), liquid phase epitaxy (LPE), hydride vapor phase epitaxy (HVPE), etc. In some embodiments the p-n structure is substantially a single crystal.
[0021] In some embodiments, the epitaxially grown layers of Group lll-V materials can be formed using a high growth rate vapor deposition process. The high growth rate deposition process allows for growth rates of greater than 5 pm/hr, such as about 10 pm/hr or greater, or as high as about 100 pm/hr or greater. The high growth rate process includes heating a wafer to a deposition temperature of about
550°C or greater, within a processing system, exposing the wafer to a deposition gas containing a chemical precursor, such as a group Ill-containing precursor gas and a group V-containing precursor gas, and depositing a layer containing a Group lll-V material on the wafer. The group Mi-containing precursor gas may contain a group III element, such as indium, gallium, or aluminum. For example, the group Ill-containing precursor gas may be chosen from the list: trimethyl aluminum, triethyl aluminum, trimethyl gallium, triethyl gallium, trimethyl indium, triethyl indium, di- isopropylmethylindium, ethyldimethylindium. The group V-containing precursor gas may contain a group V element, such as nitrogen, phosphorus, arsenic, or antimony.
For example, the group V-containing precursor gas may be chosen from the list: phenyl hydrazine, dimethylhydrazine, tertiarybutylamine, ammonia, phosphine,
tertiarybutyl phosphine, bisphosphinoethane, arsine, tertiarybutyl arsine, monoethyl arsine, trimethyl arsine, trimethyl antimony, triethyl antimony, tri-isopropyl antimony, stibine.
[0022] The deposition processes for depositing or forming Group lll-V materials, as described herein, can be conducted in various types of deposition chambers. For example, one continuous feed deposition chamber that may be utilized for growing, depositing, or otherwise forming Group lll-V materials is described in the commonly assigned U.S. Patent Application Nos. 12/475,131 and 12/475,169, both filed on May 29, 2009, which are herein incorporated by reference in their entireties.
[0023] Some examples of layers usable in device and methods for forming such layers are disclosed in copending U.S. Patent Application No. 12/939,077, filed November 3, 2010, and incorporated herein by reference in its entirety.
[0024] The p-n structure may contain various arsenide, nitride, and phosphide layers, such as but not limited to GaAs, AIGaAs, InGaP, InGaAs, AllnGaP,
AllnGaAs, InGaAsP, AllnGaAsP, GaN, InGaN, AIGaN, AllnGaN, GaP, alloys thereof, derivatives thereof and combinations thereof. In general, the p-n structure comprises a Group lll-V semiconductor and includes at least one of the group consisting of: gallium, aluminum, indium, phosphorus, nitrogen, and arsenic. In one embodiment the p-n structure comprises gallium arsenide material, and derivatives thereof.
[0025] For example, in one embodiment the p-n structure comprises a p-type aluminum gallium arsenide layer or stack disposed above an n-type gallium arsenide layer or stack. In one example, the p-type aluminum gallium arsenide stack has a thickness within a range from about 100 nm to about 3,000 nm and the n-type gallium arsenide stack has a thickness within a range from about 100 nm to about
3,000 nm. In one example, the n-type gallium arsenide stack has a thickness within a range from about 700 nm to about 2500 nm.
[0026] In another embodiment, the p-n structure comprises indium gallium phosphide material, and derivatives thereof. The indium gallium phosphide material may contain various indium gallium phosphide layers, such as an indium gallium phosphide, aluminum indium gallium phosphide, etc. For example, in one embodiment the p-n structure comprises a p-type aluminum indium gallium phosphide layer or stack disposed above an n-type indium gallium phosphide layer or stack.
[0027] In one example, the p-type aluminum indium gallium phosphide stack has a thickness within a range from about 100 nm to about 3,000 nm and the n-type indium gallium phosphide stack has a thickness within a range from about 100 nm to about 3,000 nm. In one example, the n-type indium gallium phosphide stack has a thickness within a range from about 400 nm to about 1 ,500 nm.
[0028] In another embodiment, the p-n structure comprises indium gallium arsenide phosphide material, and derivatives thereof. The indium gallium arsenide phosphide material may contain various indium gallium arsenide phosphide layers, such as an indium gallium phosphide, aluminum indium gallium phosphide, indium gallium arsenide phosphide, aluminum indium gallium arsenide phosphide etc. For example, in one embodiment the p-n structure comprises a p-type aluminum indium gallium phosphide layer or stack disposed above an n-type indium gallium arsenide phosphide layer or stack.
[0029] In another embodiment, the p-n structure comprises aluminum indium gallium phosphide material, and derivatives thereof. The aluminum indium gallium
phosphide material may contain various aluminum indium gallium phosphide layers, such as an aluminum indium phosphide, aluminum indium gallium phosphide, etc. For example, in one embodiment the p-n structure comprises a p-type aluminum indium phosphide layer or stack disposed above an n-type aluminum indium gallium phosphide layer or stack.
[0030] In another embodiment, the p-n structure comprises multiple p-n junctions. Each p-n junction may contain various arsenide, nitride, and phosphide layers, such as GaAs, AIGaAs, InGaP, InGaAs, AllnGaP, AllnGaAs, InGaAsP, AllnGaAsP, GaN, InGaN, AIGaN, AllnGaN, GaP, alloys thereof, derivatives thereof and combinations thereof. In general each p-n junction comprises a Group lll-V semiconductor and includes at least one of the group consisting of: gallium, aluminum, indium, phosphorus, nitrogen, and arsenic.
[0031] Furthermore, the junction formed between the two layers can be a heterojunction that is, the N-layer and P-layer could be of different material or a homojunction, that is, both the N-layer and P-layer could be the same material (both layers being GaAs or both layers InGaP, for example) and that would be within the spirit and scope of the present invention. Also the p-n structure could have either doping polarity, with n-type material at the top of the device and p-type material at the bottom, or alternatively with p-type material at the top of the device and n-type material at the bottom. Furthermore, the optoelectronic device could be comprised of multiple p-n layers grown in series, for example, to form a multijunction photovoltaic cell.
[0032] In some embodiments, the p-n structure may comprise a textured surface. This textured surface can improve the scattering of light at that surface, as well as
improve adhesion to both metal and dielectric layers. In some embodiments, the texturing is achieved during the growth of the materials that comprise the p-n structure. This may be achieved at least in part for by exploiting a lattice mismatch between at least two materials in the p-n structure, for example in a Stranski- Krastanov process or a Volmer-Weber process. In another embodiment, a layer in or on the p-n structure may act as an etch mask and texturing can be provided by an etching process. In yet another embodiment, texturing may be provided by physical abrasion such as sandpaper or sandblasting or particle blasting or similar processes.
[0033] In addition, in an embodiment, the back side and/or the front side of the p- n structure can be textured to improve light scattering into and/or out of the device.
[0034] Referring back to Figure 1 , a dielectric layer is then patterned on the p-n structure, via step 104 providing one or more openings for electrical contacts. In one embodiment, a dielectric layer with an array of openings is disposed on a p-n structure, forming a plurality of apertures extending into the p-n structure. In an embodiment, the openings for electrical contacts may be patterned such that front metal contacts and openings for electrical contact to back metal layer are offset to prevent short circuits. In another embodiment, the front and back metal contacts may be aligned.
[0035] In an embodiment, the dielectric layer is disposed by using various methods such as but not limited to spin coating, dip coating, spray coating, physical vapor deposition (PVD) (including sputtering, evaporation, and electron-beam evaporation, etc.), chemical vapor deposition (CVD) (including metalorganic chemical vapor deposition (MOCVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma-
enhanced chemical vapor deposition (PECVD), ion-beam assisted chemical vapor deposition (IBAD CVD), etc.), atomic layer deposition (ALD), powder coating, sol gel, chemical bath deposition (CBD), close space sublimation (CSS), inkjet printing, screen printing and lamination. The patterning of the dielectric layer can achieved either directly during the dielectric disposition process, for example in a printing process or by using a shadow mask, or indirectly in a process subsequent to the disposition process by using various techniques comprising wet or dry etching through the dielectric layer, patterning the dielectric layer using photolithography, electron-beam lithography, imprint lithography, and laser ablation etc.
[0036] What is meant by "directly patterning" is that the pattern is provided during the dielectric deposition in an additive process, without the need for a subsequent subtractive step to remove significant amounts of dielectric to form the pattern, for example using inkjet printing, shadow masking, or screen printing, etc. What is meant by "indirect patterning" is that there is a patterning step subsequent to the dielectric deposition step, usually in a subtractive process or combination of processes, such as in wet or dry etching, photolithography, electron-beam
lithography, imprint lithography, or laser ablation, etc.
[0037] For depositing a dielectric layer using an inkjet printing technique, a dielectric material of specific viscosity and drying properties is used such that the dielectric material is liquid during the application process and becomes solid after optional curing. Depending on the properties of the dielectric material used, it can be cured at elevated temperature or under ultraviolet light if required, or simply at room temperature, for example by evaporation of solvent components in the dielectric material. If the dielectric material used is photosensitive it may be cured using light
and if the dielectric material used is not photosensitive it may be cured using heat. For some dielectric materials a combination of light and heat may be used for curing.
[0038] The dielectric layer may have a thickness within a range from about 10 nm to about 10 pm, preferably, from about 20 nm to about 2000 nm, and more preferably, from about 50 nm to about 1000 nm. In some embodiments, the thickness of the dielectric layer may differ substantially based on the technique used for deposition of the dielectric layer. For example, the thickness of the dielectric layer deposited using screen printing may be different from that deposited using inkjet printing. For example, typical film thickness obtained using inkjet printing after curing is in the range of about 10 nm to about 10 pm, more typically in the range of about 100 nm to about 1000 nm, more typically about 500 nm. Thinner layers are generally harder to control as they require better control of the spreading.
[0039] In some embodiments, the dielectric layer has openings to provide for electrical connection between layers above and below the dielectric. Each opening within the dielectric layer may have a diameter within a range from about 5 μ to about 1000 pm, and preferably from about 20 pm to about 500 pm. Typical via width obtained by inkjet printing is in the range of about 10 pm to about 1000 pm, for example 50 pm - 500 pm, and more typically 60 pm - 250 pm. Smaller via width is generally preferred but is generally harder to control. In other embodiments the dielectric layer has no openings and an electrical connection is provided by the dielectric layer itself.
[0040] In one embodiment, the dielectric layer comprises organic or inorganic dielectric materials that are resistant to etching by acids such as hydrochloric acid, sulfuric acid or hydrofluoric acid, for example during an epitaxial lift off (ELO)
process. The dielectric materials can also be transparent and provide adhesion to both metal and semiconductor layers. The dielectric materials can also be electrically insulating or electrically conducting. The organic dielectric materials may comprise any of polyolefin, polycarbonate, polyester, epoxy, fluoropolymer, derivatives thereof and combinations thereof. The inorganic dielectric materials may comprise any of arsenic trisulfide, arsenic selenide, a-alumina (sapphire), magnesium fluoride, calcium fluoride, diamond, derivatives thereof and combinations thereof.
[0041] In some embodiments, the dielectric layer contains a dielectric material with a refractive index within a range from about 1 to about 3. In an embodiment, the dielectric layer can be physically or optically textured. The physical and/or optical texture may be provided by embedding particles within the dielectric material. In this embodiment, the dielectric material comprises particles such as alumina, titania, silica or combinations thereof, to scatter light, disposed on a p-n structure.
[0042] In an embodiment, the dielectric layer contains a dielectric material whose coefficient of thermal expansion (CTE) is similar to that of the Group lll-V
semiconductor onto which it is disposed. In another embodiment the CTE of the dielectric materials in the dielectric layer are dissimilar from that of the Group lll-V semiconductor onto which they are disposed.
[0043] In another embodiment, the dielectric layer comprises a textured surface to scatter light and improve adhesion to both metal and semiconductor layers.
Texturing of the dielectric surface can be achieved by particle or other mask deposition followed by etching, particle blasting, mechanical imprinting such as imprint lithography or stamping, laser ablation, wet etching or dry etching.
[0044] In another embodiment, the dielectric layer comprises a surface diffraction grating to disperse light. The pitch and facet profile of the surface diffraction grating is chosen such that at the band gap wavelength: 1. Zeroth order diffraction is minimized and 2. First order diffraction angle is higher than the angle of total internal reflection. The diffraction grating with increased angle allows more light to be diffracted into the optoelectronic device. Grating of the dielectric surface may be accomplished by mechanical imprinting such as but not limited to imprint lithography, imprint stamping or laser ablation. Alternatively, other techniques such as
photolithography, electron-beam lithography, interference lithography, etc. may be used.
[0045] Adhesion between the p-n structure and the dielectric material can be improved by texturing the p-n structure or the dielectric layer as described above, or chemically, for example with alkylphosphonate monolayers or derivatives thereof. The adhesion layer may have a thickness within a range from about a monolayer to about 100 A. The dielectric adhesion layer may be deposited by a variety of techniques including, but not limited to, atomic layer deposition (ALD), spincoating, inkjetting, chemical bath deposition (CBD) or dipcoating techniques.
[0046] Referring again back to Figure 1 , a metallic layer is then disposed on the dielectric layer. In some embodiments, in which the dielectric layer has been provided with openings via step 106, the metallic layer makes one or more contacts with the p-n structure through these openings.
[0047] The metallic layer may contain at least one metal, such as silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof. In specific
examples, the metallic layer may contain silver, copper, or gold. The metallic layer may have a thickness within a range from about 1 nm to about 10,000 nm, preferably, from about 10 nm to about 4000 nm.
[0048] In an embodiment, the metallic layer may comprise one or more layers made of the same or different metals. For example, the metallic layer may comprise an adhesion layer comprising materials such as but not limited to nickel,
molybdenum, tungsten, titanium, chromium, palladium, alloys thereof, derivatives thereof, or combinations thereof with a thickness less than 100 nm, and preferably less than 20 nm, along with a reflector layer comprising materials such as but not limited to silver, gold, aluminum, copper, platinum, alloys thereof, derivatives thereof, or combinations thereof with a thickness more than 50 nm.
[0049] Additional metallic layers may be also deposited, for example to improve the electrical or mechanical properties of the combination of metal layers, and may comprise a back metal with varying thickness. In another embodiment, metallic contacts may be formed separately from the metallic layer. For example the metal in the apertures in the dielectric may be deposited prior to the dielectric deposition or prior to the metal reflector.
[0050] In an embodiment, the metallic layer comprises a metallic reflector layer disposed on or over the dielectric layer, and a plurality of reflector protrusions formed within the dielectric layer extending from the metallic reflector layer and into the p-n structure. In an embodiment, the metallic reflector layer may be textured. The metallic reflector layer thus formed may be on the back side of the optoelectronic device. For example, if the optoelectronic device is a photovoltaic device, the metallic reflector may be on the side of the device away from incident light.
[0051] The metallic reflector may contain at least one metal, such as silver, gold, aluminum, nickel, copper, platinum, palladium, alloys thereof, derivatives thereof, and combinations thereof. In specific examples, the metallic reflector layer may contain silver, copper, aluminum, platinum, or gold, alloys thereof, derivatives thereof, or combinations thereof. The metallic reflector layer may have a thickness within a range from about 1 nm to about 10,000 nm or greater. In some examples, the thickness of the metallic reflector layer may be from about 10 nm to about 4000 nm.
[0052] Similarly, the reflector protrusions contain at least one metal, such as silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof. In specific examples, the reflector protrusions may contain silver, copper, or gold. Each protrusion may have a diameter within a range from about 5 μιτι to about 100 pm, and preferably from about 50 pm to about 500 pm. Each protrusion may have a length within a range from about 10 nm to about 10 pm, such as from about 50 nm to about 1000 nm. In some embodiments the reflector protrusion diameter or length may be defined by the vias in the dielectric, and the dielectric layer thickness, respectively.
[0053] In an embodiment, under the reflector protrusions there is an adhesion layer comprising materials such as but not limited to nickel, molybdenum, tungsten, titanium, chromium, palladium, alloys thereof, derivatives thereof, or combinations thereof. The adhesion layer may have a thickness within a range from about 1 A to about 100 nm. The metallic adhesion layer may be deposited by a variety of
techniques including, but not limited to, PVD (including evaporation and sputtering for example), electroless plating, electroplating, ALD, or CVD techniques.
[0054] In an embodiment, above the metallic layer are additional layers such as an adhesive, epoxy, or glue layer and above that layer there is a carrier layer such as a plastic. This can act as a handle material to hold the p-n structure, dielectric layer, and metal layer after a lift off step such as epitaxial liftoff (ELO). The mechanical properties of the adhesive and carrier layers may also affect the liftoff process itself, for example by affecting the overall stiffness of the combined handle, adhesive, p-n structure, dielectric layer, and metal layer structure during the liftoff. The carrier layer may also be flexible.
[0055] Referring back to Figure 1 , the p-n structure, the dielectric layer and the metal layer are then lifted off the substrate, via step 108. In some embodiments a thin film optoelectronic device is subsequently removed from a support substrate or wafer, for example during an epitaxial lift off (ELO) process, a laser lift off (LLO) process, ion implantation and liftoff, liftoff by etching of a buried oxide layer or a buried porous layer, or a spalling process etc., where the thin film optoelectronic device compromises the p-n structure, the patterned dielectric layer, and the metal layer. The thin film optoelectronic devices thus formed may be flexible, single crystal devices.
[0056] In an embodiment, the optoelectronic device can include a plurality of non- continuous metal contacts that improve the reflectivity and reduce the power losses associated with the configuration of the back surface of the device. By reducing the amount of metal in direct contact with the semiconductor, plasmonic losses at the back contact are reduced, improving the angle-averaged reflectivity of the back
contact, which in turn increases the minority carrier density in the device under illumination, improving the external fluorescence of the device and reducing the loss of recycled band edge photons within the device. These features are of particular importance in a photovoltaic cell and for light-emitting diode (LED) applications. For example, in a photovoltaic cell, a dielectric reflector may increase the open-circuit and operating voltage of the device. Accordingly, described below in conjunction with the accompanying figures are multiple embodiments of an optoelectronic device which utilizes such contacts.
[0057] By "non-continuous" metal contacts it is not necessarily implied that the metal contacts are disconnected. The metal contacts could be all connected together, or they could be disconnected. The metal contacts may be disconnected in this sense if for example there is an array of separate of contacts between the metal and the p-n structure. The metal contacts may be connected in this sense if for example there is a connected "finger" pattern where the metal connects to the p-n structure, such that metal does not contact the entirety of the p-n structure surface. The metal may also be connected to each other through the metallic layer itself. The front metal contacts may be non-continuous yet connected, in that they do not cover the entire front surface of the device (which would block the incident sunlight in the case of a photovoltaic cell, or the exiting light in the case of an LED), and yet are connected such that power can be input or extracted by making contact to a single point on the top metal of the device (in addition to making connection to the back of the device).
[0058] The non-continuous metal contacts in any of the above mentioned embodiments can be arranged such that there is no alignment (in the sense of an
imaginary perpendicular line drawn directly through the device) between the contacts on the top of the device and the plurality of non-continuous metal contacts directly adjacent to the p-n structure material on the back of the device. Alternatively there may be some area of alignment, but reduced relative to the total area of the front metal. In some embodiments, there may still be alignment between the front metal and the back mirror or the reflective metal, but there may be a dielectric between them. In other embodiments there is no back mirror metal. In either case, this can provide an additional advantage in that the chance of a metal-on-metal short, either during device fabrication or after the device has aged, can be greatly reduced. This can improve manufacturing yield and product reliability. In other embodiments the degree of alignment between back metal and front metal is substantially unchanged.
[0059] Finally, it is well understood by those of ordinary skill in the art that additional layers could exist either on top of the structures shown, or underneath them. For example, underneath the reflector metal there could be other support layers such as metals, polymers, glasses, or any combination thereof.
[0060] Figures 2a-e depict different stages of fabrication of an optoelectronic device comprising a dielectric layer according to an embodiment of the invention in which the dielectric is patterned directly, for example using an inkjet printing technique. As shown in Figure 2a, a p-n structure 204 is disposed on a substrate 202. A dielectric layer 206 is then disposed in a pattern on the p-n structure 204 as shown in Figure 2b, for example using inkjet printing. The dielectric layer 206 is then optionally cured, for example using heat, light, and/or time. After curing there are openings 208 through the dielectric layer 206 as shown in Figure 2c. The size and shape of the dielectric 206 and the openings 208 may or may not change between
patterned deposition and optional curing. A metallic layer 210 in then disposed on top of the dielectric layer 206 with metal protrusions forming through openings 208 as shown in Figure 2d. The optoelectronic device thus formed is then lifted off the substrate using a lift off technique, for example, ELO. For example, in case of a photovoltaic device, once the device is lifted off, the metallic layer is on the back side of the device, away from the light facing side, as illustrated in Figure 2e, and the metallic layer as well as the metallic protrusions enhance the efficiency of the device by scattering the light passing through the device within the device.
[0061] In an embodiment, the dielectric layer 206 comprises inkjet droplets. The inkjet droplets may wet the surface immediately on contact, at a wetting angle determined by the surface preparation and the associated surface energy. The droplets 206 may start spreading immediately and stop spreading once curing is complete and all the solvent has been driven out of the ink. The pitch may be unchanged during the cure but the droplet height may be reduced and droplet width may be increased. Defining the via size is a matter of controlling droplet volume, spreading rate (surface condition) and cure rate. In other embodiments involving direct patterning the droplets may be substantially unchanged between the deposition of the dielectric and any curing step.
[0062] In an embodiment, the optoelectronic device comprises a dielectric layer wherein the dielectric layer is patterned indirectly by using techniques such as etching or dissolving. For example, a p-n structure 204 is disposed on a substrate 202. A dielectric layer is then disposed on the p-n structure 204. The dielectric layer is then etched or dissolved to provide openings through the dielectric layer. A
metallic layer is then disposed on top of the dielectric layer with metal protrusions forming through openings.
[0063] Figures 3a-f depict different stages of fabrication of an optoelectronic device comprising a p-n structure where the surface of the p-n structure is textured and a dielectric layer patterned using an indirect patterning technique, such as lithography, according to yet another embodiment of the invention. As shown in Figures 3a and 3b, a textured p-n structure 304 is disposed on a substrate 302. A dielectric layer 306 is then disposed on the p-n structure 304 as shown in Figure 3c. The dielectric layer 306 is etched or dissolved to provide openings 308 through the dielectric layer 306 as shown in Figure 3d. A metallic layer 310 in then disposed on top of the dielectric layer 306 with metal protrusions forming through openings 308 as shown in Figure 3e. The optoelectronic device thus formed is then lifted off the substrate using a lift off technique, for example, ELO. For example, in case of a photovoltaic device, once the device is lifted off, the metallic layer is on the back side of the device, away from the light facing side, as illustrated in Figure 3f, and the metallic layer as well as the metallic protrusions enhance the efficiency of the device by scattering the light passing through the device within the device.
[0064] In an embodiment, the optoelectronic device comprises a p-n structure where the surface of the p-n structure is textured and a dielectric layer patterned using a direct patterning technique, such as inkjet printing. As shown in Figures 3a and 3b, a textured p-n structure 304 is disposed on a substrate 302. A dielectric layer is then disposed in a pattern on the p-n structure 304. The dielectric layer is then optionally cured, for example using heat, light, and/or time. After curing there are openings through the dielectric layer. The size and shape of the dielectric and
the openings may or may not change between patterned deposition and optional curing. A metallic layer in then disposed on top of the dielectric layer with metal protrusions forming through openings.
[0065] Figures 4 a-e depict exemplary embodiments of an optoelectronic device comprising a dielectric layer after it is separated from the substrate according to the present invention. Figures 4 a-e generally depict different embodiments comprising a p-n structure 404, a dielectric layer 406 and a metallic layer 410. As shown in figures 4a and 4b, the surface of the p-n structure 404 can be smooth with patterned dielectric layer 406. As shown in figures 4c, 4d and 4e, the surface of the p-n structure can be textured. The dielectric layer 406 may or may not conform to the surface texture of the p-n structure 404. Figures 4a, 4b and 4e illustrate the dielectric layer 406 conforming to the surface texture of the p-n structure 404. Figures 4c and 4d illustrate the dielectric layer 406 not conforming to the surface texture of the p-n structure 404. The dielectric layer 406 may be patterned indirectly as illustrated in figures 4b, 4d and 4e by a subtractive process such as wet or dry etching, photolithography, electron-beam lithography, imprint lithography, or laser ablation, etc. Alternatively, the dielectric layer 406 may be patterned directly as illustrated in figures 4a and 4c by an additive process such as inkjet printing, shadow masking, or screen printing, etc.. The dielectric layer 406 may inherit the texture of the p-n structure, as shown in figure 4e. Alternatively, the dielectric layer may have a different texture from the p-n structure, for example, because of an additional texturing step, or because of a property of the dielectric. Alternatively the dielectric may be smooth, as shown in figure 4b. The metallic layer 410 may also be textured (not shown) or smooth.
[0066] The metal layer 410 may or may not conform to the structure of the dielectric layer 406. In a preferred embodiment, the surface of the p-n structure 404 is textured, with the dielectric layer 406 disposed on or over the p-n structure 404, where the dielectric layer 406 may not inherit the surface structure of the p-n structure 404, and a metal layer 410 disposed on or over the dielectric layer 406 with a texture conforming that of the dielectric layer 406. In an alternate embodiment, the dielectric layer 406 may inherit the surface structure of the p-n structure 404 and a metal layer 410 disposed on or over the dielectric layer 406 with a texture
conforming to that of the dielectric layer 406 (not shown).
[0067] Figure 5 illustrates an optoelectronic device with front metal contacts after it is separated from the substrate according to an embodiment of the invention. As shown in Figure 5, a dielectric layer 506 is disposed on a p-n structure 504. The dielectric layer 506 can be patterned either directly or indirectly, as described above, to provide openings 508 through the dielectric layer 506 as shown. A metallic layer 510 is then disposed on top of the dielectric layer 506 with metal protrusions forming through openings 508. The optoelectronic device is also provided with front metal contacts 512. In some embodiments the front metal contacts 512 are arranged such that there is no alignment (in the sense of an imaginary perpendicular line drawn directly through the device) between the front metal contacts 512 on the top of the device and the plurality of non-continuous metal contacts directly adjacent to the p-n structure material on the back of the device as illustrated by metal protrusions formed through openings 508. In another embodiment, the front and back metal contacts may be aligned. Optionally, an anti-reflection coating (ARC) may be deposited on the optoelectronic device as well (not shown in the figures).
[0068] In an embodiment, the front and/or back metal contacts can be deposited on the optoelectronic device before or after the device is separated from the substrate. In another embodiment, additional layers can be deposited on the optoelectronic device before or after the device is separated from the substrate.
[0069] Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. For example, the metal contacts on either the front side and/or the back side of a device can be replaced by a highly conductive yet transparent or semi-transparent layer, for example a transparent conductive oxide and that would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
Claims
1. An optoelectronic device comprising:
a p-n structure;
a patterned dielectric layer on the p-n structure; and
a metal layer disposed on the dielectric layer;
wherein the patterned dielectric layer comprises a dielectric material and wherein the dielectric material has a chemical resistance to acids and provides adhesion to the p-n structure and the metal layer; and
wherein the metal layer makes one or more contact to the p-n structure.
2. The optoelectronic device of claim 1 , wherein the p-n structure comprises one or more group lll-V semiconductor layers.
3. The optoelectronic device of claim 1, wherein the p-n structure comprises a physically textured surface.
4. The optoelectronic device of claim 1 , wherein the dielectric layer comprises dielectric materials that are resistant to etching by acids such as hydrochloric acid, sulfuric acid or hydrofluoric acid during an epitaxial lift off (ELO) process.
5. The optoelectronic device of claim 4, wherein the dielectric materials are organic comprising any of polyolefin, polycarbonate, polyester, epoxy, fluoropolymer, derivatives thereof and combinations thereof.
6. The optoelectronic device of claim 4, wherein the dielectric materials are inorganic comprising any of arsenic trisulfide, arsenic selenide, a-alumina (sapphire), magnesium fluoride, calcium fluoride, diamond, derivatives thereof and combinations thereof.
7. The optoelectronic device of claim 1 , wherein the dielectric layer is optically textured.
8. The optoelectronic device of claim 7, wherein the optical texturing is accomplished by disposing particles from the group consisting of alumina, titania, silica, derivatives thereof and combinations thereof; wherein the particles are disposed any of between the p-n structure and the dielectric layer, within the dielectric layer, between the dielectric layer and the metal layer or a combination thereof.
9. The optoelectronic device of claim 1 , wherein the dielectric layer comprises a physically textured surface.
10. The optoelectronic device of claim 9, wherein the physical texturing of the dielectric surface is achieved by any of etching, exposure to a plasma, particle blasting, mechanical imprinting, laser ablation, wet etch, dry etch and a combination thereof.
11. The optoelectronic device of claim 1 , wherein the dielectric layer comprises a surface diffraction grating.
12. The optoelectronic device of claim 11 , wherein the surface diffraction grating is achieved by mechanical imprinting.
13. The optoelectronic device of claim 1 , wherein the metal layer further comprises a metallic reflector layer.
14. The optoelectronic device of claim 13, wherein the metallic reflector layer comprises a metal selected from the group consisting of silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof.
15. The optoelectronic device of claim 1 , wherein a plurality of apertures are disposed within the dielectric layer extending into the p-n structure.
16. The optoelectronic device of claim 15, wherein the plurality of apertures comprise metallic reflector protrusions.
17. The optoelectronic device of claim 16, wherein the metallic reflector protrusions comprise a metal selected from the group consisting of silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof.
18. The optoelectronic device of claim 1 , wherein the p-n structure comprises multiple p-n junctions.
19. The optoelectronic device of claim 1 , further including metallic contacts to the front side of the device, positioned such that the metallic contacts to the front side of the device and the locations at which the metal layer makes contact to the p-n structure are offset to prevent short circuits.
20. The optoelectronic device of claim 1 , wherein the device is a flexible single- crystal device.
21. A method for fabricating an optoelectronic device comprising:
providing a p-n structure;
patterning a dielectric layer on the p-n structure;
and
disposing a metal layer on the dielectric layer;
wherein the metal layer makes one or more contact to the p-n structure; and
then lifting the device off the substrate, such that after the lift off the p-n structure is closer than the patterned dielectric layer to a front side of the device; wherein the device comprises the p-n structure, the patterned dielectric layer, and the metal layer.
22. The method of claim 21 , wherein the p-n structure comprises one or more Group lll-V semiconductor layers.
23. The method of claim 21 , wherein the p-n structure comprises a physically textured surface.
24. The method of claim 21 , wherein the dielectric layer comprises dielectric materials that are resistant to etching by acids such as hydrochloric acid, sulfuric acid or hydrofluoric acid during an epitaxial lift off (ELO) process.
25. The method of claim 21 , wherein the dielectric materials are organic comprising any of polyolefin, polycarbonate, polyester, epoxy, fluoropolymer, derivatives thereof and combinations thereof.
26. The method of claim 21 , wherein the dielectric materials are inorganic comprising any of arsenic trisulfide, arsenic selenide, a-alumina (sapphire), magnesium fluoride, derivatives thereof and combinations thereof.
27. The method of claim 21 , wherein the dielectric layer is provided by using any of spin coating, dip coating, spray coating, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), powder coating, sol gel, ion-beam assisted chemical vapor deposition (IBAD CVD), chemical bath deposition, Inkjet printing, screen printing and lamination.
28. The method of claim 21 , wherein the patterning of the dielectric layer is done by using any of wet etching, dry etching, disposing dielectric layer using inkjet printing, photolithography, shadow masking, imprint lithography, laser ablation and screen printing.
29. The method of claim 21 wherein the dielectric layer is optically textured.
30. The method of claim 29, wherein the optical texturing is accomplished by disposing particles from the group consisting of alumina, titania, silica, derivatives thereof and combinations thereof; wherein the particles are disposed any of between the p-n structure and the dielectric layer, within the dielectric layer, between the dielectric layer and the metal layer or a combination thereof.
31. The method of claim 21 , wherein the dielectric layer comprises a physically textured surface.
32. The method of claim 21 , wherein the metal layer further comprises a metallic reflector layer.
33. The method of claim 32, wherein the metallic reflector layer comprises a metal selected from the group consisting of silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof.
34. The method of claim 21 , wherein a plurality of apertures are disposed within the dielectric layer extending into the p-n structure.
35. The method of claim 34, wherein the plurality of apertures comprise metallic reflector protrusions.
36. The method of claim 35, wherein the metallic reflector protrusions comprise a metal selected from the group consisting of silver, gold, aluminum, nickel, copper, platinum, palladium, molybdenum, tungsten, titanium, chromium, alloys thereof, derivatives thereof, and combinations thereof.
37. The method of claim 21 , wherein the p-n structure comprises multiple p-n junctions.
38. The method of claim 24, further including metallic contacts to the front side of the device, positioned such that the metallic contacts to the front side of the device
and the locations at which the metal layer makes contact to the p-n structure are offset to prevent short circuits.
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US14/846,675 US20150380576A1 (en) | 2010-10-13 | 2015-09-04 | Optoelectronic device with dielectric layer and method of manufacture |
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