CN108604620A

CN108604620A - The more knot opto-electronic devices tied as bottom with IV races semiconductor

Info

Publication number: CN108604620A
Application number: CN201780008978.4A
Authority: CN
Inventors: 布兰登·M·卡耶斯; 何甘
Original assignee: Awbscqemgk Inc
Current assignee: Zishi Energy Co.,Ltd.
Priority date: 2016-01-29
Filing date: 2017-01-27
Publication date: 2018-09-28
Also published as: WO2017132534A1; KR20180107174A; EP3408871A1; JP2019506742A

Abstract

It discloses one kind and tying opto-electronic device (200) and manufacturing method more.This method is included in the first p n structures (208) of offer on substrate (212), wherein the first p n structures include the first base layer of first semiconductor with first band gap, so that the lattice constant match of the lattice constant and substrate of the first semiconductor, and wherein the first semiconductor includes III V races semiconductor.This method includes providing the 2nd p n structures (206), wherein the 2nd p n structures include the second base layer of the second semiconductor with the second band gap, the wherein lattice constant match of the lattice constant of the second semiconductor and the first semiconductor, and wherein the second semiconductor includes IV races semiconductor.This method further includes the more knot opto-electronic devices for having the first p n structures and the 2nd p n structures from substrate desquamation, wherein more knot phototube components are flexible devices.

Description

The more knot opto-electronic devices tied as bottom with IV races semiconductor

Cross reference to related applications

This application claims entitled " the MULTI-JUNCTION OPTOELECTRONIC submitted on January 26th, 2017 The U. S. application No.15/417 of DEVICE WITH GROUP IV SEMICONDUCTOR AS A BOTTOM JUNCTION ", Entitled " the MULTI-JUNCTION OPTOELECTRONIC DEVICE WITH submitted on January 29th, 105 and 2016 The U.S. Provisional Application No.62/289,070's of GROUP IV SEMICONDUCTOR AS A BOTTOM JUNCTION " is preferential Power.The application is also entitled " the MULTI-JUNCTION OPTOELECTRONIC DEVICE " submitted on December 4th, 2012 U. S. application No.13/705,064 part continuation application, and require its priority submits on November 3rd, 2010 The U. S. application No.12/ of entitled " OPTOELECTRONIC DEVICES INCLUDING HETEROJUNCTION LAYER " The U. S. application No.12/605 of entitled " the PHOTOVOLTAIC DEVICE " that submits on October 23rd, 939,077 and 2009, 108 continuous application part simultaneously requires its priority.The disclosure of each in these earlier applications is whole by quoting It is incorporated herein.

Technical field

The present disclosure relates generally to opto-electronic semiconductor module, relate more specifically to there is IV races semiconductor to tie as bottom More knot opto-electronic devices and the method for manufacturing more knot opto-electronic devices.

Background technology

It needs to provide opto-electronic semiconductor module, also referred to as opto-electronic device, the efficiency phase with the sub- device of Traditional photovoltaic Than having higher efficiency.However, these improved devices are needed with cost-effectiveness, it is easy to accomplish and/or adapt to existing Environment.The present disclosure describes the various aspects for the technical solution for solving these demands.

Invention content

It discloses a kind of more knot opto-electronic devices tied as bottom with IV races semiconductor and manufactures more knot photoelectricity The method of sub- device.Method for manufacturing more knot opto-electronic devices includes providing the first p-n structure on substrate, wherein first P-n structure includes the first base layer of first semiconductor with first band gap so that the lattice constant and lining of the first semiconductor The lattice constant match at bottom, and wherein the first semiconductor includes Group III-V semiconductor.This method further includes in the first p-n junction Second p-n structure is provided on structure, wherein the second p-n structure includes the second base layer of the second semiconductor with the second band gap, The wherein lattice constant match of the lattice constant of the second semiconductor and the first semiconductor, and wherein the second semiconductor includes IV races Semiconductor.This method further includes removing more knot opto-electronic devices from substrate, wherein more knot opto-electronic devices include the first p-n Structure and the second p-n structure, and wherein more knot opto-electronic devices are flexible devices.

In another aspect of the present disclosure, opto-electronic devices of tying include the first p-n structure more, wherein the first p-n structure includes First base layer of the first semiconductor with first band gap so that the lattice constant of the first semiconductor and the lattice constant of substrate Matching, and wherein the first semiconductor includes Group III-V semiconductor.More knot opto-electronic devices further include by the first p-n junction The second p-n structure being epitaxially-formed on structure, wherein the second p-n structure includes the of the second semiconductor with the second band gap Two base layers, wherein the lattice constant match of the lattice constant of the second semiconductor and the first semiconductor, and wherein the second half lead Body includes IV races semiconductor.More knot opto-electronic devices are removed from substrate and include the first p-n structure and the second p-n junction Structure.More knot opto-electronic devices formed in this way are flexible devices.

At the another aspect of the disclosure, opto-electronic devices of tying include the first p- with the first p-n junction and the second p-n junction more N structures, wherein the first p-n junction includes the first monocrystalline Group III-V semiconductor for having first band gap so that the first monocrystalline III-V The lattice constant of race's semiconductor and the lattice constant match of substrate.More knot opto-electronic devices further include by the first p-n junction The second p-n structure being epitaxially-formed on structure, wherein the second p-n structure includes the second monocrystalline IV races with the second band gap half The third p-n junction of conductor, and the lattice constant Yu the first monocrystalline Group III-V semiconductor of wherein the second monocrystalline IV races semiconductor Lattice constant match.More knot opto-electronic devices are removed from substrate and include the first p-n structure and the second p-n structure.With More knot opto-electronic devices that this mode is formed are flexible devices.In one embodiment or embodiment, substrate includes GaAs Chip, and the third p-n junction of the second p-n structure includes the IV races semiconductor being made of Si, Ge, Sn or combinations thereof so that After more knot opto-electronic devices are detached with substrate, IV races semiconductor forms the bottom of the separate external light source of more knot opto-electronic devices Knot.

Description of the drawings

It, can be by reference to showing in the accompanying drawings in order to be more fully understood the features described above and various aspects of the disclosure Go out some of various embodiments or embodiment is more particularly described the disclosure summarized briefly above.However, It should be noted that attached drawing illustrates only the embodiment of various aspects of the disclosure or the example of embodiment, therefore it is not construed as limiting Its range is made, because the disclosure can allow other equally effective embodiment or embodiment.

Fig. 1 is the work for showing more knot opto-electronic devices of the formation with p-n structure according to various aspects described herein The flow chart of skill, the p-n structure include that the IV races semiconductor for using GaAs substrate is tied as bottom.

Fig. 2 shows the example according to more knot opto-electronic devices with p-n structure of various aspects of the disclosure, the p-n Structure, which is included in, uses GaAs to be tied as bottom as the IV races semiconductor of substrate before device is detached with substrate.

Fig. 3 shows another example of more knot opto-electronic devices with p-n structure according to various aspects of the disclosure, should P-n structure, which is included in, uses GaAs to be tied as bottom as the IV races semiconductor of substrate after device is detached with substrate.

Fig. 4 shows to use GaAs substrate before device is detached with substrate according to various aspects of the disclosure The example of three knot opto-electronic devices of the epitaxial growth that SiGe or SiGeSn is tied as bottom.

Fig. 5 shows that according to various aspects of the disclosure, SiGe or SiGeSn are as bottom after device is detached with substrate Another example of three knot opto-electronic devices of the epitaxial growth of knot and preceding Metal contacts.

Fig. 6 shows another example of more knot opto-electronic devices according to various aspects of the disclosure.

Fig. 7 A show more knot photoelectricity with single p-n junction in the first p-n structure according to various aspects of the disclosure The example of sub- device.

Fig. 7 B show the more knot photoelectricity having in the first p-n structure there are two p-n junction according to various aspects of the disclosure The example of sub- device.

Fig. 7 C show the more knot photoelectricity of the various aspects according to the disclosure having in the first p-n structure there are three p-n junction The example of sub- device.

Specific implementation mode

The present disclosure relates generally to opto-electronic semiconductor modules, also referred to as opto-electronic device, relate more specifically to IV More knot opto-electronic devices that race's semiconductor is tied as bottom.It provides and is described below so that those of ordinary skill in the art can make Make and using the feature of the disclosure and for the use of, and the description is provided under the background of patent application and its requirement.To being provided Embodiment and the example and generic principles described herein of embodiment and the various modifications of feature for art technology It will be apparent for personnel.Therefore, the disclosure be not limited to shown in embodiment or embodiment example, but It is consistent with the widest range for meeting principles and features described herein.

As described above, this disclosure relates to more knot opto-electronic devices for being tied as bottom with IV races semiconductor and for shape At the manufacturing process of this opto-electronic device.Therefore, the present disclosure describes the various aspects of the manufacture of thin-film device, such as photovoltaic Device, light emitting diode (LED) or other opto-electronic devices may be used as more knot opto-electronic devices as described herein.

For example, it is desirable to improve the performance of the opto-electronic device of such as photovoltaic cell or light emitting diode to improve its efficiency, Without significantly affecting cost or increasing the overall dimensions of device.Therefore, these devices should have cost-effectiveness, easy to implement And/or adapt to existing environment.The present disclosure describes the various aspects for the technical solution for solving these demands.

In general, being improved by improving light absorption/transfer efficiency of battery or the light generation efficiency of light emitting diode (LED) The performance of such as opto-electronic device of photovoltaic cell (for example, solar cell) or LED.There can be different band gap by growth Material so that highest band gap material is located at the side (for example, front) towards light and minimum band gap material is located at opposite side (for example, back side) manufactures high-efficiency photovoltaic battery.This causes different layers to absorb the photon of different-energy, improves photovoltaic cell Efficiency, because this arrangement causes more photons to be absorbed and therefore generates the electric current of bigger.This can use different sides Method is realized；But each method the shortcomings that having its own.

In order to improve efficiency, the material (that is, material with different energy gaps) for growing multilayer difference band gap is needed, but this Lead to the lattice mismatch between growth substrates and different layers and between different layers, to reduce obtained photovoltaic cell Whole efficiency (generates similar poor efficiency) in the operation of light emitting diode.Therefore, another method is used to go bad (metamorphic) gradient layer is to allow the difference of lattice constant, for example, growing lattice mistake using InGaAs bottom knot The more knot opto-electronic devices (for example, multijunction solar cell of lattice mismatch) matched.Modification Manners lead to the metal largely wasted The MOCVD tool throughputs of organic chemical vapor deposition (MOCVD) precursor material and reduction.

The method different from the above method is to grow more knot opto-electronic devices of Lattice Matching using Ge as bottom knot. Ge is widely used as the bottom battery (for example, to provide bottom knot) of more knot opto-electronic devices based on GaAs.However, due to Ge With less than best band gap, therefore the significant decrease of transfer efficiency can be led to using Ge.In addition, there are small between Ge and GaAs Lattice mismatch.In order to overcome the problems, such as these, semiconductor In is added to form InGaAs in GaAs sometimes, so as to improve with Ge The Lattice Matching of substrate.However, if substrate is GaAs, this technology using InGaAs may not work, because The lattice constant of InGaAs and the lattice constant of GaAs are dramatically different, lead to the lattice mismatch between both materials.

Using IV races element, also referred to as IV races semiconductor, including Si, Ge and/or Sn combination as based on the more of GaAs Better Lattice Matching may be implemented in the bottom battery of knot opto-electronic device.For example, compared with Ge substrates, it can be in the crystalline substance of SiGe Preferably matching is realized between lattice constant and the lattice constant of GaAs substrates.In addition, for more knot photoelectron devices based on GaAs The efficiency of part, the band gap of SiGe is closer to best band gap.Therefore, SiGe includes the SiGe of lattice mismatch, can be used for increasing band gap To improve the efficiency of more knot opto-electronic devices.

This document describes being used to form including IV races semiconductor as bottom battery (example according to various aspects of the disclosure Such as, with provide bottom knot) more knot opto-electronic devices method various aspects.In the disclosure, in an embodiment or implementation In mode, SiGe can be used as the bottom battery of more knot opto-electronic devices based on GaAs, better with GaAs substrates to realize Lattice Matching and higher band gap are to improve efficiency.

Many thin-film devices (for example, more knot opto-electronic devices of such as photovoltaic cell or LED) as described herein are usually wrapped Layer containing epitaxial growth, the layer of the epitaxial growth are formed on the sacrificial layer for being set to and supporting above substrate or chip. The thin-film device being consequently formed can be flexible unitary device.Once thin-film device is formed by epitaxy technique, then by film Device is removed from support substrate or chip or separation, such as removes (ELO) technique, laser lift-off (LLO) technique or stripping in extension During falling technique etc..

As used in the disclosure, layer can be described as deposition " above other one or more layers ".It should Term indicates that this layer can be deposited directly on the top of other layers, or can indicate in some embodiments or embodiment One or more extra plays can be deposited between the layer and other layers.In addition, other layers can arrange in any order.In order to The feature of the disclosure is more fully described, with reference to the discussion below in conjunction with attached drawing.

Fig. 1 is the exemplary flow chart for showing the method 100 for manufacturing or being formed more knot opto-electronic devices.In Fig. 1 institutes In the example shown, according to various aspects described herein, opto-electronic devices of tying include p-n structure more, which includes using GaAs is tied as the IV races semiconductor of substrate as bottom.In one embodiment or embodiment, method 100 includes, 102 Sacrificial layer is provided on gaas substrates, the first p-n structure is provided on sacrificial layer 104, tunnel knot is optionally provided 106, The second p-n structure is provided on the first p-n structure 108,110 on mostly knot opto-electronic device (or more pn junction p n structures) Support layer is provided, and 112 more than the substrate desquamation knot opto-electronic device and support layer.In one embodiment or embodiment In, regardless of whether providing support layer, opto-electronic devices of tying can be removed more from substrate.It, can in the one side of method 100 The first p-n structure is provided with (or on sacrificial layer on gaas substrates) on gaas substrates, as shown in 104 in Fig. 1.p-n Structure can refer to the structure with one or more semiconductor layers, and wherein form one by one or more of semiconductor layers A or multiple p-n junctions.

In some embodiments or embodiment, such as before depositing p-n structure, sacrificial layer can be set on substrate (for example, in Fig. 1 102) are removed or are detached can be removed (ELO) technique or other similar techniques by using extension P-n structure.Sacrificial layer may include AIA, AIGaAs, AIGaInP or AllnP or other layers or combinations thereof with high Al content, And it is used to form the lattice structure of the layer in battery, then it is etched and removes during ELO techniques.In other implementations In example, the stripping technology substituted, such as laser lift-off (LLO), ion implanting can be used simultaneously to remove, by etching buried oxide Layer is buried the stripping of porous layer or is peeled off.

In one embodiment or embodiment, the first p-n structure can be grown on substrate (for example, on substrate On sacrificial layer), it is, for example, possible to use GaAs chips, epitaxially grown layer is used as by III-V material (for example, iii-v is partly led Body) made of film.First p-n structure being epitaxially-formed by using various technologies, for example, Organometallic Chemistry Be vapor-deposited (MOCVD), molecular beam epitaxy (MBE), metal organic vapor (MOVPE or OMVPE), liquid phase epitaxy (LPE), Hydride gas-phase epitaxy (HYPE) closes space gas phase transmission (close-spaced vapor transport, CSVT) extension etc.. In some embodiments, the first p-n structure is substantially monocrystalline.First p-n structure may include single-crystal semiconductor material.

In some embodiments or embodiment, it can be used Seedling height rate depositing operation (for example, Seedling height rate gas phase Depositing operation) form the epitaxially grown layer of III-V material.Seedling height rate depositing operation makes the material of growth have foot For the quality of all kinds of opto-electronic devices as described herein.Seedling height rate depositing operation allow growth rate be more than 5 μm/it is small When, for example, about 10 μm/hour or more, or up to about 100 μm/hour or more.For example, growth rate can be about 10 μm/hour, about 20 μm/hour, about 30 μm/hour, about 40 μm/hour, about 50 μm/hour, about 60 μm/hour, about 70 μm/hour, about 80 μm/ Certain special speeds between any two in hour, about 90 μm/hour or about 100 μm/hour, these values are (for example, about 25 μm/hour-are in 20 μm/hour between 30 μm/hour) or these values in any two between a certain range (example Such as, from about 20 μm/hour to about 30 μm/hour).In some embodiments or embodiment, Seedling height rate depositing operation is permitted Perhaps growth rate is more than 100 μm/hour, includes the growth rate of about 120 μm/hour.Such as the term used in the disclosure " about " 1%, 2%, 3%, 4%, 5% or 10% variation for example from nominal value can be indicated.Seedling height rate depositing operation Including：Heated the wafer in processing system about 550 DEG C or more depositing temperature (for example, depositing temperature may be up to 750 DEG C or 850℃)；Expose a wafer to the deposition gases containing precursor, such as the precursor of the precursor gases containing III group and the race containing V Gas；And the layer containing III-V material is deposited on chip.Precursor gases containing III group can contain group-III element, as indium, Gallium or aluminium.For example, the precursor gases containing III group can be trimethyl aluminium, triethyl aluminum, trimethyl gallium, triethyl-gallium, trimethyl One kind in indium, triethylindium, diisopropyl methyl indium or ethyl dimethyl indium.The precursor gases of the race containing V can contain V races member Element, such as nitrogen, phosphorus, arsenic or antimony.For example, the precursor gases of the race containing V can be phenylhydrazine, dimethylhydrazine, tert-butylamine, ammonia, phosphine, tertiary butyl In phosphine, two phosphino- ethane, arsine, tertiary butyl arsine, single arsino-ethane, trimethyl arsine, trimethylantimony, antimony triethyl or triisopropyl antimony It is a kind of.

It as described herein, can be in various types of settling chambers for depositing or being formed the depositing operation of III-V material It carries out.For example, in the commonly assigned U.S. Patent application No.12/475,131 and 12/ submitted on May 29th, 2009 One kind is described in 475,169 (issuing as United States Patent (USP) No.8,602,707) to can be used for growing, deposit or otherwise The continuous feed settling chamber of III-V material is formed, entire contents are incorporated herein by reference.

In the commonly assigned United States Patent (USP) No.9,136,418 and hair on November 3rd, 2015 of the publication on the 15th of September in 2015 The layer that can be used in device is disclosed in the United States Patent (USP) No.9,178,099 of cloth and forms some of the method for this layer shows Example, and their full content is incorporated herein by reference.

In one embodiment or embodiment, the first p-n structure includes multiple p-n junctions, for example, the first p-n junction, second P-n junction is until the n-th p-n junction.That is, the first p-n structure may include one, two or more p-n junction.At one In example, the first p-n structure only includes a p-n junction.Each in the first to the (n-1)th p-n junction may include various arsenides, Phosphide and nitride layer, as AlGaAs, InGaAs, AlInGaAsP, AlInP, InGaP, AlInGaP, GaP, GaN, InGaN, AlGaN, AlInGaN, its alloy, its derivative or combinations thereof.For example, nitride and phosphide layers may include InGaP, AlInGaP, GaN, InGaN, AlGaN, AlInGaN, GaP, these any one of alloy or these any one of Derivative in it is one or more.N-th p-n junction may include various arsenides, phosphide and nitride layer, as GaAs, AlGaAs, InGaAs, AlInGaAs, InGaAsP, AlInGaAsP, GaN, InGaN, its alloy, its derivative and combinations thereof.It is logical Often, each in these p-n junctions includes Group III-V semiconductor, and include in gallium, aluminium, indium, phosphorus, nitrogen or arsenic at least one Kind.

In one embodiment or embodiment, the first p-n junction of the first p-n structure includes InGaP material or it spreads out Biology.InGaP material may include various InGaP layers, such as InGaP, AlGaInP.For example, implementing at one In example or embodiment, the first p-n structure includes p-type AlGaInP layer or is arranged on N-shaped InGaP layer or lamination The lamination of side, the wherein combination of the two laminations can form the first p-n junction.As described in this disclosure, lamination can be referred to One group of more than one layer so that N-shaped lamination includes one group of more than one layer, and wherein at least one of group layer is N-shaped Layer or include n-type material, and p-type lamination include one group of more than one layer, wherein at least one of group layer be p-type layer Or including p-type material.

In one example, the thickness of p-type AlGaInP lamination is in the range of about 100nm to about 3,000nm, and The thickness of N-shaped InGaP lamination is in the range of about 100nm to about 3,000nm.In one example, N-shaped InGaP is folded The thickness of layer is in the range of about 400nm to about 1,500nm.

In another embodiment or embodiment, the first p-n junction of the first p-n structure include AlGaInP material or its Derivative.AlGaInP material may include various AlGaInP layers, such as aluminum phosphate indium, AlGaInP.For example, one In a embodiment or embodiment, p-n structure includes the p-type aluminum phosphate indium being arranged above N-shaped AlGaInP layer or lamination Layer or lamination, the wherein combination of the two laminations can form the first p-n junction.

In one embodiment, the first p-n junction of the first p-n structure, the second p-n junction or the n-th p-n junction include GaAs Material and its derivative, for example, GaAs, AlGaAs, InGaAs, AllnGaAs, InGaAsP, AlInGaAsP, its alloy, it spreads out Biology and combinations thereof.GaAs material may include various gallium arsenide layers, such as GaAs, aluminum gallium arsenide, InGaAsP, aluminum indium arsenide Gallium etc..For example, in one embodiment, the n-th p-n junction includes the p-type aluminium arsenide being arranged on N-shaped gallium arsenide layer or lamination Gallium layer or lamination.

In one embodiment or embodiment, the first p-n junction, the second p-n junction or the n-th p-n junction of the first p-n structure Including gallium phosphide material and its derivative, for example, GaP, InGaP, AlInP, AlGaP, AlInGaP, InGaAsP, AlInGaAsP, Its alloy, its derivative and combination thereof.

It, can be between emitter layer and base layer (for example, in p-n junction or p-n junction for some embodiments or embodiment Between emitter and base layer in structure) form boundary layer or middle layer.Middle layer may include any suitable iii-v chemical combination Object semiconductor, such as GaAs, AlGaAs, InGaP, AlInGaP, InGaAsP, AlInGaAsP, AlInP or combinations thereof.Middle layer can Be n adulterate, p doping or unintentionally adulterate.The thickness of boundary layer can be in for example, about 5nm to the range of about 200nm It is interior.Middle layer can be made of between p doped layers and n doped layers material identical with n doped layers or p doped layers, Or can be made of the material different from n doped layers or p doped layers, and/or can be graded composition layer.It is consequently formed Middle layer can provide the position offset from corresponding p-n junction for one or more hetero-junctions.This offset can allow to drop Dark current in low device, so as to improve its performance.

In one embodiment or embodiment, can on the first p-n structure two p-n structure of growth regulation (in such as Fig. 1 Shown in 106).Second p-n structure may include the layer of epitaxial growth, is made as by IV races material (for example, IV races semiconductor) Film.Can the second p-n structure be formed by using the epitaxial growth of different technologies, for example, plasma enhanced chemical Vapor deposition (PECVD), physical vapour deposition (PVD) (PVD) or sub-atmospheric CVD (APCVD).Other technologies can be used It is formed outside the second p-n structure, including sputtering, atomic layer deposition (ALD), hydride gas-phase epitaxy (HVPE), metal organic vapors Prolong (MOVPE or OMVPE), metal organic chemical vapor deposition (MOCVD), inductively coupled plasma enhancing chemical vapor deposition (ICP-CVD), hot line chemical vapor deposition (HWCVD), the chemical gaseous phase of low-pressure chemical vapor deposition (LPCVD) and other forms It deposits (CVD).In some embodiments or embodiment, the second p-n structure is substantially monocrystalline (for example, the second p-n structure can Including single-crystal semiconductor material).For this purpose, the first p-n structure after growth is transferred to another chamber together with growth substrates, To use another growth technique such as PECVD, PVD or APCVD in the second p-n structure of grown on top of the first p-n structure.Gao Sheng Long rate depositing operation allow growth rate be more than 5 μm/hour, such as from about 10 μm/hour or more, or up to about 100 μm/hour with On.For example, growth rate can be about 10 μm/hour, about 20 μm/hour, about 30 μm/hour, about 40 μm/hour, about 50 μm/small When, about 60 μm/hour, about 70 μm/hour, about 80 μm/hour, about 90 μm/hour or about 100 μm/hour, in these values Certain special speeds (for example, about 25 μm/hour-in 20 μm/hour between 30 μm/hour) between any two or these A certain range (for example, from about 20 μm/hour to about 30 μm/hour) between any two in value.).In some embodiments Or in embodiment, Seedling height rate depositing operation allows growth rate to be more than 100 μm/hour, including about 120 μm/hour Growth rate.

In one embodiment or embodiment, method 100 may include via step 102 on substrate (for example, GaAs) The first knot (for example, p-n junction) of first p-n structure (for example, InGaP) is provided.It can be grown on first p-n junction additionally P-n junction, such as GaAs.In one embodiment or embodiment, the first p-n junction may include various arsenides, nitride and phosphorus Compound layer, such as GaAs, AlGaAs, InGaP, AlInGaP, GaN, InGaN, AlGaN, AlInGaN, GaP, its alloy, its derivative Object and combinations thereof, additional p-n junction may include GaAs, AlGaAs, InGaP, AlInGaP, InGaAs, AllnGaAs, Any one of InGaAsP, AlInGaAsP, its alloy, its derivative and combinations thereof.

The first p-n structure being consequently formed is transferred to another growth room, then 108 on the first p-n structure shape At the second p-n structure, for example, SiGe.In the embodiment or embodiment, the lattice constant of substrate and the first p-n structure Lattice constant match, and the lattice constant match of the lattice constant of the second p-n structure and the first p-n structure.Ordinary skill people Member will recognize that this matching of lattice constant further includes having each other the almost material of matched lattice constant.For example, lining The semi-conducting material at bottom can have and the lattice constant match (or matching substantially) of the first semi-conducting material of the first p-n structure Lattice constant, and the lattice constant match of the lattice constant of the first semi-conducting material and second p-n structure (or basic With).The matching of lattice constant or basic matching refer to allowing two differences and adjacent semi-conducting material to form band gap variation Region without the variation for introducing crystal structure.As described above, method 100 further includes optionally 106 in the first p-n structure And/or provide tunnel between second multiple p-n junctions in p-n structure or between the first p-n structure and the second p-n structure Knot forms more pn junction p n structures for more tying opto-electronic device.Tunnel knot provides the first p-n structure and/or the second p-n junction Between multiple p-n junctions in structure or the thermocouple between the first p-n structure and the second p-n structure and/or the rest part of device It closes.Other p-n junctions in first p-n structure and the second p-n structure are that the voltage of more pn junction p n structures generates p-n junction.It can be with Based on III-V material by using with same or similar equipment described herein and technology next life long tunnel knot with growth regulation one P-n structure, or based on IV races material tunnel can be grown by using with same or similar equipment described herein and technology Road knot is with two p-n structure of growth regulation.In another embodiment or embodiment, tunnel knot can be based on III-V material and IV races material may use more than one technology growth.In this case, for example, can terminate to mix with heavily doped layer or n Then the growth of miscellaneous or p doping surfaces III-V materials starts the IV races of heavily doped layer of the growth with opposite dopant type Material.

In one embodiment or embodiment, the second p-n structure includes IV races semiconductor, such as, but not limited to Si, Ge, The setting of the mixture of two or more in Sn, C or these materials, wherein p-type silicon germanium layer or lamination is in n-type silicon germanium layer or folded Layer top.In one example, the thickness of p-type silicon germanium lamination is in the range of about 100nm to about 3,000nm, and n-type silicon germanium The thickness of lamination is in the range of about 100nm to about 3,000nm.In one example, the thickness of n-type silicon germanium lamination is about In the range of 700nm to about 2,500nm.

In another embodiment or embodiment, the second p-n structure includes multiple p-n junctions.Each p-n junction can include each Kind IV races semiconductor layer, can use different source materials to grow, including but not limited to isobutyl group germane, tri-chlorination alkyl Germanium, dimethylamino germanium terchoride, germane, silane, disilane, silicon tetrachloride, carbon tetrabromide, tribromide carbon chloride etc.. In general, each p-n junction includes IV races semi-conducting material and includes at least one of silicon, germanium, tin and carbon and these materials In the mixture of two or more.

In addition, for both the first p-n structure and the second p-n structure, the knot formed between two layers can be hetero-junctions, i.e., The N layers for forming knot and P layers can be made from a different material or homojunction, that is, the N layers for forming knot and P layers can be by identical Material be made, for example, being all for two layers GaAs or being all for two layers InGaP.In addition, p-n structure can have any doping polarity, Wherein n-type material is located at the top of structure or knot, p-type material is located at the bottom of structure or knot or p-type material be located at structure or The top of knot, n-type material are located at the bottom of structure or knot.

In some embodiments or embodiment, one of the first p-n structure or the second p-n structure are above to may include line Physics and chemistry surface.The texturizing surfaces can improve the light scattering at the surface, and improve the adherency to metal layer and dielectric layer. In some embodiments or embodiment, the veining on surface can be realized in the growth period of the material including p-n structure.This can To be realized at least partially through the lattice mismatch between at least two materials used in p-n structure, such as In Stranski-Krastanov techniques or Volmer-Weber techniques, veining is generated with interface between the materials. In another embodiment or embodiment, in p-n structure or on layer may act as etching mask, and line can be provided by etch process Physics and chemistry.It, can be by physical grinding, such as sand paper or sandblasting or particle sandblasting or similar side in another embodiment or embodiment Method provides veining.It, can be by generating microcosmic non-uniform feature on the surface in another embodiment or embodiment Non-uniform etch technique veining is provided.In addition it is possible to use the technology similar with the technology used in silicon veining is come It realizes veining, including is for example etched using " the random pyramid " of such as KOH or " inverted pyramid ".

In addition, in one embodiment or embodiment, the back side of p-n structure and/or front are (for example, closest to light quilt Photovoltaic cell receives or side emitted by the LED) it can be textured to improve the light scattering for entering and/or leaving device. In some embodiments or embodiment, veining is more likely to be applied to the back side (for example, back side veining), in this case, IV races semi-conducting material is textured using one or more in above-mentioned veining technology.

Then can be in Fig. 1 110 deposit support layer in the more pn junction p n structures being consequently formed.Support layer can be with Including dielectric layer, semiconductor contact layer (or simple contact layer), passivation layer, including transparent conducting oxide layer, anti-reflection coating, gold Belong to one or more of coating, adhesive phase, epoxy resin layer or plastic coating.In one embodiment or embodiment, Support layer is by acid, such as to the acid as ELO or a part for similar technique, one or more materials with chemical stability Material composition.

In the case of including a part of the dielectric layer as support layer wherein, dielectric layer includes organic or inorganic Dielectric material.Organic dielectric materials include polyolefin, makrolon, polyester, epoxy resin, fluoropolymer, its derivative and Any one of a combination thereof, and Inorganic Dielectric Material includes ArsenicTrisulfide, arsenic selenium, Alpha-alumina (sapphire), fluorination Any one of magnesium, its derivative and combinations thereof.

In the case of including a part of the contact layer (or multiple contact layers) as support layer wherein, contact layer can Including III-V material, such as GaAs (GaAs), this depends on the required composition of final photovoltaic cells.According to being described herein Embodiment or embodiment, contact layer can be that N-shaped is highly doped.In some embodiments or embodiment, doping concentration It can be greater than about 5 × 10¹⁸cm^-3In the range of, for example, greater than about 5 × 10¹⁸cm^-3To about 1 × 10¹⁹cm^-3.Contact layer it is highly doped Miscellaneous permission forms Ohmic contact with the metal layer deposited later, and this Ohmic contact is formed without any annealing steps, As described below.

In some embodiments or embodiment, contact layer can be the GaAs (GaAs) doped with silicon (Si).For example, It is formed in some embodiments or embodiment of structure sheaf using Seedling height rate as described above, silicon dopant can be used (as n dopants) makes doping concentration reach 5 × 10¹⁸cm^-3More than.For example, precursor can be introduced with fast growth rate technique Disilane deposits silicon dopant.In other embodiment or embodiment, selenium (Se) or tellurium (Te) can be used as forming structure sheaf Dopant.

Contact layer can be formed with the thickness of about 10nm or more, for example, about 50nm.In some embodiments or embodiment, Structure can formed contact layer before the ELO techniques that growth chip detaches.In some alternate embodiments or embodiment In, contact layer can be formed in the later phases after this ELO techniques.In each of embodiment as described herein or embodiment In kind example, used contact layer may include that n metal alloys contact site, p Metal contacts, n Metal contacts, p metals close One or more of golden contact site or other suitable contact sites, the entitled " Metallic such as submitted on November 3rd, 2010 Contacts for Photovoltaic Devices and Low-temperature Fabrication Processes The U.S. Patent application No.12/939 of Thereof ", described in 050, which is incorporated herein by reference.Metal contacts The other types of layer, structure and material can also be used together with various types of opto-electronic devices described in the disclosure.

Then, as shown in 112 in Fig. 1, more pn junction p n structures or more knot opto-electronic device and support layer can by from Substrate desquamation (for example, separation, removal).

The embodiment of this more knot opto-electronic device or the embodiment also provides back reflection layer, after also referred to as reflective Contact site is metallic reflector or metal-dielectric reflecting layer.Contact site can be stripped it in device after these are reflective It is preceding or deposit later, and may include one or more in silver, aluminium, gold, platinum, copper, nickel or its alloy.After reflective The thickness of the layer of contact site can be in the range of for example, about 0.01 μm to about 1 μm, preferably from about 0.05 μm to about 0.5 μm, more preferably from about 0.1 μm to about 0.3 μm, for example, about 0.2 μm or about 0.1 μm ().Layer with reflective rear contact site can pass through Gas-phase deposition deposit, as physical vapour deposition (PVD) (PVD), sputtering, electron beam deposition (e- beams), ALD, CVD, PE-ALD or PE-CVD, or pass through other depositing operations, including ink jet printing, silk-screen printing, evaporation, plating, electroless deposition (e-less) Or combinations thereof.The various aspects of reflective rear contact site are described in U.S. Patent application No.12/939,050.Metal contact layer Other types, structure and material can be used for various types of opto-electronic devices described in the disclosure.

Fig. 2 shows according to the embodiments of more knot opto-electronic devices 200 with p-n structure of the disclosure or embodiment Example, the p-n structure include the IV races semiconductor tied as bottom and use GaAs conducts before device is detached with substrate Substrate.In one embodiment or embodiment, more knot 200 epitaxial growths of opto-electronic device are under sunlight is lateral, from the first p-n The last ligament gap of first p-n junction of structure to the second p-n structure reduces.For example, as shown in Fig. 2, tying opto-electronic device 200 more Epitaxial growth is to reduce from first the 208 to the second p-n structure of p-n structure, 206 band gap, wherein the first p-n structure under sunlight is lateral 208 include one or more p-n junctions, further comprises III-V group semi-conductor material, such as InGaP and GaAs, the second p-n junction Structure 206 includes p-n junction, further comprises IV races semi-conducting material, such as SiGe or SiGeSn.In one embodiment or embodiment party In formula, the second p-n structure 206 may include more than one p-n junction.It can between the first p-n structure 208 and the second p-n structure 206 Selection of land provides tunnel knot 204.Before depositing the first p-n structure 208, sacrificial layer 210 can be set on GaAs substrates 212, Such as the layer made of AlGaAs or AlAs.Sacrificial layer 210 can be provided so that extension stripping (ELO) technique stripping can be used by the The multijunction structure that one p-n structure, the second p-n structure and optional tunnel knot are formed.

Fig. 3 shows embodiment or the embodiment party of more knot opto-electronic devices 300 with the second p-n structure according to the disclosure The example of formula, second p-n structure include the IV races semiconductor tied as bottom and the use after device is detached with substrate GaAs is as substrate.In one embodiment or embodiment, tie opto-electronic devices 300 be shown as sunlight it is lateral on, from Second the 302 to the first p-n structure of p-n structure, 306 band gap increases, wherein the first p-n structure 306 includes one or more p-n junctions.

More generally, for more knot opto-electronic devices 300 in Fig. 3, for example, the first p-n structure 306 includes iii-v Semiconductor, the second p-n structure 302 include IV races semiconductor, such as SiGe.First p-n structure 306 can also include the first p-n junction With the second p-n junction.In a non-limiting example, the first p-n junction includes InGaP semi-conducting materials, and the second p-n junction includes GaAs half Conductor material.Other examples can have the first p-n made of the Group III-V semiconductor different from those of in above-mentioned example Knot and the second p-n junction.Tunnel knot 304 is optionally provided between the first p-n structure 306 and the second p-n structure 302.This causes Following opto-electronic device, wherein the second p-n structure 302 includes IV races semi-conducting material, such as SiGe, for example, it forms more knot light The bottom battery or knot of the multijunction structure of electronic device 300, and bottom battery or knot wherein after device is detached with substrate Far from incident light.

In one embodiment or embodiment, the first p-n structure 306 and/or the second p-n structure 302 may include with band The one or more p-n junctions for sequence (for example, from maximum energy gap to the smallest energy gap) growth that gap declines so that in device and substrate After separation, the p-n junction far from the device-side for receiving incident light has minimum band gap, and the closest device for receiving incident light The p-n junction of part side has maximum band gap.

Fig. 4 shows three embodiments of knot opto-electronic device 400 or the showing for embodiment of the epitaxial growth according to the disclosure Example, wherein SiGe or SiGeSn are tied as bottom and are used GaAs substrate before device is detached with substrate.At one In embodiment or embodiment, the three knot opto-electronic device 400 of epitaxial growth on GaAs chips 412.It sinks on GaAs chips 412 Product GaAs buffer layers 414, followed by AlAs releasing layers 410.Then, GaAs contact layers 416 are deposited on AlAs releasing layers 410, Followed by front window layer 418, for example, AlGalnP or AlInP.First p-n of the first p-n structure after front window layer 418 Growth includes the tunnel knot 404' of such as AlGaAs, GaAs or InGaP on knot 402, wherein the first p-n junction 402 includes AlInGaP, InGaP or AlGaAs absorbed layer.The one or more materials different from AlGaAs, GaAs or InGaP can also be used Expect next life long tunnel knot 404'.First p-n structure further includes above the first p-n structure and tunnel knot 404', if there is Words, the second p-n junction 406 of top, such as GaAs absorbed layers.Second p-n structure includes the first p-n junction 408, can be referred to as three The third p-n junction of opto-electronic device 400 is tied, wherein the first p-n junction 408 includes SiGe or SiGeSn absorbed layers.Second p-n structure The first p-n junction 408 can be coupled to the second p-n junction of the first p-n structure (if present) via tunnel knot 404 " 406.The first and second p-n junctions (for example, p-n junction 402 and 406) of first p-n structure and the part as the second p-n structure The laterally lower growth of third p-n junction (for example, p-n junction 408) sunlight, from the first p-n junction to the second p-n junction and from the 2nd p-n The reduction of third p-n junction band gap is tied, and is coupled by tunnel knot 404' and 404 ".Support layer (not shown) can device with It is deposited on the second p-n structure before or after substrate separation.

Fig. 5 shows the embodiment or embodiment of the three knot opto-electronic devices 500 of one embodiment according to the disclosure Example, wherein SiGe or SiGeSn are tied as bottom and use GaAs substrate and preceding gold after device is detached with substrate Belong to contact site.Three knot opto-electronic devices 500 as shown in Figure 5 include anti-reflection coating (ARC) 526, preceding Metal contacts 524, Contact layer 516, front window layer 518, for example, AlGaInP or AlInP.Three knot opto-electronic devices 500 further include the first p-n structure With the second p-n structure.First p-n structure includes the first p-n junction 502, such as AlGaAs or InGaP, the second p-n junction 506, such as GaAs.Second p-n structure includes third p-n junction 508, such as SiGe or SiGeSn, and wherein third p-n junction 508 is far from incident The bottom battery of light, followed by reflecting layer or reflective rear contact site 520.Third p-n junction 508 is referred to as the second p-n junction First p-n junction of structure.First p-n junction 502, the second p-n junction 506 and third p-n junction 508 can by using tunnel knot 504' and 504 " are electrically coupled, as shown in figure 5, wherein the first p-n junction 502, the second p-n junction 506 and third p-n junction 508 are three knot photoelectrons The voltage of device 500 generates knot, and tunnel knot 504' and 504 " provide the first, second, and third p-n junction and/or device remaining Being electrically coupled between part.

In one embodiment or embodiment of three knot opto-electronic devices 500, bottom knot (for example, the second p-n structure Third p-n junction 508) it may include IV races semiconductor comprising at least one of SiGe, SiGeSn, SiSn or GeSn.It is similar Ground, the first p-n junction (for example, first p-n junction 502 of the first p-n structure) may include Group III-V semiconductor comprising At least one of AlInGaP, InGaP or AlGaAs.In addition, the second p-n junction 506 of the first p-n structure may include iii-v Semiconductor.Furthermore, it is possible to which there are the third p-n junction (not shown) of the first p-n structure.It is more fully described below with reference to Fig. 7 C The example of the third p-n junction of one p-n structure.

Although embodiment or embodiment shown in the example of Figure 4 and 5 describe three knot opto-electronic devices (for example, device Part 400 and 500), but those of ordinary skill in the art will readily recognize that one or more additional p-n structures and/or additional P-n junction can in a similar way be added in device 400 and 500, on existing p-n structure and/or p-n junction or it Under, and the rest part of device may be coupled to by one or more tunnel junction layers.Those of ordinary skill in the art also recognize Knowing a variety of materials listed can be different from the example listed herein.In addition, each p-n formed in device 400 and 500 Knot can be homojunction or hetero-junctions, that is to say, that according to the disclosure, N layers and P layers can be made of identical material, or N layers and P layers of person can be made from a variety of materials.In addition, the doping of the material in p-n structure or p-n junction can invert.Example Such as, p-type material can be placed on the top of structure or knot, and towards the sun, and n-type material can be placed on the bottom of structure or knot Portion.

Fig. 6 shows another example of embodiment or embodiment according to more knot opto-electronic devices 600 of the disclosure.More knots Opto-electronic device 600 includes semiconductor structure 602,606 and 608.Semiconductor structure 602 corresponds to the first p-n junction, semiconductor junction Structure 606 corresponds to the second p-n junction, and semiconductor structure 608 corresponds to third p-n junction, and wherein semiconductor structure 602 and 606 can be with It is a part for the first p-n structure, semiconductor structure 608 can be a part for the second p-n structure.In one embodiment or reality It applies in mode, semiconductor structure 602,606 and 608 is including the n-layer being coupled and p layers (for example, to be formed as each knot At least one p-n junction of a part for structure).However, those of ordinary skill in the art will readily recognize that, a variety of materials, including but It is not limited to GaAs, AlGaAs, InGaP, InGaAs, AlInGaP, InGaAsP and its alloy etc., can be used for any one in these Layer, and meet the disclosure.In addition, the knot (for example, p-n junction) formed between two layers (for example, n-layer and p layers) needs not be Hetero-junctions, that is to say, that the knot can be that n-layer and p layers are made of identical material (for example, two layers are all GaAs or are all AlGaAs homojunction), and meet the disclosure.In addition, the doping of the material in p-n structure or p-n junction can invert.Example Such as, p-type material can be placed on the top of structure or knot, and towards the sun, and n-type material can be placed on the bottom of structure or knot Portion.In addition, mostly knot opto-electronic devices 600 may include the multiple p-n layers of growth of for example connecting.

It is multiple contact member 628a- on the top side of semiconductor structure 602 in the embodiment or embodiment 628n.Each topside contacts component 628a-628n includes optional anti-reflection coating (ARC) 626, at optional ARC 626 The n Metal contacts 624 in face and GaAs (GaAs) contact site 622 below n Metal contacts 624.In semiconductor junction It is multiple discontinuous contact portion 640a-640n on the rear side of structure 608.Each discontinuous contact portion 640a-640n includes being coupled to The optional contact layer 634 of the rear side of semiconductor structure 608 and the p- Metal contacts 636 below contact layer 634.It is optional ARC layer 632 can also exist on the rear sides of more knot opto-electronic devices 600, as shown in Figure 6.In ARC 632 and semiconductor junction It can be with textured layer 630 between structure 608.

Similar with Fig. 5, contact layer may include III-V group semi-conductor material, and such as GaAs (GaAs), this depends on final light The required composition of electronic device.According to embodiment described herein or embodiment, contact layer can be that N-shaped is highly doped. In some embodiments or embodiment, the doping concentration of contact layer can be greater than about 5 × 10¹⁸cm^-3In the range of, for example, from big In about 5 × 10¹⁸cm^-3To about 1 × 10¹⁹cm^-3.It the highly doped permissions of the contact layers of more knot opto-electronic devices 600 and deposits later Metal layer forms Ohmic contact, and this Ohmic contact is formed without executing annealing.

As described above, mostly knot opto-electronic device 600 includes three structures (for example, three p-n structures).One of structure With higher band gap and place or be located on the tops of more knot opto-electronic devices 600, and another structure have compared with It low band gap and places or is located on the bottoms of more knot opto-electronic devices 600.

Structure 602 can be described as p-n structure 602, have the band gap than 608 higher of structure or bigger, and include window 618 (for example, AllnP, AlGaInP or AIGaAs) of layer, n-type material (for example, AlInGaP, InGaP or AlGaAs) and p-type Expect (for example, AlInGaP, InGaP or AlGaAs).Structure 602 can optionally include rear side Window layer (for example, AllnP, AlGaInP or AlGaAs).Structure 602 is electrically connected and is optically connected to structure 606 by tunnel junction structure 604', and structure 606 can With referred to as p-n structure 606.Tunnel junction structure 604' includes p-type heavily doped layer and N-shaped heavily doped layer, for example, GaAs, InGaP or AlGaAs。

Structure 608 can be described as p-n structure 608, have lower than structure 602 or smaller band gap, and include N-shaped Material (for example, SiGe), p-type material (for example, SiGe).Structure 608 can optionally include rear side Window layer, for example, AllnP, AIGaInP or AIGaAs.In some embodiments or embodiment, rear side Window layer can correspond to veining layer 630.Structure 608, which passes through tunnel junction structure 604, " is electrically connected and is optically connected to structure 606.Tunnel junction structure 604 " includes p-type Heavily doped layer and N-shaped heavily doped layer, such as GaAs, InGaP or AlGaAs.

Those of ordinary skill in the art will readily recognize that a variety of materials listed can be different from the example listed herein.This Outside, the p-n junction formed in structure 602 and/or 608 can be homojunction or hetero-junctions, that is to say, that n-layer and p layers can It is made (for example, homojunction) of identical material, or (for example, hetero-junctions) can be made from a variety of materials, and all accorded with Close the disclosure.In addition, material doped in p-n structure or p-n junction can invert.For example, p-type material can be placed on structure or The top of knot, towards the sun, and n-type material can be placed on the bottom of structure or knot.It, can be by one as shown in structure 606 A or multiple additional p-n structures are added to more knot opto-electronic devices 600, and structure 606 is properly termed as p-n structure 606.Structure 606 can be coupled to the rest part of device by tunnel junction layer or layer.

In conjunction with one or more of above-mentioned Fig. 1-6, various structures shown in Fig. 7 A-7C can be based on and form more knot light The various embodiments or embodiment of electronic device.In one example, as shown in Figure 7 A, mostly knot opto-electronic devices 700 can be with Including the first p-n junction 710 made of III-V group semi-conductor material and the second p-n junction made of IV races semi-conducting material 715.In one aspect, the first p-n junction 710 can be GaAs p-n junctions, and the second p-n junction 715 can be SiGe p-n junctions so that More knot opto-electronic devices 700 have GaAs on SiGe.On the other hand, the first p-n junction 710 can be GaAs p-n junctions, the Two p-n junctions 715 can be SiGeSn p-n junctions so that more knot opto-electronic devices 700 have GaAs on SiGeSn.In addition, the One p-n junction 710 can be a part for the first p-n structure, and the second p-n junction 715 can be a part for the second p-n structure.

In another example, as shown in Figure 7 B, mostly knot opto-electronic device 720 may include by Group III-V semiconductor material First p-n junction 730 and the second p-n junction 735 and the third p-n junction 740 made of IV semi-conducting materials made of material.At one Aspect, the first p-n junction 730 can be InGaP p-n junctions, and the second p-n junction 735 can be GaAs p-n junctions, third p-n junction 740 Can be SiGe p-n junctions so that more knot opto-electronic devices 720 have InGaP/GaAs on SiGe.On the other hand, first P-n junction 730 can be AlGaAs p-n junctions, and the second p-n junction 735 can be GaAs p-n junctions, and third p-n junction 740 can be SiGe p-n junctions so that more knot opto-electronic devices 720 have AlGaAs/GaAs on SiGe.It yet still another aspect, the first p-n junction 730 can be InGaP p-n junctions, and the second p-n junction 735 can be GaAs p-n junctions, and third p-n junction 740 can be SiGeSn p- N is tied so that more knot opto-electronic devices 720 have InGaP/GaAs on SiGeSn.It yet still another aspect, the first p-n junction 730 can be with It is AlGaAs p-n junctions, the second p-n junction 735 can be GaAs p-n junctions, and third p-n junction 740 can be SiGeSn p-n junctions, make Much knot opto-electronic device 720 has AlGaAs/GaAs on SiGeSn.In addition, the first p-n junction 730 and the second p-n junction 735 Can be a part for the first p-n structure, third p-n junction 740 can be a part for the second p-n structure.

In another example, as seen in figure 7 c, mostly knot opto-electronic device 750 may include by Group III-V semiconductor material Expect manufactured first p-n junction 760, the second p-n junction 765 and third p-n junction 770 and the 4th made of IV races semi-conducting material P-n junction 780.In one aspect, the first p-n junction 760 can be AlInGaP p-n junctions, and the second p-n junction 765 can be InGaAsP P-n junction, third p-n junction 770 can be GaAs p-n junctions, and the 4th p-n junction 780 can be SiGe p-n junctions so that tie photoelectricity more Sub- device 750 has AlInGaP/InGaAsP/GaAs on SiGe.On the other hand, the first p-n junction 760 can be AlInGaP p-n junctions, the second p-n junction can be AlGaAs p-n junctions, and third p-n junction 770 can be GaAs p-n junctions, the 4th p- N knots 780 can be SiGe p-n junctions so that more knot opto-electronic devices 750 have AlInGaP/AlGaAs/GaAs on SiGe. It yet still another aspect, the first p-n junction 760 can be AlInGaP p-n junctions, the second p-n junction 765 can be InGaAsP p-n junctions, the Three p-n junctions 770 can be GaAs p-n junctions, and the 4th p-n junction 780 can be SiGeSn p-n junctions so that tie opto-electronic device more 750 have AlInGaP/InGaAsP/GaAs on SiGeSn.It yet still another aspect, the first p-n junction 760 can be AlInGaP p- N is tied, and the second p-n junction 765 can be AlGaAs p-n junctions, and third p-n junction 770 can be GaAs p-n junctions, the 4th p-n junction 780 Can be SiGeSn p-n junctions so that more knot opto-electronic devices 750 have AlInGaP/AlGaAs/GaAs on SiGeSn.This Outside, the first p-n junction 760, the second p-n junction 765 and third p-n junction 770 can be a part for the first p-n structure, the 4th p-n junction 780 can be a part for the second p-n structure.

Although foregoing teachings are related to the example embodiment or embodiment of various aspects of the disclosure, can not take off Other and further embodiment or reality of various aspects of the disclosure can be designed in the case of base region from the disclosure Mode is applied, and its range is indicated in the appended claims.Therefore, attached drawing be intended to be illustrative rather than defining or limiting property 's.Particularly, many design elements can change, including but not limited to：Opto-electronic device may include p-on-n rather than n- The knot of on-p, the structure in opto-electronic device may include two or more knots, and opto-electronic device may include as homogeneity The knot of knot, tunnel knot can be made of AlGaAs, GaAs or InGaP or other materials, in opto-electronic device or photoelectron device Other layers in the structure of part can be replaced with different materials, for example, AIGaAs or AlGaInP replaces AllnP etc., and light The reflecting layer of electronic device can be made completely of metal or metal alloy and is made of dielectric and metal or metal alloy.

Although according to the illustrated embodiment or embodiment describes the disclosure, those of ordinary skill in the art It will readily appreciate that, there may be the modifications of embodiment or embodiment, and these modifications will meet the disclosure.Therefore, exist Without departing from the scope of the appended claims, those of ordinary skill in the art can carry out many modifications.

Claims

1. a kind of method that opto-electronic device is tied in manufacture more, this method include：

The first p-n structure is provided on substrate, wherein first p-n structure includes the first semiconductor for having first band gap First base layer so that the lattice constant match of the lattice constant and the substrate of first semiconductor, and it is wherein described First semiconductor includes Group III-V semiconductor；

The second p-n structure is provided on first p-n structure, wherein second p-n structure includes having the second band gap Second base layer of the second semiconductor, wherein the lattice constant of the lattice constant of second semiconductor and first semiconductor Matching, and wherein described second semiconductor includes IV races semiconductor；With

More knot opto-electronic devices are removed from the substrate,

Wherein described more knot opto-electronic devices include first p-n structure and second p-n structure.

2. according to the method described in claim 1, wherein described more knot opto-electronic devices are flexible devices.

3. according to the method described in claim 1, the wherein described substrate includes GaAs chips.

4. according to the method described in claim 1, wherein existing between first p-n structure and second p-n structure First tunnel knot.

5. according to the method described in claim 1, wherein described first semiconductor include GaAs, AlGaAs, InGaP, InGaAs, AlInGaP, AlInGaAs, InGaAsP, AlInGaAsP, GaN, InGaN, AlGaN, AlInGaN, GaP, its alloy or its derivative It is one or more in object.

6. according to the method described in claim 1, wherein described second semiconductor includes Si, Ge, C, Sn, its alloy or its derivative It is one or more in object.

7. according to the method described in claim 1, wherein described second semiconductor has the energy gap smaller than first semiconductor.

8. according to the method described in claim 1, one or both of wherein described first p-n structure or described second p-n structure Including physical texture surface.

9. according to the method described in claim 8, wherein by using Stranski-Krastanov techniques or Volmer- Any of Weber techniques make the lattice mismatch between at least two materials in the p-n structure realize the physics Texturizing surfaces.

10. according to the method described in claim 1, wherein described first p-n structure further includes one or more p-n junctions.

11. according to the method described in claim 1, wherein described second p-n structure further includes one or more p-n junctions.

12. according to the method described in claim 1, wherein described more knot opto-electronic device further includes support layer, the support layer With dielectric layer, semiconductor contact layer, passivation layer, including transparent conducting oxide layer, anti-reflection coating, metal coating, adhesive phase, One or more of epoxy resin layer or plastic coating.

13. according to the method for claim 12, wherein the support layer has chemistry steady the acid used in stripping technology It is qualitative.

14. according to the method described in claim 1, at least one in wherein described first p-n structure and second p-n structure A includes hetero-junctions.

15. according to the method described in claim 1, further including providing the sacrifice for being suitable for extension stripping technology over the substrate Layer.

16. according to the method for claim 15, wherein the sacrificial layer includes AlAs.

17. according to the method described in claim 1, wherein by using including one of the following or multiple epitaxial growth works Skill provides first p-n structure：

Metal organic chemical vapor deposition (MOCVD) technique,

Hydride gas-phase epitaxy (HVPE) technique,

Molecular beam epitaxy (MBE) technique,

Metal organic vapor (MOVPE or OMVPE) technique,

Liquid phase epitaxy (LPE) technique, or

Close space gas phase transmission (CSVT) epitaxy technique.

18. according to the method described in claim 1, wherein described second semiconductor is by one of the following or multiple generations：

Plasma enhanced chemical vapor deposition (PECVD) technique,

Physical vapour deposition (PVD) (PVD) technique,

Sub-atmospheric CVD (APCVD) technique,

Atomic layer deposition (ALD) technique,

HVPE techniques,

MOVPE or OMVPE techniques,

MOCVD techniques,

Low-pressure chemical vapor deposition (LPCVD) technique,

Hot line chemical vapor deposition (HWCVD) technique,

Inductively coupled plasma enhances chemical vapor deposition (ICP-CVD) technique,

Or the CVD of other forms.

19. according to the method described in claim 1, further including removing (ELO) technique using extension, for tying photoelectricity by described more Sub- device is removed from the substrate.

20. a kind of more knot opto-electronic devices, including：

First p-n structure, wherein first p-n structure includes the first base layer of first semiconductor with first band gap, So that the lattice constant match of the lattice constant and the substrate of first semiconductor, and the wherein described first semiconductor packet Include Group III-V semiconductor；With

By the second p-n structure being epitaxially-formed on first p-n structure, wherein second p-n structure includes Second base layer of the second semiconductor with the second band gap, wherein the lattice constant of second semiconductor and described the first half The lattice constant match of conductor, and wherein described second semiconductor includes IV races semiconductor,

Wherein described more knot opto-electronic device is removed from the substrate, and includes first p-n structure and described Second p-n structure.

21. more knot opto-electronic devices according to claim 20, wherein more knot opto-electronic devices are flexible devices.

22. more knot opto-electronic devices according to claim 20, wherein the substrate includes GaAs chips.

23. more knot opto-electronic devices according to claim 20, wherein in first p-n structure and the 2nd p-n There is the first tunnel knot between structure.

24. it is according to claim 20 tie opto-electronic device, wherein first semiconductor include GaAs, AlGaAs, InGaP、InGaAs、AlInGaP、AlInGaAs、InGaAsP、AlInGaAsP、GaN、InGaN、AlGaN、AlInGaN、GaP、 It is one or more in its alloy or derivatives thereof.

25. it is according to claim 20 tie opto-electronic device, wherein second semiconductor include Si, Ge, C, Sn, its It is one or more in alloy or derivatives thereof.

26. it is according to claim 20 tie opto-electronic device, wherein second semiconductor has than described the first half The small energy gap of conductor.

27. more knot opto-electronic devices according to claim 20, wherein first p-n structure and second p-n junction One or both of structure includes physical texture surface.

28. more knot opto-electronic devices according to claim 20, wherein first p-n structure further includes one or more P-n junction.

29. more knot opto-electronic devices according to claim 20, wherein second p-n structure further includes one or more P-n junction.

30. more knot opto-electronic devices according to claim 20, wherein more knot opto-electronic devices further include support layer, There is the support layer dielectric layer, semiconductor contact layer, passivation layer, including transparent conducting oxide layer, anti-reflection coating, metal to apply It is one or more in layer, adhesive phase, epoxy resin layer or plastic coating.

31. more knot opto-electronic devices according to claim 30, wherein the support layer during stripping technology to using Acid have chemical stability.

32. more knot opto-electronic devices according to claim 20, wherein first p-n structure and second p-n junction At least one of structure includes hetero-junctions.

33. a kind of more knot opto-electronic devices, including：

First p-n structure, wherein first p-n structure further includes the first p-n junction and the second p-n junction, wherein first p-n Knot includes the first monocrystalline Group III-V semiconductor for having first band gap so that the lattice of the first monocrystalline Group III-V semiconductor The lattice constant match of constant and substrate；With

By the second p-n structure being epitaxially-formed on first p-n structure, wherein second p-n structure includes The third p-n junction of the second monocrystalline IV races semiconductor with the second band gap, and the wherein described second monocrystalline IV races semiconductor The lattice constant match of lattice constant and the first monocrystalline Group III-V semiconductor,

34. more knot opto-electronic devices according to claim 33, wherein more knot opto-electronic devices are flexible devices.

35. more knot opto-electronic devices according to claim 33, wherein the third p-n junction of second p-n structure Including one or more to form the separate outer of more knot opto-electronic devices in Si, Ge, C, Sn, its alloy or derivatives thereof It ties the bottom of portion's light source.