CN109639138A - A kind of positive and negative level shifting circuit - Google Patents
A kind of positive and negative level shifting circuit Download PDFInfo
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- CN109639138A CN109639138A CN201811599626.3A CN201811599626A CN109639138A CN 109639138 A CN109639138 A CN 109639138A CN 201811599626 A CN201811599626 A CN 201811599626A CN 109639138 A CN109639138 A CN 109639138A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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Abstract
The invention discloses a kind of positive and negative level shifting circuits, including not overlapping clock module and positive and negative level switch module；The first input end of clock module is not overlapped and the second input terminal is respectively connected to control signal and positive voltage, the first input end of positive and negative level switch module and the second input terminal connect positive voltage and negative voltage respectively；First output end of not overlapping clock module exports the first signal, and the second output terminal of not overlapping clock module exports second signal；When the level for controlling signal is low level, the first output end of positive and negative level switch module exports negative voltage, and the second output terminal of positive and negative level switch module exports positive voltage；When the level for controlling signal is high level, the first output end of positive and negative level switch module exports positive voltage, and the second output terminal of positive and negative level switch module exports negative voltage.The present invention can be realized positive and negative level conversion function.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of positive and negative level shifting circuits.
Background technique
In Integrated circuit IC design process, to adapt to different circuit module design requirements, different voltages, example are generally required
Such as in switching circuit, it is desirable to provide positive and negative level control switch pipe is turned on and off, but the input voltage of circuit is usually
Single, therefore, when IC design, which needs a kind of positive and negative level shifting circuit that input voltage is converted into different circuits, to be needed
The relevant voltage wanted.
To sum up, the problem of being difficult to realize positive and negative level conversion exists in the prior art.
Summary of the invention
The embodiment of the invention provides a kind of positive and negative level shifting circuits, it is intended to solve existing in the prior art to be difficult to reality
The problem of existing positive and negative level conversion.
The embodiment provides a kind of positive and negative level shifting circuits, including not overlapping clock module and positive negative level
Conversion module；
The first input end and the second input terminal of not overlapping clock module are respectively connected to control signal and positive voltage, do not overlap
The first output end and second output terminal of clock module connect the first controlled end of positive and negative level switch module and second controlled respectively
End, the first input end of positive and negative level switch module and the second input terminal connect positive voltage and negative voltage, positive and negative level conversion respectively
Module is additionally provided with the first output end and second output terminal；
First output end of not overlapping clock module exports the first signal, the second output terminal output of not overlapping clock module
Second signal；
When the level for controlling signal is low level, the first signal is high level signal, and second signal is low level signal, just
First output end of negative level conversion module exports negative voltage, and the second output terminal of positive and negative level switch module exports positive voltage；
When the level for controlling signal is high level, the first signal is low level signal, and second signal is high level signal, just
First output end of negative level conversion module exports positive voltage, and the second output terminal of positive and negative level switch module exports negative voltage.
Existing beneficial effect is the embodiment of the present invention compared with prior art: it can be realized positive and negative level conversion function,
The clock (the first signal and second signal) that two-phase does not overlap is generated by not overlapping clock module, to control positive and negative level conversion
The on-off of module, the generating positive and negative voltage that cannot can not be exported overlappingly improve the reliability of level conversion process.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without any creative labor, it can also be obtained according to these attached drawings others
Attached drawing.
Fig. 1 is the structural schematic diagram for the positive and negative level shifting circuit that one embodiment of the present of invention provides；
The electrical block diagram of not overlapping clock module in Fig. 1 that Fig. 2 provides for one embodiment of the present of invention；
The electrical block diagram of positive and negative level switch module in Fig. 1 that Fig. 3 provides for one embodiment of the present of invention；
The circuit structure signal of another positive and negative level switch module in Fig. 1 that Fig. 4 provides for one embodiment of the present of invention
Figure.
Specific embodiment
In order to make those skilled in the art more fully understand this programme, below in conjunction with attached in this programme embodiment
Figure, is explicitly described the technical solution in this programme embodiment, it is clear that described embodiment is this programme a part
Embodiment, instead of all the embodiments.Based on the embodiment in this programme, those of ordinary skill in the art are not being made
The range of this programme protection all should belong in every other embodiment obtained under the premise of creative work.
The specification and claims of this programme and term " includes " and other any deformations in above-mentioned attached drawing are
Refer to " including but not limited to ", it is intended that cover and non-exclusive include.In addition, term " first " and " second " etc. are for distinguishing
Different objects, not for description particular order.
Realization of the invention is described in detail below in conjunction with specific attached drawing:
Fig. 1 shows a kind of structure of positive and negative level shifting circuit provided by one embodiment of the invention, for the ease of saying
Bright, only parts related to embodiments of the present invention are shown, and details are as follows:
As shown in Figure 1, a kind of positive and negative level shifting circuit provided by the embodiment of the present invention, including do not overlap clock module
100 and positive and negative level switch module 200；
The first input end and the second input terminal of not overlapping clock module 100 are respectively connected to control signal Vin and positive voltage
VDD, the first output end and second output terminal of not overlapping clock module 100 connect the first of positive and negative level switch module 200 respectively
Controlled end and the second controlled end, the first input end and the second input terminal of positive and negative level switch module 200 meet positive voltage VDD respectively
With negative voltage VEE, positive and negative level switch module 200 is additionally provided with the first output end and second output terminal；
First output end of not overlapping clock module 100 exports the first signal V1, the second of not overlapping clock module 100
Output end exports second signal V2；
When the level for controlling signal Vin is low level, the first signal V1For high level signal, second signal V2For low level
First output end of signal, positive and negative level switch module 200 exports negative voltage VEE, and the second of positive and negative level switch module 200 is defeated
Outlet exports positive voltage VDD；
When the level for controlling signal Vin is high level, the first signal V1For low level signal, second signal V2For high level
First output end of signal, positive and negative level switch module 200 exports positive voltage VDD, and the second of positive and negative level switch module 200 is defeated
Outlet exports negative voltage VEE.
As shown in Figure 1, signal involved in the present embodiment includes: control signal Vin, positive voltage VDD, negative voltage VEE, the
One signal V1, second signal V2, the first output signal V of the first output end output of positive and negative level switch module 200O1, positive negative electricity
The second output terminal of flat conversion module 200 exports the second output signal VO2。
In the present embodiment, the first signal V1Level and second signal V2Level keep reverse phase, that is to say, that the electricity of the two
Flat is always reverse phase, cannot be identical, one be positive level, another be negative level.
The present invention can be realized positive and negative level conversion function, generate what two-phase did not overlapped by not overlapping clock module 100
Clock (the first signal V1With second signal V2), to control the on-off of positive and negative level switch module 200, cannot can not export overlappingly
Generating positive and negative voltage improves the reliability of level conversion process, and circuit structure is simple, area is small, at low cost, is easily integrated and real
Existing, technological flexibility and stability are higher.
As shown in Fig. 2, in one embodiment of the invention, not overlapping clock module 100 includes first and non-unit
NAND1, second and non-unit NAND2, third and non-unit NAND3, the first rp unit INV and the first buffer cell BUF；
First with the first input end of non-unit NAND1 and the second input terminal respectively with not overlapping clock module 100 the
One input terminal and the second input terminal correspond, the input of the output end and the first rp unit INV of first and non-unit NAND1
The input terminal of end and the first buffer cell BUF connect altogether, and the output termination second of the first rp unit INV is with non-unit NAND2's
First input end, the first input end of output the termination third and non-unit NAND3 of the first buffer cell BUF, third and non-list
The output end of the second input terminal of first NAND3 and second and non-unit NAND2 connect not forming overlappingly the first of clock module 100 altogether
Output end, second connects to be formed altogether and not overlap with the second input terminal of non-unit NAND2 and the output end of third and non-unit NAND3
The second output terminal of clock module 100.
As shown in Fig. 2, first includes the first NAND gate with non-unit NAND1, second includes second with non-unit NAND2
NAND gate, third and non-unit NAND3 include third NAND gate, and the first rp unit INV includes the first phase inverter.
As shown in Fig. 2, the first buffer cell BUF includes three state buffer.
As shown in Fig. 2, the working principle of not overlapping clock module 100 are as follows:
When the level for controlling signal Vin is low level, first exports high level, the first rp unit with non-unit NAND1
INV exports low level, and the first buffer cell BUF exports high level, the second the first signal V exported with non-unit NAND21For
High level, the second signal V of third and non-unit NAND3 output2For low level.
When the level for controlling signal Vin is high level, first exports low level, the first rp unit with non-unit NAND1
INV exports high level, and the first buffer cell BUF exports low level, the second the first signal V exported with non-unit NAND21For
Low level, the second signal V of third and non-unit NAND3 output2For high level.
As shown in figure 3, in one embodiment of the invention, positive and negative level switch module 200 includes first switch unit
210 and second switch unit 220；
First output end of the not overlapping clock module 100 of the controlled termination of first switch unit 210, first switch unit
210 first input end and the second input terminal connect positive voltage VDD and negative voltage VEE, the output end of first switch unit 210 respectively
Be positive the first output end of negative level conversion module 200；
The second output terminal of the not overlapping clock module 100 of the controlled termination of second switch unit 220, second switch unit
220 first input end and the second input terminal connect positive voltage VDD and negative voltage VEE, the output end of second switch unit 220 respectively
Be positive the second output terminal of negative level conversion module 200；
The first of first switch unit 210 draws the second exit of termination second switch unit 220, first switch unit
The second of 210 draws the first exit of termination second switch unit 220；
When first output end of not overlapping clock module 100 exports high level signal, the second of first switch unit 210
It is connected between input terminal and its output end；When first output end of not overlapping clock module 100 exports low level signal, first is opened
It closes and is connected between the first input end and its output end of unit 210；
When the second output terminal of not overlapping clock module 100 exports high level signal, the second of second switch unit 220
It is connected between input terminal and its output end；When the second output terminal of not overlapping clock module 100 exports low level signal, first is opened
It closes and is connected between the first input end and its output end of unit 210.
As shown in figure 3, first switch unit 210 includes third PMOS tube MP3, the 7th PMOS tube MP7, the 7th NMOS tube
MN7 and third NMOS tube MN3；
The grid of third PMOS tube MP3 is the controlled end of first switch unit 210, and the source electrode of third PMOS tube MP3 is the
The first input end of one switch unit 210, the drain electrode of third PMOS tube MP3 connect the source electrode of the 7th PMOS tube MP7, the 7th PMOS tube
The drain electrode of the grounded-grid GND, the 7th PMOS pipe MP7 of MP7 and the drain electrode of the 7th NMOS tube MN7 connect to be formed altogether and state first switch
The output end of unit 210, the source electrode and third NMOS tube MN3 of the grounded-grid GND of the 7th NMOS tube MN7, the 7th NMOS tube MN7
Drain electrode connect the first exit to form first switch unit 210 altogether, the grid of the 3rd NMOS pipe MN3 is first switch unit
210 the second exit, the source electrode of third NMOS tube MN3 are 210 second input terminal of first switch unit.
As shown in figure 3, second switch unit 220 includes the 4th PMOS tube MP4, the 8th PMOS tube MP8, the 8th NMOS tube
MN8 and the 4th NMOS tube MN4；
The source electrode of 4th PMOS tube MP4 is the first input end of second switch unit 220, the grid of the 4th PMOS pipe MP4
For the controlled end of second switch unit 220, the drain electrode of the 4th PMOS tube MP4 connects the source electrode of the 8th PMOS tube MP8, the 8th PMOS tube
The drain electrode of the grounded-grid GND, the 8th PMOS pipe MP8 of MP8 and the drain electrode of the 8th NMOS tube MN8 connect to form second switch list altogether
The output end of member 220, the source electrode and the 4th NMOS tube MN4 of the grounded-grid GND of the 8th NMOS tube MN8, the 8th NMOS tube MN8
Drain electrode connect the first exit to form second switch unit 220 altogether, the grid of the 4th NMOS pipe MN4 is second switch unit
220 the second exit, the source electrode of the 4th NMOS tube MN4 are the second input terminal of second switch unit 220.
As shown in figure 3, the working principle of positive and negative level switch module 200 are as follows:
1, as the first signal V1For high level and second signal V2When for low level: third PMOS tube MP3 cut-off, the 7th
PMOS tube MP7 conducting, due to the grounded-grid GND of the 7th NMOS tube MN7, the source electrode of the 4th NMOS tube MN4 meets negative voltage VEE,
Grid, the source electrode of grid of the electric current through the 7th NMOS tube MN7, source electrode to the 4th NMOS tube MN4, therefore, the 7th NMOS tube MN7 is led
It is logical, similarly, third NMOS tube MN3 conducting, the first output signal VO1For negative level；In addition, the 4th PMOS pipe MP4 is connected, the 8th
PMOS tube MP8 conducting, the 8th NMOS tube MN8 conducting, the 4th NMOS pipe MN4 conducting, the second output signal VO2For high level.
2, as the first signal V1For low level and second signal V2When for high level: third PMOS tube MP3 conducting, the 7th
PMOS tube MP7 conducting, the 7th NMOS tube MN7 conducting, third NMOS tube MN3 conducting, the first output signal VO1For high level；The
Four PMOS tube MP4 cut-off, the 8th PMOS pipe MP8 conducting, the 8th NMOS tube MN8 conducting, the 4th NMOS tube MN4 conducting, second is defeated
Signal V outO2For low level.
In the present embodiment, clock (the first signal V for not overlapped by two-phase1With second signal V2), output two-way reverse phase
Signal (the first output signal VO1With the second output signal VO2), positive and negative level conversion is realized, and avoid level and overlap,
Stability is high.
As shown in figure 3, positive and negative level switch module 200 further includes third switch unit 230 and the 4th switch unit 240；
First output end of the not overlapping clock module 100 of the controlled termination of third switch unit 230, third switch unit
230 first input end and the second input terminal meet positive voltage VDD and negative voltage VEE respectively；
The second output terminal of the not overlapping clock module 100 of the controlled termination of 4th switch unit 240, the 4th switch unit
240 first input end and the second input terminal meet positive voltage VDD and negative voltage VEE respectively；
The first of third switch unit 230 draws the second exit of the 4th switch unit 240 of termination, third switch unit
The second of 230 draws the first exit of the 4th switch unit 240 of termination.
As shown in figure 3, third switch unit 230 includes the first PMOS tube MP1, the 5th PMOS tube MP5, the 5th NMOS tube
MN5 and the first NMOS tube MN1；
The source electrode of first PMOS tube MP1 is the first input end of third switch unit 230, the grid of the first PMOS pipe MP1
For the controlled end of third switch unit 230, the drain electrode of the first PMOS tube MP1 connects the source electrode of the 5th PMOS tube MP5, the 5th PMOS tube
The drain electrode of the grounded-grid GND, the 5th PMOS pipe MP5 of MP5 connect the drain electrode of the 5th NMOS tube MN5, the grid of the 5th NMOS tube MN5
Pole is grounded GND, and the drain electrode of the source electrode of the 5th NMOS tube MN5 and the first NMOS tube MN1 connect to form third switch unit 230 altogether
First exit, the grid of the first NMOS tube MN1 are the second exit of third switch unit 230, the first NMOS tube MN1's
Source electrode is the second input terminal of third switch unit 230.
As shown in figure 3, the 4th switch unit 240 includes the second PMOS tube MP2, the 6th PMOS tube MP6, the 6th NMOS tube
MN6 and the second NMOS tube MN2；
The source electrode of second PMOS tube MP2 is the first input end of the 4th switch unit 240, the grid of the 2nd PMOS pipe MP2
For the controlled end of the 4th switch unit 240, the drain electrode of the second PMOS tube MP2 connects the source electrode of the 6th PMOS tube MP6, the 6th PMOS tube
The drain electrode of the grounded-grid GND, the 6th PMOS pipe MP6 of MP6 connect the drain electrode of the 6th NMOS tube MN6, the grid of the 6th NMOS tube MN6
Pole is grounded GND, and the drain electrode of the source electrode of the 6th NMOS tube MN6 and the second NMOS tube MN2 connect to form the 4th switch unit 240 altogether
First exit, the grid of the second NMOS tube MN2 are the second exit of the 4th switch unit 240, the second NMOS tube MN2's
Source electrode is the second input terminal of the 4th switch unit 240.
In the present embodiment, by increasing third switch unit 230 and the 4th switch unit 240, make the first output signal VO1
With the second output signal VO2Level it is more stable, reduce interference.
As shown in figure 4, in one embodiment, positive and negative level switch module 200 includes first switch unit 210, second
Switch unit 220, third switch unit 230 and the 4th switch unit 240.
The source electrode of 5th NMOS tube MN5 connects altogether with the grid of the second NMOS tube MN2 and the grid of the 4th NMOS tube MN4, the
The source electrode of six NMOS tube MN6 connects altogether with the grid of the first NMOS tube MN1 and the grid of third NMOS tube MN3.
It should be noted that description of the invention port identical with numbering in the drawing or pin are to be connected to.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although referring to before
Stating embodiment, invention is explained in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (10)
1. a kind of positive and negative level shifting circuit, which is characterized in that including not overlapping clock module and positive and negative level switch module；
The first input end and the second input terminal of the not overlapping clock module are respectively connected to control signal and positive voltage, it is described not
The first output end and second output terminal of overlapping clock module connect respectively the positive and negative level switch module the first controlled end and
Second controlled end, the first input end and the second input terminal of the positive and negative level switch module connect positive voltage and negative voltage respectively,
The positive and negative level switch module is additionally provided with the first output end and second output terminal；
First output end of the not overlapping clock module exports the first signal, the second output terminal of the not overlapping clock module
Export second signal；
When the level of the control signal is low level, first signal is high level signal, and the second signal is low electricity
First output end of ordinary mail number, the positive and negative level switch module exports the negative voltage, the positive and negative level switch module
Second output terminal exports the positive voltage；
When the level of the control signal is high level, first signal is low level signal, and the second signal is high electricity
First output end of ordinary mail number, the positive and negative level switch module exports the positive voltage, the positive and negative level switch module
Second output terminal exports the negative voltage.
2. positive and negative level shifting circuit as described in claim 1, which is characterized in that the not overlapping clock module includes first
With non-unit, second and non-unit, third and non-unit, the first rp unit and the first buffer cell；
Described first is defeated with the first of the not overlapping clock module respectively with the first input end of non-unit and the second input terminal
Enter end and the second input terminal correspond, described first with the input terminal of the output end of non-unit and first rp unit and
The input terminal of first buffer cell connects altogether, the output termination described second and the first of non-unit of first rp unit
Input terminal, the output of first buffer cell terminate the first input end of the third and non-unit, the third and non-list
Second input terminal of member and the output end of described second and non-unit connect to form first output for not overlapping clock module altogether
End, described second with the output end of the second input terminal of non-unit and the third and non-unit when connecing to form described not overlapping altogether
The second output terminal of clock module.
3. positive and negative level shifting circuit as claimed in claim 2, which is characterized in that described first with non-unit include first with
NOT gate, described second includes the second NAND gate with non-unit, and the third and non-unit include third NAND gate, and described first is anti-
Phase element includes the first phase inverter.
4. positive and negative level shifting circuit as claimed in claim 2, which is characterized in that first buffer cell includes that tri-state is slow
Rush device.
5. positive and negative level shifting circuit as described in claim 1, which is characterized in that the positive and negative level switch module includes the
One switch unit and second switch unit；
First output end of not overlapping clock module, the first switch unit described in the controlled termination of the first switch unit
First input end and the second input terminal connect positive voltage and negative voltage respectively, the output end of the first switch unit be it is described just
First output end of negative level conversion module；
The second output terminal of not overlapping clock module, the second switch unit described in the controlled termination of the second switch unit
First input end and the second input terminal connect positive voltage and negative voltage respectively, the output end of the second switch unit be it is described just
The second output terminal of negative level conversion module；
The first of the first switch unit draws the second exit for terminating the second switch unit, the first switch list
The second of member draws the first exit for terminating the second switch unit；
When first output end of the not overlapping clock module exports high level signal, the second input of the first switch unit
It is connected between end and its output end；When first output end of the not overlapping clock module exports low level signal, described first
It is connected between the first input end of switch unit and its output end；
When the second output terminal of the not overlapping clock module exports high level signal, the second input of the second switch unit
It is connected between end and its output end；When the second output terminal of the not overlapping clock module exports low level signal, described first
It is connected between the first input end of switch unit and its output end.
6. positive and negative level shifting circuit as claimed in claim 5, which is characterized in that the first switch unit includes third
PMOS tube, the 7th PMOS tube, the 7th NMOS tube and third NMOS tube；
The grid of the third PMOS tube is the controlled end of the first switch unit, and the source electrode of the third PMOS tube is described
The first input end of first switch unit, the drain electrode of the third PMOS tube connect the source electrode of the 7th PMOS tube, and the described 7th
The grounded-grid of PMOS tube, the drain electrode of the 7th PMOS tube and the drain electrode of the 7th NMOS tube connect to be formed altogether and state first switch
The output end of unit, the grounded-grid of the 7th NMOS tube, source electrode and the third NMOS tube of the 7th NMOS tube
Drain electrode connects the first exit to form the first switch unit altogether, and the grid of the third NMOS tube is the first switch list
Second exit of member, the source electrode of the third NMOS tube are second input terminal of first switch unit.
7. positive and negative level shifting circuit as claimed in claim 5, which is characterized in that the second switch unit includes the 4th
PMOS tube, the 8th PMOS tube, the 8th NMOS tube and the 4th NMOS tube；
The source electrode of 4th PMOS tube is the first input end of the second switch unit, and the grid of the 4th PMOS tube is
The controlled end of the second switch unit, the drain electrode of the 4th PMOS tube connect the source electrode of the 8th PMOS tube, and the described 8th
The grounded-grid of PMOS tube, the drain electrode of the 8th PMOS tube and the drain electrode of the 8th NMOS tube connect to form described second and open altogether
Close the output end of unit, the grounded-grid of the 8th NMOS tube, the source electrode of the 8th NMOS tube and the 4th NMOS tube
Drain electrode connect the first exit to form the second switch unit altogether, the grid of the 4th NMOS tube is the second switch
Second exit of unit, the source electrode of the 4th NMOS tube are the second input terminal of the second switch unit.
8. positive and negative level shifting circuit as claimed in claim 5, which is characterized in that the positive and negative level switch module further includes
Third switch unit and the 4th switch unit；
First output end of not overlapping clock module, the third switch unit described in the controlled termination of the third switch unit
First input end and the second input terminal connect positive voltage and negative voltage respectively；
The second output terminal of not overlapping clock module, the 4th switch unit described in the controlled termination of 4th switch unit
First input end and the second input terminal connect positive voltage and negative voltage respectively；
The first of the third switch unit draws the second exit for terminating the 4th switch unit, and the third switch is single
The second of member draws the first exit for terminating the 4th switch unit.
9. positive and negative level shifting circuit as claimed in claim 8, which is characterized in that the third switch unit includes first
PMOS tube, the 5th PMOS tube, the 5th NMOS tube and the first NMOS tube；
The source electrode of first PMOS tube is the first input end of the third switch unit, and the grid of first PMOS tube is
The controlled end of the third switch unit, the drain electrode of first PMOS tube connect the source electrode of the 5th PMOS tube, and the described 5th
The grounded-grid of PMOS tube, the drain electrode of the 5th PMOS tube connect the drain electrode of the 5th NMOS tube, the 5th NMOS tube
Grounded-grid, the source electrode of the 5th NMOS tube and the drain electrode of first NMOS tube connect to form the third switch unit altogether
First exit, the grid of first NMOS tube are the second exit of the third switch unit, first NMOS tube
Source electrode be the third switch unit the second input terminal.
10. positive and negative level shifting circuit as claimed in claim 8, which is characterized in that the 4th switch unit includes second
PMOS tube, the 6th PMOS tube, the 6th NMOS tube and the second NMOS tube；
The source electrode of second PMOS tube is the first input end of the 4th switch unit, and the grid of second PMOS tube is
The controlled end of 4th switch unit, the drain electrode of second PMOS tube connect the source electrode of the 6th PMOS tube, and the described 6th
The grounded-grid of PMOS tube, the drain electrode of the 6th PMOS tube connect the drain electrode of the 6th NMOS tube, the 6th NMOS tube
Grounded-grid, the source electrode of the 6th NMOS tube and the drain electrode of second NMOS tube connect to form the 4th switch unit altogether
First exit, the grid of second NMOS tube are the second exit of the 4th switch unit, second NMOS tube
Source electrode be the 4th switch unit the second input terminal.
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| CN201811599626.3A CN109639138A (en) | 2018-12-26 | 2018-12-26 | A kind of positive and negative level shifting circuit |
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| CN201811599626.3A CN109639138A (en) | 2018-12-26 | 2018-12-26 | A kind of positive and negative level shifting circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107857A (en) * | 1995-09-05 | 2000-08-22 | Sharp Kabushiki Kaisha | Level converting circuit |
| CN104766631A (en) * | 2015-04-21 | 2015-07-08 | 苏州芯宽电子科技有限公司 | Positive-negative high-voltage level switching circuit |
| CN104796171A (en) * | 2015-03-25 | 2015-07-22 | 广州钧衡微电子科技有限公司 | Control circuit applied to SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) radiofrequency switches |
| CN104901699A (en) * | 2015-06-24 | 2015-09-09 | 中国电子科技集团公司第二十四研究所 | CMOS master-slave mode sampling holding circuit |
| CN107094012A (en) * | 2017-03-22 | 2017-08-25 | 尚睿微电子（上海）有限公司 | A kind of level shifting circuit and method |
-
2018
- 2018-12-26 CN CN201811599626.3A patent/CN109639138A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107857A (en) * | 1995-09-05 | 2000-08-22 | Sharp Kabushiki Kaisha | Level converting circuit |
| CN104796171A (en) * | 2015-03-25 | 2015-07-22 | 广州钧衡微电子科技有限公司 | Control circuit applied to SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) radiofrequency switches |
| CN104766631A (en) * | 2015-04-21 | 2015-07-08 | 苏州芯宽电子科技有限公司 | Positive-negative high-voltage level switching circuit |
| CN104901699A (en) * | 2015-06-24 | 2015-09-09 | 中国电子科技集团公司第二十四研究所 | CMOS master-slave mode sampling holding circuit |
| CN107094012A (en) * | 2017-03-22 | 2017-08-25 | 尚睿微电子（上海）有限公司 | A kind of level shifting circuit and method |
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