WO2016192447A1 - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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WO2016192447A1
WO2016192447A1 PCT/CN2016/077489 CN2016077489W WO2016192447A1 WO 2016192447 A1 WO2016192447 A1 WO 2016192447A1 CN 2016077489 W CN2016077489 W CN 2016077489W WO 2016192447 A1 WO2016192447 A1 WO 2016192447A1
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pattern
electrode
electrode protection
protection
layer pattern
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PCT/CN2016/077489
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English (en)
French (fr)
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孔祥永
辛龙宝
成军
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京东方科技集团股份有限公司
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Priority to US15/313,141 priority Critical patent/US9847400B2/en
Publication of WO2016192447A1 publication Critical patent/WO2016192447A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a preparation method thereof, and a display device.
  • LCD liquid crystal display
  • TFT Thin Film Transistor
  • a metal having a low resistance property such as copper or a copper alloy
  • the metal surface is easily oxidized, and the thickness of the oxide layer is temporally changed.
  • the increase and increase increase which causes the contact resistance of the source and the drain to increase, thereby causing the connection resistance of the active layer pattern and the source pattern and the drain pattern to be too high, thereby affecting the yield of the product.
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device, which avoids an active layer pattern and a surface due to surface oxidation due to a material having low resistance characteristics of the first electrode pattern and the second electrode pattern.
  • An electrode pattern and a second electrode pattern are connected to a problem that the resistance is too high.
  • an array substrate comprising: a substrate, a setting a first electrode pattern, a second electrode pattern, and an active layer pattern on the base substrate, a first electrode protection pattern covering the first electrode pattern, and a second electrode protection pattern covering the second electrode pattern;
  • the active layer pattern is disposed between the first electrode pattern and the second electrode pattern; the first electrode protection pattern and the second electrode protection pattern are respectively connected to both sides of the active layer pattern.
  • the material of the first electrode pattern and the second electrode pattern is copper or a copper alloy.
  • the first electrode pattern is covered by the first electrode protection pattern except for the lower surface in contact with the substrate substrate, and the first electrode protection pattern extends the first extension portion toward the active layer pattern, The first extension is covered by the first side of the active layer pattern;
  • the second electrode pattern is covered by the second electrode protection pattern except for the lower surface in contact with the substrate substrate, and the second electrode protection pattern extends the second extension portion toward the active layer pattern, and the second extension portion is separated by the active layer The second side of the pattern is covered.
  • the array substrate further includes: a first buffer layer pattern disposed between the first electrode pattern and the first electrode protection pattern, and disposed between the second electrode pattern and the second electrode protection pattern The second buffer layer pattern.
  • the material of the first electrode protection pattern, the second electrode protection pattern, the first buffer layer pattern and/or the second buffer layer pattern is molybdenum-niobium alloy or titanium.
  • the array substrate further includes: a gate insulating layer pattern disposed over the first electrode protection pattern, the second electrode protection pattern, and the active layer pattern, and a gate pattern disposed over the gate insulating layer pattern And a pixel electrode pattern;
  • the gate insulating layer pattern includes a via hole configured to electrically connect the pixel electrode pattern to the first electrode protection pattern or the second electrode protection pattern.
  • a method for fabricating an array substrate includes: forming a substrate; forming a first electrode pattern and a second electrode pattern on the substrate; forming a first electrode pattern a first electrode protection pattern and a second electrode protection pattern covering the second electrode pattern; forming an active layer pattern between the first electrode protection pattern and the second electrode protection pattern; wherein the first electrode protection pattern and the second electrode The protection patterns are respectively connected to both sides of the active layer pattern.
  • the first electrode pattern and the second electrode pattern are formed on the base substrate Forming a first buffer layer pattern overlying the surface of the first electrode pattern and a second buffer layer pattern overlying the surface of the second electrode pattern; wherein the first electrode protection pattern covers the first buffer layer pattern and The first electrode pattern, the second electrode protection pattern covers the second buffer layer pattern and the second electrode pattern.
  • a first buffer layer pattern covering the surface of the first electrode pattern is further formed and covered in the second
  • the second buffer layer pattern on the surface of the electrode pattern includes:
  • the method further includes: forming a gate insulating layer pattern including via holes on the first electrode protection pattern, the second electrode protection pattern, and the active layer pattern; and performing the same pattern on the gate insulating layer pattern The process forms a gate pattern and a pixel electrode pattern; wherein the pixel electrode pattern is electrically connected to the first electrode protection pattern or the second electrode protection pattern through the via.
  • the material of the first electrode protection pattern, the second electrode protection pattern, the first buffer layer pattern and/or the second buffer layer pattern is molybdenum-niobium alloy or titanium.
  • the material of the first electrode pattern and the second electrode pattern is copper or a copper alloy.
  • a display device comprising the above array substrate.
  • an array substrate, a preparation method thereof, and a display device provided by the embodiment of the present invention form a coating on a first electrode pattern and a second electrode pattern made of a material having low resistance characteristics.
  • a first electrode protection pattern of an electrode pattern, and a second electrode protection pattern covering the second electrode pattern forming an active layer pattern between the first electrode protection pattern and the second electrode protection pattern, avoiding the first electrode
  • the surface layer is oxidized to cause a problem that the active layer pattern is too high in connection with the first electrode pattern and the second electrode pattern, thereby improving the yield of the product.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic flow chart of a method for preparing the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic structural view of the array substrate provided by the embodiment of the present invention after the first step is completed;
  • FIG. 5 is a schematic structural view after the third step is completed when preparing the array substrate provided by the embodiment of the present invention.
  • FIG. 6 is a schematic structural view after the fourth step is completed when preparing the array substrate provided by the embodiment of the present invention.
  • FIG. 7 is a schematic structural view after the fifth step is completed when preparing the array substrate provided by the embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the invention.
  • an embodiment of the present invention provides an array substrate including a substrate substrate 9 , a first electrode pattern 11 , a second electrode pattern 12 , and an active layer pattern 5 disposed on the base substrate 9 , a first electrode protection pattern 3 covering the first electrode pattern 11 , and a second electrode pattern 12 a second electrode protection pattern 4; wherein the active layer pattern 5 is disposed between the first electrode pattern 11 and the second electrode pattern 12; the first electrode protection pattern 3 and the second electrode protection pattern 4 and the active layer pattern 5, respectively Connected on both sides.
  • the array substrate is formed by forming a first electrode protection pattern 3 covering the first electrode pattern 11 on the first electrode pattern 11 and the second electrode pattern 12 made of a material having low resistance characteristics, and coating the second electrode pattern 12.
  • the second electrode protection pattern 4 forms the active layer pattern 5 between the first electrode protection pattern 3 and the second electrode protection pattern 4, avoiding the case where the first electrode pattern 11 and the second electrode pattern 12 are made of a material having low resistance characteristics
  • the problem that the resistance of the active layer pattern 5 and the first electrode pattern 11 and the second electrode pattern 12 is too high due to surface oxidation thereof improves the yield of the product.
  • the material of the first electrode pattern 11 and the second electrode pattern 12 is a material having low resistance characteristics and high activity, such as copper or a copper alloy, and examples of the present invention are exemplified by copper.
  • the material of the active layer pattern 5 may be Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Indium Oxide (In 2 O 3 ), and oxidation. At least one of transparent metal oxide semiconductor materials such as zinc (ZnO).
  • the first electrode pattern 11 is covered by the first electrode protection pattern 3 except for the lower surface in contact with the substrate substrate 9, and the first electrode protection pattern 3 extends out of the active layer pattern 5 by the first extension portion 31, first The extension portion 31 is covered by the first side of the active layer pattern 5; the second electrode pattern 12 is covered by the second electrode protection pattern 4 except for the lower surface in contact with the substrate substrate 9, and the second electrode protection pattern 4 is oriented
  • the active layer pattern 5 extends out of the second extension 41, and the second extension 41 is covered by the second side of the active layer pattern 5.
  • the first electrode pattern 11 and the second electrode pattern 12 are caused to be formed.
  • Cu is oxidized, so the above array substrate further includes: a first buffer layer pattern 21 disposed between the first electrode pattern 11 and the first electrode protection pattern 3, and a second electrode pattern 12 and a second electrode protection pattern 4 A second buffer layer pattern 22 is in between.
  • the first slow The punch layer pattern 21 and the second buffer layer pattern 22 cover the first electrode pattern 11 and the second electrode pattern 12, respectively, effectively preventing the formation of the first electrode protection pattern 3 and the second electrode protection pattern 4,
  • the Cu of the surface of the one electrode pattern 11 and the second electrode pattern 12 is oxidized.
  • the materials of the first electrode protection pattern 3, the second electrode protection pattern 4, the first buffer layer pattern 21, and/or the second buffer layer pattern 22 are materials for preventing Cu oxidation and Cu diffusion, for example, molybdenum. Niobium alloy (MoNb) or titanium (Ti).
  • the array substrate further includes: a gate insulating layer pattern 6 disposed over the first electrode protection pattern 3, the second electrode protection pattern 4, and the active layer pattern 5, and a gate pattern 7 and pixels disposed over the gate insulating layer pattern 6.
  • the gate insulating layer pattern 6 includes a via for electrically connecting the pixel electrode pattern 8 to the first electrode protection pattern 3 or the second electrode protection pattern 4.
  • the first electrode pattern 11 and the second electrode pattern 12 may be a source pattern and a drain pattern, that is, when the first electrode pattern 11 represents a source pattern, then the second The electrode pattern 12 represents a drain pattern, and correspondingly, the first electrode protection pattern 3 covering the first electrode pattern 11 is equivalent to being electrically connected to the source pattern, and the second electrode protection pattern 4 covering the second electrode pattern 12 is equivalent.
  • the second electrode protection pattern is electrically connected to the drain pattern, and the pixel electrode pattern 8 is electrically connected to the second electrode protection pattern 4 electrically connected to the drain pattern.
  • the second electrode pattern 12 represents In the case of the source pattern, the pixel electrode pattern 8 is electrically connected to the first electrode protection pattern 3 electrically connected to the drain pattern; it should be understood that the first electrode pattern 11 is in FIG. 7 of the embodiment of the present invention.
  • the source pattern is represented, and the second electrode pattern 12 is represented by a drain pattern.
  • FIG. 2 is a schematic flow chart of a method for preparing the array substrate shown in FIG. 1.
  • an embodiment of the present invention further provides a method for fabricating an array substrate. After forming the substrate substrate 9, the method further includes the following steps:
  • Step 101 forming a first electrode pattern 11 and a second electrode pattern 12 on the base substrate 9;
  • Step 102 forming a first electrode protection pattern 3 covering the first electrode pattern 11 and a second electrode protection pattern 4 covering the second electrode pattern 12;
  • Step 103 forming an active layer pattern 5 between the first electrode protection pattern 3 and the second electrode protection pattern 4; wherein the first electrode protection pattern and the second electrode protection pattern are respectively associated with the active layer The sides of the pattern are connected.
  • the first electrode pattern 11 and the second electrode pattern 12 made of a material having low resistance characteristics are first formed, and then the first electrode pattern 11 is formed on the first electrode pattern 11 and the second electrode pattern 12, respectively.
  • An electrode protection pattern 3, and a second electrode protection pattern 4 covering the second electrode pattern 12, the first electrode pattern 11 and the second electrode pattern 12 are effectively prevented by the first electrode protection pattern 3 and the second electrode protection pattern 4.
  • FIG. 3 is a schematic structural view of the array substrate provided by the embodiment of the present invention after the first step is completed.
  • 4 is a schematic structural view after the second step is completed when the array substrate provided by the embodiment of the present invention is prepared.
  • FIG. 5 is a schematic structural view after the third step is completed when the array substrate provided by the embodiment of the present invention is prepared.
  • FIG. 6 is a schematic structural view after the fourth step is completed when the array substrate provided by the embodiment of the present invention is prepared.
  • FIG. 7 is a schematic structural view after the fifth step is completed when the array substrate provided by the embodiment of the present invention is prepared.
  • the flow of the method for preparing the array substrate is described in detail below.
  • the flow of the method for preparing the array substrate may include the following steps:
  • Step 201 forming an electrode material layer 1 on the base substrate 9, and after forming the electrode material layer 1, forming a buffer material layer 2, as shown in FIG.
  • the above-mentioned base substrate 9 may be a glass substrate, a quartz substrate, or an organic resin substrate.
  • the electrode material layer 1 is made of a material having low resistance characteristics and high activity, such as copper or a copper alloy, and examples of the present invention are exemplified by Cu.
  • the material of the first buffer layer pattern 21 and the second buffer layer pattern 22 is a material that prevents Cu oxidation and Cu diffusion, and is, for example, molybdenum-niobium alloy (MoNb) or titanium (Ti).
  • Step 202 forming a first electrode pattern 11, a second electrode pattern 12, and a first buffer layer pattern 21 covering the surface of the first electrode pattern 11 and a second buffer covering the surface of the second electrode pattern 12 by one patterning process.
  • the layer pattern 22 is as shown in FIG.
  • Step 203 forming a first electrode protection pattern 3 covering the first buffer layer pattern 21 and the first electrode pattern 11, and forming a second electrode protection pattern 4 covering the second buffer layer pattern 22 and the second electrode pattern 12.
  • the first electrode protection pattern 3 covers the first electrode pattern 11 in a portion overlapping with the substrate substrate 9, and both ends of the first electrode protection pattern 3 are disposed on the substrate substrate 9.
  • the second electrode protection pattern 4 covers the second electrode pattern 12 except the portion to which the base substrate 9 is attached, and both ends of the second electrode pattern 12 include the second extension portion 41 provided on the base substrate 9.
  • the first extension portion 31 of the first electrode protection pattern 3 and the second extension portion 41 of the second electrode protection pattern 4 are respectively connected to both sides of the active layer pattern 5.
  • Forming the first electrode protection pattern 3 and the second electrode protection pattern 4 in the above step 103 can be understood as depositing electrodes on the first electrode pattern 11, the first buffer layer pattern 21, the second electrode pattern 12, and the second buffer layer pattern 22. The material layer is protected, and then the first electrode protection pattern 3 and the second electrode protection pattern 4 are formed by an etching patterning process.
  • This embodiment is for illustrative purposes only, and embodiments of the present invention are not limited to the specific embodiments thereof.
  • the material of the first electrode protection pattern 3 and the second electrode protection pattern 4 is a material that prevents Cu oxidation and Cu diffusion, and is, for example, molybdenum-niobium alloy (MoNb) or titanium (Ti).
  • the electrode material layer 1 having a low resistance characteristic can be used to manufacture an array substrate having higher resolution, better performance, and larger size.
  • Forming the buffer material layer 2 on the electrode material layer can effectively prevent Cu diffusion of the electrode material layer, and prevent large-area Cu during subsequent etching to form the first electrode protection pattern 3 and the second electrode protection pattern 4. Oxidized.
  • Forming the first electrode pattern 11, the second electrode pattern 12, and the first buffer layer pattern 21 overlying the surface of the first electrode pattern and the second buffer layer pattern 22 overlying the surface of the second electrode pattern by one patterning process The problem of forming the first electrode pattern 11 and the second electrode pattern 12 while simplifying the process of diffusing and oxidizing Cu of the first electrode pattern 11 and the second electrode pattern 12 is also effectively prevented.
  • Step 204 forming an active layer pattern 5 respectively connected to the first electrode protection pattern 3 and the second electrode protection pattern 4 between the first electrode protection pattern 3 and the second electrode protection pattern 4, as shown in FIG.
  • Step 205 depositing a gate insulating layer on the first electrode protection pattern 3, the second electrode protection pattern 4, and the active layer pattern 5, and patterning the gate insulating layer to form a gate insulating layer pattern 6 including via holes, such as Figure 7 shows.
  • Step 206 depositing a transparent conductive layer (for example, ITO) on the gate insulating layer pattern 6, and forming the gate pattern 7 and the pixel electrode pattern 8 through the same patterning process on the transparent conductive layer, as shown in FIG.
  • the pixel electrode pattern 8 is electrically connected to the first electrode protection pattern 3 or the second electrode protection pattern 4 through via holes.
  • first electrode pattern 11 is protected by the first electrode protection pattern 3 and the first electrode protection pattern 3 is electrically connected to the first electrode pattern 11, and the second electrode protection pattern 4 is used to the second electrode pattern.
  • 12 is protected and the second electrode protection pattern 4 is electrically connected to the second electrode pattern 12 such that the pixel electrode pattern 8 is electrically connected to the first electrode protection pattern 3 or the second electrode protection pattern 4, corresponding to the first electrode pattern 11 or the second electrode pattern 12 is electrically connected to prevent the pixel electrode pattern 8 from being in contact with the first electrode pattern 11 or the second electrode pattern 12 when Cu diffusion or oxidation on the first electrode pattern 11 or the second electrode pattern 12 is prevented.
  • the problem of electrical connection which in turn increases the yield of the product.
  • the above-described gate pattern 7 and the pixel electrode pattern 8 are made of the same material and formed by the same patterning process, and the process is simplified with respect to the separate formation of the gate pattern 7 and the pixel electrode pattern 8.
  • the first electrode pattern 11 and the second electrode pattern 12 may be a source pattern and a drain pattern, that is, when the first electrode pattern 11 represents a source pattern, then the second The electrode pattern 12 represents a drain pattern.
  • the first electrode protection pattern 3 covering the first electrode pattern 11 is electrically connected to the source pattern
  • the second electrode protection pattern 4 covering the second electrode pattern 12 is equivalent to Electrically connected to the drain pattern
  • the pixel electrode pattern 8 is electrically connected to the second electrode protection pattern 4 electrically connected to the drain pattern.
  • the second electrode pattern 12 represents a source.
  • the pixel electrode pattern 8 is electrically connected to the first electrode protection pattern 3 electrically connected to the drain pattern. It should be understood that in FIG. 1 of the embodiment of the present invention, the first electrode pattern 11 represents the source pattern, and the second electrode pattern 12 represents the drain pattern for illustration.
  • the electrode material layer 1, the buffer material layer 2, and the electrode may each be formed by vacuum deposition or magnetron sputtering.
  • the first electrode pattern, the second electrode pattern, the first buffer layer pattern, the second buffer layer pattern, the first electrode protection pattern, the second electrode protection pattern, the gate insulating layer pattern, the gate pattern, and the pixel electrode pattern may all pass The etched patterning process is formed, and embodiments of the present invention will not be described in detail.
  • the electrode material layer 1 can be understood as a layer including the pixel electrode pattern 8 or the pre-formed pixel electrode pattern 8
  • the buffer material layer 2 can be understood to include the first buffer layer pattern 21 and the second buffer layer pattern 22 Or a layer of the first buffer layer pattern 21 and the second buffer layer pattern 22 is pre-formed.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display device in the embodiment of the present invention may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板及其制备方法、显示装置，阵列基板包括：衬底基板（9），设置在衬底基板上的第一电极图案（11）、第二电极图案（12）和有源层图案（5），包覆第一电极图案的第一电极保护图案（3），以及包覆第二电极图案的第二电极保护图案（4）；其中，有源层图案设置在第一电极图案和第二电极图案之间；第一电极保护图案和第二电极保护图案分别与有源层图案的两侧连接。避免了由于第一电极图案和第二电极图案采用低电阻特性的材料时，因其表面氧化导致有源层图案无法与第一电极图案和第二电极图案连接的问题，提高了产品的良率。

Description

一种阵列基板及其制备方法、显示装置
本申请要求2015年6月4日递交的中国专利申请第201510303435.8号的优先权，在此全文引用上述中国专利申请所公开的内容以作为本申请的一部分。
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
近年来，显示技术得到了快速的发展，在以液晶显示器(Liquid Crystal Display，简称LCD)为代表的显示技术领域中，由于分辨率的提高和显示尺寸的增大、以及显示装置中驱动器电路的集成需要低电阻的布线，因此，具有低电阻特性的金属例如铜(Cu)已经应用于制作显示装置中的的栅线、数据线、以及薄膜晶体管(Thin Film Transistor，简称TFT)的栅极、源极和漏极。
然而由于具有低电阻特性的金属例如铜或铜合金的活性比较强，在刻蚀形成连接源极和漏极的有源层时，该金属表面容易发生氧化，并且氧化层的厚度随着时间的增加而不断增加，这样造成源极和漏极的接触电阻增加，从而导致有源层图案与源极图案和漏极图案连接电阻过高，进而影响产品的良率。
发明内容
本发明的实施例提供了一种阵列基板及其制备方法、显示装置，避免了由于第一电极图案和第二电极图案采用低电阻特性的材料时，因其表面氧化导致有源层图案与第一电极图案和第二电极图案连接电阻过高的问题。
根据本发明的第一方面，提供一种阵列基板，包括：衬底基板，设置 在衬底基板上的第一电极图案、第二电极图案和有源层图案，包覆第一电极图案的第一电极保护图案，以及包覆第二电极图案的第二电极保护图案；其中，有源层图案设置在第一电极图案和第二电极图案之间；第一电极保护图案和第二电极保护图案分别与有源层图案的两侧连接。
在本发明的实施例中，第一电极图案和第二电极图案的材质为铜或铜合金。
在本发明的实施例中，第一电极图案除与衬底基板接触的下表面外都被第一电极保护图案所覆盖，且第一电极保护图案向有源层图案延伸出第一延伸部，第一延伸部被有源层图案的第一侧覆盖；
第二电极图案除与衬底基板接触的下表面外都被第二电极保护图案所覆盖，且第二电极保护图案向有源层图案延伸出第二延伸部，第二延伸部被有源层图案的第二侧覆盖。
在本发明的实施例中，阵列基板还包括：设置在第一电极图案和第一电极保护图案之间的第一缓冲层图案，和设置在第二电极图案和第二电极保护图案之间的第二缓冲层图案。
在本发明的实施例中，第一电极保护图案、第二电极保护图案、第一缓冲层图案和/或第二缓冲层图案的材质为钼铌合金或钛。
在本发明的实施例中，阵列基板还包括：设置在第一电极保护图案、第二电极保护图案和有源层图案上方的栅绝缘层图案，以及设置在栅绝缘层图案上方的栅极图案和像素电极图案；
栅绝缘层图案包括过孔，过孔被配置为使像素电极图案与第一电极保护图案或第二电极保护图案电连接。
根据本发明的第二方面，还提供了一种阵列基板的制备方法，包括：形成衬底基板；在衬底基板上形成第一电极图案和第二电极图案；形成包覆第一电极图案的第一电极保护图案和包覆第二电极图案的第二电极保护图案；在第一电极保护图案和第二电极保护图案之间形成有源层图案；其中，第一电极保护图案和第二电极保护图案分别与有源层图案的两侧连接。
在本发明的实施例中，在衬底基板上形成第一电极图案和第二电极图 案时，还形成覆盖在第一电极图案表面上的第一缓冲层图案和覆盖在第二电极图案表面上的第二缓冲层图案；其中，第一电极保护图案包覆第一缓冲层图案以及第一电极图案，第二电极保护图案包覆第二缓冲层图案以及第二电极图案。
在本发明的实施例中，在衬底基板上形成第一电极图案和第二电极图案时，还形成覆盖在所述第一电极图案表面上的第一缓冲层图案和覆盖在所述第二电极图案表面上的第二缓冲层图案包括：
在衬底基板上形成电极材料层；在形成电极材料层之后，形成缓冲材料层；通过一次构图工艺形成第一电极图案、第二电极图案以及第一缓冲层图案和第二缓冲层图案。
在本发明的实施例中，方法还包括：在第一电极保护图案、第二电极保护图案、有源层图案上形成包括过孔的栅绝缘层图案；在栅绝缘层图案上通过同一次构图工艺形成栅极图案和像素电极图案；其中，像素电极图案通过过孔与第一电极保护图案或第二电极保护图案电连接。
在本发明的实施例中，第一电极保护图案、第二电极保护图案、第一缓冲层图案和/或第二缓冲层图案的材质为钼铌合金或钛。
在本发明的实施例中，第一电极图案和第二电极图案的材质为铜或铜合金。
根据本发明的第三方面，还提供了一种显示装置，包括上述的阵列基板。
由上述技术方案可知，本发明的实施例提供的一种阵列基板及其制备方法、显示装置，通过在采用低电阻特性的材料制成的第一电极图案和第二电极图案上形成包覆第一电极图案的第一电极保护图案，以及包覆第二电极图案的第二电极保护图案，在第一电极保护图案和第二电极保护图案之间形成有源层图案，避免了由于第一电极图案和第二电极图案采用低电阻特性的材料时，因其表面氧化导致有源层图案与第一电极图案和第二电极图案连接电阻过高的问题，提高了产品的良率。
附图说明
为了更清楚地说明本发明的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本发明的一些实施例，而非对本发明的限制，其中：
图1为根据本发明的实施例提供的阵列基板的结构示意图；
图2为图1所示的阵列基板的制备方法的流程示意图；
图3为制备本发明的实施例提供的阵列基板时完成第一步后的结构示意图；
图4为制备本发明的实施例提供的阵列基板时完成第二步后的结构示意图；
图5为制备本发明的实施例提供的阵列基板时完成第三步后的结构示意图；
图6为制备本发明的实施例提供的阵列基板时完成第四步后的结构示意图；
图7为制备本发明的实施例提供的阵列基板时完成第五步后的结构示意图；
元件列表：
1、电极材料层；2、缓冲材料层；3、第一电极保护图案；4、第二电极保护图案；5、有源层图案；6、栅绝缘层图案；7、栅极图案；8、像素电极图案；9、衬底基板；11、第一电极图案；12、第二电极图案；21、第一缓冲层图案；22、第二缓冲层图案；31、第一延伸部；41、第二延伸部。
具体实施方式
下面结合附图，对发明的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。
图1为根据本发明的实施例提供的阵列基板的结构示意图。如图1所示，本发明的实施例提供了一种阵列基板，该阵列基板包括衬底基板9、 设置在衬底基板9上的第一电极图案11、第二电极图案12和有源层图案5，包覆第一电极图案11的第一电极保护图案3，以及包覆第二电极图案12的第二电极保护图案4；其中，有源层图案5设置在第一电极图案11和第二电极图案12之间；第一电极保护图案3和第二电极保护图案4分别与有源层图案5的两侧连接。
阵列基板通过在采用低电阻特性的材料制成的第一电极图案11和第二电极图案12上形成包覆第一电极图案11的第一电极保护图案3，以及包覆第二电极图案12的第二电极保护图案4，在第一电极保护图案3和第二电极保护图案4之间形成有源层图案5，避免了第一电极图案11和第二电极图案12采用低电阻特性的材料时，因其表面氧化导致有源层图案5与第一电极图案11和第二电极图案12连接电阻过高的问题，提高了产品的良率。
第一电极图案11和第二电极图案12的材质为低电阻特性且活性较强的材质，例如铜或铜合金，本发明的实施例均以铜进行举例说明。有源层图案5的材质可以采用铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)、铟锡锌氧化物(Indium Tin Zinc Oxide，简称ITZO)、氧化铟(In2O3)、以及氧化锌(ZnO)等透明金属氧化物半导体材料中的至少一种。
第一电极图案11除与衬底基板9接触的下表面外都被第一电极保护图案3所覆盖，且第一电极保护图案3向有源层图案5延伸出第一延伸部31，第一延伸部31被有源层图案5的第一侧覆盖；第二电极图案12除与衬底基板9接触的下表面外都被第二电极保护图案4所覆盖，且第二电极保护图案4向有源层图案5延伸出第二延伸部41，第二延伸部41被有源层图案5的第二侧覆盖。
为了防止在形成包覆第一电极图案11的第一电极保护图案3，和形成包覆第二电极图案12的第二电极保护图案4时，导致第一电极图案11和第二电极图案12的Cu被氧化，故上述阵列基板还包括：设置在第一电极图案11和第一电极保护图案3之间的第一缓冲层图案21，和设置在第二电极图案12和第二电极保护图案4之间的第二缓冲层图案22。该第一缓 冲层图案21和第二缓冲层图案22分别覆盖在第一电极图案11和第二电极图案12的上方，有效的防止了在形成第一电极保护图案3和第二电极保护图案4时，第一电极图案11和第二电极图案12表面的Cu被氧化。
可理解的是，上述第一电极保护图案3、第二电极保护图案4、第一缓冲层图案21和/或第二缓冲层图案22的材质为防止Cu氧化以及Cu扩散的材质，例如：钼铌合金(MoNb)或钛(Ti)。
阵列基板还包括：设置在第一电极保护图案3、第二电极保护图案4和有源层图案5上方的栅绝缘层图案6，以及设置在栅绝缘层图案6上方的栅极图案7和像素电极图案8。栅绝缘层图案6包括过孔，该过孔用于使像素电极图案8与第一电极保护图案3或第二电极保护图案4电连接。
在本发明的实施例中，上述的第一电极图案11和第二电极图案12可以为源极图案和漏极图案，也就是说，在第一电极图案11代表源极图案时，则第二电极图案12代表漏极图案，相应的，包覆第一电极图案11的第一电极保护图案3相当于与源极图案电连接，以及包覆第二电极图案12的第二电极保护图案4相当于与漏极图案电连接，像素电极图案8则与与漏极图案电连接的第二电极保护图案4电连接，相反的，若第一电极图案11代表漏极图案，第二电极图案12代表源极图案时，则像素电极图案8则与与漏极图案电连接的第一电极保护图案3电连接；应当理解的是，本发明的实施例的附图7中是以第一电极图案11代表源极图案，第二电极图案12代表漏极图案进行举例说明的。
图2为图1所示的阵列基板的制备方法的流程示意图。如图2所示，本发明实施例还提供了一种阵列基板的制备方法，在形成衬底基板9后，该方法还包括以下步骤：
步骤101、在衬底基板9上形成第一电极图案11和第二电极图案12；
步骤102、形成包覆第一电极图案11的第一电极保护图案3和包覆第二电极图案12的第二电极保护图案4；
步骤103、在第一电极保护图案3和第二电极保护图案4之间形成有源层图案5；其中，第一电极保护图案和第二电极保护图案分别与有源层 图案的两侧连接。
上述方法通过先采用低电阻特性的材料制成的第一电极图案11和第二电极图案12，然后分别在第一电极图案11和第二电极图案12上形成包覆第一电极图案11的第一电极保护图案3，以及包覆第二电极图案12的第二电极保护图案4，通过第一电极保护图案3以及第二电极保护图案4有效防止了第一电极图案11和第二电极图案12的Cu扩散；在第一电极保护图案3和第二电极保护图案4之间形成有源层图案5相对于直接在第一电极图案11和第二电极图案12之间形成有源层图案5，有效避免了刻蚀有源层图案5的过程中导致Cu氧化，进而避免了有源层图案5与第一电极图案11和第二电极图案12之间电阻过高的问题。
图3为制备本发明的实施例提供的阵列基板时完成第一步后的结构示意图。图4为制备本发明的实施例提供的阵列基板时完成第二步后的结构示意图。图5为制备本发明的实施例提供的阵列基板时完成第三步后的结构示意图。图6为制备本发明的实施例提供的阵列基板时完成第四步后的结构示意图。图7为制备本发明的实施例提供的阵列基板时完成第五步后的结构示意图。
下面对上述阵列基板的制备方法的流程进行详细说明，该阵列基板的制备方法的流程可以包括以下步骤：
步骤201、在衬底基板9上形成电极材料层1，在形成电极材料层1之后，形成缓冲材料层2，如图3所示。
举例来说，上述的衬底基板9可以为玻璃基板、石英基板或有机树脂基板。电极材料层1材质为低电阻特性且活性较强的材质，例如铜或铜合金，本发明的实施例均以Cu进行举例说明。第一缓冲层图案21和第二缓冲层图案22的材质为防止Cu氧化以及Cu扩散的材质，例如：钼铌合金(MoNb)或钛(Ti)等。
步骤202、通过一次构图工艺形成第一电极图案11、第二电极图案12以及覆盖在第一电极图案11表面上的第一缓冲层图案21和覆盖在第二电极图案12表面上的第二缓冲层图案22，如图4所示。
步骤203、形成包覆第一缓冲层图案21和第一电极图案11的第一电极保护图案3，以及形成包覆第二缓冲层图案22和第二电极图案12的第二电极保护图案4。
如图5所示，上述第一电极保护图案3包覆除与衬底基板9贴覆部分的第一电极图案11，且第一电极保护图案3的两端包括设置在衬底基板9上的第一延伸部31。第二电极保护图案4包覆除与衬底基板9贴覆部分的第二电极图案12，且第二电极图案12的两端包括设置在衬底基板9上的第二延伸部41。第一电极保护图案3的第一延伸部31与第二电极保护图案4的第二延伸部41分别与有源层图案5的两侧连接。
上述步骤103中形成第一电极保护图案3和第二电极保护图案4可以理解为在第一电极图案11、第一缓冲层图案21、第二电极图案12、第二缓冲层图案22上沉积电极保护材料层，然后通过刻蚀的构图工艺形成第一电极保护图案3和第二电极保护图案4。该实施方式仅用于举例说明，本发明的实施例不对其具体的实施方式进行限定。
上述第一电极保护图案3和第二电极保护图案4的材质为防止Cu氧化以及Cu扩散的材质，例如：钼铌合金(MoNb)或钛(Ti)等。
在上述步骤201至步骤203中，采用低电阻特性的电极材料层1可以制造出分辨率更高、性能更好，且尺寸较大的阵列基板。在电极材料层上形成缓冲材料层2，可以有效的防止电极材料层的Cu扩散，以及在后续刻蚀形成第一电极保护图案3和第二电极保护图案4的过程中，防止大面积的Cu被氧化。通过一次构图工艺形成第一电极图案11、第二电极图案12以及覆盖在第一电极图案表面上的第一缓冲层图案21和覆盖在第二电极图案表面上的第二缓冲层图案22，在简化形成第一电极图案11和第二电极图案12的工艺的同时还有效的防止了第一电极图案11和第二电极图案12的Cu扩散和氧化的问题。
步骤204、在第一电极保护图案3和第二电极保护图案4之间形成分别与第一电极保护图案3和第二电极保护图案4相连的有源层图案5，如图6所示。
步骤205、在第一电极保护图案3、第二电极保护图案4、有源层图案5上沉积栅绝缘层，并对栅绝缘层做图案化处理形成包括过孔的栅绝缘层图案6，如图7所示。
步骤206、在栅绝缘层图案6上沉积透明导电层(例如：ITO)，并对该透明导电层通过同一次构图工艺形成栅极图案7和像素电极图案8，如图1所示。像素电极图案8通过过孔与第一电极保护图案3或第二电极保护图案4电连接。
可以理解的是，采用上述第一电极保护图案3对第一电极图案11进行保护并且第一电极保护图案3与第一电极图案11电连接，以及采用第二电极保护图案4对第二电极图案12进行保护并且第二电极保护图案4与第二电极图案12电连接，从而使像素电极图案8在与第一电极保护图案3或第二电极保护图案4电连接，相当于与第一电极图案11或第二电极图案12电连接，防止了在第一电极图案11或第二电极图案12上的Cu扩散或氧化时，导致像素电极图案8无法与第一电极图案11或第二电极图案12电连接的问题，进而提高了产品的良率。
上述栅极图案7和像素电极图案8的材质相同，且通过同一次构图工艺形成，相对于单独形成栅极图案7和像素电极图案8简化了工艺。
在本发明的实施例中，上述的第一电极图案11和第二电极图案12可以为源极图案和漏极图案，也就是说，在第一电极图案11代表源极图案时，则第二电极图案12代表漏极图案，相应的，包覆第一电极图案11的第一电极保护图案3相当于与源极图案电连接，包覆第二电极图案12的第二电极保护图案4相当于与漏极图案电连接，像素电极图案8则与与漏极图案电连接的第二电极保护图案4电连接，相反的，若第一电极图案11代表漏极图案，第二电极图案12代表源极图案时，则像素电极图案8则与与漏极图案电连接的第一电极保护图案3电连接。应当理解的是，本发明的实施例的附图1中是以第一电极图案11代表源极图案，第二电极图案12代表漏极图案进行举例说明的。
上述步骤201至步骤206中，上述电极材料层1、缓冲材料层2、电极 保护层、栅绝缘层、透明导电层均可以通过真空沉积或磁控溅射的方式形成。上述第一电极图案、第二电极图案、第一缓冲层图案、第二缓冲层图案、第一电极保护图案、第二电极保护图案、栅绝缘层图案、栅极图案和像素电极图案均可以通过刻蚀的构图工艺形成，本发明的实施例不再进行详细说明。
另外，需要说明的是，电极材料层1可以理解为包括像素电极图案8或预形成像素电极图案8的层，缓冲材料层2可以理解为包括第一缓冲层图案21和第二缓冲层图案22或预形成第一缓冲层图案21和第二缓冲层图案22的层。
本发明的实施例还提供了一种显示装置，包括如上述的阵列基板。
本发明的实施例中的显示装置可以为：手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进 行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围，其均应涵盖在本发明的权利要求和说明书的范围当中。

Claims (13)

  1. 一种阵列基板，包括：衬底基板，设置在所述衬底基板上的第一电极图案、第二电极图案和有源层图案，包覆所述第一电极图案的第一电极保护图案，以及包覆所述第二电极图案的第二电极保护图案；其中，有源层图案设置在所述第一电极图案和所述第二电极图案之间；所述第一电极保护图案和所述第二电极保护图案分别与所述有源层图案的两侧连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一电极图案和所述第二电极图案的材质为铜或铜合金。
  3. 根据权利要求1所述的阵列基板，其中，所述第一电极图案除与所述衬底基板接触的下表面外都被所述第一电极保护图案所覆盖，且所述第一电极保护图案向所述有源层图案延伸出第一延伸部，所述第一延伸部被所述有源层图案的第一侧覆盖；
    所述第二电极图案除与所述衬底基板接触的下表面外都被所述第二电极保护图案所覆盖，且所述第二电极保护图案向所述有源层图案延伸出第二延伸部，所述第二延伸部被所述有源层图案的第二侧覆盖。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：设置在所述第一电极图案和所述第一电极保护图案之间的第一缓冲层图案，和设置在所述第二电极图案和所述第二电极保护图案之间的第二缓冲层图案。
  5. 根据权利要求4所述的阵列基板，其中，所述第一电极保护图案、所述第二电极保护图案、所述第一缓冲层图案和/或所述第二缓冲层图案的材质为钼铌合金或钛。
  6. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：设置在所述第一电极保护图案、第二电极保护图案和有源层图案上方的栅绝缘层图案，以及设置在所述栅绝缘层图案上方的栅极图案和像素电极图案；
    所述栅绝缘层图案包括过孔，所述过孔被配置为使所述像素电极图案与所述第一电极保护图案或所述第二电极保护图案电连接。
  7. 一种阵列基板的制备方法，包括：
    形成衬底基板；
    在衬底基板上形成第一电极图案和第二电极图案；
    形成包覆所述第一电极图案的第一电极保护图案和包覆所述第二电极图案的第二电极保护图案；
    在所述第一电极保护图案和所述第二电极保护图案之间形成有源层图案；
    其中，所述第一电极保护图案和所述第二电极保护图案分别与所述有源层图案的两侧连接。
  8. 根据权利要求7所述的方法，其中，在所述在衬底基板上形成第一电极图案和第二电极图案时，还形成覆盖在所述第一电极图案表面上的第一缓冲层图案和覆盖在所述第二电极图案表面上的第二缓冲层图案；
    其中，所述第一电极保护图案包覆所述第一缓冲层图案以及第一电极图案，所述第二电极保护图案包覆所述第二缓冲层图案以及第二电极图案。
  9. 根据权利要求8所述的方法，其中，在所述在衬底基板上形成第一电极图案和第二电极图案时，还形成覆盖在所述第一电极图案表面上的第一缓冲层图案和覆盖在所述第二电极图案表面上的第二缓冲层图案包括：
    在衬底基板上形成电极材料层；
    在形成所述电极材料层之后，形成缓冲材料层；
    通过一次构图工艺形成所述第一电极图案、所述第二电极图案以及所述第一缓冲层图案和所述第二缓冲层图案。
  10. 根据权利要求8所述的方法，其中，所述方法还包括：
    在所述第一电极保护图案、第二电极保护图案、有源层图案上形成包括过孔的栅绝缘层图案；
    在所述栅绝缘层图案上通过同一次构图工艺形成栅极图案和像素电极图案；
    其中，所述像素电极图案通过所述过孔与所述第一电极保护图案或第二电极保护图案电连接。
  11. 根据权利要求8所述的方法，其中，所述第一电极保护图案、所 述第二电极保护图案、所述第一缓冲层图案和/或所述第二缓冲层图案的材质为钼铌合金或钛。
  12. 根据权利要求7-11其中任一项所述的方法，其中，所述第一电极图案和所述第二电极图案的材质为铜或铜合金。
  13. 一种显示装置，包括如权利要求1-6中任一项所述的阵列基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3614426A4 (en) * 2017-04-20 2020-12-09 Boe Technology Group Co. Ltd. CONDUCTIVE SAMPLE STRUCTURE AND MANUFACTURING PROCESS FOR IT AS WELL AS ARRAY SUBSTRATE AND DISPLAY DEVICE

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104992949B (zh) * 2015-06-04 2018-03-09 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050070055A1 (en) * 2003-09-29 2005-03-31 Masafumi Kunii Thin film transistor and method for production thereof
CN104022076A (zh) * 2014-05-27 2014-09-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104300008A (zh) * 2014-10-30 2015-01-21 京东方科技集团股份有限公司 一种电极结构、薄膜晶体管、阵列基板及显示面板
CN104992949A (zh) * 2015-06-04 2015-10-21 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001223365A (ja) * 2000-02-10 2001-08-17 Fujitsu Ltd 薄膜トランジスタ及びその製造方法
KR100439345B1 (ko) * 2000-10-31 2004-07-07 피티플러스(주) 폴리실리콘 활성층을 포함하는 박막트랜지스터 및 제조 방법
KR20060062913A (ko) * 2004-12-06 2006-06-12 삼성전자주식회사 표시 장치용 배선과 상기 배선을 포함하는 박막트랜지스터 표시판 및 그 제조 방법
US8748892B2 (en) * 2009-10-09 2014-06-10 Lg Display Co., Ltd. Thin film transistor and method for fabricating the same
KR101671952B1 (ko) * 2010-07-23 2016-11-04 삼성디스플레이 주식회사 표시 기판 및 이의 제조 방법
CN202443974U (zh) * 2012-02-29 2012-09-19 北京京东方光电科技有限公司 一种阵列基板及应用其的显示装置
JP2014143410A (ja) * 2012-12-28 2014-08-07 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
CN203423181U (zh) * 2013-08-23 2014-02-05 华映视讯（吴江）有限公司 氧化物半导体薄膜晶体管基板
KR102248645B1 (ko) * 2013-12-02 2021-05-04 엘지디스플레이 주식회사 금속 산화물 반도체를 포함하는 박막 트랜지스터 기판 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050070055A1 (en) * 2003-09-29 2005-03-31 Masafumi Kunii Thin film transistor and method for production thereof
CN104022076A (zh) * 2014-05-27 2014-09-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104300008A (zh) * 2014-10-30 2015-01-21 京东方科技集团股份有限公司 一种电极结构、薄膜晶体管、阵列基板及显示面板
CN104992949A (zh) * 2015-06-04 2015-10-21 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3614426A4 (en) * 2017-04-20 2020-12-09 Boe Technology Group Co. Ltd. CONDUCTIVE SAMPLE STRUCTURE AND MANUFACTURING PROCESS FOR IT AS WELL AS ARRAY SUBSTRATE AND DISPLAY DEVICE

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