WO2016188009A1 - 用于驱动显示面板的驱动芯片、显示装置及驱动控制方法 - Google Patents
用于驱动显示面板的驱动芯片、显示装置及驱动控制方法 Download PDFInfo
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- WO2016188009A1 WO2016188009A1 PCT/CN2015/091542 CN2015091542W WO2016188009A1 WO 2016188009 A1 WO2016188009 A1 WO 2016188009A1 CN 2015091542 W CN2015091542 W CN 2015091542W WO 2016188009 A1 WO2016188009 A1 WO 2016188009A1
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- 230000005540 biological transmission Effects 0.000 claims abstract description 141
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- 238000004519 manufacturing process Methods 0.000 description 3
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
- G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
Definitions
- the present disclosure relates to driving of a display panel, and more particularly to a driving chip, a display device, and a driving control method for driving a display panel.
- TFT Thin film transistor
- LCD thin film transistor
- CPU central processing unit
- display panels such as a liquid crystal display panel, a light emitting diode (LED) display panel, and an organic light emitting diode (OLED) display panel; the above display panels all need to be driven by a gate.
- the chip and the data driving chip input a gate driving signal and a data driving signal to the display panel to drive the display panel for display.
- a plurality of driving chips are generally disposed in the non-display area of the display panel, and each of the driving chips corresponds to a plurality of signal transmission lines located in the display area.
- the signal transmission line is a data line or a gate line
- the plurality of driving chips are used to provide a data driving signal to the data line or a gate driving signal to the gate line.
- An object of the embodiments of the present disclosure is to provide a driving chip, a display device, and a driving control method for driving a display panel to reduce power consumption of the driving chip.
- an embodiment of the present disclosure discloses a driving chip for driving a display panel
- the driving chip has N pins, and the N is an integer greater than or equal to 2, and the N tubes
- the foot corresponds to N signal transmission lines disposed on the display panel, and the pin is connected to the corresponding signal transmission line through a transmission line, and the N pins include a first pin and a second pin.
- the transmission wiring includes a first transmission line connected to the first pin and a second transmission line connected to the second pin, the length of the first transmission line being greater than The length of the second transmission wiring
- the driving chip includes:
- a signal generating module configured to generate N driving signals, each driving signal corresponding to one of the pins;
- the N driving signals include: a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin, wherein a current intensity of the first driving signal is greater than a second driving The current strength of the signal.
- the driving chip is a data driving chip or a gate driving chip.
- the signal generating module specifically includes:
- a first signal generating unit configured to generate N initial signals
- a signal adjustment unit configured to adjust a current intensity of the initial signal according to a length of a transmission line to which the pin corresponding to the initial signal is connected, to obtain N driving signals;
- the driving signal has the same voltage value as the corresponding initial signal.
- the signal adjustment unit specifically includes:
- control unit configured to determine a bias current of the plurality of voltage follower units according to a length of the transmission wiring to which the pin corresponding to the initial signal is connected;
- the control unit outputs a first bias current for a voltage follower unit corresponding to the first pin and a second bias current for a voltage follower unit corresponding to the second pin, the current of the first bias current The intensity is greater than the current intensity of the second bias current.
- each of the voltage follower units is an operational amplifier connected to an inverting input.
- control unit is implemented by a timing control unit.
- the N pins are divided into M pin groups, and M is an integer greater than or equal to 2.
- Each pin belongs to and belongs to only one group; the control unit is the same The pins in one pin group output the same bias current; for any two of the M pin groups corresponding to the average length of different transmission wirings, one of the pin groups corresponds to the transmission wiring
- the maximum value of the length is smaller than the minimum value of the length of the transmission wiring corresponding to the other pin group, and the current intensity of the bias current output by the control unit to the pin group corresponding to the average length of the larger transmission wiring is greater than The current of the bias current output to the pin group corresponding to the average length of the smaller transmission wiring is strong.
- the current intensity of the driving signal corresponding to the pin connecting the longer transmission wires is greater than the connection.
- the current intensity of the drive signal corresponding to the pin of the short transmission wiring is greater than the connection.
- the pins of the different length transmission wires are connected, and the control unit outputs a voltage corresponding to the pin connecting the longer transmission wires.
- the current intensity of the bias current of the unit is greater than the current intensity of the bias current of the voltage follower unit corresponding to the pin connected to the shorter transmission wiring.
- the N signal transmission lines are spaced apart along the first direction, and the length of the transmission wiring connecting the N signal transmission lines is gradually decreased along the first direction and then gradually increased. Big.
- An embodiment of the present disclosure also provides a display device including the above-described driving chip.
- An embodiment of the present disclosure further provides a driving control method for driving a driving chip of a display panel
- the driving chip has N pins, and the N is an integer greater than or equal to 2, and the N tubes
- the foot corresponds to N signal transmission lines disposed on the display panel, and the pin is connected to the corresponding signal transmission line through a transmission line, and the N pins include a first pin and a second pin.
- the transmission wiring includes a first transmission line connected to the first pin and a second transmission line connected to the second pin, the length of the first transmission line being greater than The length of the second transmission wiring
- the driving control method includes:
- the N driving signals include: a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin, wherein a current intensity of the first driving signal is greater than a second driving Letter The current intensity of the number.
- the driving chip is a data driving chip or a gate driving chip.
- the generating the N driving signals specifically includes:
- the driving signal has the same voltage value as the corresponding initial signal.
- the step of adjusting a current intensity of the initial signal according to a length of a transmission line to which a pin corresponding to the initial signal is connected includes:
- the current intensity of the bias current corresponding to the first pin is greater than the current intensity of the bias current corresponding to the second pin.
- the step of determining a bias current corresponding to the pin according to a length of a transmission line to which the pin corresponding to the initial signal is connected includes:
- determining a bias current corresponding to the any one of the pin groups according to a maximum value of a length of the transmission wiring corresponding to the any one of the pin groups, and The determined bias current is supplied to all of the pins in any one of the pin groups;
- the output to each of the pin groups corresponding to the average length of the larger transmission wiring is The current intensity of the current is greater than the current intensity of the bias current output to each of the pin groups corresponding to the average length of the smaller transmission wiring.
- the current intensity of the driving signal corresponding to the pin connecting the longer transmission wires is greater than the connection.
- the current intensity of the drive signal corresponding to the pin of the short transmission wiring is greater than the connection.
- the driving capability of different driving signals is adaptively set according to driving requirements corresponding to different driving signals, instead of setting all driving signals to meet the maximum driving demand, and satisfying different driving signals.
- the corresponding drive requirements reduce the power consumption of the product.
- FIG. 1 is a schematic diagram of a transmission wiring connecting a driving chip and a corresponding signal transmission line in the related art
- FIG. 2 is a schematic structural diagram of a driving chip for driving a display panel according to an embodiment of the present disclosure
- FIG. 3 is a schematic structural diagram of a signal generating module according to an embodiment of the present disclosure.
- FIG. 4 is a schematic structural diagram of a first signal generating unit of a gate driving chip according to an embodiment of the present disclosure
- FIG. 5 is a schematic structural diagram of a first signal generating unit of a data driving chip according to an embodiment of the present disclosure
- FIG. 6 is a schematic structural diagram of a signal adjustment unit according to an embodiment of the present disclosure.
- FIG. 7 is a schematic structural diagram of a signal adjusting unit according to an embodiment of the present disclosure
- FIG. 8 is a schematic diagram of a driving control method according to an embodiment of the present disclosure.
- FIG. 1 is a schematic diagram of a transmission wiring connecting a driving chip and a corresponding signal transmission line in the related art.
- a fan-out area 102 is disposed between the driving chip 101 and the corresponding signal transmission line 105.
- the fan-out area 102 is provided with a plurality of extending from the output pin 103 of the driving circuit to the display panel display area.
- the wiring 104 is transmitted to connect the output pin 103 of the drive circuit and the corresponding signal transmission line 105.
- the signal transmission line is a gate line or a data line; correspondingly, the transmission line 104 transmits a gate driving signal or a data driving signal to the signal transmission line.
- the length of the transmission wiring 104 is not completely the same.
- the load of the data driving signal includes a portion located in the display area and a transmission wiring located in the non-display area.
- the portion of the load corresponding to the data driving signal supplied to the different signal transmission lines in the display area is basically the same, but the transmission wiring for transmitting the data driving signal, as shown in FIG. 1, has a great difference in length. . This difference in length will result in no The same load.
- the driving capability of all the driving signals to be transmitted to the signal transmission line 105 generated by the driving chip 101 is the same, that is, the current intensities of all the driving signals are the same; and the loads corresponding to the driving signals are different, and the driving signals correspond to There are also differences in drive requirements.
- all driving signals generated by the driving chip 101 need to meet the maximum driving demand. Obviously, designing all drive signals based on maximum drive requirements can result in wasted power.
- the driving capability of different driving signals is set according to the driving requirements corresponding to different driving signals, instead of setting all driving signals to meet the maximum driving requirement, and satisfying different driving signals.
- the corresponding drive requirements reduce the power consumption of the product.
- the driving chip has N pins 103, N is an integer greater than or equal to 2, and the N tubes
- the legs 103 correspond to N signal transmission lines disposed in the display area of the display panel, and the pins 103 and the corresponding signal transmission lines are connected by a transmission line 104, wherein the N pins include a first pin and a second pin, the transmission line 104 includes a first transmission line connected to the first pin and a second transmission line connected to the second pin, the first transmission The length of the wiring is greater than the length of the second transmission wiring, and the driving chip further includes:
- a signal generating module 201 configured to generate N driving signals, each driving signal corresponding to one of the pins;
- the N driving signals include: a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin, wherein a current intensity of the first driving signal is greater than a second driving The current strength of the signal.
- the signal transmission line may be a gate line or a data line
- the driving chip provided by the embodiment of the present disclosure may be applied to provide gate driving to the gate line.
- One of the signal driving chip of the signal and the data driving chip for providing the data driving signal to the data line can also be applied to both the data driving chip and the gate driving chip, which will be described in detail later.
- Different data lines or gate lines have the same characteristics except for the location, such as fabrication process, materials, connected devices, characteristics of connected devices, and the like. So if you only consider the load level of the drive signal In the portion of the display area, different data lines or gate lines have the same driving capability requirements.
- the driving capability of the signal needs to consider not only the portion of the load located in the display area but also the transmission wiring outside the display area and connecting the pins of the driving chip and the signal transmission line.
- the driving capability of different driving signals is adaptively set according to driving requirements corresponding to different driving signals, instead of setting all driving signals to meet the maximum driving demand, and satisfying different driving signals.
- the corresponding drive requirements reduce the power consumption of the product.
- the driver chip has nine pins 103 corresponding to the nine transmission wirings 104, and the length of the intermediate transmission wiring 104 is the shortest, so that the driving signal transmitted by the transmission wiring 104 is driven.
- the ability requirements are the lowest.
- the two transmission wirings 104 on the leftmost and rightmost sides are much longer than the length of the transmission wiring 104 located in the middle, and therefore the driving capability of the driving signals transmitted by the two transmission wirings 104 is the highest.
- the driving capability of the driving signal is located in the display area, and the driving capability of the driving signal is: current intensity X, and the driving capability of the longest transmission wiring to the driving signal is: current intensity is Y, transmission wiring per unit length
- the driving ability of the driving signal is required to be: current intensity Z, and the length difference between the shortest transmission wiring and the longest transmission wiring is A unit length.
- the current intensity of all the driving signals can be set to ensure that the driving signals transmitted by all the transmission lines can meet the corresponding driving capability requirements.
- the current intensity of the driving signal transmitted by the shortest transmission wiring is less than X+Y, as may be set to X+Y-AZ. Therefore, embodiments of the present disclosure can reduce the power consumption of a product while satisfying the driving requirements corresponding to different driving signals.
- the driving chip of the specific embodiment of the present disclosure can use the signal generating module described above to generate driving signals with different driving capabilities as long as the following two characteristics are satisfied, so as to reduce power consumption:
- connection wiring between the plurality of pins and the corresponding signal transmission line is different.
- the driving chip of the embodiment of the present disclosure can be applied to a data driving chip in a liquid crystal display panel, or can be applied to a gate driving chip in a liquid crystal display panel, or can be applied to a data driving chip in an OLED display panel, or Used in scanning driver chips in OLED display panels, etc.
- it can also be used for the data driving chip and the gate driving chip in the liquid crystal display panel or the data driving chip and the scanning driving chip in the OLED display panel at the same time, which are not illustrated here.
- the foregoing signal generating module may be implemented in various manners, and a simple implementation manner of the present invention is as follows.
- the signal generating module specifically includes:
- a first signal generating unit configured to generate N initial signals
- a signal adjustment unit configured to adjust a current intensity of the initial signal according to a length of a transmission line to which the pin corresponding to the initial signal is connected, to obtain N driving signals;
- the driving signal has the same voltage value as the corresponding initial signal.
- the first signal generating unit corresponding to different driving chips is different, and the gate driving chip and the data driving chip for the liquid crystal display panel are respectively described below.
- the function is to determine whether the scanning line is turned on or off.
- the first signal generating unit is as shown in FIG. 4, and includes: a shift register, a potential shifter, and Digital to analog converter (DAC).
- the shift register transfers the logic state of the input stage to the output stage. Therefore, as long as the start time of the frame time, the synchronous signal scanned in the vertical direction is sent to the first-stage shift register according to the charging time required by the pixel electrode, and the shift register of each level is controlled by the clock signal in the vertical direction.
- the time of the output state can be sequentially outputted to turn on or off the logic state of the corresponding scan line;
- Each stage of the shift register can be designed to scan from top to bottom and from bottom right to top, and the power supply voltage is generally 3V or 5V.
- the potential shifter functions to transfer a low logic voltage of 3V/0V or 5V/0V to a high-open voltage of 20V or more and a low-off voltage of -5V or less required for switching thin film transistors (TFTs). At this point, N initial signals for driving the scan lines are obtained.
- the driving chip When the driving chip is applied to the data driving chip, it is used to generate a control voltage required for displaying the image. Therefore, the first signal generating unit of the data driving chip is different from the first signal generating unit of the scan driving chip, and the basic The workflow is as follows: by the control of the shift register, the horizontal clock and the horizontal direction scan the synchronization signal to control the operation time, and the first group of data registers realized by the lock mode are turned on one by one, and the n-th Number of digitized videos to be displayed on pixels on one scan line Stored in order;
- the next synchronization signal is scanned in the horizontal direction, and the data is simultaneously transferred to the second group.
- the data register In the data register;
- DAC digital-to-analog converter
- the first signal generating unit is as shown in FIG. 5, and includes:
- the shift register is the same as the shift register in the scan driver circuit, but the frequency of operation is much faster;
- the data register which stores the digital data, is memorized by using a latch formed by the interconnection of the two inverter outputs and the input end;
- a potential shifter that boosts the low potential of the data register output, such as boosting 0V-5V to 0V-14V;
- a digital-to-analog converter converts the digital signal data into an analog voltage that drives the pixel electrode.
- the first signal generating unit determines the voltage of the finally output driving signal, and the voltage is unchangeable.
- the signal adjusting unit specifically includes:
- control unit configured to determine a bias current of the plurality of voltage follower units according to a length of the transmission wiring to which the pin corresponding to the initial signal is connected;
- the control unit outputs a first bias current of the voltage following unit corresponding to the first pin and a second bias current of the voltage following unit corresponding to the second pin, and the current intensity of the first bias current is greater than the second The current strength of the bias current.
- the initial signal is the same as the voltage value of the corresponding driving signal; under the action of the bias current, the current intensity of the initial signal is adjusted to obtain a corresponding driving signal number.
- the voltage follower unit is implemented by an operational amplifier connected to the output terminal and the inverting input terminal.
- the above control unit can be implemented by using a separate control chip, but in view of the convenience and cost of implementation, in the specific embodiment of the present disclosure, the above control unit is implemented by a timing controller (TCON).
- TCON timing controller
- the plurality of voltage following units are in one-to-one correspondence with the N pins, that is, N voltage following units may be disposed, and current output minimization control is performed on signals output by each of the pins to achieve work.
- N voltage following units may be disposed, and current output minimization control is performed on signals output by each of the pins to achieve work.
- the least expensive effect can correspond to a plurality of pins.
- group management is performed.
- the N pins are divided into M pin groups, M is an integer greater than or equal to 2, each pin belongs to and belongs to only one group; the control unit is the same pin group The pin in the middle outputs the same minimum bias current that satisfies the demand; for any two of the M pin sets corresponding to the average length of different transmission wires, one of the pin groups corresponds to the transmission wiring The maximum value of the length is smaller than the minimum value of the length of the transmission wiring corresponding to the other pin group, and the control unit corresponds to the offset of each pin output in the pin group of the average length of the larger transmission wiring The current intensity of the current is greater than the current intensity of the bias current output to each of the pin groups corresponding to the average length of the smaller transmission wiring.
- the data driving chip and the gate driving chip are respectively described below as follows.
- the gate driving chip has N1+N2+N3+N4+N5 pins, and each pin passes through one transmission.
- the pins are sorted according to the length of the corresponding transmission line from small to large, and are numbered as the first pin, the second pin, the N1 pin...N1+N2 Pins...N1+N2+N3 pins...N1+N2+N3+N4 pins...N1+N2+N3+N4+N5 pins, and the above N1+N2+ N3+N4+N5 pins are divided into 5 groups, and the corresponding pin combinations are:
- the maximum value among the lengths of the transmission wirings corresponding to one of the pin combinations is smaller than the minimum of the lengths of the transmission wirings corresponding to the other of the other pin combinations.
- control unit outputs the same bias current for the pins in the same pin group.
- the other features of the different gate lines except the position are the same, such as the fabrication process, the materials, the connected devices, the characteristics of the connected devices, and the like. Therefore, if only the load of the driving signal is considered to be located in the portion of the display area, the requirements of the different gate lines for the driving capability are the same. On the other hand, if the transmission wiring is taken into consideration, the drive signal output from the longest pin of the corresponding transmission wiring has the highest driving capability.
- the minimum bias current that satisfies the corresponding requirement of the gate line is set based on the longest pin of the corresponding transmission line in the pin combination.
- the bias current output by the control unit is larger for the pin combination in which the average length of the corresponding transmission wiring is larger.
- the above is only a description of dividing the pins into five groups.
- the above-mentioned packets may be more, and the more packets, the more significant the power consumption is reduced.
- the data driving chip has M1+M2+M3+M4 pins, and each pin is connected to the data line through a transmission wiring. Then, according to the length of the corresponding transmission wiring, the pins are sorted and numbered as the first pin, the second pin, the M1 pin, the M1+M2 pins, etc. M1+M2+M3 pins... The M1+M2+M3+M4 pins, and the above M1+M2+M3+M4 pins are divided into 4 groups, and the corresponding pin combinations are:
- Combination 4 M1+M2+M3+1, M1+M2+M3+2, ..., M1+M2+M3+M4;
- the maximum value among the lengths of the transmission wirings corresponding to one of the pin combinations is smaller than the minimum of the lengths of the transmission wirings corresponding to the other of the other pin combinations.
- control unit outputs the same bias current for the pins in the same pin group.
- the other data lines have the same characteristics except for the position, such as the manufacturing process, the materials, the connected devices, the characteristics of the connected devices, and the like. Therefore, if only the load of the drive signal is considered to be located in the display area, the requirements of the different data lines for the drive capability are the same. On the other hand, if the transmission wiring is taken into consideration, the drive signal output from the longest pin of the corresponding transmission wiring has the highest driving capability.
- the minimum bias current that satisfies the corresponding requirements of different data lines is determined based on the longest pin of the corresponding transmission line in the pin combination.
- the bias current output by the control unit is larger for the pin combination in which the average length of the corresponding transmission wiring is larger.
- an embodiment of the present disclosure further provides a display device including the above-described driving chip.
- the display device can be: a liquid crystal panel, an electronic paper, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, A product or part that has any display function, such as a tablet.
- the embodiment of the present disclosure further provides a driving control method for controlling a driving chip of a display panel
- the driving chip has N pins, and the N is greater than or equal to 2.
- the N pins correspond to N signal transmission lines disposed on the display panel, and the pins are connected to corresponding signal transmission lines through transmission wires, and the N pins include a first pin.
- the transmission wiring includes a first transmission line connected to the first pin and a second transmission line connected to the second pin, the first transmission The length of the wiring is greater than the length of the second transmission wiring
- the driving control method includes:
- the N driving signals include: a first driving signal corresponding to the first pin and a second driving signal corresponding to the second pin, wherein a current intensity of the first driving signal is greater than a second driving The current strength of the signal.
- the driving chip is a data driving chip or a gate driving chip.
- the generating the N driving signals specifically includes:
- the driving signal has the same voltage value as the corresponding initial signal.
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Abstract
Description
管脚新编号 | 偏置电流水平 | TCON代码 |
[1,N1] | 最小 | 00h |
[N1+1,N1+N2] | 次小 | 04h |
[N1+N2+1,N1+N2+N3] | 中间 | 08h |
[N1+N2+N3+1,N1+N2+N3+N4] | 次大 | 0Ch |
[N1+N2+N3+N4+1,N1+N2+N3+N4+N5] | 最大 | OFh |
管脚新编号 | 偏置电流水平 | TCON代码 |
[1,M1] | 最小 | 00h |
[M1+1,M1+M2] | 次小 | 05h |
[M1+M2+1,M1+M2+M3] | 次大 | 0Bh |
[M1+M2+M3+1,M1+M2+M3+M4] | 最大 | 0Fh |
Claims (17)
- 一种用于驱动显示面板的驱动芯片,所述驱动芯片上具有N个管脚,所述N为大于或等于2的整数,所述N个管脚对应于设置于所述显示面板的N条信号传输线,所述管脚与对应的信号传输线之间通过传输配线连接;其中,所述N个管脚包括第一管脚和第二管脚,所述传输配线中包括与所述第一管脚相连接的第一传输配线和与所述第二管脚相连接的第二传输配线,所述第一传输配线的长度大于所述第二传输配线的长度,所述驱动芯片包括:信号生成模块,用于生成N个驱动信号,每一个驱动信号对应于一个所述管脚;所述N个驱动信号中包括:与所述第一管脚对应的第一驱动信号和与所述第二管脚对应的第二驱动信号,所述第一驱动信号的电流强度大于第二驱动信号的电流强度。
- 根据权利要求1所述的用于驱动显示面板的驱动芯片,其中,所述驱动芯片为数据驱动芯片或栅极驱动芯片。
- 根据权利要求1或2所述的用于驱动显示面板的驱动芯片,其中,所述信号生成模块具体包括:第一信号生成单元,用于生成N个初始信号;信号调整单元,用于根据所述初始信号对应的管脚所连接的传输配线的长度调整所述初始信号的电流强度,得到N个驱动信号;其中驱动信号与对应的初始信号的电压值相同。
- 根据权利要求3所述的用于驱动显示面板的驱动芯片,其中,所述信号调整单元具体包括:多个电压跟随单元,连接所述第一信号生成单元;控制单元,用于根据初始信号对应的管脚所连接的传输配线的长度确定所述多个电压跟随单元的偏置电流;所述控制单元输出用于第一管脚对应的电压跟随单元的第一偏置电流和用于第二管脚对应的电压跟随单元的第二偏置电流,所述第一偏置电流的电流强度大于所述第二偏置电流的电流强度。
- 根据权利要求4所述的用于驱动显示面板的驱动芯片,其中,每个所述电压跟随单元为一输出端与反相输入端连接的运算放大器。
- 根据权利要求4所述的用于驱动显示面板的驱动芯片,其中,所述控制单元为时序控制单元。
- 根据权利要求4所述的用于驱动显示面板的驱动芯片,其中,所述N个管脚分为M个管脚组,M为大于或等于2的整数,每一个管脚属于且仅属于一个组;所述控制单元对同一个管脚组中的管脚输出相同的偏置电流;对于所述M个管脚组中任意两个对应于不同传输配线平均长度的管脚组,其中一个管脚组对应的传输配线的长度的最大值小于另一个管脚组对应的传输配线的长度的最小值,且所述控制单元向对应于较大传输配线平均长度的管脚组中的每个管脚输出的偏置电流的电流强度大于向对应于较小传输配线平均长度的管脚组中的每个管脚输出的偏置电流的电流强。
- 根据权利要求4-6中任一项所述的用于驱动显示面板的驱动芯片,其中,对于所述N个管脚中任意两个连接不同长度传输配线的管脚,连接较长传输配线的管脚对应的驱动信号的电流强度大于连接较短传输配线的管脚对应的驱动信号的电流强度。
- 根据权利要求8所述的用于驱动显示面板的驱动芯片,其中,对于所述N个管脚中任意两个连接不同长度传输配线的管脚,所述控制单元输向连接较长传输配线的管脚对应的电压跟随单元的偏置电流的电流强度大于输向连接较短传输配线的管脚对应的电压跟随单元的偏置电流的电流强度。
- 根据权利要求1所述的用于驱动显示面板的驱动芯片,其中,所述N条信号传输线沿第一方向间隔排开,连接所述N条信号传输线的传输配线的长度沿所述第一方向先逐渐减小再逐渐增大。
- 一种显示装置,包括权利要求1-10中任意一项所述的驱动芯片。
- 一种驱动控制方法,用于控制显示面板的驱动芯片,所述驱动芯片上具有N个管脚,所述N为大于或等于2的整数,所述N个管脚对应于设置于所述显示面板的N条信号传输线,所述管脚与对应的信号传输线之间通过传输配线连接,其中,所述N个管脚包括第一管脚和第二管脚,所述传输配线中包括与所述第一管脚相连接的第一传输配线和与所述第二管脚相连接的第二传输 配线,所述第一传输配线的长度大于所述第二传输配线的长度,所述驱动控制方法包括:生成N个驱动信号,每一个驱动信号对应于一个所述管脚;所述N个驱动信号中包括:与所述第一管脚对应的第一驱动信号和与所述第二管脚对应的第二驱动信号,所述第一驱动信号的电流强度大于第二驱动信号的电流强度。
- 根据权利要求12所述的驱动控制方法,其中,所述驱动芯片为数据驱动芯片或栅极驱动芯片。
- 根据权利要求12或13所述的驱动控制方法,其中,所述生成N个驱动信号具体包括:生成N个初始信号;根据所述初始信号对应的管脚所连接的传输配线的长度调整所述初始信号的电流强度,得到N个驱动信号;其中驱动信号与对应的初始信号的电压值相同。
- 根据权利要求14所述的驱动控制方法,其中,所述根据所述初始信号对应的管脚所连接的传输配线的长度调整所述初始信号的电流强度的步骤包括:根据所述初始信号对应的管脚所连接的传输配线的长度确定所述管脚对应的偏置电流;其中,所述第一管脚对应的偏置电流的电流强度大于所述第二管脚对应的偏置电流的电流强度。
- 根据权利要求15所述的驱动控制方法,其中,所述根据所述初始信号对应的管脚所连接的传输配线的长度确定所述管脚对应的偏置电流的步骤包括:将所述N个管脚分为M个管脚组,M为大于或等于2的整数,其中,每一个管脚属于且仅属于一个组,对于所述M个管脚组中任意两个对应于不同传输配线平均长度的管脚组,其中一个管脚组对应的传输配线的长度中的最大值小于另一个管脚组对应的传输配线的长度中的最小值;对于所述M个管脚组中任意一个管脚组,根据所述任意一个管脚组对应的 传输配线的长度中的最大值确定与所述任意一个管脚组对应的偏置电流,并将确定的偏置电流输给所述任意一个管脚组中的所有管脚;其中,对于所述M个管脚组中任意两个对应于不同传输配线平均长度的管脚组,向对应于较大传输配线平均长度的管脚组中的每个管脚输出的偏置电流的电流强度大于向对应于较小传输配线平均长度的管脚组中的每个管脚输出的偏置电流的电流强度。
- 根据权利要求14所述的驱动控制方法,其中,对于所述N个管脚中任意两个连接不同长度传输配线的管脚,连接较长传输配线的管脚对应的驱动信号的电流强度大于连接较短传输配线的管脚对应的驱动信号的电流强度。
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CN104835472B (zh) * | 2015-05-28 | 2018-01-02 | 合肥京东方光电科技有限公司 | 用于驱动显示面板的驱动芯片、显示装置及驱动控制方法 |
CN105118452A (zh) * | 2015-08-20 | 2015-12-02 | 京东方科技集团股份有限公司 | 栅极驱动方法和结构 |
CN105810174A (zh) * | 2016-06-01 | 2016-07-27 | 京东方科技集团股份有限公司 | 源极驱动芯片、显示装置及其驱动方法 |
JP6840948B2 (ja) * | 2016-07-25 | 2021-03-10 | 船井電機株式会社 | 液晶表示装置 |
CN107025892B (zh) * | 2017-04-27 | 2020-02-07 | 武汉华星光电技术有限公司 | 数据驱动电路与显示面板 |
CN107195271B (zh) * | 2017-07-31 | 2019-04-05 | 京东方科技集团股份有限公司 | 驱动芯片及显示面板 |
KR102476183B1 (ko) * | 2018-02-19 | 2022-12-09 | 삼성디스플레이 주식회사 | 표시 장치 |
CN108920017A (zh) * | 2018-08-21 | 2018-11-30 | 广州视源电子科技股份有限公司 | 触摸屏及其驱动方法和装置 |
CN109509449B (zh) * | 2018-12-19 | 2021-07-06 | 惠科股份有限公司 | 电流调节电路、驱动电路及显示装置 |
TWI690918B (zh) * | 2019-04-17 | 2020-04-11 | 友達光電股份有限公司 | 驅動電路及其驅動方法 |
CN111048029B (zh) * | 2019-12-31 | 2023-05-05 | 视涯科技股份有限公司 | 数据驱动电路、驱动芯片、显示装置及其驱动方法 |
CN112259036B (zh) * | 2020-11-06 | 2023-12-22 | 合肥芯颖科技有限公司 | 一种显示面板和电子设备 |
CN114664241A (zh) * | 2022-04-13 | 2022-06-24 | 北京欧铼德微电子技术有限公司 | 驱动装置、驱动芯片及电子设备 |
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