WO2016162938A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2016162938A1 WO2016162938A1 PCT/JP2015/060808 JP2015060808W WO2016162938A1 WO 2016162938 A1 WO2016162938 A1 WO 2016162938A1 JP 2015060808 W JP2015060808 W JP 2015060808W WO 2016162938 A1 WO2016162938 A1 WO 2016162938A1
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- WO
- WIPO (PCT)
- Prior art keywords
- power supply
- capacitor
- semiconductor device
- bump
- external connection
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 239000003990 capacitor Substances 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 239000010409 thin film Substances 0.000 claims description 50
- 239000003985 ceramic capacitor Substances 0.000 description 29
- 230000000694 effects Effects 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 230000000087 stabilizing effect Effects 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
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Definitions
- the present invention relates to a semiconductor device, and in particular, to a semiconductor device including a semiconductor chip die-bonded to a support and a capacitor.
- Patent Document 1 As this type of semiconductor device, for example, a technique disclosed in Patent Document 1 is known.
- an upper chip 2 as a semiconductor chip is die-bonded face-up on a lower chip 7 as a support.
- the semiconductor device 1 an example is shown in which the upper chip 2 and the passive chip component 3 such as a chip capacitor mounted around the upper chip 2 are connected via a wire 5 and a wiring substrate 4. Yes.
- the wiring distance from the semiconductor chip die-bonded to the support to the capacitor is shortened, the noise reduction effect of the capacitor is improved, and the reliability in high frequency operation of the semiconductor chip is improved.
- a semiconductor device to be improved is provided.
- a semiconductor device disclosed in the present specification is a semiconductor device including a support and a semiconductor chip die-bonded and mounted on the support in a face-up manner, and electrically connects the semiconductor chip to the outside A plurality of external connection portions, an intermediate substrate provided on the semiconductor chip opposite to the support and connecting the semiconductor chip to the plurality of external connection portions, and connecting the semiconductor chip and the intermediate substrate A plurality of connection bumps, wherein the semiconductor chip has a plurality of electrode pads connected to the intermediate substrate via the plurality of electrode pads, and the plurality of connection bumps are formed on the semiconductor chip.
- a plurality of power supply bumps for supplying electric power wherein the intermediate substrate is connected to the plurality of electrode pads via the plurality of power supply bumps;
- the intermediate substrate is provided on the semiconductor chip, and is directly connected to the electrode pad of the semiconductor chip via the power bump.
- the capacitor is formed on the intermediate substrate and connected to the electrode pad of the semiconductor chip via the power bump. Therefore, the wiring distance from the semiconductor chip to the capacitor is significantly shortened compared to the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring. That is, according to the semiconductor device of this configuration, the wiring distance from the semiconductor chip die-mounted on the holder to the capacitor can be shortened. Therefore, it is possible to improve the noise reduction effect of the capacitor, thereby stabilizing the power supply and improving the reliability in high frequency operation of the semiconductor chip.
- the capacitor may be a thin film capacitor formed on the bump surface of the intermediate substrate and connected to the plurality of power supply pads.
- the thin film capacitor is formed on the bump surface of the intermediate substrate, and is connected to the power pad on the bump surface and the electrode pad of the semiconductor chip only through the power bump. For this reason, the wiring distance from the semiconductor chip to the thin film capacitor is greatly reduced compared to the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring.
- the capacitor further includes a chip capacitor formed on the external connection surface, and the chip capacitor is connected in parallel to the thin film capacitor via a via plug formed in the intermediate substrate. It is good.
- a multilayer ceramic capacitor having a larger capacity than the thin film capacitor is further connected in parallel to the thin film capacitor. Therefore, compared with the case of using only a thin film capacitor, it is possible to further improve the noise reduction effect of the capacitor, thereby stabilizing the power supply and improving the reliability of the LSI chip 10 in the high frequency operation.
- the capacitor is a thin film capacitor formed on the external connection surface, and the thin film capacitor is connected to the plurality of power supply bumps via via plugs formed in the intermediate substrate. It is good also as a structure. According to this configuration, the wiring distance can be reduced as compared with the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring.
- the capacitor is a chip capacitor formed on the external connection surface, and the chip capacitor is connected to the plurality of power supply bumps via via plugs formed in the intermediate substrate. It is good also as a structure. According to this configuration, the wiring distance can be reduced as compared with the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring. In addition, since the chip capacitor is stacked on the semiconductor chip, the area of the semiconductor device can be reduced. This can contribute to miniaturization of a circuit board such as a mother board on which a semiconductor device is mounted.
- the capacitor is a chip capacitor formed on the external connection surface, and the chip capacitor is connected to the plurality of power bumps via a power supply wiring portion formed on the external connection surface. It is good also as a structure connected. According to this configuration, the wiring distance can be reduced as compared with the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring. Further, since the chip capacitor is stacked on the semiconductor chip, the area of the semiconductor device can be reduced, and the number of via plugs in the intermediate substrate can be reduced.
- the capacitor includes a first electrode and a second electrode, and the plurality of power supply bumps apply a power supply voltage of one polarity to the semiconductor chip, and the semiconductor
- a second power supply bump for applying a power supply voltage of the other polarity to the chip, and the via plug includes a first via plug for connecting the first electrode to the first power supply bump, and the second electrode for the second power supply.
- the second electrode of the chip capacitor is connected to the first power supply bump through the second power supply wiring portion formed on the external connection surface, and the second via plug is connected to the first power supply bump.
- the wiring circuit of the chip capacitor is formed separately on the bump surface and the external connection surface.
- the first power supply wiring portion related to the positive voltage is formed on the bump surface
- the second power supply wiring portion related to the ground voltage is formed on the external connection surface. Therefore, compared with the case where the wiring circuit is formed only on the external connection surface, the circuit pattern of the wiring circuit can be simplified and formed short. Thereby, the value of ESR (equivalent series resistance) and ESL (equivalent series inductance) generated in the wiring circuit can be reduced.
- the plurality of power supply pads and the plurality of external connection pads are connected by via plugs formed in the intermediate substrate, and the plurality of external connection pads and the plurality of external connection portions are Further, it may be configured to be connected by wire bonding. According to this configuration, the wiring distance from the semiconductor chip to the capacitor can be shortened in a configuration in which the semiconductor chip and the external connection portion are connected via wire bonding.
- the wiring distance from the semiconductor chip die-bonded to the support to the capacitor is shortened, the noise reduction effect of the capacitor is improved, and the reliability in high frequency operation of the semiconductor chip is improved.
- a semiconductor device can be provided.
- FIG. 3 is a plan view showing an external connection surface of an intermediate substrate of the semiconductor device of Embodiment 1.
- FIG. 2 is a plan view showing a bump surface of an intermediate substrate of the semiconductor device of Embodiment 1.
- Schematic sectional view showing another example of the semiconductor device of Embodiment 1 Schematic cross-sectional view of the semiconductor device of Embodiment 2
- Schematic sectional view showing another example of the semiconductor device of Embodiment 2 Schematic sectional view showing another example of the semiconductor device of Embodiment 2
- FIG. 9 is a plan view showing an external connection surface of the intermediate substrate of the semiconductor device of FIG. The top view which shows the bump surface of the intermediate board of the semiconductor device of FIG.
- the semiconductor device 1 of the first embodiment is a QFN (Quad Flat No Lead Package) type semiconductor device, as shown in FIG.
- the semiconductor device 1 includes a support 2 and an LSI chip (an example of a “semiconductor chip”) 10 that is die-bonded and mounted on the support 2 face-up. Further, the semiconductor device 1 is provided on the LSI chip 10 on the side opposite to the plurality of external connection parts 3 and the support 2 for electrically connecting the LSI chip 10 to the outside, and the LSI chip 10 is connected to the plurality of external connection parts 3. And a plurality of connection bumps 6 for connecting the LSI chip 10 and the intermediate substrate 20 to each other.
- the LSI chip 10 has a plurality of electrode pads 11 connected to the intermediate substrate 20 on the surface 12 opposite to the surface to be die-bonded.
- the intermediate substrate 20 has a quadrilateral shape in a plan view as shown in FIGS. 3 and 4, for example, a BT resin (prepreg sheet) that is heat-pressed.
- the intermediate substrate 20 is not limited to BT (bismaleimide triazine) resin.
- BT bismaleimide triazine
- it may be made of glass such as borosilicate glass, quartz glass, soda glass, etc., as long as thin film forming processing and metal fine processing can be performed.
- the intermediate substrate 20 has a bump surface (lower surface) 22 that faces the LSI chip 10 (see FIG. 4), and the bump surface 22 has a plurality of connection bumps 6 formed on the plurality of electrode pads 11 of the LSI chip 10. Is connected. Specifically, each connection bump 6 is connected to a pad 21 formed on the bump surface 22.
- the plurality of connection bumps 6 are connected to the plurality of electrode pads 11 of the LSI chip 10 in addition to the signal bumps 6 and include power supply bumps (6V, 6G) for supplying power to the LSI chip 10 (FIG. 2).
- the pad 21 includes a plurality of power pads (21V, 21G) connected to the plurality of electrode pads (11V, 11G) via the plurality of power bumps (6V, 6G).
- the power supply bump 6V is a bump for applying a predetermined positive voltage to the LSI chip 10
- the power supply bump 6G is a bump for applying a ground voltage (zero voltage) to the LSI chip 10.
- the positive voltage corresponds to the power supply voltage of one polarity applied to the LSI chip 10
- the ground voltage corresponds to the power supply voltage of the other polarity applied to the LSI chip 10.
- the reverse may be sufficient. That is, the power supply voltage with one polarity may be a ground voltage, and the power supply voltage with the other polarity may be a positive voltage.
- the letter “V” is attached to the reference numeral of the member related to the positive voltage
- the letter “G” is attached to the reference numeral of the member related to the ground voltage.
- V is a member related to a signal other than the power supply, or when it is not particularly necessary to distinguish
- “V” or “G” is not attached to the reference numeral.
- the intermediate substrate 20 is a surface opposite to the bump surface 22, and has an external connection surface (upper surface) 24 on which a plurality of external connection pads 23 connected to the external connection portion 3 are formed, and a power bump (6V). , 6G). Further, a plurality of via plugs 25 connected to the plurality of pads 21 and the plurality of external connection pads 23 are formed in the intermediate substrate 20.
- the capacitor is a thin film capacitor 30 formed on the bump surface 22 of the intermediate substrate 20 and directly connected to the power supply pads (21V, 21G) as shown in FIG. 1 and FIG.
- the cross section of the intermediate substrate 20 shown in FIGS. 1 and 2 is taken along the line AA of FIG.
- the thin film capacitor 30 includes a first surface electrode 31, a second surface electrode 32, and a dielectric layer 33.
- Each of the first surface electrode 31, the second surface electrode 32, and the dielectric layer 33 has a quadrilateral shape along the four sides of the intermediate substrate 20 in plan view, for example, as shown in FIG. It is composed of a thin film sheet. That is, the thin film capacitor 30 is a sheet-like capacitor having a quadrilateral shape in plan view.
- FIG. 4 is a plan view of the intermediate substrate 20 as viewed from the LSI chip 10 side.
- the first surface electrode 31 includes a bump connection portion 31V, and the bump connection portion 31V is directly connected to the power supply bump 6V.
- the second surface electrode 32 includes a bump connection part 32G, and the bump connection part 32G is directly connected to the power supply bump 6G. That is, the thin film capacitor 30 has a so-called bypass capacitor function.
- the bump connection portions (31V, 32G) also serve as power supply pads (21V, 21G) to which the power supply bumps (6V, 6G) are connected.
- FIG. 4 shows an example in which bump connection portions 31V and 32G are formed at four locations on the surface electrodes 31 and 32, respectively, but the present invention is not limited to this.
- connection bumps 6 are formed on the electrode pads 11 of the LSI chip 10 by a known method.
- the connection bump 6 is, for example, a gold stack bump. Note that the connection bumps 6 are not limited to gold stack bumps, and may be, for example, micro solder balls. Further, the connection bump 6 may be formed on the pad 21 of the intermediate substrate 20.
- the thin film capacitor 30 is formed on the bump surface 22 of the intermediate substrate 20 as follows, for example.
- a dielectric film made of a metal oxide film such as STO is formed on a metal substrate.
- a metal thin film, such as a copper thin film, is formed thereon by sputtering, for example, and patterned to form the first surface electrode 31, the bump connection portion 32G of the second surface electrode 32, and the pad 21.
- the bump connection portion 31 ⁇ / b> V power supply pad 21 ⁇ / b> V
- V power supply pad 21 ⁇ / b> V
- a BT resin prepreg sheet
- the metal substrate is removed to expose the dielectric film, and the dielectric film is patterned to form the dielectric layer 33.
- the second surface electrode 32 is formed on the dielectric layer 33 by, for example, generating a metal thin film, for example, a copper thin film, by a sputtering method using a mask.
- the bump connection portion 32G power supply pad 21G
- the first surface electrode 31 and the bump connection portion 32 ⁇ / b> G have a structure embedded in the insulating portion (BT resin) of the intermediate substrate 20.
- the first surface electrode 31 and the second surface electrode 32 are rectangular electrodes having substantially the same shape and the same size.
- a thin film capacitor 30 in which the first surface electrode 31, the dielectric layer 33, and the second surface electrode 32 are laminated in this order on the bump surface 22 of the intermediate substrate 20 is formed.
- the method of creating the thin film capacitor 30 on the bump surface 22 of the intermediate substrate 20 is not limited to the above method.
- the first surface electrode 31 is formed integrally with the bump connection portion 31V on the surface (bump surface) 22 of the intermediate substrate 20 by, for example, a metal sputtering method or a plating method.
- a dielectric layer 33 made of a metal oxide film such as ITO or STO is formed so as to cover the first surface electrode 31.
- the second surface electrode 32 is formed on the dielectric layer 33 by sputtering or plating in the same manner as the first surface electrode 31.
- the first surface electrode 31 or the like has a structure that is not embedded in the insulating portion (BT resin) of the intermediate substrate 20.
- vias are formed at predetermined positions in the intermediate substrate 20 by, for example, laser processing, and a plurality of via plugs 25 are formed by filling the vias with, for example, a copper material.
- the intermediate substrate 20 is connected to the LSI chip 10 by connecting the connection bumps 6 to the pads 21 corresponding to the via plugs 25 on the bump surface 22 of the intermediate substrate 20 using, for example, ultrasonic waves. .
- the space between the LSI chip 10 and the intermediate substrate 20 is filled with, for example, an underfill (not shown).
- the external connection pad 23 on the intermediate substrate 20 and the external connection portion 3 are connected by wire bonding using a wire 4, for example, a gold wire.
- a wire 4 for example, a gold wire.
- the LSI chip 10 and the intermediate substrate 20 and the like are molded to a predetermined size with the molding resin 5 to complete the semiconductor device 1 as shown in FIG.
- the intermediate substrate 20 is directly connected to the LSI chip 10 via the connection bumps 6.
- the thin film capacitor 30 is formed on the bump surface 22 of the intermediate substrate 20 and is connected to the LSI chip 10 only through the power supply bumps 6V and 6G connected to the bump surface 22. Therefore, the wiring distance from the LSI chip 10 to the thin film capacitor 30 is significantly shortened compared to the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring.
- the wiring distance from the LSI chip 10 to the thin film capacitor 30 is shortened to improve the noise reduction effect of the thin film capacitor 30, thereby stabilizing the power supply, and the LSI The reliability of the chip 10 in the high frequency operation can be improved.
- the thin film capacitor 30 may be formed on the external connection surface 24 of the intermediate substrate 20.
- the thin film capacitor 30 is connected to the power supply bumps (6V, 6G) via via plugs 25 formed in the intermediate substrate 20.
- the first surface electrode 31 of the thin film capacitor 30 is connected to the power supply bump 6V via the bump connection portion 31V and the via plug 25V.
- the second surface electrode 32 of the thin film capacitor 30 is connected to the power supply bump 6G via the bump connection portion 32G and the via plug 25G.
- the wiring distance can be shortened as compared with the conventional capacitor connected to the LSI chip 10 via the wire and the substrate wiring. Therefore, the noise reduction effect of the thin film capacitor 30 can be improved, thereby stabilizing the power supply and improving the reliability of the LSI chip 10 in the high frequency operation.
- the semiconductor device 1 ⁇ / b> A according to the second embodiment is different from the semiconductor device 1 according to the first embodiment only in a capacitor disposed on the intermediate substrate 20. That is, in the semiconductor device 1 ⁇ / b> A, in addition to the thin film capacitor 30 of the semiconductor device 1, a multilayer ceramic capacitor (an example of “chip capacitor”) 40 is disposed on the intermediate substrate 20.
- the chip capacitor is not limited to a multilayer ceramic capacitor (MLCC).
- the multilayer ceramic capacitor 40 is formed on the external connection surface 24 of the intermediate substrate 20 and connected in parallel to the thin film capacitor 30 via via plugs 25VV and 25GG formed in the intermediate substrate 20. Specifically, as shown in FIG. 6, the first electrode 41 of the multilayer ceramic capacitor 40 is connected to the first surface electrode 31 of the thin film capacitor 30 via the pad 26 on the external connection surface 24 and the via plug 25 VV. Yes. The second electrode 42 of the multilayer ceramic capacitor 40 is connected to the second surface electrode 32 of the thin film capacitor 30 through the pad 26 and the via plug 25GG.
- Example 1 of Embodiment 2 the thin film capacitor 30 may be omitted from the configuration of the semiconductor device 1A of the second embodiment. That is, in this example, the semiconductor device 1 ⁇ / b> B includes a multilayer ceramic capacitor 40 formed on the external connection surface (upper surface) 24 of the intermediate substrate 20 as a capacitor provided on the intermediate substrate 20.
- the multilayer ceramic capacitor 40 is connected to power supply bumps (6V, 6G) via via plugs 25VV, 25GG formed in the intermediate substrate 20.
- the first electrode 41 of the multilayer ceramic capacitor 40 is connected to the power supply bump 6V via the power supply wiring portion 27V that also serves as the via plug 25VV and the power supply pad 21V.
- the second electrode 42 of the multilayer ceramic capacitor 40 is connected to the power supply bump 6G through the power supply wiring portion 27G that also serves as the via plug 25GG and the power supply pad 21G.
- the wiring distance can be shortened as compared with the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring. Therefore, the noise reduction effect of the thin film capacitor 30 can be improved, thereby stabilizing the power supply and improving the reliability of the LSI chip 10 in the high frequency operation. Further, since the multilayer ceramic capacitor 40 is overlaid on the LSI chip 10, the area of the semiconductor device can be reduced. This can contribute to miniaturization of a circuit board such as a mother board on which a semiconductor device is mounted.
- Example 2 of Embodiment 2 in the configuration of the semiconductor device 1B shown in FIG. 7, the connection form of the multilayer ceramic capacitor 40 to the LSI chip 10 may be changed. That is, in the example illustrated in FIG. 8, the semiconductor device 1 ⁇ / b> C includes a multilayer ceramic capacitor 40 formed on the external connection surface (upper surface) 24 of the intermediate substrate 20 as a capacitor provided on the intermediate substrate 20.
- the multilayer ceramic capacitor 40 is connected to power supply bumps (6V, 6G) through power supply wiring portions 28V, 28G formed on the external connection surface 24.
- the first electrode 41 of the multilayer ceramic capacitor 40 is connected to the power supply bump 6V through the power supply wiring portion 28V also serving as a pad, the via plug 25V, and the power supply pad 21V.
- the second electrode 42 of the multilayer ceramic capacitor 40 is connected to the power supply bump 6G through the power supply wiring portion 28G that also serves as a pad, the via plug 25G, and the power supply pad 21G.
- the external connection surface 24 of the intermediate substrate 20 may be covered with a solder resist 29.
- the wiring distance can be shortened as compared with the conventional capacitor connected to the semiconductor chip via the wire and the substrate wiring. Therefore, the noise reduction effect of the thin film capacitor 30 can be improved, thereby stabilizing the power supply and improving the reliability of the LSI chip 10 in the high frequency operation. Further, since the multilayer ceramic capacitor 40 is overlaid on the LSI chip 10, the area of the semiconductor device can be reduced. This can contribute to miniaturization of a circuit board such as a mother board on which a semiconductor device is mounted. Further, the number of via plugs 25 can be reduced as compared with the semiconductor device 1B shown in FIG.
- Example 3 of Embodiment 2 in the configuration of the semiconductor device 1B shown in FIG. 7, the connection form of the multilayer ceramic capacitor 40 to the LSI chip 10 may be changed. That is, in the example illustrated in FIG. 9, the semiconductor device 1 ⁇ / b> D includes a multilayer ceramic capacitor 40 formed on the external connection surface (upper surface) 24 of the intermediate substrate 20 as a capacitor provided on the intermediate substrate 20, as with the semiconductor device 1 ⁇ / b> B.
- the semiconductor device 1 ⁇ / b> D includes a multilayer ceramic capacitor 40 formed on the external connection surface (upper surface) 24 of the intermediate substrate 20 as a capacitor provided on the intermediate substrate 20, as with the semiconductor device 1 ⁇ / b> B.
- the first electrode 41 of the multilayer ceramic capacitor 40 is formed on the pad 26 ⁇ / b> V formed on the external connection surface 24, the via plug 25 ⁇ / b> VV (an example of the first via plug) formed in the intermediate substrate 20, and the bump surface 22.
- the power supply wiring portion (an example of the first power supply wiring portion) 27V is connected to the power supply bump (an example of the first power supply bump) 6V through the connected power supply portion (an example of the first power supply wiring portion) 27V.
- the bump connection portion 28GG also serves as a pad 23 connected to the via plug 25G as shown in FIG.
- the bump connection portion 27VV also serves as a power supply pad 21V to which the power supply bump 6V is connected.
- the second electrode 42 is connected to a power supply wiring portion (an example of a second power supply wiring portion) 28G formed on the external connection surface 24 and a via plug 25G (an example of a second via plug) different from the via plug 25VV. It is connected to a power bump (an example of a second power bump) 6G.
- the power supply wiring portion 27V and the power supply wiring portion 28G are equivalent to the first surface electrode 31 and the second surface electrode 32 of the thin film capacitor 30 shown in FIG. It is formed in the shape of a plane electrode having substantially the same shape and a quadrilateral shape. Note that the power supply wiring portion 27V and the power supply wiring portion 28G do not have to be formed in a planar electrode shape as shown in FIGS.
- the wiring circuit of the multilayer ceramic capacitor 40 is separated into the bump surface 22 and the external connection surface 24 as compared with the semiconductor device 1B shown in FIG. That is, the power supply wiring portion 27V related to the positive voltage is formed on the bump surface 22, and the power supply wiring portion 28G related to the ground voltage is formed on the external connection surface 24. Therefore, compared with the semiconductor device 1B shown in FIG. 7, the circuit pattern of the wiring circuit of the multilayer ceramic capacitor 40 can be simplified and formed short.
- the power supply wiring portion 27V and the power supply wiring portion 28G are each formed in a surface electrode shape, similarly to the surface electrodes 31 and 32 of the thin film capacitor 30 shown in FIG. Therefore, the power supply wiring portion 27V, the insulator portion of the intermediate substrate 20, and the power supply wiring portion 28G constitute a capacitor connected in parallel to the multilayer ceramic capacitor 40. Therefore, depending on the adjustment of the dielectric constant of the insulator portion and the like, the noise reduction effect of the multilayer ceramic capacitor 40 can be further improved as compared with the semiconductor device 1B shown in FIG. 7, thereby stabilizing the power supply and the LSI chip. It is also possible to improve the reliability in 10 high frequency operations.
- the present invention is not limited to this.
- the present invention can be applied to, for example, a QFP type semiconductor device.
- the present invention can be applied to any semiconductor device including a semiconductor chip that is die-bonded and mounted face-up on a support.
- SYMBOLS 1 Semiconductor device, 2 ... Support body, 3 ... External connection part, 4 ... Wire, 6 ... Connection bump, 6V, 6G ... Power supply bump, 10 ... LSI chip, 11 ... Electrode pad, 20 ... Intermediate substrate, 21V, 21G Power supply pad, 24 External connection surface, 25 Via plug, 27 V First power wiring portion, 28 G Second power wiring portion, 30 Thin film capacitor, 40 Multilayer ceramic capacitor, 41 First electrode, 42 First 2 electrodes
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Abstract
Description
本構成によれば、薄膜コンデンサは、中間基板のバンプ面に形成され、バンプ面の電源パッド、および電源バンプのみを介して半導体チップの電極パッドに接続される。そのため、半導体チップから薄膜コンデンサまでの配線距離は、従来の、ワイヤおよび基板配線を介して半導体チップに接続されるコンデンサと比べて、配線距離が大幅に短縮されている。
本構成によれば、薄膜コンデンサに比べて大容量の、例えば、積層セラミックコンデンサが、さらに、薄膜コンデンサに並列に接続される。そのため、薄膜コンデンサのみの場合と比べて、さらに、コンデンサのノイズ削減効果を向上させ、それによって、電源を安定化させ、LSIチップ10の高周波動作に於ける信頼性を向上させることができる。
本構成によれば、従来の、ワイヤおよび基板配線を介して半導体チップに接続されるコンデンサと比べて、配線距離を短縮することができる。
本構成によれば、従来の、ワイヤおよび基板配線を介して半導体チップに接続されるコンデンサと比べて、配線距離を短縮することができる。また、チップコンデンサを半導体チップの上に重ねる構造であるため、半導体装置の面積を削減できる。それは、半導体装置が搭載されるマザーボード等の回路基板の小型化に寄与できる。
本構成によれば、従来の、ワイヤおよび基板配線を介して半導体チップに接続されるコンデンサと比べて、配線距離を短縮することができる。また、チップコンデンサを半導体チップの上に重ねる構造であるため、半導体装置の面積を削減できるとともに、中間基板内のビアプラグの数を削減することができる。
本構成によれば、チップコンデンサの配線回路が、バンプ面と外部接続面とに分離されて形成されている。例えば、バンプ面上には正電圧に係る第1電源配線部が形成され、外部接続面上にはグランド電圧に係る第2電源配線部が形成される。そのため、配線回路が外部接続面にのみ形成される場合と比べて、の配線回路の回路パターンを簡易化し、短く形成することができる。それによって、配線回路に発生するESR(等価直列抵抗)や、ESL(等価直列インダクタンス)の値を小さくすることができる。
本構成によれば、半導体チップと外部接続部とが、ワイヤボンディングを介して接続される構成において、半導体チップからコンデンサまでの配線距離を短くできる。
本発明の実施形態1を、図1ないし図5を用いて説明する。
1.実施形態1の半導体装置の構成
本実施形態1の半導体装置1は、図1に示されるように、QFN(Quad Flat No Lead Package)型の半導体装置である。半導体装置1は、図1に示されるように、支持体2と、支持体2上にフェイスアップでダイボンディング実装されたLSIチップ(「半導体チップ」の一例)10とを備える。また、半導体装置1は、LSIチップ10を電気的に外部に接続する複数の外部接続部3、支持体2と反対側のLSIチップ10上に設けられ、LSIチップ10を複数の外部接続部3に接続する中間基板20、および、LSIチップ10と中間基板20とを接続する複数の接続バンプ6を備える。
周知の方法によって、所定の支持体2上にフェイスアップでダイボンディングされたLSIチップ10を準備する。また、LSIチップ10の電極パッド11上に、周知の方法によって接続バンプ6を形成する。接続バンプ6は例えば、金スタックバンプである。なお、接続バンプ6は、金スタックバンプに限られず、例えば、マイクロ半田ボールであってもよい。また、接続バンプ6は中間基板20のパッド21に形成されるものであってもよい。
次に、第1面電極31等を埋め込むように第1面電極31上にからBTレジン(プリプレグシート)を加熱圧着して中間基板20の絶縁部を形成する。次いで、金属基材を除去して誘電体膜を露出させて、誘電体膜をパターニングして誘電体層33を形成する。次いで、誘電体層33上に、例えば、マスクを用いたスパッタリング手法によって金属薄膜、例えば銅薄膜を生成することによって、第2面電極32を形成する。その際、バンプ接続部32G(電源パッド21G)は第2面電極32と一体化される。この作成方法では、図2に示されるように、第1面電極31およびバンプ接続部32Gは、中間基板20の絶縁部(BTレジン)に埋め込まれた構造となる。
実施形態1においては、中間基板20は、LSIチップ10上に、接続バンプ6を介して直接、接続されている。また、薄膜コンデンサ30は、中間基板20のバンプ面22に形成され、バンプ面22に接続された電源バンプ6V,6Gのみを介してLSIチップ10に接続される。そのため、LSIチップ10から薄膜コンデンサ30までの配線距離は、従来の、ワイヤおよび基板配線を介して半導体チップに接続されるコンデンサと比べて、配線距離が大幅に短縮されている。そのため、実施形態1の半導体装置1によれば、LSIチップ10から薄膜コンデンサ30までの配線距離を短くして、薄膜コンデンサ30のノイズ削減効果を向上させ、それによって、電源を安定化させ、LSIチップ10の高周波動作に於ける信頼性を向上させることができる。
なお、図5に示されるように、薄膜コンデンサ30が、中間基板20の外部接続面24上に形成されていてもよい。この場合、薄膜コンデンサ30は、中間基板20内に形成されたビアプラグ25を介して電源バンプ(6V,6G)に接続される。詳しくは、薄膜コンデンサ30の第1面電極31は、バンプ接続部31Vおよびビアプラグ25Vを介して電源バンプ6Vに接続されている。また、薄膜コンデンサ30の第2面電極32は、バンプ接続部32Gおよびビアプラグ25Gを介して電源バンプ6Gに接続されている。
5.実施形態2の半導体装置の構成
次に、実施形態2を、図6ないし図11を参照して説明する。なお、実施形態1と同一の部材には、同一の符号を付しその説明を省略する。そのため、実施形態1との相違点のみ説明する。
実施形態2では、薄膜コンデンサ30の第1.第2面電極(31,32)を低インピーダンスな電源配線部として利用して、薄膜コンデンサ30に比べて大容量の積層セラミックコンデンサ40が、LSIチップ10の電極パッド11V,11Gに接続されている。そのため、実施形態1と比べて、さらに、薄膜コンデンサ30のノイズ削減効果を向上させ、それによって、電源を安定化させ、LSIチップ10の高周波動作に於ける信頼性を向上させることができる。
なお、図7に示されるように、実施形態2の半導体装置1Aの構成から薄膜コンデンサ30を省略してもよい。すなわち、この例では、半導体装置1Bは、中間基板20に設けられたコンデンサとして、中間基板20の外部接続面(上面)24に形成される積層セラミックコンデンサ40を有する。積層セラミックコンデンサ40は、中間基板20内に形成されたビアプラグ25VV、25GGを介して電源バンプ(6V,6G)に接続される。
また、図8に示されるように、図7に示す半導体装置1Bの構成において、積層セラミックコンデンサ40のLSIチップ10への接続形態を変更してもよい。すなわち、図8に示す例では、半導体装置1Cは、中間基板20に設けられたコンデンサとして、中間基板20の外部接続面(上面)24に形成される積層セラミックコンデンサ40を有する。積層セラミックコンデンサ40は、外部接続面24上に形成された電源配線部28V,28Gを介して電源バンプ(6V,6G)に接続される。
また、図9に示されるように、図7に示す半導体装置1Bの構成において、積層セラミックコンデンサ40のLSIチップ10への接続形態を変更してもよい。すなわち、図9に示す例では、半導体装置1Dは、半導体装置1Bと同様に、中間基板20に設けられたコンデンサとして、中間基板20の外部接続面(上面)24に形成される積層セラミックコンデンサ40を有する。
また、図10および図11に示されるように、電源配線部27Vおよび電源配線部28Gは、それぞれ、図4に示される薄膜コンデンサ30の第1面電極31および第2面電極32と同等に、ほぼ同一形状で、四辺形の形状を有する面電極状に形成されている。なお、電源配線部27Vおよび電源配線部28Gは、図10および図11に示されるような面電極状に形成されていなくてもよい。
本発明は上記記述及び図面によって説明した実施形態に限定されるものではなく、例えば次のような種々の態様も本発明の技術的範囲に含まれる。
Claims (8)
- 支持体と、前記支持体上にフェイスアップでダイボンディング実装された半導体チップとを備えた半導体装置であって、
前記半導体チップを電気的に外部に接続する複数の外部接続部と、
前記支持体と反対側の前記半導体チップ上に設けられ、前記半導体チップを前記複数の外部接続部に接続する中間基板と、
前記半導体チップと前記中間基板とを接続する複数の接続バンプと、を備え、
前記半導体チップは、前記複数の接続バンプを介して前記中間基板と接続される複数の電極パッドを有し、
前記複数の接続バンプは、前記半導体チップに電力を供給するための複数の電源バンプを含み、
前記中間基板は、
前記複数の電源バンプを介して前記複数の電極パッドと接続される複数の電源パッドと、
前記半導体チップと対向し、前記複数の電源パッドが形成されたバンプ面と、
前記バンプ面と反対側の面であって、前記外部接続部と接続される複数の外部接続パッドが形成された外部接続面と、
前記複数の電源バンプに接続されるコンデンサと、を含む、半導体装置。 - 請求項1に記載された半導体装置において、
前記コンデンサは、前記中間基板の前記バンプ面に形成され、前記複数の電源バンプに接続される薄膜コンデンサである、半導体装置。 - 請求項2に記載された半導体装置において、
前記コンデンサは、前記外部接続面に形成されたチップコンデンサをさらに含み、
前記チップコンデンサは、前記中間基板内に形成されたビアプラグを介して前記薄膜コンデンサに並列に接続される、半導体装置。 - 請求項1に記載された半導体装置において、
前記コンデンサは、前記外部接続面に形成された薄膜コンデンサであり、
前記薄膜コンデンサは、前記中間基板内に形成されたビアプラグを介して前記複数の電源バンプに接続される、半導体装置。 - 請求項1に記載された半導体装置において、
前記コンデンサは、前記外部接続面に形成されるチップコンデンサであり、
前記チップコンデンサは、前記中間基板内に形成されたビアプラグを介して前記複数の電源バンプに接続される、半導体装置。 - 請求項5に記載された半導体装置において、
前記コンデンサは、第1電極と第2電極とを含み、
前記複数の電源バンプは、前記半導体チップへ一方の極性の電源電圧を印加する第1電源バンプと、前記半導体チップへ他方の極性の電源電圧を印加する第2電源バンプとを含み、
前記ビアプラグは、前記第1電極を前記第1電源バンプに接続する第1ビアプラグと、前記第2電極を前記第2電源バンプに接続する第2ビアプラグとを含み、
前記チップコンデンサの前記第1電極は、前記外部接続面上に形成されたパッド、前記第1ビアプラグ、および前記バンプ面に形成された第1電源配線部を介して前記第1電源バンプに接続され、
前記チップコンデンサの前記第2電極は、前記外部接続面上に形成された第2電源配線部、および前記第2ビアプラグを介して前記第2電源バンプに接続されている、半導体装置。 - 請求項1に記載された半導体装置において、
前記コンデンサは、前記外部接続面に形成されるチップコンデンサであり、
前記チップコンデンサは、前記外部接続面上に形成された電源配線部を介して前記電源バンプに接続される、半導体装置。 - 請求項1から請求項7のいずれか一項に記載された半導体装置において、
前記複数の電源パッドと前記複数の外部接続パッドとは、前記中間基板内に形成されたビアプラグによって接続され、
前記複数の外部接続パッドと前記複数の外部接続部とは、ワイヤボンディングで接続される、半導体装置。
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US20190148290A1 (en) * | 2017-11-15 | 2019-05-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Two-Dimensional Via Pillar Structures |
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