WO2016138880A1 - 一种多频段信号处理方法及设备 - Google Patents

一种多频段信号处理方法及设备 Download PDF

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WO2016138880A1
WO2016138880A1 PCT/CN2016/075642 CN2016075642W WO2016138880A1 WO 2016138880 A1 WO2016138880 A1 WO 2016138880A1 CN 2016075642 W CN2016075642 W CN 2016075642W WO 2016138880 A1 WO2016138880 A1 WO 2016138880A1
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feedback signal
common feedback
processing
band
signal
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PCT/CN2016/075642
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English (en)
French (fr)
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熊军
孙华荣
段滔
肖鹏
王杰丽
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大唐移动通信设备有限公司
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Publication of WO2016138880A1 publication Critical patent/WO2016138880A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

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  • the present invention relates to the field of communications technologies, and in particular, to a multi-band signal processing method and device.
  • the frequency band distribution of these three modulated signals is shown in Figure 1.
  • (a) shows the input signal
  • (b) shows the output signal.
  • the frequency interval ⁇ ⁇ 2- ⁇ 1 of the two frequency bands ⁇ 1 and ⁇ 2 of the input signal, with a large frequency interval ⁇ , It is far away from the input signal frequency, so it is easy to filter out.
  • the remaining distortion only includes in-band intermodulation and inter-band intermodulation.
  • FIG. 2 it is a DPD (Digital Pre-Distortion) processing block diagram of a dual-band cell in the prior art, and the dual-band DPD system architecture includes a signal extraction and analysis stage, The processing stage and the synthesis stage.
  • the prior art adopts 2D-DPD (2Dimensional DPD) technology or more complicated 2D-TCMP-DPD (2Dimensional Time Cross Memory Polynomial DPD) for multi-band.
  • the model can complete the pre-distortion processing of the multi-band signal, the processing is complicated and the required hardware resource consumption is relatively large.
  • the embodiment of the invention provides a multi-band signal processing method for simplifying the sampling rate of the feedback signal and optimizing the feedback signal matrix U, thereby saving hardware resources.
  • the method includes:
  • the common feedback signal is predistorted by a DPD model.
  • the multi-band signal in each of the common feedback signal groups is collected by using a low-speed ADC, including:
  • the common feedback signal of the common feedback signal group is acquired by a low speed ADC.
  • the collected common feedback signal and the original training sequence are subjected to multiple interpolation processing, including:
  • the acquired common feedback signal and the original training sequence are subjected to 2 ⁇ interpolation or 4 ⁇ interpolation.
  • pre-distortion processing the common feedback signal by using a DPD model including:
  • a DPD coefficient is obtained according to the autocorrelation matrix.
  • the embodiment of the invention further provides a multi-band signal processing device, which comprises:
  • a group module for combining signals in a frequency band of a multi-band signal into a common feedback signal group
  • a first processing module configured to perform a common feedback process on each of the common feedback signal groups
  • An acquisition module is configured to collect multi-band signals in each of the common feedback signal groups by using a low-speed ADC, and perform multi-interpolation processing on the collected common feedback signals and the original training sequence;
  • a second processing module configured to perform predistortion processing on the common feedback signal by using a DPD model.
  • the collecting module is specifically configured to:
  • the common feedback signal of the common feedback signal group is acquired by a low speed ADC.
  • the collecting module is specifically configured to:
  • the acquisition module performs 2x interpolation or 4x interpolation on the collected common feedback signal and the original training sequence, so that the common feedback signal is in a high-speed sampling state for signal correlation synchronization processing.
  • the second processing module is specifically configured to:
  • a DPD coefficient is obtained according to the autocorrelation matrix.
  • the embodiment of the invention further provides a multi-band signal processing device, which comprises: a processor, a transceiver and a memory;
  • transceiver is configured to receive and transmit data under the control of the processor
  • the memory is used to store data used by the processor to perform operations
  • the processor can be used to read programs in memory and perform the following procedures:
  • the common feedback signal is predistorted by a DPD model.
  • the processor reads the program in the memory and performs the following process:
  • the common feedback signal of the common feedback signal group is acquired by a low speed ADC.
  • the processor reads the program in the memory and performs the following process:
  • the acquired common feedback signal and the original training sequence are subjected to 2 ⁇ interpolation or 4 ⁇ interpolation to perform signal correlation synchronization processing in the high-speed sampling state.
  • the processor reads a program in the memory and performs the following process:
  • a DPD coefficient is obtained according to the autocorrelation matrix.
  • the common feedback signal group is subjected to the common feedback processing, and the low-speed ADC is used for
  • the multi-band signals in the feedback signal group are collected, and the collected common feedback signals and the original training sequence are multi-time interpolated.
  • the common feedback signal is pre-distorted by the DPD model.
  • FIG. 1 is a schematic diagram of a power spectrum signal of a dual band transmitter in the prior art
  • FIG. 2 is a block diagram of DPD processing of a dual-band cell in the prior art
  • FIG. 3 is a schematic flowchart of a multi-band signal processing method according to an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a simplified DPD processing apparatus after filtering a feedback signal matrix according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a combination of two groups of FAED four frequency bands and a common feedback frequency band according to a specific embodiment of the present invention
  • FIG. 6 is a schematic diagram of intermodulation and intermodulation information output by an original two-band signal after passing through a power amplifier according to an embodiment of the present invention
  • FIG. 7 is a schematic diagram of inter-modulation and inter-modulation frequency band information of a least effective acquisition in a dual frequency band according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram of a feedback signal before entering an ADC according to an embodiment of the present invention.
  • FIG. 9 is a signal spectrum diagram of an ADC after low speed acquisition according to an embodiment of the present invention.
  • FIG. 10 is a frequency spectrum diagram of a feedback signal and a training sequence after interpolation filtering according to an embodiment of the present invention
  • FIG. 11 is a block diagram of a DPD common feedback implementation in a specific embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of a multi-band signal processing device according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a multi-band signal processing device according to an embodiment of the present invention.
  • the pre-distortion processing method adopted in the prior art for multi-band can complete the pre-distortion processing of the multi-band signal, but the processing is complicated, and the required hardware resource consumption is relatively large. Therefore, the embodiment of the present invention provides a multi-band signal processing method, which optimizes the feedback signal matrix, thereby saving the algorithm device of hardware resources, and enables carrier aggregation between more frequency bands. As shown in FIG. 3, the method includes the following steps:
  • S301 The signals in the frequency band of the multi-band signal are mutually combined to form a common feedback signal group.
  • S302 Perform common feedback processing on each of the common feedback signal groups.
  • the embodiment of the present invention first performs the dual-band common feedback processing of S301-S302, so that the low-speed feedback ADC (Analog-to-digital converter) and the low-speed DAC transmitter can be used.
  • the predistortion processing of the wide bandwidth signal is completed and the requirements of the transmit DAC can also be reduced.
  • the step first filters out the third-order external intermodulation information of the multi-band signal in each of the common feedback signal groups, and then collects the common feedback signal group through the low-speed ADC. A total of feedback signals.
  • the preferred embodiment of the present invention performs the 2 ⁇ interpolation or the 4 ⁇ interpolation of the collected common feedback signal and the original training sequence, so that the common feedback signal is in a high-speed sampling state.
  • Signal related synchronization processing performs the 2 ⁇ interpolation or the 4 ⁇ interpolation of the collected common feedback signal and the original training sequence, so that the common feedback signal is in a high-speed sampling state.
  • the signal collected by the feedback and the original signal are subjected to multiple interpolation filtering, and then the memory polynomial model with the wide-band time-interval term can be selected to calculate the DPD coefficient.
  • the U matrix composed of the feedback signal is filtered, so that the intermodulation information U of the matrix corresponds to the feedback information, and the U matrix in the matrix inversion is filtered. Since there are multi-order intermodulation information, the autocorrelation U matrix can be filtered. The sideband intermodulation information constituting the U matrix is thus filtered out.
  • the step first generates the autocorrelation matrix by canceling the power amplifier rated linear gain processing, and then filtering the sideband intermodulation information constituting the autocorrelation matrix, and acquiring the DPD coefficient according to the autocorrelation matrix.
  • the filtering process is mainly used to filter the intermodulation and intermodulation information of the far sidebands of the U matrix, and the far-end intermodulation information generally refers to the 3rd-order intermodulation sideband information.
  • multiple frequency band signals are pre-distorted, and the adjacent frequency band signals are combined to form a common feedback, and the third-order intermodulation of the respective bandwidths is collected, and the out-of-band information is filtered by the anti-aliasing filter in front of the ADC.
  • the multi-band signal is acquired by the relatively low-speed ADC, and then the feedback signal and the training sequence are interpolated to start the training of the pre-distortion coefficient.
  • TCMP time-interleaved memory polynomial model
  • z(n) represents the predistorted signal output at time n
  • x(n) represents the original signal input at time n
  • n represents the input moment of the original signal
  • m represents the memory of the original signal.
  • w represents the predistortion parameter
  • M represents the memory depth
  • Q represents the nonlinear order
  • L represents the maximum cross-sampling point
  • q represents the nonlinear order index.
  • the signal u is obtained.
  • u m,q,l (n) denotes a first feedback signal for canceling the rated linear gain of the power amplifier
  • G denotes a rated linear gain
  • n denotes an input timing of the first feedback signal
  • m denotes a memory moment of the first feedback signal
  • M denotes a memory Depth
  • Q represents a nonlinear order
  • L represents the maximum cross-sampling point
  • q represents a nonlinear order index
  • l represents a cross-sampling point.
  • the filter filters the matrix U, the sampling rate of the feedback signal can be reduced, thereby greatly simplifying the ADC acquisition bandwidth and the hardware requirements of the analog channel, saving hardware development costs and improving efficiency.
  • two sets of common feedback signal processing can be used. By selecting two sets of relatively close frequency bands to complete the common feedback processing, the minimum bandwidth of the third frequency intermodulation of the respective frequency bands can be collected, which can reduce the processing requirements of the ADC/DAC (Digital to Analog Converter), and The processing speed of an FPGA (Field-Programmable Gate Array) can be reduced.
  • ADC/DAC Digital to Analog Converter
  • FPGA Field-Programmable Gate Array
  • the original two-band signal is outputted by the power amplifier and the intermodulation and intermodulation information.
  • the multi-band uses F (1880 ⁇ 1915MHz) + A (2010 ⁇ 2025MHz) frequency band information as an example, its specific
  • the various intermodulation information and intermodulation information of F/A are shown in Fig. 7. Since the wide enough bandwidth signal cannot be collected, the incoming common feedback signal first filters out the third-order external intermodulation information, as shown in FIG. 8, so that the filtering bandwidth of the feedback signal is determined according to the sampling rate information, and the low-speed ADC can be used. Collect feedback signals.
  • the signal z(n) of the transmitted signal x(n) processed by the high-speed predistortion channel is as shown in the formula (1).
  • the acquired feedback signal is represented by y(n).
  • the predistortion processing model and the forward channel model are the same, and the predistortion coefficient w is also calculated by the following model. The calculation process is as follows:
  • the feedback signal y(n) needs to eliminate the rated linear gain G of the power amplifier, and obtain the signal u m,q,l(n) according to the formula (2 ) .
  • the LUT Look-Up-Table
  • the LUT represents a predistortion parameter index table
  • ) represents the signal amplitude
  • the LUT represents an index table of predistortion parameters.
  • the following describes the generation process of the LUT table:
  • the amplitude interval in the LUT table is generated as follows:
  • the storage space of one LUT is the length of A*(2L+1)*M.
  • ) is a predistortion parameter corresponding to the input original signal amplitude
  • the LUT is a lookup table that uses a fixed-point approach to store DPD coefficients.
  • the storage method of the embodiment of the present invention is one-dimensional, and the storage space of the LUT can be saved.
  • the above equations are overdetermined equations.
  • the solution of the linear equation is determined by the principle of least squares.
  • the matrix decomposition method or the fast Cholesky decomposition method is used to solve the matrix coefficients.
  • the depth M and the intermodulation order Q are calculated by configuration.
  • the combination of the autocorrelation matrix U and the interleaved sampling point is L.
  • U conv(U,pfir), filtering out the sideband intermodulation information that makes up the U matrix.
  • the above DPD common feedback implementation block diagram is shown in Figure 11.
  • the original signal is pre-distorted at high speed, and then output to the DAC, which is output to the power amplifier through the modulator, and the output signal of the power amplifier is collected, and after pre-distortion processing
  • the signal output effect of the PA is shown in Figure 12. From the two coordinate points marked in the figure, it can be seen that the APD effect (ACJ (Adjacent Channel Power Ratio) of the DPD is at least 53dBc (ie, two). The difference between the coordinate points in the Y direction). Satisfying the system requirements, although the distal end is tilted, it can be filtered by the antenna filter at this time.
  • ACJ Adjacent Channel Power Ratio
  • the hardware resources consumed by the multi-band pre-distortion can be greatly reduced, and when the two frequency bands are relatively close, the 2D-DPD system can be effectively replaced, and the one-dimensional
  • the LUT table replaces the two-dimensional LUT table, and the two-stage multiplier replaces the first-order multiplier. Therefore, the storage space of the LUT table can be reduced to more than 1/4 of the 2D-DPD, and the hardware multiplier can be reduced by half.
  • the requirement for the sampling rate of the feedback signal is reduced. For example, only 245 MHz is required for F+A common feedback, and the prior art requires at least an acquisition rate of 491 MHz, which saves hardware costs.
  • the embodiment of the present invention further provides a multi-band signal processing device, as shown in FIG.
  • the group module 131 is configured to combine signals of the frequency bands in the multi-band signal into a common feedback signal group;
  • the first processing module 132 is configured to perform common feedback processing on each of the common feedback signal groups
  • An acquisition module 133 configured to use a low-speed ADC to perform multi-band signals in each of the common feedback signal groups The number is collected, and the collected common feedback signal and the original training sequence are multi-interpolated;
  • the second processing module 134 is configured to perform predistortion processing on the common feedback signal by using a DPD model.
  • the collecting module uses a low-speed ADC to collect multi-band signals in each of the common feedback signal groups, specifically:
  • the common feedback signal of the common feedback signal group is acquired by a low speed ADC.
  • the collecting module performs multi-interpolation processing on the collected common feedback signal and the original training sequence, specifically:
  • the acquisition module performs 2x interpolation or 4x interpolation on the collected common feedback signal and the original training sequence, so that the common feedback signal is in a high-speed sampling state for signal correlation synchronization processing.
  • the second processing module is specifically configured to:
  • a DPD coefficient is obtained according to the autocorrelation matrix.
  • the embodiment of the present invention further provides a device, which can implement the process of multi-band signal processing in the embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.
  • the apparatus may include: a processor 1400, a memory 1420, a transceiver 1410, and a bus interface.
  • the processor 1400 is responsible for managing the bus architecture and general processing, and the memory 1420 can store data used by the processor 1400 in performing operations.
  • the transceiver 1410 is configured to receive and transmit data under the control of the processor 1400.
  • the bus architecture may include any number of interconnected buses and bridges, specifically linked by one or more processors represented by processor 1400 and various circuits of memory represented by memory 1420.
  • the bus architecture can also be used to make various other devices such as peripherals, voltage regulators, and power management circuits.
  • the links are linked together and these are well known in the art and, therefore, will not be further described herein.
  • the bus interface provides an interface.
  • Transceiver 1410 can be a plurality of components, including a transmitter and a transceiver, providing means for communicating with various other devices on a transmission medium.
  • the processor 1400 is responsible for managing the bus architecture and general processing, and the memory 1420 can store data used by the processor 1400 in performing operations.
  • the flow of the multi-band signal processing disclosed in the embodiment of the present invention may be applied to the processor 1400 or implemented by the processor 1400.
  • each step of the process of multi-band signal processing may be completed by an integrated logic circuit of hardware in the processor 1400 or an instruction in a form of software.
  • the processor 1400 can be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can be implemented or executed in an embodiment of the invention.
  • a general purpose processor can be a microprocessor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented as a hardware processor, or may be performed by a combination of hardware and software modules in the processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 1420, and the processor 1400 reads the information in the memory 1420 and performs the steps of multi-band signal processing in conjunction with its hardware.
  • the processor 1400 is configured to read a program in the memory 1420 and perform the following process:
  • the common feedback signal is predistorted by a DPD model.
  • the processor 1400 reads the program in the memory 1420 and performs the following process:
  • the common feedback signal of the common feedback signal group is acquired by a low speed ADC.
  • the processor 1400 reads the program in the memory 1420 and performs the following process:
  • the acquired common feedback signal and the original training sequence are subjected to 2 ⁇ interpolation or 4 ⁇ interpolation to perform signal correlation synchronization processing in the high-speed sampling state.
  • the processor 1400 reads the program in the memory 1420 and performs the following process:
  • a DPD coefficient is obtained according to the autocorrelation matrix.
  • the present invention can be implemented by hardware or by means of software plus a necessary general hardware platform.
  • the technical solution of the present invention may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including several The instructions are for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various implementation scenarios of the present invention.
  • modules in the apparatus in the implementation scenario may be distributed in the apparatus for implementing the scenario according to the implementation scenario description, or may be correspondingly changed in one or more devices different from the implementation scenario.
  • the modules of the above implementation scenarios may be combined into one module, or may be further split into multiple sub-modules.

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Abstract

本发明公开了一种多频段信号处理方法，在将多频段信号中频段较近的信号互相组成共反馈信号组后，对各共反馈信号组进行共反馈处理，利用低速ADC对各共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理，最后通过DPD模型对共反馈信号进行预失真处理。并在处理过程中根据多阶交调信息对自相关U矩阵进行滤波处理，滤除组成U矩阵远端边带的交调和互调信息。从而降低了多频段预失真所消耗的硬件资源。

Description

一种多频段信号处理方法及设备
本申请要求在2015年3月5日提交中国专利局、申请号为201510098512.0、发明名称为“一种多频段信号处理方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，尤其涉及一种多频段信号处理方法及设备。
背景技术
随着技术的不断发展，对于一个基站***来说，其将要支持2频段以上3频段或者4频段，其中每一个频段超宽频信号都需要进行数字预失真处理。
对于多频段的预失真架构，以两频段信号为例，两频段功率输出存在三种交调和互调，一种是带内交调(in-band intermodulation)，带外交调(out-of-band intermodulation)和频段间互调(cross modulation)，这三种调制信号的频带分布如图1所示。其中的(a)示出了输入信号，(b)示出了输出信号，输入信号的两个频段ω1和ω2的频率间隔Δω＝ω2-ω1，由于频率间隔Δω较大，所以带外交调产物离输入信号频点较远，从而容易滤除，剩下的失真仅包括带内交调和频段间互调。
如图2所示，为现有技术中双频段小区的DPD(Digital Pre-Distortion，数字预失真)处理框图，该双频段DPD***架构包括信号提取和分析阶段(the signal extraction and analysis stage)、处理阶段(the processing stage)以及综合阶段(the synthesis stage)。虽然现有技术针对多频段采用2D-DPD(2Dimensional DPD，二维数字预失真)技术或者更为复杂的2D-TCMP-DPD(2Dimensional Time Cross Memory Polynomial DPD，二维时间交叉记忆多项式数字预失真)模型，虽然能够完成对多频段信号的预失真处理，但是处理复杂，所需的硬件资源消耗比较大。
发明内容
本发明实施例提供了一种简化反馈信号采样速率、优化反馈信号矩阵U的多频段信号处理方法，从而节省了硬件资源。该方法包括：
将多频段信号中频段较近的信号互相组成共反馈信号组；
对每个所述共反馈信号组进行共反馈处理；
利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
通过DPD模型对所述共反馈信号进行预失真处理。
优选地，利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，包括：
滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息；
通过低速ADC采集所述共反馈信号组的共反馈信号。
优选地，将采集得到的共反馈信号以及原始训练序列进行多倍内插处理，包括：
将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插。
优选地，通过DPD模型对所述共反馈信号进行预失真处理，包括：
将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵；
滤除组成所述自相关矩阵的边带交调信息；
根据所述自相关矩阵获取DPD系数。
相应地，本发明实施例还提出了一种多频段信号处理设备，其特征在于，包括：
合组模块，用于将多频段信号中频段较近的信号互相组成共反馈信号组；
第一处理模块，用于对每个所述共反馈信号组进行共反馈处理；
采集模块，用于利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
第二处理模块，用于通过DPD模型对所述共反馈信号进行预失真处理。
优选地，所述采集模块，具体用于：
滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息；
通过低速ADC采集所述共反馈信号组的共反馈信号。
优选地，所述采集模块，具体用于：
所述采集模块将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插，以使所述共反馈信号处于高速采样状态下进行信号相关同步处理。
优选地，所述第二处理模块具体用于：
将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵；
滤除组成所述自相关矩阵的边带交调信息；
根据所述自相关矩阵获取DPD系数。
相应地，本发明实施例还提出了一种多频段信号处理设备，其特征在于，包括：处理器，收发机和存储器；
其中，收发机用于在处理器的控制下接收和发送数据；
存储器用于保存处理器执行操作时所使用的数据；
处理器可以用于读取存储器中的程序，执行下列过程：
将多频段信号中频段较近的信号互相组成共反馈信号组；
对各所述共反馈信号组进行共反馈处理；
利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
通过DPD模型对所述共反馈信号进行预失真处理。
优选地，为利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，处理器读取存储器中的程序，执行下列过程：
滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息；
通过低速ADC采集所述共反馈信号组的共反馈信号。
优选地，为将采集得到的共反馈信号以及原始训练序列进行多倍内插处理，处理器读取存储器中的程序，执行下列过程：
将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插，以使所述共反馈信号处于高速采样状态下进行信号相关同步处理。
优选地，为通过DPD模型对所述共反馈信号进行预失真处理，处理器读取存储器中的程序，执行下列过程：
将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵；
滤除组成所述自相关矩阵的边带交调信息；
根据所述自相关矩阵获取DPD系数。
由此可见，通过应用本发明实施例的技术方案，在将多频段信号中频段较近的信号互相组成共反馈信号组后，对各共反馈信号组进行共反馈处理，利用低速ADC对各共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理，最后通过DPD模型对共反馈信号进行预失真处理。从而降低了多频段预失真所消耗的硬件资源。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中双频段发射机的功率谱信号示意图；
图2为现有技术中双频段小区的DPD处理框图；
图3为本发明实施例提出的一种多频段信号处理方法的流程示意图；
图4为本发明具体实施例所提出的一种通过对反馈信号矩阵滤波后简化DPD处理装置流程示意图；
图5为本发明具体实施例中FAED四个频段2组共反馈频段的组合示意图；
图6为本发明具体实施例中原始的两频段信号通过功放后输出的交调和互调信息示意图；
图7为本发明具体实施例中双频段内的最低有效采集的交调和互调频段信息示意图；
图8为本发明具体实施例中进入ADC之前的反馈信号示意图；
图9为本发明具体实施例中ADC低速采集后的信号频谱图；
图10为本发明具体实施例中反馈信号和训练序列内插滤波之后的频谱图；
图11为本发明具体实施例中DPD共反馈实现框图；
图12为本发明具体实施例中共反馈DPD后的效果图；
图13为本发明实施例提出的一种多频段信号处理设备的结构示意图；
图14为本发明实施例提供的一种多频段信号处理设备的结构示意图。
具体实施方式
如背景技术所述，现有技术针对多频段采用的预失真处理方法能够完成对多频段信号的预失真处理，但是处理复杂，所需的硬件资源消耗比较大。为此本发明实施例提供了一种多频段信号处理方法，通过优化反馈信号矩阵，从而节省硬件资源的算法装置，并且使得更多频段之间的载波聚合提供了可能。如图3所示，该方法包括以下步骤：
S301，将多频段信号中频段较近的信号互相组成共反馈信号组。
S302，对各所述共反馈信号组进行共反馈处理。
对于多频信号，本发明实施例首先对其进行S301-S302的双频段共反馈处理，这样采用低速反馈ADC(Analog-to-digital converter，模拟数字转换器)采集器和低速DAC发射器即可完成宽带宽信号的预失真处理并且也能够降低发射DAC的要求。
S303，利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理。
在本发明优选的实施例中，该步骤首先滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息，随后通过低速ADC采集所述共反馈信号组的 共反馈信号。
此外，对于内插处理流程，本发明优选的实施例通过将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插，以使所述共反馈信号处于高速采样状态下进行信号相关同步处理。
在通过以上处理之后将反馈采集回来的信号和原始信号进行多次内插滤波后，后续即可选择宽频带有时间交叉项的记忆多项式模型进行DPD系数的计算。
S304，通过DPD模型对所述共反馈信号进行预失真处理。
对反馈信号组成的U矩阵进行滤波处理，这样使得矩阵的交调信息U和反馈信息对应，对矩阵求逆中的U矩阵进行滤波。由于有多阶交调信息，故此可以对自相关U矩阵进行滤波处理。从而滤除组成U矩阵的边带交调信息。
具体地，该步骤首先将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵，随后滤除组成所述自相关矩阵的边带交调信息，再根据所述自相关矩阵获取DPD系数。其中，滤除处理主要是用于滤除组成U矩阵远端边带的交调和互调信息，远端交调信息一般是指3阶交调边带外信息。
为了进一步阐述本发明实施例的技术思想，现结合如图4所示的具体流程示意图，对本发明实施例的技术方案进行说明。
首先多个频段信号进行预失真处理，把邻近的频段信号合并形成共反馈，采集各自带宽的3阶交调，带外信息被ADC前面的抗混叠滤波器滤除。
其次采用相对低速ADC采集多频段信号，然后对反馈信号和训练序列均进行内插后开始预失真系数的训练。
然后完成反馈信号和训练序列的幅度校准，采样点对齐等校准工作。因为多频段信号模型交调和互调比较复杂，为此采用PVS模型中的一种时间交叉记忆多项式模型(TCMP)：
Figure PCTCN2016075642-appb-000001
在公式(1)中，z(n)表示n时刻输出的经过预失真处理后的信号，x(n)表示n时刻输入的原始信号，n表示原始信号的输入时刻，m表示原始信号的记忆时刻，w表示预失真参数，M表示记忆深度，Q表示非线性阶数，L表示最大交叉采样点，q表示非线性阶数索引。
之后反馈信号y需消除功放额定线性增益，得到信号u
Figure PCTCN2016075642-appb-000002
Figure PCTCN2016075642-appb-000003
um,q,l(n)表示消除功放额定线性增益的第一反馈信号，G表示额定线性增益，n表示第一反馈信号的输入时刻，m表示第一反馈信号的记忆时刻，M表示记忆深度，Q表示非线性阶数，L表示最大交叉采样点，q表示非线性阶数索引，l表示交叉采样点。
根据得到的u，对其进行滤波处理，滤除组成U矩阵的边带交调信息，其中，U＝conv(U,pfir)，通过此滤波处理，就和前面的反馈信号滤波对应，最后通过矩阵
Figure PCTCN2016075642-appb-000004
求逆得到DPD系数。
由于滤波器对矩阵U进行了滤波处理，从而能够降低反馈信号的采样速率，从而大大简化ADC采集带宽和对模拟通道的硬件要求，节省了硬件开发成本，提高效率。
由于多频段***中的不同频段之间的聚合会越来越多，以图5所示的4个频段信号为例，可以采用2组共反馈信号处理。通过挑选两组相对较近的频段完成共反馈的处理，能够采集的最小带宽各自频段的3阶交调，这样能够降低ADC/DAC(Digital to analog converter，数字模拟转换器)的处理要求，并且能够降低FPGA(Field－Programmable Gate Array，现场可编程门阵列)的处理速度。
如图6所示，为原始的两频段信号通过功放后输出的交调和互调信息。该多频段以F(1880～1915MHz)+A(2010～2025MHz)频段信息为例，其具体的 F/A的各种交调信息和互调信息如图7所示。由于无法采集到足够宽的带宽信号，故此进入的共反馈信号首先滤除3阶外部互调信息，如图8示意，这样根据采样速率的信息决定反馈信号的滤除带宽，能够采用低速的ADC采集反馈信号。
进入低速ADC信号带采集到的信号频谱如图9所示，而经过2被内插的共反馈信号和训练序列2倍内插滤波之后的原始信号频谱图则如图10所示，至此得到共反馈的F+A信号之后，再次对反馈信号和原始训练序列进行多倍内插(2倍或者4倍内插)，使得信号处于高速采样状态下进行信号相关同步处理。同步相关处理完成之后，由于两个频段占用的信号带宽较宽，故此需要采用DPD模型来完成对多频段宽频信号的预失真处理，具体流程如下：(其中x(n)为输入预失真器的中频信号)
(1)发射信号x(n)经过高速预失真通道处理后的信号z(n)有如公式(1)所示。
在该具体实施例中，用y(n)表示采集的反馈信号，经过的预失真处理模型和前向通道的模型一样，也是通过如下模型来计算预失真系数w，计算过程如下：
Figure PCTCN2016075642-appb-000005
(2)为了保持功率平衡，反馈信号y(n)需消除功放额定线性增益G，根据公式(2)得到信号um,q,l(n)。
(3)上述信号的矩阵表示如下：
反馈信号：
Figure PCTCN2016075642-appb-000006
参考信号：
z＝Uw，z＝[z(0),…,z(N-1)]T
目标DPD系数：
w＝[w1000,…,wM000,…,w1Q00,…,wMQLL]T
(4)目标DPD系数的最小二乘解表示如下：
Figure PCTCN2016075642-appb-000007
在得到预失真系数之后，根据预失真系数W得到LUT(Look-Up-Table，显示查找表)表最终如下，此时仅仅是一维表就可以完成DPD系数的更新。
Figure PCTCN2016075642-appb-000008
其中，LUT表示预失真参数索引表，LUTm(|x(n-m)|)表示原始信号的信号幅值|x(n-m)|在LUT表中所对应的预失真参数。
首先，LUT表示预失真参数的索引表，为了便于理解，以下对LUT表的生成过程进行简要说明：
假设输入信号最大值为mv＝max(|y(n)|)，LUT的最大尺寸A，那么LUT表中的幅度间隔是
Figure PCTCN2016075642-appb-000009
在上述假设的基础上LUT的生成方式如下：
Figure PCTCN2016075642-appb-000010
根据上式可知，一个LUT的存储空间是A*(2L+1)*M的长度。
LUTm(|x(n-m)|)是按照输入的原始信号幅度|x(n-m)|为索引对应的预失真参数，而又因为：
Figure PCTCN2016075642-appb-000011
Figure PCTCN2016075642-appb-000012
Figure PCTCN2016075642-appb-000013
其中LUT是查找表，使用定点化方式来存储DPD系数。使用本发明实施例存储方式是一维的，能够节省LUT的存储空间。
由于采样点的数目N多于模型系数个数，因此上述方程组为超定方程组。为此，这里应用最小二乘原理确定线性方程的解，实际过程中采用矩阵的QR分解方法或者快速Cholesky分解方法求解矩阵系数。对于PVS模型，通过配置，记忆深度M，交调阶数Q。交错采样点为L就可以完成自相关矩阵U和的组合。其中U矩阵中的元素u＝um,q,l1，由于有多阶交调信息，故此可以对U矩阵进行滤波处理。U＝conv(U,pfir)，滤除组成U矩阵的边带交调信息。
以上DPD共反馈实现框图如图11所示，在采用上述一系列方法之后，对原始信号进行高速预失真，然后输出给DAC，通过调制器输出给功放，采集功放输出信号，通过预失真处理后经过PA的信号输出效果如图12所示，从图中标记的两个坐标点可以看出共反馈后的DPD效果ACPR(Adjacent Channel Power Ratio，邻信道功率比)至少可以达到53dBc左右(即两个坐标点在Y方向的差值)。满足***要求，虽然远端有翘起，但是此时能够通过天线滤波器给予滤除。
基于上述流程可以看出，通过应用本发明的技术方案，能够极大的降低多频段预失真所消耗的硬件资源，在两个频段相离较近时，能够有效取代2D-DPD***，一维LUT表代替二维LUT表，两级乘法器代替一级乘法器。从而LUT表的存储空间能够降低到2D-DPD的1/4以上，硬件乘法器能够降低一半。对反馈信号的采样速率的要求降低，例如F+A共反馈时仅仅需要采集245MHZ，现有技术至少需要采集速率491MHZ，这样节省硬件成本。
为达到以上技术目的，本发明实施例还提出了一种多频段信号处理设备，如图13所示，包括：
合组模块131，用于将多频段信号中频段较近的信号互相组成共反馈信号组；
第一处理模块132，用于对各所述共反馈信号组进行共反馈处理；
采集模块133，用于利用低速ADC对各所述共反馈信号组内的多频段信 号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
第二处理模块134，用于通过DPD模型对所述共反馈信号进行预失真处理。
在具体的应用场景中，所述采集模块利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，具体为：
滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息；
通过低速ADC采集所述共反馈信号组的共反馈信号。
在具体的应用场景中，所述采集模块将采集得到的共反馈信号以及原始训练序列进行多倍内插处理，具体为：
所述采集模块将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插，以使所述共反馈信号处于高速采样状态下进行信号相关同步处理。
在具体的应用场景中，所述第二处理模块具体用于：
将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵；
滤除组成所述自相关矩阵的边带交调信息；
根据所述自相关矩阵获取DPD系数。
基于相同的技术构思，本发明实施例还提供了一种装置，该装置可以实现本发明实施例多频段信号处理的流程。
参见图14，为本发明实施例提供的装置的结构示意图，该装置可包括：处理器1400、存储器1420、收发机1410以及总线接口。
处理器1400负责管理总线架构和通常的处理，存储器1420可以存储处理器1400在执行操作时所使用的数据。收发机1410用于在处理器1400的控制下接收和发送数据。
总线架构可以包括任意数量的互联的总线和桥，具体由处理器1400代表的一个或多个处理器和存储器1420代表的存储器的各种电路链接在一起。总线架构还可以将诸如***设备、稳压器和功率管理电路等之类的各种其他电 路链接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口提供接口。收发机1410可以是多个元件，即包括发送机和收发机，提供用于在传输介质上与各种其他装置通信的单元。处理器1400负责管理总线架构和通常的处理，存储器1420可以存储处理器1400在执行操作时所使用的数据。
本发明实施例揭示的多频段信号处理的流程，可以应用于处理器1400中，或者由处理器1400实现。在实现过程中，多频段信号处理的流程的各步骤可以通过处理器1400中的硬件的集成逻辑电路或者软件形式的指令完成。处理器1400可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1420，处理器1400读取存储器1420中的信息，结合其硬件完成多频段信号处理的步骤。
具体地，处理器1400，用于读取存储器1420中的程序，执行下列过程：
将多频段信号中频段较近的信号互相组成共反馈信号组；
对各所述共反馈信号组进行共反馈处理；
利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
通过DPD模型对所述共反馈信号进行预失真处理。
优选地，为利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，处理器1400读取存储器1420中的程序，执行下列过程：
滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息；
通过低速ADC采集所述共反馈信号组的共反馈信号。
优选地，为将采集得到的共反馈信号以及原始训练序列进行多倍内插处理，处理器1400读取存储器1420中的程序，执行下列过程：
将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插，以使所述共反馈信号处于高速采样状态下进行信号相关同步处理。
优选地，为通过DPD模型对所述共反馈信号进行预失真处理，处理器1400读取存储器1420中的程序，执行下列过程：
将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵；
滤除组成所述自相关矩阵的边带交调信息；
根据所述自相关矩阵获取DPD系数。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到本发明可以通过硬件实现，也可以借助软件加必要的通用硬件平台的方式来实现。基于这样的理解，本发明的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施场景所述的方法。
本领域技术人员可以理解附图只是一个优选实施场景的示意图，附图中的模块或流程并不一定是实施本发明所必须的。
本领域技术人员可以理解实施场景中的装置中的模块可以按照实施场景描述进行分布于实施场景的装置中，也可以进行相应变化位于不同于本实施场景的一个或多个装置中。上述实施场景的模块可以合并为一个模块，也可以进一步拆分成多个子模块。
上述本发明序号仅仅为了描述，不代表实施场景的优劣。
以上公开的仅为本发明的几个具体实施场景，但是，本发明并非局限于此，任何本领域的技术人员能思之的变化都应落入本发明的保护范围。

Claims (9)

  1. 一种多频段信号处理方法，其特征在于，包括：
    将多频段信号中频段较近的信号互相组成共反馈信号组；
    对每个所述共反馈信号组进行共反馈处理；
    利用低速模拟数字转换器ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
    通过数字预失真DPD模型对所述共反馈信号进行预失真处理。
  2. 如权利要求1所述的方法，其特征在于，利用低速ADC对各所述共反馈信号组内的多频段信号进行采集，包括：
    滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息；
    通过低速ADC采集所述共反馈信号组的共反馈信号。
  3. 如权利要求1所述的方法，其特征在于，将采集得到的共反馈信号以及原始训练序列进行多倍内插处理，包括：
    将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插。
  4. 如权利要求1所述的方法，其特征在于，通过DPD模型对所述共反馈信号进行预失真处理，包括：
    将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵；
    滤除组成所述自相关矩阵的边带交调信息；
    根据所述自相关矩阵获取DPD系数。
  5. 一种多频段信号处理设备，其特征在于，包括：
    合组模块，用于将多频段信号中频段较近的信号互相组成共反馈信号组；
    第一处理模块，用于对每个所述共反馈信号组进行共反馈处理；
    采集模块，用于利用低速模拟数字转换器ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
    第二处理模块，用于通过数字预失真DPD模型对所述共反馈信号进行预 失真处理。
  6. 如权利要求5所述的设备，其特征在于，所述采集模块，具体用于：
    滤除各所述共反馈信号组内的多频段信号的3阶外部互调信息；
    通过低速ADC采集所述共反馈信号组的共反馈信号。
  7. 如权利要求5所述的设备，其特征在于，所述采集模块，具体用于：
    将采集得到的共反馈信号以及原始训练序列进行2倍内插或4倍内插。
  8. 如权利要求5所述的设备，其特征在于，所述第二处理模块具体用于：
    将所述共反馈信号通过消除功放额定线性增益处理生成自相关矩阵；
    滤除组成所述自相关矩阵的边带交调信息；
    根据所述自相关矩阵获取DPD系数。
  9. 一种多频段信号处理设备，其特征在于，包括：处理器、存储器和收发机；
    所述收发机，用于在所述处理器的控制下接收和发送数据；
    所述存储器，用于保存处理器执行操作时所使用的数据；
    所述处理器，用于读取所述存储器中的程序，执行下列过程：
    将多频段信号中频段较近的信号互相组成共反馈信号组；
    对各所述共反馈信号组进行共反馈处理；
    利用低速模拟数字转换器ADC对各所述共反馈信号组内的多频段信号进行采集，并将采集得到的共反馈信号以及原始训练序列进行多倍内插处理；
    通过数字预失真DPD模型对所述共反馈信号进行预失真处理。
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