WO2016056655A1 - Procédé de fabrication d'un dispositif semiconducteur - Google Patents

Procédé de fabrication d'un dispositif semiconducteur Download PDF

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Publication number
WO2016056655A1
WO2016056655A1 PCT/JP2015/078802 JP2015078802W WO2016056655A1 WO 2016056655 A1 WO2016056655 A1 WO 2016056655A1 JP 2015078802 W JP2015078802 W JP 2015078802W WO 2016056655 A1 WO2016056655 A1 WO 2016056655A1
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Prior art keywords
temperature
semiconductor device
filler composition
interlayer filler
semiconductor
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PCT/JP2015/078802
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English (en)
Japanese (ja)
Inventor
慎 池本
河瀬　康弘
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三菱化学株式会社
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    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G59/00—Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device by thermocompression bonding a semiconductor chip having solder bumps and a semiconductor substrate having electrode pads by means of a thermocompression bonding apparatus via an interlayer filler composition.
  • a plurality of substrates such as a semiconductor substrate on which a semiconductor device layer is formed and an organic substrate are placed perpendicular to the substrate surface.
  • Multilayer semiconductor devices are known in which a semiconductor substrate and an organic substrate are stacked. More specifically, semiconductor substrates are connected to each other with electrical signal terminals such as solder bumps between the substrates.
  • a three-dimensional stacked semiconductor device having a structure in which an interlayer filler composition is filled between substrates and the substrates are bonded to each other by an interlayer filler composition layer is known.
  • a layer made of an inter-layer filler composition (ICF: Inter Chip Fill) is formed on a wafer on which a semiconductor device layer is formed, and heated to be B-staged as necessary. Then, the chip is cut out by dicing, the obtained semiconductor substrates are stacked, a plurality of temporary bondings are repeated by pressure heating, and finally the pre-application method (Pre- A process based on applied process has been proposed (see, for example, Non-Patent Document 1).
  • ICF Inter Chip Fill
  • FIG. 2 is a perspective view showing a method of manufacturing a semiconductor device by the pre-applied method, and an interlayer filling is performed by a coating nozzle 4 on a semiconductor chip 2 on which a plurality of solder bumps 1 composed of land terminals 1A and solder 1B are formed.
  • the agent composition 3 FIG. 2 (a)
  • the interlayer filler composition layer 5 FIG. 2 (b)
  • the B-stage is formed, and the interlayer filler composition
  • the semiconductor chip 2 on which the physical layer 5 is formed is reversed, and the interlayer filler composition is placed on the semiconductor substrate 7 on which the electrode pad 6 is formed, which is placed on the stage (not shown) of the thermocompression bonding apparatus.
  • the layer 5 side is made to oppose, and it presses with the head which is not illustrated (illustration 2 (c)).
  • the interlayer filler composition is cured, and the semiconductor is interposed through the cured adhesive layer 8 of the interlayer filler composition.
  • a semiconductor device 10 in which the chip 2 and the semiconductor substrate 7 are bonded can be obtained (FIG. 2D).
  • the stacked semiconductor device repeats such a process, and an electrode pad is formed on the surface of the semiconductor chip 10 of the semiconductor device 10 shown in FIG. 2D (in this case, the surface opposite to the cured adhesive layer 8 of the semiconductor chip 2). 2) is further manufactured by repeating the step of bonding the semiconductor chip 2 on which the interlayer filler composition layer 5 shown in FIG. 2B is formed.
  • Voids occur in the cured adhesive layer.
  • the generation of voids is thought to be caused by the low-molecular components in the interlayer filler composition volatilizing under the heating conditions of the bonding process and curing process, but if voids exist in the cured adhesive layer, electrical bonding
  • the shrinkage difference such as temperature change is increased, and the adhesion surface is peeled off or cracked, so that the performance as a semiconductor device is impaired.
  • the interlayer filler composition layer is formed by supplying the interlayer filler composition 3 on the semiconductor chip 2 on which the solder bumps 1 are formed as shown in FIG. Even if the agent composition 3 does not reach the narrow gap between the solder bumps 1 and 1 sufficiently, a void portion that becomes a void is formed similarly to the above (1), and the same problem as described above occurs.
  • the present invention is excellent in bondability and conductivity without producing voids (voids) in the cured adhesive layer when bonding between a semiconductor chip and a semiconductor chip or between a semiconductor chip and a semiconductor chip in the manufacture of a semiconductor device.
  • Another object of the present invention is to provide a method for manufacturing a high-quality and highly reliable semiconductor device by forming a cured adhesive layer.
  • the gist of the present invention is as follows.
  • Formula 1 H + 0.526S 310
  • Formula 2 H + 0.8S 580
  • Formula 3 H + 1.25S 725
  • Formula 4 (In formulas 1 to 4, H represents the head temperature (° C.) during bonding, and S represents the stage temperature (° C.) during bonding.)
  • thermocompression bonding apparatus having a head and a stage capable of individually adjusting the temperature.
  • Formula 1 H + 0.526S 310
  • Formula 2 H + 0.8S 580
  • Formula 3 H + 1.25S 725
  • Formula 4 (In formulas 1 to 4, H represents the head temperature (° C.) during bonding, and S represents the stage temperature (° C.) during bonding.)
  • thermocompression bonding apparatus In a method of manufacturing a semiconductor device, including a step of bonding a semiconductor chip having solder bumps and a semiconductor substrate having electrode pads using a thermocompression bonding apparatus via an interlayer filler composition, the thermocompression bonding apparatus The solder bump and electrode pad are brought into contact with each other when the temperature of only one of the head and the stage is 120 ° C. or higher. After the solder bump and the electrode pad are in contact, the contact between the solder bump and the electrode pad on the head or stage A method for manufacturing a semiconductor device, wherein the temperature on the side that is sometimes less than 120 ° C. is set to be equal to or higher than the melting point of solder.
  • the interlayer filler composition is pre-applied to a semiconductor chip or a semiconductor substrate that is set on the side of the head or stage that is less than 120 ° C. at the time of contact between the solder bump and the electrode pad. 10].
  • the present invention in the manufacture of a semiconductor device, when bonding between a semiconductor chip and a substrate, or between a semiconductor chip and a semiconductor chip, no bonding (void) occurs in the cured adhesive layer, and the bonding property and conductivity Therefore, a high-quality and highly reliable semiconductor device can be manufactured. According to the present invention, it is possible to further increase the speed and capacity of the stacked semiconductor device.
  • FIG. 2A is a view showing an operation for applying an interlayer filler composition to a semiconductor chip.
  • FIG. 2B is a view showing a semiconductor chip having an interlayer filler composition layer.
  • FIG. 2 (c) is a diagram showing an operation of heat-pressure bonding a semiconductor chip having an interlayer filler composition layer onto a semiconductor substrate using a thermocompression bonding apparatus (not shown).
  • FIG. 2D is a view of a semiconductor device in which a semiconductor chip and a semiconductor substrate are bonded via a cured adhesive layer of an interlayer filler composition.
  • FIG. 3A is a photograph of the appearance of the semiconductor device manufactured in Example 25, and FIG. 3B is a photograph of the same cross section.
  • an interlayer filler composition used for bonding a semiconductor chip having solder bumps and a semiconductor substrate having electrode pads may be referred to as an “interlayer filler composition”.
  • the “semiconductor chip” and “semiconductor substrate” in the present invention may be collectively referred to as “substrate”.
  • the semiconductor chip and the semiconductor substrate are made of any material that can be normally used as a semiconductor substrate in the manufacture of an integrated circuit.
  • the substrate on which the solder bump is formed is connected to the “semiconductor chip” and the solder bump.
  • a substrate on which an electrode pad is formed is called a “semiconductor substrate”.
  • the semiconductor chip and the semiconductor substrate may be provided with a through electrode (hereinafter sometimes abbreviated as TSV), a semiconductor element circuit, and the like, and are connected between the substrates via solder bumps and electrode pads.
  • TSV through electrode
  • the substrate may be regarded as a semiconductor chip or a semiconductor substrate.
  • a single substrate is not considered as a “semiconductor chip” and a “semiconductor substrate” at the same time.
  • thermocompression bonding apparatus In the method for producing a semiconductor device of the present invention, a thermocompression bonding apparatus is used to heat and press-bond a semiconductor chip having solder bumps and a semiconductor substrate having electrode pads via an interlayer filler composition described later.
  • the temperature of the head and the stage of the thermocompression bonding apparatus is bonded as a temperature condition in the range surrounded by the following four formulas in a graph in which the head temperature shown in FIG. 1 is the vertical axis and the stage temperature is the horizontal axis. It is characterized by that.
  • the head temperature is the temperature of the heater of the head of the thermocompression bonding apparatus
  • the stage temperature is the temperature of the heater of the stage of the thermocompression bonding apparatus.
  • H + 1.9S 590 ...
  • H represents the head temperature (° C.) during bonding
  • S represents the stage temperature (° C.) during bonding.
  • the temperatures of the head and the stage of the thermocompression bonding apparatus are individually adjusted, and bonding is performed as a temperature condition within the range surrounded by the above four equations. Therefore, it is distinguished from a bonding method in which the substrates to be bonded are put in a furnace or the like typified by a high-temperature bath and the whole is heated. However, it does not exclude that the temperature of the head and the stage becomes the same as a result of the individual temperature adjustment.
  • a thermocompression bonding apparatus having a head and a stage capable of individually adjusting the temperature a thermocompression bonding apparatus “Flip Chip Bonder (FC3000S)” manufactured by Toray Engineering Co., Ltd. used in the examples described later can be used.
  • the temperature of the head and stage that are individually temperature-controlled is either because the time required to raise their temperature can be shortened to increase production efficiency or to reduce the energy required for temperature increase.
  • One is preferably lower than the other.
  • the head temperature and the stage temperature are preferably different.
  • the above temperature condition may be employed for bonding by the thermocompression bonding apparatus, but the stage temperature is preferably 70 to 500 ° C., and 100 to 450 in order to sufficiently exhibit the functions required for the interlayer material. ° C is more preferable, 120 to 430 ° C is more preferable, the head temperature is preferably 70 to 500 ° C, more preferably 100 to 450 ° C, and still more preferably 120 to 430 ° C. Further, the temperature of the head and the stage is preferably higher than a certain point in order to ensure electrical bonding, and at least one of them is preferably higher than 225 ° C., more preferably 230 ° C. or higher. More preferred is 235 ° C. or higher.
  • the applied pressure in the bonding step under the above specific temperature condition is 0.1 to 50 kgf / cm 2 , particularly preferably 0.1 to 10 kgf / cm 2 .
  • the heating and pressing time is 0.1 to 30 seconds, and preferably 0.5 to 10 seconds. Note that after the heat and pressure bonding by the thermocompression bonding apparatus, it may be once removed from the apparatus, cooled to room temperature, and then cured by heating to 100 to 200 ° C.
  • the semiconductor device manufacturing method of the present invention includes a semiconductor chip and an electrode pad having solder bumps according to a conventional method, except that the temperature and temperature of the head and stage of the thermocompression bonding apparatus are individually adjusted and the above temperature conditions are adopted. It is possible to perform bonding with a semiconductor substrate having For example, as shown in FIG. 2A, the interlayer filling of the present invention is applied from a coating nozzle 4 onto a semiconductor substrate (semiconductor chip) 2 on which a plurality of solder bumps 1 composed of land terminals 1A and solder 1B are formed. By supplying the agent composition 3, as shown in FIG.2 (b), after forming the interlayer filler composition layer 5, B-stage is performed as needed.
  • the semiconductor chip 2 on which the interlayer filler composition layer 5 was formed was turned upside down and placed on a stage (not shown) of a thermocompression bonding apparatus, as shown in FIG.
  • the interlayer filler composition layer 5 side is opposed to the semiconductor substrate 7 on which the electrode pads 6 are formed, and pressed by a head (not shown).
  • the interlayer filler composition is cured by heating and pressurizing the semiconductor substrate 7 and the semiconductor chip 2 between the head and the stage of the thermocompression bonding apparatus under the above temperature conditions, as shown in FIG.
  • the semiconductor device 10 is obtained in which the semiconductor chip 2 and the semiconductor substrate 7 are bonded via the cured adhesive layer 8 of the interlayer filler composition.
  • a stacked semiconductor device having a plurality of semiconductor chips 2 repeats such a process, and the semiconductor chip 2 of the semiconductor device 10 shown in FIG. 2D (in this case, opposite to the cured adhesive layer 8 of the semiconductor chip 2).
  • the electrode pad is formed on the side surface.) Further, it is manufactured by repeating the step of bonding the semiconductor chip 2 formed with the interlayer filler composition layer 5 shown in FIG. Can do.
  • the first semiconductor chip is regarded as the semiconductor substrate in the present invention
  • the second semiconductor chip is in the present invention. It is regarded as a semiconductor chip.
  • a substrate made of any material that can be used as a semiconductor substrate in the manufacture of an integrated circuit can be used.
  • a silicon substrate is preferably used.
  • the silicon substrate may be used as it is depending on the diameter of the substrate, or may be used after being thinned to 100 ⁇ m or less by backside polishing such as backside etching or backgrinding. good.
  • Fine solder balls may be used to form solder bumps, and after forming openings by lithography, solder plating is performed directly on the base of the openings or after nickel or copper posts are formed, After removing the resist material, solder bumps may be formed by heat treatment.
  • the solder composition is not particularly limited, but a solder containing tin as a main component is preferably used in consideration of electrical bondability and low-temperature bondability.
  • the land terminal can be formed by forming a thin film on the substrate using PVD (Physical Vapor Deposition) or the like and then removing unnecessary portions by lithography resist film formation and dry or wet etching. .
  • the material of the land terminal is not particularly limited as long as it can be bonded to the solder bump, but gold, copper, nickel and the like can be preferably used in consideration of the bonding property and reliability to the solder.
  • the interlayer filler composition layer by the pre-apply method can be formed by a conventionally known forming method, for example, a dip method, a spin coat method, a spray coat method, a blade method, or any other method.
  • the interlayer filler composition layer may be formed on the side of the semiconductor chip 2 having solder bumps as shown in FIG. 2, or may be formed on the side of the semiconductor substrate 7 having electrode pads as in the examples described later. Alternatively, they may be formed on both of them.
  • this amount of supply The interlayer filler composition may be applied so as to be.
  • a B-stage process may be performed by performing a baking process at an arbitrary temperature of 60 to 130 ° C.
  • the baking treatment may be performed at a constant temperature, but in order to smoothly remove the volatile components in the composition, the baking treatment may be performed under reduced pressure conditions.
  • a baking process by stepwise temperature rise may be performed within a range in which the curing of the resin does not proceed. For example, baking can be performed for 5 to 90 minutes each at 60 ° C., then at 80 ° C., and further at 120 ° C.
  • thermocompression bonding apparatus Manufacturing of a semiconductor device having a step of joining a semiconductor chip having a solder bump and a semiconductor substrate having an electrode pad using a thermocompression bonding apparatus through an interlayer filler composition, as typified by the present invention
  • the conditions of the various processes before the bonding are also independently important for manufacturing a high-quality semiconductor device.
  • a high quality semiconductor device can be manufactured especially when the conditions of the process of joining using a thermocompression bonding apparatus and the conditions of various processes before the joining are preferable conditions.
  • the solder bump and the electrode pad are in contact with each other before the heat and pressure bonding is performed, but at the time of the contact, the temperature of only one of the head or the stage of the thermocompression bonding apparatus is used.
  • the solder bump and the electrode pad are brought into contact with each other at a temperature of 120 ° C. or higher.
  • heating and pressurizing bonding may be performed by setting the temperature of the head or stage on the side that is lower than 120 ° C. when the solder bump and the electrode pad are in contact with each other as a temperature condition equal to or higher than the melting point of the solder. preferable.
  • the interlayer filler composition is more preferably preliminarily applied to a chip or a substrate set on the side that is lower than 120 ° C. when the solder bump and the electrode pad are in contact with each other.
  • the viscosity of the interlayer filler composition is too high, it may become an obstacle at the time of heat-pressure bonding. Therefore, when the solder bump and the electrode pad are in contact with each other, the temperature on the side of less than 120 ° C. is 40 It is preferable that the temperature is not lower than ° C.
  • the semiconductor chip to be bonded may be temporarily bonded to the semiconductor chip and / or the semiconductor substrate.
  • the temperature for temporary bonding is preferably 80 ° C. to 150 ° C.
  • the temporary bonding may be repeated for the number of layers of the substrate, or the substrates may be stacked and then temporarily bonded together by heating. Provisional bonding, between the substrates as necessary, preferably 1gf / cm 2 ⁇ 50Kgf / cm 2, more preferably it is preferably carried out under a load of 10gf / cm 2 ⁇ 10Kgf / cm 2.
  • the interlayer filler composition of the present invention preferably contains an epoxy resin (A), a curing agent (B), a filler (C) and a flux (D), and has a viscosity at 130 ° C. (hereinafter referred to as “ ⁇ 130 ”). Is preferably 100 Pa ⁇ s or less.
  • the interlayer filler composition of the present invention preferably further contains a curing accelerator (E) and a dispersing agent (F).
  • the interlayer filler composition of the present invention preferably has a low viscosity with a viscosity ⁇ 130 at 130 ° C. of 100 Pa ⁇ s or less. If the ⁇ 130 of the interlayer filler composition is higher than 100 Pa ⁇ s, the interlayer filler composition is difficult to flow during bonding, and bonding failure may occur.
  • ⁇ 130 of the interlayer filler composition of the present invention is more preferably 50 Pa ⁇ s or less, and particularly preferably 10 Pa ⁇ s or less. However, if this viscosity is excessively low, fillet formation becomes difficult, so that the ⁇ 130 of the interlayer filler composition of the present invention is preferably 0.1 Pa ⁇ s or more.
  • a low-viscosity epoxy resin (A) contained in the interlayer filler composition is used, or a curing agent (B) or other components are used. What is necessary is just to adjust a composition.
  • the viscosity of the interlayer filler composition is a value measured by the method described in the Examples section below.
  • Epoxy resin (A) The epoxy resin (A) used in the present invention is preferably a compound having two or more epoxy groups in order to improve the glass transition temperature of the interlayer filler composition of the present invention.
  • the range of epoxy groups contained in one molecule is 1 or more and 8 or less. Is more preferable, and more preferably 2 or more and 3 or less.
  • the epoxy resin (A) used in the present invention is an epoxy compound having an aromatic ring of a bisphenol A skeleton, a bisphenol F skeleton, or a biphenyl skeleton. It is preferable to use it.
  • bisphenol A type epoxy resin bisphenol F type epoxy resin, bisphenol S type epoxy resin, biphenyl type epoxy resin, naphthalene ring-containing epoxy resin, epoxy resin having a dicyclopentadiene skeleton, phenol novolac type resin, cresol
  • novolac type epoxy resins triphenylmethane type epoxy resins, aliphatic epoxy resins, aliphatic epoxy resin copolymer epoxy resins, and the like.
  • bisphenol A type epoxy resins bisphenol F type epoxy resins, bisphenol S type epoxy resins, biphenyl type epoxy resins or naphthalene ring-containing epoxy resins are preferable, and bisphenol A type epoxy resins, bisphenol F type epoxy resins are more preferable.
  • a naphthalene ring-containing epoxy resin or a biphenyl type epoxy resin is used.
  • a polyfunctional epoxy resin is also used as the epoxy resin (A) used in the present invention.
  • Polyfunctional epoxy resins include phenol novolac resin, cresol novolac resin, bisphenol A novolak resin, dicyclopentadiene phenol resin, phenol aralkyl resin, naphthol novolac resin, biphenyl novolac resin, terpene phenol resin, heavy oil modified phenol resin, etc.
  • Glycidyls such as epoxy resins produced from phenols, various phenolic compounds such as polyhydric phenol resins obtained by condensation reaction of phenols with aldehydes such as hydroxybenzaldehyde, crotonaldehyde, and glyoxal, and epihalohydrins Ether type polyfunctional epoxy resins are preferred.
  • epoxy resins (A) may be used alone or in a combination of two or more in any combination and ratio.
  • the curing agent (B) used in the present invention refers to a substance that contributes to the crosslinking reaction between the crosslinking groups of the epoxy resin (A).
  • curing agent (B) What is generally known as an epoxy resin hardening
  • phenolic curing agents aliphatic amines, polyether amines, alicyclic amines, aromatic amines and other amine curing agents, acid anhydride curing agents, amide curing agents, tertiary amines, imidazoles or the like Derivatives, organic phosphines, phosphonium salts, tetraphenylboron salts, organic acid dihydrazides, boron halide amine complexes, polymercaptan curing agents, isocyanate curing agents, blocked isocyanate curing agents, and the like.
  • phenolic curing agents include bisphenol A, bisphenol F, 4,4'-dihydroxydiphenylmethane, 4,4'-dihydroxydiphenyl ether, 1,4-bis (4-hydroxyphenoxy) benzene, 1,3-bis (4-hydroxyphenoxy) benzene, 4,4'-dihydroxydiphenyl sulfide, 4,4'-dihydroxydiphenyl ketone, 4,4'-dihydroxydiphenyl sulfone, 4,4'-dihydroxybiphenyl, 2,2'-dihydroxybiphenyl 10- (2,5-dihydroxyphenyl) -10H-9-oxa-10-phosphaphenanthrene-10-oxide, phenol novolak, bisphenol A novolak, o-cresol novolak, m-cresol novolak, p-ke Zole novolak, xylenol novolak, poly-p-hydroxystyrene, hydroquinone, re
  • Examples of aliphatic amines that are amine curing agents include ethylenediamine, 1,3-diaminopropane, 1,4-diaminopropane, hexamethylenediamine, 2,5-dimethylhexamethylenediamine, trimethylhexamethylenediamine, diethylenetriamine, Examples include iminobispropylamine, bis (hexamethylene) triamine, triethylenetetramine, tetraethylenepentamine, pentaethylenehexamine, N-hydroxyethylethylenediamine, tetra (hydroxyethyl) ethylenediamine, and the like.
  • polyether amines examples include triethylene glycol diamine, tetraethylene glycol diamine, diethylene glycol bis (propylamine), polyoxypropylene diamine, polyoxypropylene triamines, and the like.
  • Cycloaliphatic amines include isophorone diamine, metacene diamine, N-aminoethylpiperazine, bis (4-amino-3-methyldicyclohexyl) methane, bis (aminomethyl) cyclohexane, 3,9-bis (3-amino). (Propyl) -2,4,8,10-tetraoxaspiro (5,5) undecane, norbornenediamine and the like.
  • Aromatic amines include tetrachloro-p-xylenediamine, m-xylenediamine, p-xylenediamine, m-phenylenediamine, o-phenylenediamine, p-phenylenediamine, 2,4-diaminoanisole, 2,4 -Toluenediamine, 2,4-diaminodiphenylmethane, 4,4'-diaminodiphenylmethane, 4,4'-diamino-1,2-diphenylethane, 2,4-diaminodiphenylsulfone, 4,4'-diaminodiphenylsulfone, m-aminophenol, m-aminobenzylamine, benzyldimethylamine, 2-dimethylaminomethyl) phenol, triethanolamine, methylbenzylamine, ⁇ - (m-aminophenyl) ethylamine,
  • acid anhydride curing agents include dodecenyl succinic anhydride, polyadipic acid anhydride, polyazeline acid anhydride, polysebacic acid anhydride, poly (ethyloctadecanedioic acid) anhydride, poly (phenylhexadecanedioic acid) Anhydride, Methyltetrahydrophthalic anhydride, Methylhexahydrophthalic anhydride, Hexahydrophthalic anhydride, Methylhymic anhydride, Tetrahydrophthalic anhydride, Trialkyltetrahydrophthalic anhydride, Methylcyclohexene dicarboxylic anhydride, Methylcyclohexene tetracarboxylic Acid anhydride, phthalic anhydride, trimellitic anhydride, pyromellitic anhydride, benzophenone tetracarboxylic anhydride, ethylene glycol
  • amide type curing agents examples include dicyandiamide and polyamide resin.
  • tertiary amines examples include 1,8-diazabicyclo (5,4,0) undecene-7, triethylenediamine, benzyldimethylamine, triethanolamine, dimethylaminoethanol, tris (dimethylaminomethyl) phenol, and the like. .
  • imidazole or derivatives thereof examples include 1-cyanoethyl-2-phenylimidazole, 2-phenylimidazole, 2-ethyl-4 (5) -methylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole 1-benzyl-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1-cyanoethyl-2-phenylimidazo Lithium trimellitate, 2,4-diamino-6- [2'-methylimidazolyl- (1 ')]-ethyl-s-triazine, 2,4-diamino-6- [2'-ethyl-4'-methyl Imidazolyl- (1 ′)]-ethyl-s-triazine, 2,4 Diamin
  • organic phosphines include tributylphosphine, methyldiphenylphosphine, triphenylphosphine, diphenylphosphine, and phenylphosphine.
  • examples of the phosphonium salt include tetraphenylphosphonium / tetraphenylborate, tetraphenylphosphonium / ethyltriphenylborate, and tetrabutylphosphonium / tetrabutylborate.
  • examples of the tetraphenylboron salt include 2-ethyl-4-methylimidazole / tetraphenylborate, N-methylmorpholine / tetraphenylborate and the like.
  • curing agents (B) may be used alone or in a combination of two or more in any combination and ratio.
  • the content of the curing agent (B) in the interlayer filler composition is preferably 30 to 150 parts by weight, more preferably 50 to 120 parts by weight, per 100 parts by weight of the epoxy resin (A).
  • the curing agent (B) is a phenol curing agent, an amine curing agent, or an acid anhydride curing agent
  • the equivalent ratio of the functional group in the curing agent (B) to the epoxy group in the epoxy resin (A) Therefore, it is preferably used in a range of 0.8 to 1.5, and more preferably in a range of 0.8 to 1.2. Outside this range, unreacted epoxy groups and functional groups of the curing agent may remain, and desired physical properties may not be obtained.
  • the curing agent (B) is an amide-based curing agent, a tertiary amine, imidazole or a derivative thereof, an organic phosphine, a phosphonium salt, a tetraphenylboron salt, an organic acid dihydrazide, a boron halide amine complex, a polymercaptan-based curing agent.
  • an isocyanate curing agent, a blocked isocyanate curing agent, etc. it is preferably used in an amount of 0.1 to 20 parts by weight, preferably 0.5 to 10 parts by weight, based on 100 parts by weight of the epoxy resin (A). It is more preferable to use so that it may become this range.
  • a dicyandiamine compound it is preferably used in the range of 0.1 to 10 parts by weight, and preferably in the range of 0.5 to 6 parts by weight with respect to 100 parts by weight of the epoxy resin (A). More preferably, it is used.
  • the filler (C) is added for the purpose of improving thermal conductivity and controlling the linear expansion coefficient, and is mainly intended for controlling the linear expansion coefficient.
  • Examples of the filler (C) include at least one particle selected from the group consisting of metal, carbon, metal carbide, metal oxide, and metal nitride.
  • Examples of carbon include carbon black, carbon fiber, graphite, fullerene and diamond.
  • Examples of metal carbides include silicon carbide, titanium carbide, tungsten carbide and the like.
  • Examples of metal oxides include magnesium oxide, aluminum oxide, silicon oxide, calcium oxide, zinc oxide, yttrium oxide, zirconium oxide, cerium oxide, ytterbium oxide, sialon (ceramics made of silicon, aluminum, oxygen and nitrogen). Can be mentioned.
  • Examples of metal nitrides include boron nitride, aluminum nitride, silicon nitride and the like.
  • the shape of the filler (C) is not limited, and may be particulate, whisker, fiber, plate, or an aggregate thereof.
  • oxide or nitride is preferable among the fillers (C). More specifically, as such filler (C), alumina (Al 2 O 3 ), aluminum nitride (AlN), boron nitride (BN), silicon nitride (Si 3 N 4 ), silica (SiO 2 ), etc. Among them, Al 2 O 3 , AlN, BN or SiO 2 is preferable, and Al 2 O 3 , BN or SiO 2 is particularly preferable. As the BN filler, those disclosed in Japanese Unexamined Patent Publication No. 2013-241321 are preferably used.
  • fillers (C) may be used alone or in a combination of two or more in any combination and ratio.
  • the maximum particle diameter of the filler to be formed is preferably about 1/3 or less of the thickness of the interlayer filling layer.
  • the maximum particle size of the filler (C) is preferably 5 ⁇ m, more preferably 3 ⁇ m.
  • the content of the filler (C) in the interlayer filler composition of the present invention is preferably 10 to 500 parts by weight, preferably 20 to 400 parts by weight per 100 parts by weight of the total of the epoxy resin (A) and the curing agent (B). More preferred.
  • the content of the filler (C) is less than 10 parts by weight per 100 parts by weight of the total of the epoxy resin (A) and the curing agent (B)
  • the effect of adding the filler (C) is reduced, and the intended linear expansion
  • the coefficient and thermal conductivity may not be obtained.
  • the amount exceeds 500 parts by weight the presence of the filler (C) may hinder the bondability.
  • the flux (D) means that the metal electrical signal terminals such as solder bumps and the surface oxide film of the land (Land) are dissolved and removed when the metal terminals are soldered together, and the solder bumps are spread on the land surface. It is a compound having a function of improving the property and preventing reoxidation of the metal terminal surface of the solder bump.
  • Examples of the flux (D) used in the present invention include fats such as succinic acid, malonic acid, succinic acid, glutaric acid, adipic acid, malic acid, tartaric acid, citric acid, lactic acid, acetic acid, propionic acid, butyric acid, oleic acid, and stearic acid.
  • Aromatic carboxylic acids such as benzoic acid, salicylic acid, phthalic acid, trimellitic acid, trimellitic acid anhydride, trimesic acid, benzenetetracarboxylic acid, or acid anhydrides thereof; terpene carboxylic acids such as abietic acid and rosin, etc.
  • An organic carboxylic acid which is a hemiacetal ester obtained by reacting an organic carboxylic acid with an alkyl vinyl ether; glutamic acid hydrochloride, aniline hydrochloride, hydrazine hydrochloride, cetylpyridine bromide, phenylhydrazine hydrochloride, Tetrachloronaphthalene, methyl hydrazine hydrochloride
  • Organic halogen compounds such as methylamine hydrochloride, ethylamine hydrochloride, diethylamine hydrochloride and butylamine hydrochloride; amines such as urea and diethylenetriamine hydrazine; polyhydric alcohols such as ethylene glycol, diethylene glycol, triethylene glycol, tetraethylene glycol and glycerin
  • Inorganic acids such as hydrochloric acid, hydrofluoric acid, phosphoric acid, borohydrofluoric acid; Fluorides such as potassium fluoride, sodium fluoride
  • These compounds may be used as they are or may be microencapsulated using a coating agent made of an organic polymer or an inorganic compound. These compounds may be used individually by 1 type, and 2 or more types may be mixed and used for them in arbitrary combinations and ratios.
  • the content of the flux (D) in the interlayer filler composition of the present invention is preferably 0.1 to 10 parts by weight, more preferably 100 parts by weight of the total of the epoxy resin (A) and the curing agent (B). 0.5 to 5 parts by weight. If the content of the flux (D) is less than 0.1 parts by weight per 100 parts by weight of the total of the epoxy resin (A) and the curing agent (B), there is a risk of poor solder connection due to a decrease in oxide film removal, and 10 weights. If it exceeds the part, there is a risk of poor connection due to an increase in the viscosity of the composition.
  • the interlayer filler composition of the present invention may contain a curing accelerator (E) together with the curing agent (B) in order to lower the curing temperature and shorten the curing time.
  • a curing accelerator (E) include microencapsulation of the above compound using a coating agent such as a compound containing a tertiary amino group, imidazole or a derivative thereof, an organic phosphine, dimethylurea, an organic polymer or an inorganic compound. And the like.
  • Compounds containing tertiary amino groups include 1,8-diazabicyclo (5,4,0) undecene-7, triethylenediamine, benzyldimethylamine, triethanolamine, dimethylaminoethanol, tris (dimethylaminomethyl) phenol, etc. Is exemplified.
  • imidazole and its derivatives examples include 1-cyanoethyl-2-phenylimidazole, 2-phenylimidazole, 2-ethyl-4 (5) -methylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1-cyanoethyl-2-phenylimidazolium Trimellitate, 2,4-diamino-6- [2′-methylimidazolyl- (1 ′)]-ethyl-s-triazine, 2,4-diamino-6- [2′-ethyl-4′-methylimidazolyl] -(1 ')]-ethyl-s-triazine, 2,
  • organic phosphines include tributylphosphine, methyldiphenylphosphine, triphenylphosphine, diphenylphosphine, and phenylphosphine.
  • examples of the phosphonium salt include tetraphenylphosphonium / tetraphenylborate, tetraphenylphosphonium / ethyltriphenylborate, and tetrabutylphosphonium / tetrabutylborate.
  • examples of the tetraphenylboron salt include 2-ethyl-4-methylimidazole / tetraphenylborate, N-methylmorpholine / tetraphenylborate and the like.
  • imidazole compounds (imidazole or its derivatives) and organic polymer or inorganic compound coatings are used because of their relatively long pot life, high curability in the middle temperature range, and high heat resistance of the cured resin. It is preferable to use a microencapsulated product of the above compound.
  • curing accelerators (E) may be used alone or in a combination of two or more in any combination and ratio.
  • the content of the curing accelerator (E) is based on 100 parts by weight of the total of the epoxy resin (A) and the curing agent (B).
  • the amount is preferably 0.001 to 15 parts by weight, more preferably 0.01 to 10 parts by weight. If the content of the curing accelerator (E) is less than 0.001 part by weight per 100 parts by weight of the total of the epoxy resin (A) and the curing agent (B), the curing acceleration effect may be insufficient, If the amount exceeds part by weight, the catalyst curing reaction becomes dominant, and the reduction of voids may not be achieved.
  • the interlayer filler composition of the present invention preferably contains a dispersant (F) in order to enhance the dispersibility of the filler (C).
  • a dispersing agent (F) Any conventionally well-known thing can be used as a dispersing agent mix
  • the content of the dispersant (F) may be any ratio as long as it can solve the problems of the present invention.
  • the dispersant (F) is preferably 0.1 to 4 parts by weight, more preferably 0.1 to 2 parts by weight.
  • the interlayer filler composition of the present invention may contain various additives other than those described above within a range not impairing the effects of the present invention for the purpose of further improving the functionality.
  • additives include coupling agents for improving bondability and bondability between the epoxy resin (A) and the filler (C), UV inhibitors for improving storage stability, antioxidants, plasticizers, Examples include flame retardants, colorants, fluidity improvers, adhesion improvers with substrates (for example, thermoplastic oligomers), and the like.
  • any of these other additives may be used alone, or two or more of them may be used in a combination and ratio.
  • the amount of other additives used is that of an epoxy resin (to the extent that necessary functionality is obtained). It is preferably 10 parts by weight or less, more preferably 5 parts by weight or less, per 100 parts by weight of the total of A) and the curing agent (B).
  • Examples of the coupling agent include silane coupling agents and titanate coupling agents.
  • silane coupling agents include epoxy silanes such as ⁇ -glycidoxypropyltrimethoxysilane, ⁇ -glycidoxypropyltriethoxysilane, ⁇ - (3,4-epoxycyclohexyl) ethyltrimethoxysilane, and ⁇ -aminopropyl.
  • Triethoxysilane N- ⁇ (aminoethyl) ⁇ -aminopropyltrimethoxysilane, N- ⁇ (aminoethyl) ⁇ -aminopropylmethyldimethoxysilane, ⁇ -aminopropyltrimethoxysilane, ⁇ -ureidopropyltriethoxysilane, etc.
  • Aminosilanes such as 3-mercaptopropyltrimethoxysilane, p-styryltrimethoxysilane, vinyltrichlorosilane, vinyltris ( ⁇ -methoxyethoxy) silane, vinyltrimethoxysilane, vinyltriethoxysilane, ⁇ Methacryloxypropyl trimethoxysilane vinylsilane such, further, epoxy, amino-based, and a silane of the polymer type vinyl.
  • mercaptosilanes such as 3-mercaptopropyltrimethoxysilane, p-styryltrimethoxysilane, vinyltrichlorosilane, vinyltris ( ⁇ -methoxyethoxy) silane, vinyltrimethoxysilane, vinyltriethoxysilane, ⁇ Methacryloxypropyl trimethoxysilane vinylsilane such, further, epoxy, amino-based, and a silane of the polymer type vinyl.
  • Titanate coupling agents include isopropyl triisostearoyl titanate, isopropyl tri (N-aminoethyl / aminoethyl) titanate, diisopropyl bis (dioctyl phosphate) titanate, tetraisopropyl bis (dioctyl phosphite) titanate, tetraoctyl bis (ditridecyl) Examples thereof include phosphite) titanate, tetra (2,2-diallyloxymethyl-1-butyl) bis (ditridecyl) phosphite titanate, bis (dioctylpyrophosphate) oxyacetate titanate, and bis (dioctylpyrophosphate) ethylene titanate.
  • These coupling agents may be used alone or in a combination of two or more in any combination and ratio.
  • the content is preferably about 0.1 to 2.0% by weight with respect to the total solid content in the interlayer filler composition. If the amount of the coupling agent is small, the effect of improving the adhesion between the epoxy resin (A) and the filler (C), which is a matrix resin, by blending the coupling agent cannot be sufficiently obtained, and the amount is too large. There is a problem that the coupling agent bleeds out from the obtained cured product.
  • the interlayer filler composition of the present invention may contain thermoplastic oligomers in order to improve the fluidity during molding and to improve the adhesion to the substrate.
  • Thermoplastic oligomers include C5 or C9 petroleum resin, styrene resin, indene resin, indene / styrene copolymer resin, indene / styrene / phenol copolymer resin, indene / coumarone copolymer resin, indene / benzothiophene. Examples thereof include copolymer resins. These may be used alone or in combination of two or more.
  • the content thereof is usually 2 to 30 parts by weight, preferably 5 to 20 parts by weight with respect to 100 parts by weight of the epoxy resin (A). Part.
  • the interlayer filler composition of the present invention may further contain a surfactant, an emulsifier, a low elasticity agent, a diluent, an antifoaming agent, an ion trapping agent and the like.
  • any of conventionally known anionic surfactants, nonionic surfactants, and cationic surfactants can be used.
  • fluorine surfactants in which some or all of the C—H bonds are C—F bonds can also be preferably used.
  • the content thereof is usually 0.001 to 0.00 with respect to 100 parts by weight of the total of the epoxy resin (A) and the curing agent (B). 1 part by weight, preferably 0.003 to 0.05 part by weight.
  • An organic solvent can also be added to the interlayer filler composition of the present invention.
  • the organic solvent include acetone, methyl ethyl ketone (MEK), methyl isobutyl ketone, methyl amyl ketone, cyclohexanone and other ketones, ethyl acetate and other esters, ethylene glycol monomethyl ether and other ethers, N, N-dimethylformamide, and the like.
  • Amides such as N, N-dimethylacetamide, alcohols such as methanol and ethanol, alkanes such as hexane and cyclohexane, and aromatics such as toluene and xylene.
  • ketones such as methyl ethyl ketone and cyclohexanone, esters and ethers are preferable, and ketones such as methyl ethyl ketone and cyclohexanone are particularly preferable.
  • These organic solvents may be used alone or in a combination of two or more in any combination and ratio.
  • the interlayer filler composition of the present invention preferably does not contain an organic solvent.
  • the interlayer filler composition of the present invention usually comprises an epoxy resin (A), a curing agent (B), a filler (C), a flux (D), a curing accelerator (E) used as necessary, a dispersing agent ( F) and other additive components are uniformly mixed by a mixer or the like and then kneaded by a heating roll, a kneader or the like.
  • a dispersing agent F
  • other additive components are uniformly mixed by a mixer or the like and then kneaded by a heating roll, a kneader or the like.
  • composition ingredients In the following examples and comparative examples, the compounding components used for the preparation of the interlayer filler composition are as follows.
  • ⁇ Curing agent (B)> Amine curing agent (B1): Wakayama Seika Kogyo Co., Ltd. Product name “Seika Cure S” (amine value 124 g / equivalent, melting point 177 ° C.)
  • Acid anhydride curing agent (B3) manufactured by Mitsubishi Chemical Corporation “jER Cure YH306” (3,4-dimethyl-6- (2-methyl-1-propenyl) -4-cyclohexene-1,2-dicarboxylic acid anhydride Product, acid anhydride equivalent 117 g / equivalent, viscosity at 25 ° C. 0.1 Pa ⁇ s)
  • Curing accelerator (E) Product name “Novacure HXA3792” (mixture of microencapsulated amine curing agent and bisphenol A liquid epoxy resin) manufactured by Asahi Kasei E-Materials
  • Dispersant (F) Dispersant (F): Product name “BYK-2155” (block copolymer having pigment affinity group) manufactured by Big Chemie Japan
  • Viscosity of interlayer filler composition Viscoelasticity measuring device (Physica MCR102) manufactured by Anton Paar Japan Co., Ltd., and viscosity of interlayer filler composition as follows (complex viscosity by dynamic viscoelasticity measurement) was measured. First, the interlayer filler composition to be measured was placed between a parallel plate dish (Parallel Plate Dish) and a parallel plate ( ⁇ 20 mm), and dynamic viscoelasticity measurement was performed. The measurement condition is that 0.5% sinusoidal distortion is applied to the sample, the frequency of the distortion is 1 (Hz), and the viscosity in the process of raising the temperature at a rate of 3 ° C. per minute is from 40 ° C. to 200 ° C. measured to determine the viscosity at 130 ° C. as eta 130.
  • inorganic filler (C1) 18.0 g was added, and the mixture was stirred for 3 minutes at 2000 rpm and 1 kPa with a self-revolving stirrer, and further stirred for 5 minutes at 1600 rpm and 1 kPa.
  • 0.5 part by weight (0.06 g) of flux (D1) was added to the total resin amount, and the mixture was stirred at 1600 rpm and 1 kPa for 5 minutes to prepare an interlayer filler composition.
  • ⁇ 130 of this interlayer filler composition was 1 Pa ⁇ s or less.
  • interposer IP80Model I, 10 mm square
  • the interposer (IP80 Model I) coated with this interlayer filler composition is on the stage side
  • the silicon solder bump chip CC80 Model I, 7.3 mm square
  • the thermocompression bonding device “Flip Chip Bonder ( FC3000S) ”and thermocompression bonding was performed at 20 N (3.8 Kgf / cm 2 ) for the bonding time shown in Table 1 under the head and stage temperature conditions shown in Table 1. Then, it heat-hardened at 165 degreeC for 2 hours, and manufactured the semiconductor device.
  • Example 19 and 20 In a 150 cc stirring vessel, 3.56 g of epoxy resin (A1), 3.56 g of epoxy resin (A2), and 4.87 g of acid anhydride curing agent (B3) are weighed, and dispersant (F) is added thereto. Then, 1 part by weight (0.18 g) was blended and added to the total amount of filler (C), and the mixture was stirred at 2000 rpm and 1 kPa for 2 minutes using a self-revolving stirrer (ARV-310 manufactured by Sinky).
  • A1 epoxy resin
  • A2 epoxy resin
  • B3 4.87 g of acid anhydride curing agent
  • inorganic filler (C1) 18.0 g of inorganic filler (C1) was added, and the mixture was stirred for 3 minutes at 2000 rpm 1 and kPa with a self-revolving stirrer, and further stirred for 5 minutes at 1600 rpm and 1 kPa.
  • 1.8 g of the curing accelerator (E) and 0.5 part by weight (0.06 g) of the flux (D1) are added to the total amount of resin, and the mixture is stirred at 1600 rpm and 1 kPa for 5 minutes to obtain an interlayer filler.
  • a composition was prepared. ⁇ 130 of this interlayer filler composition was 1 Pa ⁇ s or less.
  • heat-pressure bonding was performed under the bonding conditions shown in Table 1 to manufacture a semiconductor device.
  • Examples 1 to 20 and Comparative Examples 1 to 8 were evaluated for bondability and voids, and the results are shown in Table 1.
  • “Over” means a conduction failure (resistance value is 1 M ⁇ or more).
  • inorganic filler (C2) was added, and after stirring for 5 minutes at 1800 rpm 1 kPa with a self-revolving stirrer, 16.8 g of inorganic filler (C3) was further added and stirred for 5 minutes at 1800 rpm 1 kPa.
  • 0.96 g of a curing accelerator (E) is added and stirred for 5 minutes at 1800 rpm 1 kPa.
  • 1 part by weight (0.06 g) of flux (D2) is added to the total amount of resin, and 5 at 1800 rpm 1 kPa. Stirring was performed for a minute to obtain an interlayer filler composition.
  • ⁇ 130 of this interlayer filler composition was 1 Pa ⁇ s or less.
  • interposer About 10 mg (about 20 mg / cm 2 per effective area) of the interlayer filler composition was applied to an interposer (IP80Model I, 10 mm square) manufactured by WALTS while heating to 70 ° C.
  • IP80ModelI an interposer
  • CC80ModelI, 7.3 mm square silicon solder bump chip coated with this interlayer filler composition
  • FC3000S thermocompression bonding apparatus “Flip Chip Bonder (FC3000S)” manufactured by Toray Engineering Co., Ltd.
  • FC3000S thermocompression bonding apparatus “Flip Chip Bonder (FC3000S)” manufactured by Toray Engineering Co., Ltd.
  • FC3000S Frlip Chip Bonder
  • An interposer was set on the side shown in Table 2, and thermocompression bonding was performed under the pressure conditions of the head and stage shown in Table 2 with a pressure of 20 N (3.8 kgf / cm 2 ) and a heating and pressing time of 5 seconds. Then, it heat-hardened at 180 degreeC for 2 hours, and
  • Example 25 About 2 mg (about 4 mg / cm 2 per effective area) of the interlayer filler composition used in Example 1 was applied to an interposer (IP80Model I, 10 mm square) manufactured by WALTS while heating to 70 ° C. Using an interposer (IP80Model I) and a silicon TSV chip (CC80TSV-2, 7.3 mm square) coated with this interlayer filler composition, using a thermocompression bonding apparatus “Flip Chip Bonder (FC3000S)” manufactured by Toray Engineering Co., Ltd.
  • FC3000S thermocompression bonding apparatus
  • thermocompression bonding was performed at a head temperature of 250 ° C., a stage temperature of 250 ° C., a bonding time of 5 sec, and a bonding pressure of 20 N (3.8 kgf / cm 2 ).
  • about 8 mg of the interlayer filler composition was applied to the bonded substrates while heating to 70 ° C. (about 16 mg / cm 2 per effective area), and a silicon solder bump chip (CC80 Model I, 7.3 mm square) Were heat-press bonded under the same conditions. Then, it heat-hardened at 165 degreeC for 2 hours, and manufactured the semiconductor device. As a result, there was no void and conduction was confirmed.
  • FIG. 3 shows an appearance shape and a cross-sectional photograph of the obtained semiconductor device.

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Abstract

L'invention concerne un procédé de fabrication d'un dispositif semiconducteur, selon lequel une couche adhésive durcie qui présente d'excellentes propriétés de liaison et une excellente conductivité peut être formée sans apparition de vides dans la couche adhésive durcie. Dans un procédé de fabrication d'un dispositif semiconducteur en utilisant un équipement de liaison par thermocompression pour lier ensemble par thermocompression une puce en semiconducteur munie de bossages de soudure et une carte en semiconducteurs munie de pastilles d'électrode avec une composition de charge intercouche intervenant entre elles, la liaison est réalisée dans des conditions de température telles que les températures de la tête et de la platine de l'équipement de liaison par thermocompression se trouvent dans une plage qui est définie, dans un graphique ayant un axe des ordonnées représentatif de la température de la tête et ayant un axe des abscisses représentatif de la température de la platine, par les quatre équations suivantes : H + 1,9S = 590 Équation 1, H + 0,526S = 310 Équation 2, H + 0,8S = 580 Équation 3, H + 1,25S = 725 Équation 4, où H est la température de la tête (en °C) et S est la température de la platine (en °C).
PCT/JP2015/078802 2014-10-10 2015-10-09 Procédé de fabrication d'un dispositif semiconducteur WO2016056655A1 (fr)

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