WO2016051741A1 - モータ制御装置およびモータ制御方法 - Google Patents
モータ制御装置およびモータ制御方法 Download PDFInfo
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- WO2016051741A1 WO2016051741A1 PCT/JP2015/004869 JP2015004869W WO2016051741A1 WO 2016051741 A1 WO2016051741 A1 WO 2016051741A1 JP 2015004869 W JP2015004869 W JP 2015004869W WO 2016051741 A1 WO2016051741 A1 WO 2016051741A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/08—Arrangements for controlling the speed or torque of a single motor
Definitions
- the present invention relates to a motor control device and a motor control method for freely controlling the rotation of a motor by applying a drive voltage generated by PWM control to the winding of the motor and controlling the flowing current, and in particular, to the winding.
- the present invention relates to a motor control device having a function of detecting a current value generated by applying a drive voltage, and a motor control method of the device.
- a servo motor used in FA the position, speed, and torque of a motor are controlled so as to follow a drive command (position command) from a host device (host controller).
- Digital control using a microprocessor is widely used as the control arithmetic unit.
- PWM Pulse Width Modulation
- a motor current a current value of a current flowing in a motor winding.
- the current value of the motor current is detected at regular intervals, and control is performed using PID control (proportional + integral + differential control) or the like so as to coincide with the current command value. Since the torque output by the synchronous motor (Surface Permanent Magnet Synchronous Motor) used in servo motors is proportional to the motor current, the current value of the motor current is compared with the current command value while using PWM control. By controlling to match, the torque output from the motor can be freely controlled.
- PID control proportional + integral + differential control
- FIG. 8 is a configuration diagram of a motor control device 90 including an inverter as a conventional example.
- This conventional motor control device 90 is provided with a current detection resistor 91 between the power converter 98 that is an inverter and the winding of the motor 30 in order to detect the current value of the motor current.
- the voltage generated between the two terminals of the current detection resistor 91 when the motor current flows is digitally converted by an AD (Analog-Digital) converter 95, and the digital data Di is supplied to the digital controller 97.
- AD Analog-Digital
- the motor current is generally detected by such a configuration.
- a ⁇ (delta sigma) AD converter 92 is used in the AD conversion unit 95 as shown in FIG. Reference 1).
- Such an AD conversion unit 95 includes, for example, a photocoupler, a digital filter, and the like in addition to the ⁇ AD converter 92.
- this ⁇ AD converter has a problem that it is easily affected by leakage current based on PWM control.
- the leakage current is generated at the moment of switching.
- the leakage current flows to a grounded location through a housing or wiring.
- the ⁇ AD converter converts the voltage into a 1-bit digital signal. For this reason, the current detection value after the AD conversion thinning filter includes an unnecessary current component that does not originally flow to the motor.
- the motor control device of the present invention is a motor control device that has a motor current detection unit that detects a current flowing through a winding for a motor including a stator wound with a three-phase winding, and controls the operation of the motor. is there.
- the motor control device includes a digital control unit that outputs a PWM switching signal based on an operation command from a host device, position information from an encoder, and a motor current detection value that is a current value flowing through a winding, and a switching element according to the PWM switching signal.
- a power converter that applies a drive voltage to the winding by turning on / off, a motor current detector that converts the current flowing through the winding by the drive voltage into an analog voltage, and converts the analog voltage into a 1-bit digital signal
- a ⁇ type AD converter that converts a 1-bit digital signal into a multi-bit digital signal and outputs it as a motor current detection value
- a ⁇ type AD converter and an AD conversion decimation filter A clock generator for generating a clock, and a clock of the clock generator Generating a clock stop signal for stopping only between and a stop signal generation unit.
- the stop signal generation unit generates a clock stop signal having a predetermined pulse width based on the signal change timing of the PWM switching signal.
- the clock generation unit uses the clock stop signal to generate a period of a predetermined pulse width. Only the operation clock is stopped.
- the motor control method of the present invention includes a digital control unit that outputs a PWM switching signal based on an operation command from a host device, position information from an encoder, and a motor current detection value that is a current value flowing through a winding, and PWM switching.
- a power converter that applies a drive voltage to the winding by turning on and off the switching element according to the signal, a motor current detector that converts the current flowing through the winding by the drive voltage into an analog voltage, and the analog voltage of 1 bit
- a delta-sigma type AD converter that converts to a digital signal
- an AD conversion decimation filter that converts a 1-bit digital signal into a multi-bit digital signal and outputs it as a motor current detection value
- a clock generator that generates a clock for operation, and a clock of the clock generator
- a motor of a motor control device that controls the operation of the motor with respect to a motor including a stator having a stator around which a three-phase winding is wound, and a stop signal generating unit that generates a clock stop signal for stopping the clock for a predetermined period It is a control method.
- the motor control method generates a clock stop signal having a predetermined pulse width based on the
- the present motor control device and motor control method it is possible to reduce deterioration in detection accuracy due to leakage current due to PWM switching, so that unnecessary torque generated in the motor is reduced and fine vibration can be suppressed.
- FIG. 1 is a configuration diagram of a motor control system including a motor control device according to Embodiment 1 of the present invention.
- FIG. 2 is an operation waveform diagram for explaining the operation of the AD converter used for detecting the motor current in the motor control device.
- FIG. 3 is a configuration diagram of an AD conversion unit in the motor control device.
- FIG. 4 is an operation waveform diagram in another configuration example for generating the clock stop signal Stp in the motor control device.
- FIG. 5 is an operation waveform diagram in still another configuration example for generating the clock stop signal Stp in the motor control device.
- FIG. 6 is a configuration diagram of a motor control system including the motor control device according to the second embodiment of the present invention.
- FIG. 7 is a configuration diagram showing another configuration of the motor control system including the motor control device.
- FIG. 8 is a block diagram of a conventional motor control device.
- FIG. 1 is a configuration diagram of a motor control system including a motor control device according to Embodiment 1 of the present invention
- FIG. 2 is an operation waveform diagram for explaining the operation of an AD conversion unit used for detecting a motor current. It is.
- the motor control system 100 is configured such that the motor control device 10 controls the operation of the motor 30 according to the command control of the host device 35.
- the host device 35 is configured by using, for example, a personal computer and controls the motor control device 10 by a command or the like.
- the host device 35 and the motor control device 10 are connected so as to be communicable via a control bus line or the like.
- a command from the host device 35 is transmitted to the motor control device 10, and a command from the motor control device 10 is also transmitted.
- Information is transmitted to the host device 35.
- the motor 30 which is a three-phase brushless motor, includes a stator in which windings of phases U, V, and W are wound around a stator core, and a rotor having permanent magnets.
- the drive voltage Vd generated by the motor control device 10 is applied as the drive voltage VdU for the U-phase winding, as the drive voltage VdV for the V-phase winding, and as the drive voltage VdW for the W-phase winding.
- the rotor rotates.
- An encoder 31 is disposed in the vicinity of the rotor in order to detect the rotational position of the rotor. The encoder 31 outputs the detected position information of the rotor as position information Sen to the motor control device 10.
- the motor control device 10 detects the motor current in addition to the digital control unit 17 for controlling the rotation operation of the motor 30 and the power conversion unit 18 for energizing and driving the windings of the motor 30.
- a motor current detection unit 11, an AD conversion unit 15, and a stop signal generation unit 19 are provided.
- the digital control unit 17 is composed of a DSP (Digital Signal Processor), microcomputer software, ASIC (Application Specific Integrated Circuit), or FPGA (Field Programmable Gate Array) logic circuit. That is, the digital control unit (hereinafter simply referred to as a control unit as appropriate) 17 is configured to execute each process according to software indicating a processing procedure such as a program.
- the control unit 17 mainly processes a digital signal composed of a data string in which data of a predetermined number of bits are arranged as a signal to be processed.
- the control unit 17 receives information on operation commands for commanding position, speed, torque, and the like from the host device 35. In addition, the control unit 17 transmits information of the motor control device 10 and the like to the host device 35. The control unit 17 controls the rotation operation of the motor 30 together with the communication function for transmitting such information, and performs operation control such as speed and position so that the motor 30 performs a predetermined movement.
- control unit 17 executes the following control processing based on feedback control.
- the control unit 17 generates a speed command by performing position control calculation based on the operation command for commanding the position from the host device 35 and the position information Sen of the encoder 31.
- the control unit 17 calculates a motor speed value corresponding to the actual speed of the motor 30 by differentiation of the position information Sen, and calculates a current command by speed control calculation from the motor speed value and the speed command.
- the control unit 17 calculates a current from the U-phase motor current detection value DiU and the W-phase motor current detection value DiW obtained via the motor current detection unit 11 and the AD conversion unit 15 and the calculated current command.
- the voltage command for each phase is calculated by control calculation.
- PWM Pulse Width Modulation
- a PWM switching signal (hereinafter, referred to as a PWM signal) Pw for switching driving the power conversion unit 18 is used as a U-phase PWM signal PwU.
- V phase PWM signal PwV and W phase PWM signal PwW are output.
- the control unit 17 generates the PWM signal Pw that is PWMed as follows. First, in order to perform PWM, the control unit 17 generates a triangular PWM waveform having a triangular waveform using an up / down counter. Then, the control unit 17 generates the PWM signal Pw by comparing the PWM triangular wave and the voltage command calculated by the current control calculation.
- the PWM signal Pw falls from the high level to the low level when the level of the PWM triangular wave becomes equal to or higher than the level of the voltage command in the period in which the level of the PWM triangular wave increases sequentially.
- the PWM signal Pw rises from the low level to the high level when the level of the PWM triangular wave becomes equal to or lower than the level of the voltage command during the period in which the level of the PWM triangular wave gradually decreases.
- the control unit 17 repeats such an operation to generate a PWM signal Pw composed of a pulse width or a duty ratio pulse train corresponding to the voltage command level for each phase.
- the PWM signal Pw generated in this way is supplied to the power converter 18.
- the power converter 18 receives the PWM signal Pw from the digital controller 17 to generate a drive voltage Vd, and uses the motor line as the U-phase drive voltage VdU, the V-phase drive voltage VdV, and the W-phase drive voltage VdW. These voltages are applied to the respective windings of the motor 30.
- the power conversion unit 18 is a so-called inverter and includes a power element such as an IGBT (Insulated Gate Bipolar Transistor) and a diode. That is, the power conversion unit 18 uses a switching element such as an IGBT to generate a drive voltage Vd by switching, that is, turning on / off the voltage supplied from the power source according to the PWM signal Pw. Recently, an integrated power module using an IPM (Intelligent Power Module) incorporating a pre-drive circuit for driving a power element is often used.
- IPM Intelligent Power Module
- the motor current detection unit 11 detects the amount of motor current flowing through the winding and outputs it as a current detection signal Si. Specifically, the motor currents flowing through the U-phase motor line and the W-phase motor line are converted into voltages, respectively, and output as a U-phase current detection signal SiU and a W-phase current detection signal SiW.
- a shunt resistor is generally used when the motor current is small, and a CT (Current Transfer) is generally used when the motor current is large.
- the current detection signal Si output from the motor current detection unit 11 is supplied to the AD conversion unit 15.
- the AD converter 15 includes a first AD converter 15U to which a U-phase current detection signal SiU is supplied and a second AD converter to which a W-phase current detection signal SiW is supplied. Part 15W.
- Each of the AD converters 15 includes a ⁇ AD converter 12, an AD conversion decimation filter 14, and a clock generator 13, and converts the supplied analog signal into a digital signal and outputs the digital signal.
- a ⁇ AD converter hereinafter simply referred to as an AD converter 12 which is a ⁇ analog-digital converter as described above is used.
- FIG. 3 is a configuration diagram of such an AD conversion unit 15 and a stop signal generation unit 19 described in detail below.
- the clock generation unit 13 includes a clock generator 130 and an AND gate 131.
- the clock generator 130 generates an original clock Cka that determines the conversion cycle of the AD converter 12.
- the logical product 131 calculates the logical product of the original clock Cka and the clock stop signal Stp and outputs it as an AD conversion clock Ckc. Details of the clock stop signal Stp will be described below.
- the frequency of the original clock Cka may be determined by the AD conversion resolution required for the current control of the digital control unit 17 and the allowable delay due to the thinning out of the filter, and usually a frequency of several tens of MHz is used.
- the AD converter 12 includes, for example, a comparator that compares with a threshold value, and compares the supplied current detection signal Si with the threshold value.
- the AD converter 12 converts the comparison result to a binary value to convert it into a 1-bit digital signal.
- the AD converter 12 outputs the converted 1-bit digital signal as an AD conversion signal dSi for each AD conversion clock Ckc. That is, the AD conversion signal dSi output from the AD converter 12 is a signal composed of pulses.
- the high and low levels of the signal correspond to the values 1 and 0 of the 1-bit digital signal.
- the ⁇ AD converter 12 converts the input analog voltage into a 1-bit digital signal.
- the AD conversion decimation filter (hereinafter referred to as a decimation filter as appropriate) 14 forms a digital filter having a sinc function in frequency characteristics called a sinc filter, and includes an adder 140 including an adder and a subtractor. And a subtracting unit 141.
- the adder 140 generates the multi-bit addition data Dsi by integrating the AD conversion signal dSi, which is a 1-bit digital signal output from the AD converter 12, with an adder for each AD conversion clock Ckc. .
- the number of bits of the addition data Dsi corresponds to the AD conversion resolution of the AD converter 15.
- the AD conversion clock divider 142 generates a thinned clock Ckn obtained by dividing the AD conversion clock Ckc by 1 / N (N is 2 to the power of n, where n is an integer). That is, the frequency is divided from a high clock rate of the AD conversion clock Ckk called a so-called oversampling clock to a thinned-out clock Ckn at a desired low clock rate.
- the subtraction unit 141 operates for each thinning clock Ckn, and obtains a frequency characteristic that becomes a sinc function by calculating a difference between the previous value and the current value of the addition data Dsi.
- a low-pass characteristic filter is realized by the thinning filter 14 composed of the adder 140 and the subtractor 141, and the motor after the filter that cuts the high-frequency noise and converts it into the number of bits of a desired resolution.
- a current detection value Di is generated.
- the motor current detection value DiU generated by the first AD converter 15U and the motor current detection value DiW generated by the second AD converter 15W in this way are sent to the digital controller 17. Supplied.
- the digital control unit 17 performs a current control calculation using the supplied motor current detection values DiU and DiW, and calculates a voltage command for generating each drive voltage Vd.
- the motor control device 10 generates the drive voltage Vd in which the drive waveform for driving the winding is formed in a pseudo manner by the PWM pulse by switching the switching element connected to the power source. .
- a leakage current is generated at the moment of switching, and this leakage current affects the AD converter 15 as noise or the like, and as a result, the accuracy of the motor current detection values DiU and DiW may deteriorate. Therefore, in this embodiment, in order to suppress the influence of the leakage current, a stop signal generation unit 19 is further provided as shown in FIG. In the present embodiment, the stop signal generator 19 stops the operation of the AD converter 15 for a predetermined period, thereby suppressing the influence of leakage current.
- the stop signal generator 19 is supplied with PWM signals Pw (PwU, PwV, PwW) for each phase.
- the stop signal generation unit 19 generates a clock stop signal Stp having a predetermined timing and a predetermined pulse width by using an edge where the level of the supplied PWM signal Pw changes.
- This clock stop signal Stp is supplied to each AD converter 15 and further supplied to one input of the AND gate 131 of the clock generator 13.
- FIGS. 1 to 3 an example is shown in which the clock is stopped when the clock stop signal Stp is at a low level.
- the stop signal generator 19 is supplied with a U-phase PWM signal PwU, a V-phase PWM signal PwV, and a W-phase PWM signal PwW.
- the stop signal generation unit 19 determines, for example, a timer, a one-shot circuit, or the like from the switching timings of the U-phase PWM signal PwU, the V-phase PWM signal PwV, and the W-phase PWM signal PwW. Are used to generate U-phase, V-phase, and W-phase stop determination signals Sd that are low for a predetermined period.
- the U-phase PWM signal PwU is input to the timer 191U and the stop determination signal SdU is output, and the V-phase PWM signal PwV is input to the timer 191V and stopped.
- the determination signal SdV is output
- the W-phase PWM signal PwW is input to the timer 191W
- the stop determination signal SdW is output.
- the stop determination signal Sd whose signal is at a low level only for the period of time Tsj is output as a predetermined period from the falling and rising timings of the PWM signal Pw. ing.
- the logic determination circuit 192 generates and outputs the clock stop signal Stp by determining the logical values of the stop determination signal SdU, the stop determination signal SdV, and the stop determination signal SdW. More specifically, in FIG. 2, the logic determination circuit 192 generates and outputs the clock stop signal Stp as shown in FIG. 2 by taking the logical sum of these stop determination signals SdU, SdV and SdW. Is shown.
- the time Tsj may be set longer than the duration of leakage current due to switching (generally several ⁇ s).
- the clock generation unit 13 of the AD conversion unit 15 whether or not the original clock Cka is output is controlled by the clock stop signal Stp from the stop signal generation unit 19 and is output as an AD conversion clock Ckc including a clock stop period.
- the clock stop signal Stp is at a low level
- the AD conversion clock Ckk and the thinning clock Ckn are stopped, and the operations of the AD converter 12 and the thinning filter 14 are also stopped.
- the clock stop signal Stp may be generated as follows. .
- FIG. 4 is an operation waveform diagram in another configuration example for generating the clock stop signal Stp, and may be configured to have the waveform of the clock stop signal Stp shown in FIG. That is, the clock stop signal Stp as shown in FIG. 4 is determined when the logic determination circuit 192 determines that the stop determination signal Sd of at least two phases is at a low level, and in this case, the clock stop signal Stp is at a low level. It is comprised so that it may become.
- the operation of the AD conversion unit 15 can be stopped in a predetermined period immediately after PWM switching, and deterioration in detection accuracy of the current detection signal Si due to leakage current generated in that period can be reduced.
- the clock stop time can be extended, and the amount of reduction in detection accuracy degradation can be increased.
- FIG. 5 is an operation waveform diagram in still another configuration example for generating the clock stop signal Stp, and may be configured to have the waveform of the clock stop signal Stp shown in FIG. That is, the clock stop signal Stp as shown in FIG. 5 is configured such that the logic determination circuit 192 generates the clock stop signal Stp by taking the logical product of the U-phase, V-phase, and W-phase stop determination signals Sd. is doing.
- the operation of the AD conversion unit 15 can be stopped in a predetermined period immediately after PWM switching, and deterioration in detection accuracy of the current detection signal Si due to leakage current generated in that period can be reduced. . Furthermore, according to this configuration, it is possible to reduce deterioration in detection accuracy due to leakage current even when the switching of each phase varies during motor rotation.
- FIG. 6 is a configuration diagram of a motor control system including the motor control device according to the second embodiment of the present invention.
- a difference from the first embodiment shown in FIG. 1 is a configuration for generating the clock stop signal Stp of the stop signal generation unit 59, which will be described below.
- the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
- the digital control unit 17 in addition to the U-phase PWM signal PwU, the V-phase PWM signal PwV, and the W-phase PWM signal PwW, the digital control unit 17 to the stop signal generation unit 59 Thus, a motor speed value Spd indicating the currently controlled speed is supplied.
- the stop signal generation unit 59 monitors the motor speed value Spd from the digital control unit 17, and if the motor speed value Spd is equal to or higher than a predetermined speed (speed threshold), the clock stop signal Stp is set to a high level and is less than the speed threshold. In this case, the clock stop signal Stp based on the stop determination signal described in the first embodiment is output. As described above, in the configuration of FIG. 6 of the present embodiment, the stop signal generation unit 59 determines that the low drive state is easily affected by the leakage current only when the speed of the motor 30 is determined to be less than the speed threshold. Then, the control of the clock stop only for a predetermined period by the clock stop signal Stp is executed.
- the speed threshold may be a speed at which the influence of the leakage current due to the PWM switching signal on the motor current is reduced, and is several hundreds r / min.
- FIG. 7 is a configuration diagram showing another configuration of the motor control system including the motor control device according to the second embodiment of the present invention.
- FIG. 7 shows another configuration example for controlling the operation stop of the AD conversion unit 15 according to the driving state.
- the motor control device 10 illustrated in FIG. 7 includes a stop signal generation unit 69.
- the digital control unit 17 to the stop signal generation unit 69 send the U-phase PWM signal PwU, the V-phase PWM signal PwV, and the W-phase PWM.
- a motor current detection value Di Di (DiU, DiW) is supplied.
- the stop signal generation unit 69 monitors the amplitude value of the U-phase motor current detection value DiU or the W-phase motor current detection value DiW, and if the amplitude value exceeds a predetermined value (current threshold), the stop signal generation unit 69 When Stp is set to the high level and is less than the current threshold, the clock stop signal Stp is output by the stop determination signal described in the first embodiment. As described above, in the configuration of FIG. 7 of the present embodiment, the stop signal generation unit 69 is in the low drive state that is easily affected by the leakage current only when the current flowing through the winding of the motor 30 is determined to be less than the current threshold. And the control of the clock stop only for a predetermined period by the clock stop signal Stp is executed.
- the stop signal generation unit 69 releases such clock stop control.
- the motor current detection value Di is determined based on the magnitude of the DC value obtained by rotating coordinate conversion by deriving the V-phase motor current detection value from the U-phase motor current detection value DiU and the W-phase motor current detection value DiW. May be.
- the current threshold value may be a current value at which the influence of the leakage current caused by the PWM switching signal on the motor current is small, and is 10% to 20% of the motor rated current value.
- the clock stop signal Stp is set to the H level when at least one of the motor speed value Spd and the motor current detection value Di is equal to or higher than a threshold value (speed threshold value, current threshold value). If it is less than the threshold value, the clock stop signal Stp may be output by the stop determination signal described in the first embodiment.
- the stop signal generation units 19, 59, and 69 are described with reference to a configuration example in which the stop signal generation units 19, 59, and 69 are configured with a logic circuit or the like. That is, it is realized by a motor control method that generates a clock stop signal with a predetermined pulse width based on the signal change timing of the PWM switching signal, and stops the clock for a predetermined pulse width period using the clock stop signal. May be.
- a leakage current due to PWM switching is stopped by stopping an AD conversion clock according to a clock stop signal generated from PWM switching timing. It is possible to reduce the detection accuracy degradation due to. For this reason, unnecessary torque generated in the motor is reduced and fine vibrations can be suppressed. Therefore, the present invention is particularly effective as a control device that detects motor current and performs motor control.
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Abstract
Description
図1は、本発明の実施の形態1におけるモータ制御装置を含むモータ制御システムの構成図であり、図2は、モータ電流の検出に使用するAD変換部の動作を説明するための動作波形図である。
図6は、本発明の実施の形態2におけるモータ制御装置を含むモータ制御システムの構成図である。図1に示した実施の形態1と異なるのは、停止信号生成部59のクロック停止信号Stpを生成するための構成であり、以下に説明する。なお、図1と同じ構成要素については、同じ符号を付し、詳細な説明は省略する。
11 モータ電流検出部
12 ΔΣ型ADコンバータ
13 クロック生成部
14 AD変換間引きフィルタ
15,15U,15W,95 AD変換部
17,97 ディジタル制御部
18,98 電力変換部
19,59,69 停止信号生成部
30 モータ
31 エンコーダ
35 上位装置
100 モータ制御システム
130 クロック発生器
131 論理積ゲート
140 加算部
141 減算部
142 AD変換クロック分周器
191U,191V,191W タイマ
192 論理判定回路
Claims (6)
- 3相の巻線を巻回したステータを備えるモータに対し、前記巻線に流れる電流を検出するモータ電流検出部を有し、前記モータの動作を制御するモータ制御装置であって、
上位装置からの動作指令とエンコーダからの位置情報と前記巻線に流れる電流値であるモータ電流検出値とにより、PWMスイッチング信号を出力するディジタル制御部と、
前記PWMスイッチング信号に従いスイッチング素子をオン/オフすることで前記巻線に駆動電圧を印加する電力変換部と、
前記駆動電圧により前記巻線に流れる電流を、アナログ電圧に変換する前記モータ電流検出部と、
前記アナログ電圧を1ビットのディジタル信号に変換するΔΣ型ADコンバータと、
前記1ビットのディジタル信号を多ビットのディジタル信号に変換し、前記モータ電流検出値として出力するAD変換間引きフィルタと、
前記ΔΣ型ADコンバータと前記AD変換間引きフィルタとを動作させるためのクロックを生成するクロック生成部と、
前記クロック生成部のクロックを所定の期間だけ停止させるクロック停止信号を生成する停止信号生成部とを備え、
前記停止信号生成部は、前記PWMスイッチング信号の信号変化のタイミングに基づき、所定のパルス幅のクロック停止信号を生成し、
前記クロック生成部は、前記クロック停止信号を利用して、前記所定のパルス幅の期間だけ前記クロックを停止させることを特徴とするモータ制御装置。 - 前記停止信号生成部は、前記PWMスイッチング信号の信号変化のタイミングからあらかじめ設定した時間までのパルス幅の停止判定用信号を相ごとに生成し、3相全ての前記停止判定用信号が重なる時に、前記クロック停止信号を出力し、前記クロックを停止させることを特徴とする請求項1に記載のモータ制御装置。
- 前記停止信号生成部は、前記PWMスイッチング信号の信号変化のタイミングからあらかじめ設定した時間までのパルス幅の停止判定用信号を相ごとに生成し、いずれか2相以上の前記停止判定用信号が重なる範囲で、前記クロック停止信号を出力し、前記クロックを停止させることを特徴とする請求項1に記載のモータ制御装置。
- 前記停止信号生成部は、前記PWMスイッチング信号の信号変化のタイミングからあらかじめ設定した時間までのパルス幅の停止判定用信号を相ごとに生成し、いずれか1相以上の前記停止判定用信号が存在する場合に、前記クロック停止信号を出力し、前記クロックを停止させることを特徴とする請求項1に記載のモータ制御装置。
- 前記停止信号生成部は、前記モータ電流検出値またはモータ速度値の少なくともいずれか一方があらかじめ設定した値以上になった時は停止判定用信号によらず前記クロックを出力することを特徴とする請求項2から請求項4のいずれか1項に記載のモータ制御装置。
- 上位装置からの動作指令とエンコーダからの位置情報と巻線に流れる電流値であるモータ電流検出値とにより、PWMスイッチング信号を出力するディジタル制御部と、
前記PWMスイッチング信号に従いスイッチング素子をオン/オフすることで前記巻線に駆動電圧を印加する電力変換部と、
前記駆動電圧により前記巻線に流れる電流を、アナログ電圧に変換するモータ電流検出部と、
前記アナログ電圧を1ビットのディジタル信号に変換するΔΣ型ADコンバータと、
前記1ビットのディジタル信号を多ビットのディジタル信号に変換し、前記モータ電流検出値として出力するAD変換間引きフィルタと、
前記ΔΣ型ADコンバータと前記AD変換間引きフィルタとを動作させるためのクロックを生成するクロック生成部と、
前記クロック生成部のクロックを所定の期間だけ停止させるクロック停止信号を生成する停止信号生成部とを備え、
3相の前記巻線を巻回したステータを備えるモータに対し、前記モータの動作を制御するモータ制御装置のモータ制御方法であって、
前記PWMスイッチング信号の信号変化のタイミングに基づき、所定のパルス幅のクロック停止信号を生成し、
前記クロック停止信号を利用して、前記所定のパルス幅の期間だけ前記クロックを停止させることを特徴とするモータ制御装置のモータ制御方法。
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