WO2016039177A1 - 窒化物半導体積層体の製造方法および窒化物半導体積層体 - Google Patents
窒化物半導体積層体の製造方法および窒化物半導体積層体 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 380
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 374
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/301—AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Definitions
- the present invention relates to a method for manufacturing a nitride semiconductor multilayer body represented by a semiconductor switching element such as a HEMT (High Electron Mobility Transistor) and a nitride semiconductor multilayer body.
- a semiconductor switching element such as a HEMT (High Electron Mobility Transistor) and a nitride semiconductor multilayer body.
- a nitride semiconductor which is a group III-V compound semiconductor represented by GaN (gallium nitride), has been expected to be applied to a switching element applied to a power device or the like in recent years. This is because nitride semiconductors have a large band gap of about 3.4 eV, a dielectric breakdown electric field of about 10 times, and an electron saturation speed of about 2.5 times that of conventional semiconductors using Si (silicon). This is because it has characteristics suitable for power devices, such as being large.
- a switching element in which a GaN / AlGaN heterostructure is provided on a substrate of SiC (silicon carbide), Al 2 O 3 (sapphire), Si, or the like has been proposed (for example, US Pat. No. 6,849,882). Description (see Patent Document 1)).
- AlGaN is a mixture of GaN and AlN (aluminum nitride).
- the switching element in addition to the spontaneous polarization due to the asymmetric structure in the C-axis direction of the wurtzite type which is the crystal structure of GaN, 1 ⁇ 10 12 due to the polarization due to the piezo effect due to the lattice mismatch of AlGaN and GaN.
- a two-dimensional electron gas having a high electron density of about cm ⁇ 2 to 1 ⁇ 10 13 cm ⁇ 2 is generated.
- this switching element by controlling the electron density of the two-dimensional electron gas, a state in which predetermined electrodes are electrically connected (ON state) and a state in which predetermined electrodes are not electrically connected (OFF state) (Status).
- FIGS. 7 and 8 are schematic cross-sectional views for illustrating a typical configuration of a conventional switching element 1000.
- FIG. FIG. 7 shows the switching element 1000 in the on state.
- FIG. 8 shows the switching element 1000 in the off state.
- the switching element 1000 includes a substrate 1001, a buffer layer 1002 formed on the upper surface of the substrate 1001, and an electron transit made of undoped GaN formed on the upper surface of the buffer layer 1002.
- a layer 1003, an electron supply layer 1004 made of AlGaN formed on the upper surface of the electron transit layer 1003, a source electrode 1005, a drain electrode 1006, and a gate electrode 1007 are provided.
- the source electrode 1005, the drain electrode 1006, and the gate electrode 1007 are formed on the upper surface of the electron supply layer 1004.
- the gate electrode 1007 is located between the source electrode 1005 and the drain electrode 1006.
- This switching element 1000 is a normally-on type. Therefore, as shown in FIG. 7, the electron transit layer 1003 and the electron supply layer 1004 are bonded to each other regardless of whether the potential of the gate electrode 1007 is the same as that of the source electrode 1005 or the gate electrode 1007 is open. A two-dimensional electron gas layer 1008 is generated in the vicinity of the interface where the switching element 1000 is turned on. In the switching element 1000 in the on state, if the potential of the drain electrode 1006 is higher than the potential of the source electrode 1005, current flows between the source electrode 1005 and the drain electrode 1006.
- the gate electrode 1007 when the potential of the gate electrode 1007 is lower than the threshold voltage with respect to the potential of the source electrode 1005, the electron transit layer 1003 and the electron supply layer 1004 are joined below the gate electrode 1007.
- the two-dimensional electron gas layer 1008 is not generated near the interface. That is, a depletion region 1009 located below the gate electrode 1007 is formed. Accordingly, the switching element 1000 is turned off, and no current flows between the source electrode 1005 and the drain electrode 1006.
- an electron supply layer made of AlGaN and AlN is used instead of the electron supply layer 1004 made of AlGaN.
- a method is conceivable.
- FIG. 9 is a schematic cross-sectional view for explaining a switching element 2000 including an electron supply layer 2004 made of AlGaN and AlN.
- the same parts as those in the switching element 1000 shown in FIGS. 7 and 8 are denoted by the same reference numerals, and redundant description is omitted.
- the switching element 2000 includes a substrate 1001, a buffer layer 1002, an electron transit layer 1003, an electron supply layer 2004, a source electrode 1005, a drain electrode 1006, and a gate electrode 1007.
- the electron supply layer 2004 includes a spacer layer 2004A made of AlN and a barrier layer 2004B made of AlGaN.
- the difference between the band gap of the spacer layer 2004A and the band gap of the electron transit layer 1003 is larger than the difference between the band gap of the spacer layer 2004A and the band gap of the barrier layer 2004B. Further, the lattice mismatch between the spacer layer 2004A and the electron transit layer 1003 is larger than the lattice mismatch between the spacer layer 2004A and the barrier layer 2004B. As a result, the electron density and mobility in the two-dimensional electron gas layer 1008 increase, and the on-resistance decreases.
- the spacer layer 2004A when the spacer layer 2004A is formed, the underlying electron transit layer 1003 is decomposed, and unevenness is generated on the upper surface of the electron transit layer 1003 (the interface between the electron transit layer 1003 and the spacer layer 2004A). End up. Furthermore, since the spacer layer 2004A formed on the upper surface of the electron transit layer 1003 is extremely thin with a thickness of 5 nm or less, the thickness becomes non-uniform under the influence of unevenness on the upper surface of the electron transit layer 1003. When the in-plane direction state of the electron transit layer 1003 and the spacer layer 2004A becomes non-uniform in this way, the characteristics of the switching element 2000 are degraded, such as a decrease in electron mobility.
- the unevenness on the upper surface of the electron transit layer 1003 is a problem because it causes deterioration of the characteristics of the switching element 2000.
- FIG. 10 is a schematic cross-sectional view for explaining a phenomenon in which unevenness occurs on the upper surface of the electron transit layer 1003 in the switching element 2000.
- FIG. 10 shows a case where the formation method of the spacer layer 2004A made of AlN is a MOCVD (Metal Organic Chemical Vapor Deposition) method that is most widely used as a mass production method for semiconductor elements. Is. Further, FIG. 10 shows a case where the carrier gas for transporting the liquid organometallic material to the reactor is H 2 (hydrogen) that is most widely used from the viewpoint of preventing the oxidation of the raw material and the product. It is shown.
- H 2 hydrogen
- GaN constituting the electron transit layer 1003 is decomposed into Ga (gallium) and N (nitrogen). Is done. This is because the substrate temperature (900 ° C. or higher) necessary for growing AlN constituting the spacer layer 2004A is higher than the substrate temperature (800 ° C. or higher) at which GaN constituting the electron transit layer 1003 undergoes thermal decomposition. It is. Then, N generated by thermal decomposition of GaN is separated as gaseous N 2 (nitrogen), or reacts with surrounding H 2 to be separated as NH 3 (ammonia).
- the AlN is grown at a low pressure (for example, 0.1 atm or less) in the reaction furnace from the viewpoint of suppressing the reaction of the raw material in the gas phase and promoting the reaction of the raw material on the substrate 1001.
- a low pressure for example, 0.1 atm or less
- the pressure in the reaction furnace is reduced, separation of N 2 and NH 3 is promoted, so that thermal decomposition is promoted.
- an object of the present invention is to provide a method for manufacturing a nitride semiconductor multilayer body and a nitride semiconductor multilayer body capable of suppressing the formation of irregularities on the upper surface of a specific nitride semiconductor layer.
- nitride semiconductor multilayer body includes a nitride semiconductor multilayer substrate including a substrate and a plurality of nitride semiconductor layers stacked on the substrate.
- nitride semiconductor multilayer body there is a nitride semiconductor multilayer device (for example, a switching element) formed using the nitride semiconductor multilayer substrate.
- a nitride semiconductor multilayer device for example, a switching element
- switching element 2000 of FIG. 9 is presented for convenience in order to clarify the problem of the present invention, and is not a known technique.
- a method for manufacturing a nitride semiconductor multilayer body of the present invention includes: A first nitride semiconductor layer forming step of forming a first nitride semiconductor layer above the substrate in the reaction furnace; A second nitride semiconductor layer forming step of forming a second nitride semiconductor layer above the first nitride semiconductor layer; A third nitride semiconductor layer forming step of forming a third nitride semiconductor layer having a band gap larger than that of the second nitride semiconductor layer on the upper surface of the second nitride semiconductor layer; There is no interruption between the second nitride semiconductor layer forming step and the third nitride semiconductor layer forming step, and the third nitride semiconductor layer forming step is continuous with the second nitride semiconductor layer forming step. It is characterized by being implemented.
- the second nitride semiconductor layer forming step includes A fourth nitride semiconductor layer forming step of forming a fourth nitride semiconductor layer; A fifth nitride semiconductor layer forming step of forming a fifth nitride semiconductor layer above the fourth nitride semiconductor layer,
- the substrate temperature of the fifth nitride semiconductor layer forming step is higher than the substrate temperature of the fourth nitride semiconductor layer forming step,
- the furnace pressure in the fifth nitride semiconductor layer forming step is lower than the furnace pressure in the fourth nitride semiconductor layer forming step.
- the second nitride semiconductor layer forming step includes a sixth nitride semiconductor layer forming step of forming a sixth nitride semiconductor layer between the fourth nitride semiconductor layer and the fifth nitride semiconductor layer.
- the substrate temperature in the sixth nitride semiconductor layer forming step gradually changes from the same temperature as the substrate temperature in the fourth nitride semiconductor layer forming step to the same temperature as the substrate temperature in the fifth nitride semiconductor layer forming step.
- the pressure in the furnace in the sixth nitride semiconductor layer forming step is the same as the pressure in the furnace in the fourth nitride semiconductor layer forming step to the same pressure as the pressure in the fifth nitride semiconductor layer forming step. Change gradually.
- the second nitride semiconductor layer is made of GaN
- the third nitride semiconductor layer is made of Al x Ga 1-x N (0 ⁇ x ⁇ 1).
- the nitride semiconductor laminate of the present invention is A substrate, A first nitride semiconductor layer formed above the substrate; A second nitride semiconductor layer formed above the first nitride semiconductor layer; A third nitride semiconductor layer formed on an upper surface of the second nitride semiconductor layer and having a larger band gap than the second nitride semiconductor layer; The formation of the second nitride semiconductor layer is not interrupted between the formation of the second nitride semiconductor layer and the formation of the third nitride semiconductor layer, and the formation of the third nitride semiconductor layer is continuous with the formation of the second nitride semiconductor layer. As implemented, the second nitride semiconductor layer and the third nitride semiconductor layer are formed.
- the second nitride semiconductor layer is A fourth nitride semiconductor layer having a carbon concentration of less than 5 ⁇ 10 16 / cm 3 ;
- the nitride semiconductor multilayer body of one embodiment is A sixth nitride semiconductor layer formed between the fourth nitride semiconductor layer and the fifth nitride semiconductor layer;
- the carbon concentration of the sixth nitride semiconductor layer is substantially equal to the carbon concentration of the fourth nitride semiconductor layer near the interface between the fourth nitride semiconductor layer and the sixth nitride semiconductor layer, and
- the carbon concentration of the fifth nitride semiconductor layer is substantially equal to the carbon concentration of the fifth nitride semiconductor layer near the interface between the fifth nitride semiconductor layer and the sixth nitride semiconductor layer, and the sixth nitride is formed from the lower side of the sixth nitride semiconductor layer. It gradually increases as it goes to the upper side of the semiconductor layer.
- the second nitride semiconductor layer is made of GaN
- the third nitride semiconductor layer is made of Al x Ga 1-x N (0 ⁇ x ⁇ 1).
- the surface roughness by an atomic force microscope becomes 0.5 nm or less in a scanning range of 1 ⁇ m square.
- the second nitride semiconductor layer forming step is not interrupted between the second nitride semiconductor layer forming step and the third nitride semiconductor layer forming step. Since it is carried out continuously with the physical semiconductor layer forming step, it is possible to suppress the formation of irregularities on the upper surface of the second nitride semiconductor. Therefore, it can suppress that an unevenness
- the formation of the third nitride semiconductor layer is not interrupted between the formation of the second nitride semiconductor layer and the formation of the third nitride semiconductor layer, and the formation of the third nitride semiconductor layer is the second nitride semiconductor layer. Since the second nitride semiconductor layer and the third nitride semiconductor layer are formed so as to be carried out continuously, the occurrence of irregularities on the upper surface of the second nitride semiconductor can be suppressed. Therefore, it can suppress that an unevenness
- 1 is a schematic cross-sectional view of a switching element according to a first embodiment of the present invention. It is a sequence diagram for demonstrating the electron transit layer formation process and electron supply layer formation process of 1st Embodiment of this invention. It is a schematic cross section of the switching element of 2nd Embodiment of this invention. It is a sequence diagram for demonstrating the electron transit layer formation process and electron supply layer formation process of 2nd Embodiment of this invention. It is a schematic cross section of the switching element of 3rd Embodiment of this invention. It is a sequence diagram for demonstrating the electron transit layer formation process and electron supply layer formation process of 3rd Embodiment of this invention. It is a schematic cross section of the conventional switching element of an ON state.
- a nitride semiconductor multilayer body (particularly, a nitride semiconductor multilayer substrate) and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
- a switching element which is a nitride semiconductor multilayer device using the nitride semiconductor multilayer substrate according to one embodiment of the present invention will be described as an example.
- the main part is emphasized and displayed, so that the dimensional ratio of each component on the drawing and the actual dimensional ratio are not necessarily the same. is not.
- the same reference numerals are assigned to the same components from the viewpoint of facilitating understanding of the description.
- the elements (materials) constituting the layer are exemplified, but the gist thereof constitutes the layer. It does not indicate that the element contains any element other than the element (for example, an impurity or the like).
- FIG. 1 is a schematic cross-sectional view for illustrating the configuration of a switching element SA using the nitride semiconductor multilayer substrate 10A according to the first embodiment of the present invention.
- a nitride semiconductor multilayer substrate 10A includes a substrate 11, a buffer layer 12 formed on the upper surface of the substrate 11, and an upper surface of the buffer layer 12.
- the electron transit layer 13 and the electron supply layer 14 formed on the upper surface of the electron transit layer 13 are provided.
- Each layer on the substrate 11 is formed in a reaction furnace (not shown).
- the lower surface of the electron supply layer 14 is in contact with the upper surface of the electron transit layer 13, and no other layer is interposed between the electron transit layer 13 and the electron supply layer 14.
- the buffer layer 12 is an example of a first nitride semiconductor layer.
- the electron transit layer 13 is an example of a second nitride semiconductor layer.
- the electron supply layer 14 is an example of a third nitride semiconductor layer.
- the substrate 11 is made of, for example, Si, SiC, Al 2 O 3 , GaN, AlN, ZnO (zinc oxide), GaAs (gallium arsenide), or the like.
- the buffer layer 12 is, for example, a In X Al Y Ga 1-X -Y N ( However, 0 ⁇ X + Y ⁇ 1 and,, 0 ⁇ X ⁇ 1 and,, 0 ⁇ Y ⁇ 1) .
- the substrate 11 and the buffer layer 12 may be made of the same nitride semiconductor. Further, the substrate 11 and the buffer layer 12 are not limited to the above-described materials as long as the warpage and cracks of the nitride semiconductor multilayer substrate 10A can be suppressed, and any material may be selected.
- a breakdown voltage GaN layer having a carbon concentration of 5 ⁇ 10 16 / cm 3 or more may be formed on the buffer layer 12 for the purpose of improving breakdown voltage.
- the electron transit layer 13 is made of, for example, non-doped GaN having a thickness of 1 ⁇ m to 5 ⁇ m.
- the electron transit layer 13 includes a base GaN layer 13A and a channel GaN layer 13C formed on the upper surface of the base GaN layer 13A.
- the base GaN layer 13A and the channel GaN layer 13C have different formation conditions.
- the carbon concentration of the underlying GaN layer 13A is less than 5 ⁇ 10 16 / cm 3 .
- the carbon concentration of the channel GaN layer 13C is 5 ⁇ 10 16 / cm 3 or more and 1 ⁇ 10 18 / cm 3 or more.
- the underlying GaN layer 13A is an example of a fourth nitride semiconductor layer.
- the channel GaN layer 13C is an example of a fifth nitride semiconductor layer.
- the dislocation, the bending of the nanopipe, and the like are reduced at the interface between the underlying GaN layer 13A and the buffer layer 12, and the dislocation, the nanopipe, etc. are 2 Extends to the dimensional electron gas region and adversely affects device characteristics. Even when the breakdown voltage GaN layer is formed on the buffer layer 12, if the carbon concentration of the underlying GaN layer 13A is 5 ⁇ 10 16 / cm 3 or more, the underlying GaN layer 13A and the breakdown GaN layer At the interface, dislocations and bends of nanopipes are reduced.
- the carbon concentration of the channel GaN layer 13C is less than 5 ⁇ 10 16 / cm 3 , the detailed reason is unknown, but the flatness of the interface between the channel GaN layer 13C and the spacer layer 14A decreases, and two-dimensional electrons Electron mobility in the gas region decreases.
- the carbon concentration of the channel GaN layer 13C is 1 ⁇ 10 18 / cm 3 or more, the flatness at the interface between the channel GaN layer 13C and the spacer layer 14A deteriorates due to excessive carbon, and the two-dimensional electron gas The mobility of electrons in the region decreases.
- the spacer layer 14A is not provided between the channel GaN layer 13C and the barrier layer 14B, the flatness of the interface between the channel GaN layer 13C and the barrier layer 14B deteriorates.
- the electron supply layer 14 includes, for example, a spacer layer 14A made of AlN of 5 nm or less and a barrier layer 14B made of Al Z Ga 1-Z N (where 0 ⁇ Z ⁇ 1) of 5 nm to 100 nm. Further, the band gap of the spacer layer 14A is larger than both the band gap of the base GaN layer 13A and the channel GaN layer 13C. Further, the band gap of the barrier layer 14B is larger than both of the base GaN layer 13A and the channel GaN layer 13C. That is, the electron supply layer 14 has a larger band gap than the electron transit layer 13.
- the composition ratio Z of the Al Z Ga 1 -ZN satisfies 0.1 ⁇ Z ⁇ 0.5.
- the switching element SA includes a nitride semiconductor multilayer substrate 10A, a source electrode 21, a drain electrode 22, and a gate electrode 23.
- the source electrode 21, the drain electrode 22, and the gate electrode 23 are formed on the upper surface of the electron supply layer 14.
- the gate electrode 23 is disposed between the source electrode 21 and the drain electrode 22.
- Each of the source electrode 21, the drain electrode 22, and the gate electrode 23 is composed of a metal element such as Ti, Al, Cu, Au, Pt, W, Ta, Ru, Ir, Pd, and Hf, and at least of these metal elements. An alloy including two or a nitride including at least one of these metal elements is used.
- Each of the source electrode 21, the drain electrode 22, and the gate electrode 23 may be formed of a single layer or may be formed of a plurality of layers having different compositions.
- the switching element SA is a normally-on type. Therefore, even if the potential of the gate electrode 23 is the same as that of the source electrode 21 or the gate electrode 23 is open, the two-dimensional electron gas layer 15 is located near the interface between the channel GaN layer 13C and the spacer layer 14A. Occurs, and the switching element SA is turned on. When the switching element SA is turned on, a current flows between the source electrode 21 and the drain electrode 22 if the potential of the drain electrode 22 is higher than the potential of the source electrode 21. On the other hand, when the potential of the gate electrode 23 is lower than the threshold voltage with respect to the potential of the source electrode 21, the two-dimensional electron gas layer 15 is formed near the interface between the channel GaN layer 13C and the spacer layer 14A below the gate electrode 23. No longer occurs. That is, the same region as the depletion region 1009 in FIG. 7 is formed under the gate electrode 23, and the switching element SA is turned off. When the switching element SA is turned off, no current flows between the source electrode 21 and the drain electrode 22.
- the electron supply layer 14 on the upper surface of the electron transit layer 13 made of GaN. If formation of the electron supply layer 14 is started after the substrate temperature is increased and the furnace pressure (pressure in the reaction furnace containing the substrate 11) is decreased after the electron transit layer 13 is formed, the substrate temperature is increased. While raising and lowering the furnace pressure, GaN forming the electron transit layer 13 is thermally decomposed. As a result, irregularities occur on the upper surface (interface) of the electron transit layer 13.
- the electron transit layer 13 and the electron supply layer 14 capable of suppressing the thermal decomposition of GaN constituting the electron transit layer 13 are formed. This will be described below with reference to the drawings.
- FIG. 2 is a sequence diagram showing changes in the substrate temperature, the furnace pressure, and the supply amount of the source gas in the electron transit layer forming step and the electron supply layer forming step.
- the electron transit layer 13 and the electron supply layer 14 are formed by the MOCVD method.
- the electron transit layer forming step and the electron supply layer forming step are sequentially performed in the reaction furnace after the buffer layer forming step of forming the buffer layer 12 on the upper surface of the substrate 11 in the reaction furnace.
- the horizontal axis of FIG. 2 indicates time, and the time is later on the right side of FIG.
- the vertical axis in FIG. 2 indicates the substrate temperature, the furnace pressure, or the supply amount of the source gas.
- the buffer layer forming step is an example of a first nitride semiconductor layer forming step.
- the electron transit layer forming step is an example of a second nitride semiconductor layer forming step.
- the electron supply layer forming step is an example of a third nitride semiconductor layer forming step.
- a base GaN layer 13A composed of GaN is first formed on the buffer layer 12 (base GaN layer forming step). Specifically, by supplying TMG (trimethylgallium), which is a raw material of Ga, and NH 3 , which is a raw material of N, to the reactor, the underlying GaN layer 13A composed of GaN is formed. At this time, H 2 is used as the carrier gas, the substrate temperature is T1, and the furnace pressure is P1.
- the substrate temperature T1 is, for example, 600 ° C. or higher and 1300 ° C. or lower, more preferably 700 ° C. or higher and 1200 ° C. or lower.
- the furnace pressure P1 is, for example, not less than 0.15 atm.
- the underlying GaN layer forming step is an example of a fourth nitride semiconductor layer forming step.
- the supply of TMG is stopped, and the process proceeds to the conditions of the channel GaN layer forming step.
- the substrate temperature shifts from T1 to T2, and the furnace pressure shifts from P1 to P2.
- the T2 is higher than the T1, and is, for example, 900 ° C. or higher and 1400 ° C. or lower, more preferably 900 ° C. or higher and 1200 ° C. or lower.
- the P2 is lower than the P1, for example, 0.15 atm or less.
- the supply amounts of source gases TMG and NH 3 are TMG 1 and NH 3 1 in the base GaN layer forming step and TMG 2 and NH 3 2 in the channel GaN layer forming step, respectively, and TMG 2 ⁇ TMG 1 , NH 3 2 ⁇ NH 3 1 is preferable. This is because the electron supply layer 14 is very thin as compared with the electron transit layer 13, so that the growth rate is suppressed and the film quality is stabilized.
- the channel GaN layer forming step is an example of a fifth nitride semiconductor layer forming step.
- the furnace pressure is P2
- the TMG supply amount is TMG2
- the NH 3 supply amount is NH 3 2
- the channel GaN layer 13C is formed (channel GaN layer forming step).
- the carbon concentration of the channel GaN layer 13C tends to be higher than that of the underlying GaN layer 13A due to the effect of lowering the pressure from P1 to P2.
- the NH 3 2 the supply of NH 3, while maintaining the substrate temperature T2, the furnace pressure to P2, stopping the supply of the TMG, which is the material of Al TMA
- the spacer layer 14A is formed (spacer layer forming step).
- the substrate temperature T2 and the reactor pressure P2 are already suitable for the formation of the spacer layer 14A and the barrier layer 14B. Particularly, it takes time to adjust the substrate temperature and the furnace pressure. There is no need to interrupt the formation.
- the supply of TMG is restarted to form the barrier layer 14B (barrier layer forming step). If the TMG supply amount at this time is set to the same TMG2 as the TMG supply amount in the channel GaN layer forming step, the control of the TMG supply amount from the channel GaN layer forming step to the barrier layer forming step is controlled by the mass flow controller. This is preferable because it is only necessary to open and close the valve without changing it.
- the substrate temperature and the furnace pressure are changed to the substrate temperature and the furnace pressure of the electron supply layer 14 during the formation of the electron transit layer 13.
- the electron supply layer forming step can be performed continuously to the electron transit layer forming step.
- thermal decomposition of GaN on the upper surface of the electron transit layer 13 is suppressed, and unevenness on the upper surface (interface) of the electron transit layer 13 is less likely to occur.
- the surface roughness (for example, arithmetic average roughness Ra) of the nitride semiconductor multilayer substrate 10A by the atomic force microscope that is, the surface roughness (for example, arithmetic average roughness Ra) of the upper surface of the barrier layer 14B by the atomic force microscope is obtained. It becomes 0.5 nm or less in the scanning range of 1 ⁇ m square.
- the thickness of the extremely thin spacer layer 14A of, for example, 5 nm or less can be made uniform.
- the in-plane direction state of the electron transit layer 13 and the spacer layer 14A becomes uniform, it is possible to suppress the deterioration of the characteristics of the switching element SA, such as a decrease in electron mobility in the two-dimensional electron gas 15. It becomes possible.
- the buffer layer 12 is formed on the upper surface of the substrate 11.
- the buffer layer may be formed above the substrate 11. That is, a buffer layer may be formed on the substrate 11 via another layer.
- the electron supply layer 14 is replaced with In J Al L Ga 1- JL N (provided that the barrier layer 14B made of Al Z Ga 1-Z N (where 0 ⁇ Z ⁇ 1) is used). , 0 ⁇ J + L ⁇ 1, and 0 ⁇ J ⁇ 1 and 0 ⁇ L ⁇ 1).
- FIG. 3 is a schematic cross-sectional view for illustrating the configuration of the switching element SB using the nitride semiconductor multilayer substrate 10B according to the second embodiment of the present invention.
- FIG. 4 is a sequence diagram showing changes in the substrate temperature, the furnace pressure, and the supply amount of the source gas in the electron transit layer forming step and the electron supply layer forming step of the nitride semiconductor multilayer substrate 10B.
- 3 and 4 show the configuration and manufacturing method of the nitride semiconductor multilayer substrate 10B according to the second embodiment of the present invention in the same manner as the method of FIGS. 1 and 2 of the first embodiment. It is a figure. Further, in the description of the nitride semiconductor multilayer substrate 10B below, the description of the same components as those of the first embodiment may be omitted.
- a nitride semiconductor multilayer substrate 10 ⁇ / b> B is formed on a substrate 11, a buffer layer 12 formed on the upper surface of the substrate 11, and an upper surface of the buffer layer 12.
- the electron transit layer 213 and the electron supply layer 14 formed on the upper surface of the electron transit layer 213 are provided.
- the switching element SB includes a nitride semiconductor multilayer substrate 10B, a source electrode 21, a drain electrode 22, and a gate electrode 23.
- the source electrode 21, the drain electrode 22, and the gate electrode 23 are formed on the upper surface of the electron supply layer 14.
- the gate electrode 23 is disposed between the source electrode 21 and the drain electrode 22.
- the nitride semiconductor multilayer substrate 10B is different from the nitride semiconductor multilayer substrate 10A of the first embodiment in that the base GaN layer 13A, the slope GaN layer 13B, and the channel GaN layer 13C constitute an electron transit layer 213.
- the base GaN layer 13A, the slope GaN layer 13B, and the channel GaN layer 13C have different formation conditions.
- the band gap of the spacer layer 14A is larger than any of the band gaps of the underlying GaN layer 13A, the slope GaN layer 13B, and the channel GaN layer 13C.
- the band gap of the barrier layer 14B is also larger than any of the band gaps of the underlying GaN layer 13A, the slope GaN layer 13B, and the channel GaN layer 13C. That is, the electron supply layer 14 has a larger band gap than the electron transit layer 213.
- the slope GaN layer 13B is an example of a sixth nitride semiconductor layer.
- the slope GaN layer 13B can be formed by continuing the supply of TMG and NH 3 into the reactor in the step of shifting from the base GaN layer forming step to the forming condition of the channel GaN forming step in the first embodiment. Is a layer.
- the underlying GaN layer 13A is formed on the buffer layer 12 by the same formation method as the formation method of the underlying GaN layer 13A of the first embodiment (underlying GaN forming step).
- the substrate temperature or the like is shifted to the substrate temperature or the like for forming the channel GaN layer 13C.
- the substrate temperature is changed from T1 to T2
- the furnace pressure is changed from P1 to P2
- the TMG supply amount is changed from TMG1 to TMG2
- the NH 3 supply amount is changed from NH 3 1 to NH 3 2 over a certain time. Transition slowly. During this transition, the supply of TMG and NH 3 into the reactor is continued, so that the slope GaN layer 13B is formed (slope GaN layer forming step).
- the carbon concentration of the slope GaN layer 13B is substantially equal to the carbon concentration of the base GaN 13A. Further, in the vicinity of the interface between the channel GaN layer 13C and the slope GaN layer 13B, the carbon concentration of the slope GaN layer 13B is substantially equal to the carbon concentration of the channel GaN layer 13C. Further, the carbon concentration of the slope GaN layer 13B gradually increases as it proceeds from the lower side of the slope GaN layer 13B to the upper side of the slope GaN layer 13B.
- the carbon concentration of the channel GaN layer 13C tends to be higher than that of the underlying GaN layer 13A due to the effect of lowering the furnace pressure from P1 to P2.
- the supply of TMG is stopped, the supply of TMA is started, and the spacer layer 14A is formed (spacer layer 14A). Forming step).
- the substrate temperature is T2
- the furnace pressure is P2. Since the substrate temperature T2 and the furnace pressure P2 are suitable for the formation of the spacer layer 14A and the barrier layer 14B, the spacer layer 14A is continuously formed without interruption after the formation of the channel GaN layer 13C.
- the supply of TMG is resumed to form the barrier layer 14B (barrier layer forming step), as in the method of forming the barrier layer 14B of the first embodiment.
- the TMG supply amount at this time is set to the same TMG2 as the TMG supply amount in the channel GaN layer forming step
- the control of the TMG supply amount from the channel GaN layer forming step to the barrier layer forming step is controlled by the mass flow controller. This is preferable because it is only necessary to open and close the valve without changing it.
- the substrate temperature and the furnace pressure are set to the electron supply layer 14 during the formation of the electron transit layer 213, as in the first embodiment.
- the electron supply layer forming step can be performed continuously to the electron transit layer forming step. it can.
- thermal decomposition of GaN on the upper surface of the electron transit layer 13 is suppressed, and unevenness on the upper surface (interface) of the electron transit layer 13 is less likely to occur.
- the surface roughness (for example, arithmetic average roughness Ra) of the nitride semiconductor multilayer substrate 10A by the atomic force microscope that is, the surface roughness (for example, arithmetic average roughness Ra) of the upper surface of the barrier layer 14B by the atomic force microscope is obtained. It becomes 0.5 nm or less in the scanning range of 1 ⁇ m square.
- the extremely thin spacer layer 14A having a thickness of, for example, 5 nm or less can be made uniform. Therefore, since the in-plane direction state of the electron transit layer 213 and the spacer layer 14A becomes uniform, it is possible to suppress the deterioration of the characteristics of the switching element SB such as a decrease in electron mobility.
- the substrate temperature, the pressure in the furnace, and the supply amount of the source gas are gradually changed, so that overshoot and undershoot of the substrate temperature, the furnace pressure, and the supply amount of the source gas are reduced. Occurrence is suppressed.
- FIG. 5 is a schematic cross-sectional view for illustrating the configuration of the switching element SC using the nitride semiconductor multilayer substrate 10C according to the third embodiment of the present invention.
- FIG. 6 is a sequence diagram showing changes in the substrate temperature, the furnace pressure, and the supply amount of the source gas in the electron transit layer forming step and the electron supply layer forming step of the nitride semiconductor multilayer substrate 10C.
- 5 and 6 show the configuration and manufacturing method of the nitride semiconductor multilayer substrate 10C according to the third embodiment of the present invention in the same manner as the method of FIGS. 1 and 2 of the first embodiment. It is a figure.
- the same description of the same components as those in the first embodiment may be omitted.
- a nitride semiconductor multilayer substrate 10 ⁇ / b> C is formed on a substrate 11, a buffer layer 12 formed on the upper surface of the substrate 11, and an upper surface of the buffer layer 12.
- the electron transit layer 13 and the barrier layer 14B formed on the upper surface of the electron transit layer 13 are provided.
- the lower surface of the barrier layer 14B is in contact with the upper surface of the electron transit layer 13, and no other layer is interposed between the electron transit layer 13 and the barrier layer 14B.
- the barrier layer 14B is an example of a third nitride semiconductor layer.
- the switching element SC includes a nitride semiconductor multilayer substrate 10C, a source electrode 21, a drain electrode 22, and a gate electrode 23.
- the source electrode 21, the drain electrode 22, and the gate electrode 23 are formed on the upper surface of the barrier layer 14B.
- the gate electrode 23 is disposed between the source electrode 21 and the drain electrode 22.
- the base GaN layer 13A, the slope GaN layer 13B, and the channel GaN layer 13C constitute an electron transit layer 213, and the barrier supply layer 14B alone constitutes an electron supply layer. This is different from the nitride semiconductor multilayer substrate 10A of the first embodiment.
- the underlying GaN layer 13A is formed on the buffer layer 12 by the same formation method as the formation method of the underlying GaN layer 13A of the second embodiment (underlying GaN forming step).
- the substrate temperature or the like is shifted to the substrate temperature or the like for forming the channel GaN layer 13C.
- the substrate temperature is changed from T1 to T2
- the furnace pressure is changed from P1 to P2
- the TMG supply amount is changed from TMG1 to TMG2
- the NH 3 supply amount is changed from NH 3 1 to NH 3 2 over a certain time. Transition slowly. During this transition, the supply of TMG and NH 3 into the reactor is continued, so that the slope GaN layer 13B is formed (slope GaN layer forming step).
- the carbon concentration of the slope GaN layer 13B is substantially equal to the carbon concentration of the base GaN 13A. Further, in the vicinity of the interface between the channel GaN layer 13C and the slope GaN layer 13B, the carbon concentration of the slope GaN layer 13B is substantially equal to the carbon concentration of the channel GaN layer 13C. Further, the carbon concentration of the slope GaN layer 13B gradually increases as it proceeds from the lower side of the slope GaN layer 13B to the upper side of the slope GaN layer 13B.
- the carbon concentration of the channel GaN layer 13C tends to be higher than that of the underlying GaN layer 13A due to the effect of lowering the furnace pressure from P1 to P2.
- the TMG supply amount is TMG2, the NH 3 supply amount is NH 3 2, the substrate temperature is maintained at T2, and the furnace pressure is maintained at P2.
- the barrier layer 14B to be an electron supply layer is formed (a barrier layer forming step). If the TMG supply amount at this time is set to the same TMG2 as the TMG supply amount in the channel GaN layer forming step, the control of the TMG supply amount from the channel GaN layer forming step to the barrier layer forming step is controlled by the mass flow controller. This is preferable because it is only necessary to open and close the valve without changing it.
- the substrate temperature and the furnace pressure are set to the electron supply layer 14 during the formation of the electron transit layer 213, as in the first embodiment.
- the electron supply layer forming step can be performed continuously to the electron transit layer forming step. it can.
- thermal decomposition of GaN on the upper surface of the electron transit layer 13 is suppressed, and unevenness on the upper surface (interface) of the electron transit layer 13 is less likely to occur.
- the surface roughness (for example, arithmetic average roughness Ra) of the nitride semiconductor multilayer substrate 10A by the atomic force microscope that is, the surface roughness (for example, arithmetic average roughness Ra) of the upper surface of the barrier layer 14B by the atomic force microscope is obtained. It becomes 0.5 nm or less in the scanning range of 1 ⁇ m square.
- the extremely thin spacer layer 14A having a thickness of, for example, 5 nm or less can be made uniform. Therefore, since the in-plane direction state of the electron transit layer 213 and the spacer layer 14A becomes uniform, it is possible to suppress the deterioration of the characteristics of the switching element SB such as a decrease in electron mobility.
- the substrate temperature, the pressure in the furnace, and the supply amount of the source gas are gradually changed, so that overshoot and undershoot of the substrate temperature, the furnace pressure, and the supply amount of the source gas are reduced. Occurrence is suppressed.
- the nitride semiconductor multilayer substrate 10C does not include the spacer layer 14A of the first embodiment, the on-resistance of the switching element SC is sufficiently low.
- the spacer layer 14A is formed between the electron transit layer 213 and the barrier layer 14B, the lattice mismatch between the electron transit layer 213 and the spacer layer 14A increases, and as a result, the piezo effect increases. This adversely affects long-term reliability. Therefore, it is significant that the spacer layer 14A having a reliability risk is unnecessary.
- the method for producing a nitride semiconductor laminate according to the present invention includes: A first nitride semiconductor layer forming step of forming a first nitride semiconductor layer 12 above the substrate 11 in a reaction furnace; A second nitride semiconductor layer forming step of forming second nitride semiconductor layers 13 and 213 above the first nitride semiconductor layer 12; A third nitride semiconductor layer forming step of forming third nitride semiconductor layers 14 and 14B having a band gap larger than that of the second nitride semiconductor layers 13 and 213 on the upper surfaces of the second nitride semiconductor layers 13 and 213 And There is no interruption between the second nitride semiconductor layer forming step and the third nitride semiconductor layer forming step, and the third nitride semiconductor layer forming step is continuous with the second nitride semiconductor layer forming step. It is characterized by being implemented.
- the third nitride semiconductor layer forming step is the second nitride semiconductor layer forming step. Therefore, it is possible to suppress the formation of irregularities on the upper surface of the second nitride semiconductor.
- the second nitride semiconductor layer forming step includes A fourth nitride semiconductor layer forming step of forming the fourth nitride semiconductor layer 13A; A fifth nitride semiconductor layer forming step of forming a fifth nitride semiconductor layer 13C above the fourth nitride semiconductor layer 13A,
- the substrate temperature of the fifth nitride semiconductor layer forming step is higher than the substrate temperature of the fourth nitride semiconductor layer forming step,
- the furnace pressure in the fifth nitride semiconductor layer forming step is lower than the furnace pressure in the fourth nitride semiconductor layer forming step.
- the substrate temperature is relatively high and the furnace pressure is relatively low. Therefore, even when the third nitride semiconductor layers 14 and 14B are formed at a high substrate temperature and a low furnace pressure, the second nitride semiconductor layer formation step to the third nitride semiconductor layer formation step are continuously good. It can be done.
- the substrate temperature in the sixth nitride semiconductor layer forming step gradually changes from the same temperature as the substrate temperature in the fourth nitride semiconductor layer forming step to the same temperature as the substrate temperature in the fifth nitride semiconductor layer forming step.
- the pressure in the furnace in the sixth nitride semiconductor layer forming step is the same as the pressure in the furnace in the fourth nitride semiconductor layer forming step to the same pressure as the pressure in the fifth nitride semiconductor layer forming step. Change gradually.
- the substrate temperature and the furnace pressure in the sixth nitride semiconductor layer forming step are gradually changed, defects in the second nitride semiconductor layers 13 and 213 can be reduced, and the second nitride can be reduced.
- the crystallinity of the semiconductor layers 13 and 213 can be improved.
- the substrate temperature and the furnace pressure in the sixth nitride semiconductor layer forming step gradually change, when the fifth nitride semiconductor layer forming step is started, overshoot and undershoot of the substrate temperature and the furnace temperature are started. Can be suppressed.
- the second nitride semiconductor layers 13 and 213 are made of GaN
- the third nitride semiconductor layer 14B is made of Al x Ga 1-x N (0 ⁇ x ⁇ 1).
- the lattice mismatch between the second nitride semiconductor layers 13 and 213 and the third nitride semiconductor layer 14B is reduced, long-term reliability can be improved.
- the nitride semiconductor laminate of the present invention is A substrate 11; A first nitride semiconductor layer 12 formed above the substrate 11; Second nitride semiconductor layers 13 and 213 formed above the first nitride semiconductor layer 12; A third nitride semiconductor layer formed on an upper surface of the second nitride semiconductor layer, and having a band gap larger than that of the second nitride semiconductor layer; The formation of the second nitride semiconductor layers 13 and 213 and the formation of the third nitride semiconductor layers 14 and 14B are not interrupted, and the formation of the third nitride semiconductor layers 14 and 14B is not performed. The second nitride semiconductor layers 13 and 213 and the third nitride semiconductor layers 14 and 14B are formed so as to be carried out continuously with the formation of the physical semiconductor layers 13 and 213.
- the formation of the third nitride semiconductor layers 14 and 14B is not interrupted between the formation of the second nitride semiconductor layers 13 and 213 and the formation of the third nitride semiconductor layers 14 and 14B. Since the second nitride semiconductor layers 13 and 213 and the third nitride semiconductor layers 14 and 14B are formed so as to be carried out continuously with the formation of the second nitride semiconductor layers 13 and 213, the second nitride It is possible to suppress the formation of irregularities on the upper surface of the physical semiconductor.
- the second nitride semiconductor layers 13, 213 are A fourth nitride semiconductor layer 13A having a carbon concentration of less than 5 ⁇ 10 16 / cm 3 ; A fifth nitride semiconductor layer 13C formed above the fourth nitride semiconductor layer and having a carbon concentration of 5 ⁇ 10 16 / cm 3 or more and less than 1 ⁇ 10 18 / cm 3 .
- the carbon concentration of the fourth nitride semiconductor layer 13A is less than 5 ⁇ 10 16 / cm 3 , dislocations, nanopipes, and the like generated at the interface between the first nitride semiconductor layer 12 and the fourth nitride semiconductor layer 13A are devices. It is possible to prevent adverse effects on the characteristics.
- the fifth nitride semiconductor layer 13C and the third nitride semiconductor layer have a carbon concentration of 5 ⁇ 10 16 / cm 3 or more and less than 1 ⁇ 10 18 / cm 3. It is possible to prevent the flatness of the interface between 14 and 14B from being lowered.
- the nitride semiconductor multilayer body of one embodiment is A sixth nitride semiconductor layer 13B formed between the fourth nitride semiconductor layer 13A and the fifth nitride semiconductor layer 13C;
- the carbon concentration of the sixth nitride semiconductor layer 13B is substantially equal to the carbon concentration of the fourth nitride semiconductor layer 13A in the vicinity of the interface between the fourth nitride semiconductor layer 13A and the sixth nitride semiconductor layer 13B.
- the carbon concentration of the fifth nitride semiconductor layer 13C is substantially equal to the carbon concentration of the fifth nitride semiconductor layer 13C in the vicinity of the interface between the fifth nitride semiconductor layer 13C and the sixth nitride semiconductor layer 13B. It gradually increases from the lower side toward the upper side of the sixth nitride semiconductor layer 13B.
- the carbon concentration gradually increases from the carbon concentration substantially equal to the carbon concentration of the fourth nitride semiconductor layer 13A to the carbon concentration substantially equal to the carbon concentration of the fifth nitride semiconductor layer 13C. Accordingly, the formation condition of the fourth nitride semiconductor layer 13A can be gradually shifted to the formation condition of the fifth nitride semiconductor layer 13C. As a result, defects in the second nitride semiconductor layers 13 and 213 can be reduced, and the crystallinity of the second nitride semiconductor layers 13 and 213 can be improved.
- the second nitride semiconductor layers 13 and 213 are made of GaN
- the third nitride semiconductor layer 14B is made of Al x Ga 1-x N (0 ⁇ x ⁇ 1).
- the lattice mismatch between the second nitride semiconductor layers 13 and 213 and the third nitride semiconductor layer 14B is reduced, long-term reliability can be improved.
- the surface roughness by an atomic force microscope is 0.5 nm or less in a scanning range of 1 ⁇ m square.
- the source electrode 21, the drain electrode 22, and the gate electrode 23 are formed on the upper surfaces of the third nitride semiconductor layers 14 and 14B, the upper surfaces of the third nitride semiconductor layers 14 and 14B.
- the adhesion of the source electrode 21, the drain electrode 22 and the gate electrode 23 to the substrate can be improved.
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Abstract
Description
反応炉内で基板の上方に第1窒化物半導体層を形成する第1窒化物半導体層形成工程と、
上記第1窒化物半導体層の上方に第2窒化物半導体層を形成する第2窒化物半導体層形成工程と、
上記第2窒化物半導体層の上面に、上記第2窒化物半導体層よりもバンドギャップが大きい第3窒化物半導体層を形成する第3窒化物半導体層形成工程と
を備え、
上記第2窒化物半導体層形成工程と上記第3窒化物半導体層形成工程との間は中断されず、上記第3窒化物半導体層形成工程は上記第2窒化物半導体層形成工程に連続して実施されることを特徴としている。
上記第2窒化物半導体層形成工程は、
第4窒化物半導体層を形成する第4窒化物半導体層形成工程と、
上記第4窒化物半導体層の上方に第5窒化物半導体層を形成する第5窒化物半導体層形成工程と
を有し、
上記第4窒化物半導体層形成工程の基板温度よりも、上記第5窒化物半導体層形成工程の基板温度の方が高温であり、
上記第4窒化物半導体層形成工程の炉内圧力よりも、上記第5窒化物半導体層形成工程の炉内圧力の方が低圧である。
上記第2窒化物半導体層形成工程は、上記第4窒化物半導体層と上記第5窒化物半導体層との間に第6窒化物半導体層を形成する第6窒化物半導体層形成工程を有し、
上記第6窒化物半導体層形成工程の基板温度は、上記第4窒化物半導体層形成工程の基板温度と同じ温度から、上記第5窒化物半導体層形成工程の基板温度と同じ温度まで徐々に変化し、
上記第6窒化物半導体層形成工程の炉内圧力は、上記第4窒化物半導体層形成工程の炉内圧力と同じ圧力から、上記第5窒化物半導体層形成工程の炉内圧力と同じ圧力まで徐々に変化する。
上記第2窒化物半導体層はGaNからなり、
上記第3窒化物半導体層はAlxGa1-xN(0<x<1)からなる。
基板と、
上記基板の上方に形成される第1窒化物半導体層と、
上記第1窒化物半導体層の上方に形成される第2窒化物半導体層と、
上記第2窒化物半導体層の上面に形成され、上記第2窒化物半導体層よりもバンドギャップが大きい第3窒化物半導体層と
を備え、
上記第2窒化物半導体層の形成と上記第3窒化物半導体層の形成との間は中断されず、上記第3窒化物半導体層の形成は上記第2窒化物半導体層の形成に連続して実施されるように、上記第2窒化物半導体層および上記第3窒化物半導体層が形成されることを特徴としている。
上記第2窒化物半導体層が、
炭素濃度が5×1016/cm3未満である第4窒化物半導体層と、
上記第4窒化物半導体層の上方に形成され、炭素濃度が5×1016/cm3以上、1×1018/cm3未満である第5窒化物半導体層と
を有する。
上記第4窒化物半導体層と上記第5窒化物半導体層との間に形成された第6窒化物半導体層を備え、
上記第6窒化物半導体層の炭素濃度は、上記第4窒化物半導体層と上記第6窒化物半導体層との界面付近で上記第4窒化物半導体層の炭素濃度と略等しく、かつ、上記第5窒化物半導体層と上記第6窒化物半導体層との界面付近で上記第5窒化物半導体層の炭素濃度と略等しく、かつ、上記第6窒化物半導体層の下部側から上記第6窒化物半導体層の上部側に進むにしたがって徐々に増加する。
上記第2窒化物半導体層はGaNからなり、
上記第3窒化物半導体層はAlxGa1-xN(0<x<1)からなる。
上記第3窒化物半導体層の上面では、原子間力顕微鏡による表面粗さが1μm角の走査範囲にて0.5nm以下になる。
最初に、この発明の第1実施形態に係る窒化物半導体積層基板およびその製造方法について、図面を参照して説明する。
次に、この発明の第2実施形態に係る窒化物半導体積層基板およびその製造方法について、図面を参照して説明する。
次に、この発明の第3実施形態に係る窒化物半導体積層基板およびその製造方法について、図面を参照して説明する。
反応炉内で基板11の上方に第1窒化物半導体層12を形成する第1窒化物半導体層形成工程と、
上記第1窒化物半導体層12の上方に第2窒化物半導体層13,213を形成する第2窒化物半導体層形成工程と、
上記第2窒化物半導体層13,213の上面に、上記第2窒化物半導体層13,213よりもバンドギャップが大きい第3窒化物半導体層14,14Bを形成する第3窒化物半導体層形成工程と
を備え、
上記第2窒化物半導体層形成工程と上記第3窒化物半導体層形成工程との間は中断されず、上記第3窒化物半導体層形成工程は上記第2窒化物半導体層形成工程に連続して実施されることを特徴としている。
上記第2窒化物半導体層形成工程は、
第4窒化物半導体層13Aを形成する第4窒化物半導体層形成工程と、
上記第4窒化物半導体層13Aの上方に第5窒化物半導体層13Cを形成する第5窒化物半導体層形成工程と
を有し、
上記第4窒化物半導体層形成工程の基板温度よりも、上記第5窒化物半導体層形成工程の基板温度の方が高温であり、
上記第4窒化物半導体層形成工程の炉内圧力よりも、上記第5窒化物半導体層形成工程の炉内圧力の方が低圧である。
上記第2窒化物半導体層形成工程は、上記第4窒化物半導体層13Aと上記第5窒化物半導体層13Cとの間に第6窒化物半導体層13Bを形成する第6窒化物半導体層形成工程を有し、
上記第6窒化物半導体層形成工程の基板温度は、上記第4窒化物半導体層形成工程の基板温度と同じ温度から、上記第5窒化物半導体層形成工程の基板温度と同じ温度まで徐々に変化し、
上記第6窒化物半導体層形成工程の炉内圧力は、上記第4窒化物半導体層形成工程の炉内圧力と同じ圧力から、上記第5窒化物半導体層形成工程の炉内圧力と同じ圧力まで徐々に変化する。
上記第2窒化物半導体層13,213はGaNからなり、
上記第3窒化物半導体層14BはAlxGa1-xN(0<x<1)からなる。
基板11と、
この基板11の上方に形成される第1窒化物半導体層12と、
上記第1窒化物半導体層12の上方に形成される第2窒化物半導体層13,213と、
上記第2窒化物半導体層13,213の上面に形成され、上記第2窒化物半導体層13,213よりもバンドギャップが大きい第3窒化物半導体層14,14Bと
を備え、
上記第2窒化物半導体層13,213の形成と上記第3窒化物半導体層14,14Bの形成との間は中断されず、上記第3窒化物半導体層14,14Bの形成は上記第2窒化物半導体層13,213の形成に連続して実施されるように、上記第2窒化物半導体層13,213および上記第3窒化物半導体層14,14Bが形成されることを特徴としている。
上記第2窒化物半導体層13,213が、
炭素濃度が5×1016/cm3未満である第4窒化物半導体層13Aと、
上記第4窒化物半導体層の上方に形成され、炭素濃度が5×1016/cm3以上、1×1018/cm3未満である第5窒化物半導体層13Cと
を有する。
上記第4窒化物半導体層13Aの炭素濃度が5×1016/cm3未満であることにより、第1窒化物半導体層12と第4窒化物半導体層13Aの界面で生じる転位、ナノパイプ等がデバイス特性に悪影響を与えるのを防ぐことができる。
上記第4窒化物半導体層13Aと上記第5窒化物半導体層13Cとの間に形成された第6窒化物半導体層13Bを備え、
上記第6窒化物半導体層13Bの炭素濃度は、上記第4窒化物半導体層13Aと上記第6窒化物半導体層13Bとの界面付近で上記第4窒化物半導体層13Aの炭素濃度と略等しく、かつ、上記第5窒化物半導体層13Cと上記第6窒化物半導体層13Bとの界面付近で上記第5窒化物半導体層13Cの炭素濃度と略等しく、かつ、上記第6窒化物半導体層13Bの下部側から上記第6窒化物半導体層13Bの上部側に進むにしたがって徐々に増加する。
上記第2窒化物半導体層13,213はGaNからなり、
上記第3窒化物半導体層14BはAlxGa1-xN(0<x<1)からなる。
上記第3窒化物半導体層14,14Bの上面では、原子間力顕微鏡による表面粗さが1μm角の走査範囲にて0.5nm以下になる。
11 基板
12 バッファ層
13,213 電子走行層
13A 下地GaN層
13B スロープGaN層
13C チャネルGaN層
14 電子供給層
14A スペーサ層
14B 障壁層
15 二次元電子ガス
21 ソース電極
22 ドレイン電極
23 ゲート電極
SA,SB,SC スイッチング素子
Claims (9)
- 反応炉内で基板(11)の上方に第1窒化物半導体層(12)を形成する第1窒化物半導体層形成工程と、
上記第1窒化物半導体層(12)の上方に第2窒化物半導体層(13,213)を形成する第2窒化物半導体層形成工程と、
上記第2窒化物半導体層(13,213)の上面に、上記第2窒化物半導体層(13,213)よりもバンドギャップが大きい第3窒化物半導体層14,14B)を形成する第3窒化物半導体層形成工程と
を備え、
上記第2窒化物半導体層形成工程と上記第3窒化物半導体層形成工程との間は中断されず、上記第3窒化物半導体層形成工程は上記第2窒化物半導体層形成工程に連続して実施されることを特徴とする窒化物半導体積層体の製造方法。 - 請求項1に記載の窒化物半導体積層体の製造方法において、
上記第2窒化物半導体層形成工程は、
第4窒化物半導体層(13A)を形成する第4窒化物半導体層形成工程と、
上記第4窒化物半導体層(13A)の上方に第5窒化物半導体層(13C)を形成する第5窒化物半導体層形成工程と
を有し、
上記第4窒化物半導体層形成工程の基板温度よりも、上記第5窒化物半導体層形成工程の基板温度の方が高温であり、
上記第4窒化物半導体層形成工程の炉内圧力よりも、上記第5窒化物半導体層形成工程の炉内圧力の方が低圧であることを特徴とする窒化物半導体積層体の製造方法。 - 請求項2に記載の窒化物半導体積層体の製造方法において、
上記第2窒化物半導体層形成工程は、上記第4窒化物半導体層(13A)と上記第5窒化物半導体層(13C)との間に第6窒化物半導体層(13B)を形成する第6窒化物半導体層形成工程を有し、
上記第6窒化物半導体層形成工程の基板温度は、上記第4窒化物半導体層形成工程の基板温度と同じ温度から、上記第5窒化物半導体層形成工程の基板温度と同じ温度まで徐々に変化し、
上記第6窒化物半導体層形成工程の炉内圧力は、上記第4窒化物半導体層形成工程の炉内圧力と同じ圧力から、上記第5窒化物半導体層形成工程の炉内圧力と同じ圧力まで徐々に変化することを特徴とする窒化物半導体積層体の製造方法。 - 請求項1から3までのいずれか一項に記載の窒化物半導体積層体の製造方法において、
上記第2窒化物半導体層(13,213)はGaNからなり、
上記第3窒化物半導体層(14B)はAlxGa1-xN(0<x<1)からなることを特徴とする窒化物半導体積層体の製造方法。 - 基板(11)と、
上記基板(11)の上方に形成される第1窒化物半導体層(12)と、
上記第1窒化物半導体層12の上方に形成される第2窒化物半導体層(13,213)と、
上記第2窒化物半導体層(13,213)の上面に形成され、上記第2窒化物半導体層(13,213)よりもバンドギャップが大きい第3窒化物半導体層(14,14B)と
を備え、
上記第2窒化物半導体層(13,213)の形成と上記第3窒化物半導体層(14,14B)の形成との間は中断されず、上記第3窒化物半導体層(14,14B)の形成は上記第2窒化物半導体層(13,213)の形成に連続して実施されるように、上記第2窒化物半導体層(13,213)および上記第3窒化物半導体層(14,14B)が形成されることを特徴とする窒化物半導体積層体。 - 請求項5に記載の窒化物半導体積層体において、
上記第2窒化物半導体層(13,213)が、
炭素濃度が5×1016/cm3未満である第4窒化物半導体層(13A)と、
上記第4窒化物半導体層(13A)の上方に形成され、炭素濃度が5×1016/cm3以上、1×1018/cm3未満である第5窒化物半導体層(13C)と
を有することを特徴とする窒化物半導体積層体。 - 請求項6に記載の窒化物半導体積層体において、
上記第4窒化物半導体層(13A)と上記第5窒化物半導体層(13C)との間に形成された第6窒化物半導体層(13B)を備え、
上記第6窒化物半導体層(13B)の炭素濃度は、上記第4窒化物半導体層(13A)と上記第6窒化物半導体層(13B)との界面付近で上記第4窒化物半導体層(13A)の炭素濃度と略等しく、かつ、上記第5窒化物半導体層(13C)と上記第6窒化物半導体層(13B)との界面付近で上記第5窒化物半導体層(13C)の炭素濃度と略等しく、かつ、上記第6窒化物半導体層(13B)の下部側から上記第6窒化物半導体層(13B)の上部側に進むにしたがって徐々に増加することを特徴とする窒化物半導体積層体。 - 請求項5から7までのいずれか一項に記載の窒化物半導体積層体において、
上記第2窒化物半導体層(13,213)はGaNからなり、
上記第3窒化物半導体層(14B)はAlxGa1-xN(0<x<1)からなることを特徴とする窒化物半導体積層体。 - 請求項5から8までのいずれか一項に記載の窒化物半導体積層体において、
上記第3窒化物半導体層(14,14B)の上面では、原子間力顕微鏡による表面粗さが1μm角の走査範囲にて0.5nm以下になることを特徴とする窒化物半導体積層体。
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JP2018116971A (ja) * | 2017-01-16 | 2018-07-26 | 住友電工デバイス・イノベーション株式会社 | 半導体基板の製造方法 |
JP2018200934A (ja) * | 2017-05-26 | 2018-12-20 | 株式会社サイオクス | 窒化物半導体積層物、半導体装置、窒化物半導体積層物の製造方法および半導体装置の製造方法 |
CN109417035A (zh) * | 2016-06-27 | 2019-03-01 | 赛奥科思有限公司 | 氮化物半导体层叠物、氮化物半导体层叠物的制造方法、半导体层叠物的制造方法和半导体层叠物的检查方法 |
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