WO2016033830A1 - 一种扫描驱动电路及显示面板 - Google Patents

一种扫描驱动电路及显示面板 Download PDF

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Publication number
WO2016033830A1
WO2016033830A1 PCT/CN2014/086645 CN2014086645W WO2016033830A1 WO 2016033830 A1 WO2016033830 A1 WO 2016033830A1 CN 2014086645 W CN2014086645 W CN 2014086645W WO 2016033830 A1 WO2016033830 A1 WO 2016033830A1
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WO
WIPO (PCT)
Prior art keywords
tft switch
line
switches
clock cycle
scan
Prior art date
Application number
PCT/CN2014/086645
Other languages
English (en)
French (fr)
Inventor
郭晋波
王金杰
陈彩琴
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/396,052 priority Critical patent/US9437151B2/en
Publication of WO2016033830A1 publication Critical patent/WO2016033830A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a scan driving circuit and a display panel.
  • each pixel in the display panel consists of a scan line (Gate Line) and a data line (Data Line) control.
  • the number of scan lines also increases, and the number of fan-out lines corresponding to the scan lines also increases.
  • the gate drive chip corresponding to the fan-out line (Gate The number of ICs also increases, resulting in an area occupied by the fan-out area of the display panel, which makes it impossible to design a narrow bezel.
  • the area of the fan-out area of the display panel is kept constant, as the resolution of the display panel increases, the line width of the fan-out line corresponding to each scan line in the fan-out area decreases, thereby causing the fan.
  • the line width of the outgoing line is too small and there is a problem of disconnection or signal delay.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a display panel, which can reduce the number of gate driving chips used in the fan-out area and the wiring space of the fan-out line, thereby realizing the narrow frame design of the display panel.
  • the present invention adopts a technical solution to provide a scan driving circuit, which includes a plurality of scan driving units, wherein each scan driving unit includes a fan-out line, a plurality of sets of switches, and a plurality of a control line and a plurality of scan lines, the number of switches, the number of switches in each group of switches being the same as the number of control lines and scan lines; and the plurality of control lines and at least one of each group of switches in the plurality of switches
  • the switch is connected;
  • the fan-out line is connected to the plurality of scan lines through the plurality of sets of switches, and the plurality of sets of switches are in one-to-one correspondence with the plurality of scan lines, so that the plurality of scan lines are in an open state under the control of the fan-out line and the plurality of control lines;
  • the plurality of switches includes a first group of switches and a second group of switches, the first group of switches includes a first TFT switch and a second TFT switch, and the second group of
  • the plurality of control lines are respectively connected to at least one of the switches of the plurality of switches, wherein the first control line is connected to the gate of the first TFT switch and the source of the second TFT switch, and the second control line is connected. Connected to the gate of the second TFT switch; the first control line is connected to the gate of the fourth TFT switch, and the second control line is connected to the gate of the third TFT switch and the source of the fourth TFT switch.
  • a scan driving circuit which includes a plurality of scan driving units, wherein each scan driving unit includes a fan-out line, a plurality of sets of switches, a plurality of control lines and a plurality of scan lines, the number of switches, the number of switches in each group of switches being the same as the number of control lines and scan lines; and the plurality of control lines and at least one of each group of switches in the plurality of switches A switch connection; the fan-out line is connected to the plurality of scan lines through the plurality of sets of switches, and the plurality of sets of switches are in one-to-one correspondence with the plurality of scan lines, so that the plurality of scan lines are turned on under the control of the fan-out line and the plurality of control lines .
  • the plurality of switches includes a first group of switches and a second group of switches, the first group of switches includes a first TFT switch and a second TFT switch, and the second group of switches includes a third TFT switch and a fourth TFT switch, and a plurality of control lines A first control line and a second control line are included, and the plurality of scan lines include a first scan line and a second scan line.
  • the plurality of control lines are respectively connected to at least one of the switches of the plurality of switches, wherein the first control line is connected to the gate of the first TFT switch and the source of the second TFT switch, and the second control line is connected. Connected to the gate of the second TFT switch; the first control line is connected to the gate of the fourth TFT switch, and the second control line is connected to the gate of the third TFT switch and the source of the fourth TFT switch.
  • the fan-out line is connected to the plurality of scan lines through the plurality of switches, wherein the fan-out line is connected to the source of the first TFT switch, the drain of the first TFT switch is connected to the drain of the second TFT switch, and the second TFT switch is connected.
  • the drain is connected to the first scan line; the fan-out line is connected to the source of the third TFT switch, the drain of the third TFT switch is connected to the drain of the fourth TFT switch, and the drain and the second scan of the fourth TFT switch Wire connection.
  • the first control line when the fan-out line outputs a high-level signal in the first clock cycle and the second clock cycle, the first control line outputs a high-level signal in the first clock cycle, and outputs a low-level signal in the second clock cycle, and the second control The line outputs a low level signal in a first clock cycle and a high level signal in a second clock cycle such that the first scan line is turned on in the first clock cycle, turned off in the second clock cycle, and the second scan line is in the first The clock cycle is turned off and turned on in the second clock cycle.
  • the plurality of switches includes a first group switch, a second group switch, and a third group switch
  • the first group switch includes a first TFT switch, a second TFT switch, and a third TFT switch
  • the second group switch includes a fourth TFT switch a fifth TFT switch and a sixth TFT switch
  • the third group switch includes a seventh TFT switch, an eighth TFT switch, and a ninth TFT switch
  • the plurality of control lines include a first control line, a second control line, and a third control line
  • the plurality of scan lines include a first scan line, a second scan line, and a third scan line.
  • the plurality of control lines are respectively connected to at least one of the switches of the plurality of switches, wherein the first control line is connected to the gate of the first TFT switch and the source of the second TFT switch, and the second control line is connected. Connected to the gate of the second TFT switch and the source of the third TFT switch, the third control line is connected to the gate of the third TFT switch; the first control line is connected to the gate of the fifth TFT switch, and the second control line Connected to the gate of the fourth TFT switch, the source of the fifth TFT switch, and the source of the sixth TFT switch, and the third control line is connected to the gate of the sixth TFT switch; the first control line and the ninth TFT switch The gate is connected, the second control line is connected to the gate of the eighth TFT switch, and the third control line is connected to the gate of the seventh TFT switch, the source of the eighth TFT switch, and the source of the ninth TFT switch.
  • the fan-out line is connected to the plurality of scan lines through the plurality of switches, wherein the fan-out line is connected to the source of the first TFT switch, the drain of the first TFT switch is connected to the drain of the second TFT switch, and the second TFT switch is connected.
  • the drain is connected to the drain of the third TFT switch, the drain of the third TFT switch is connected to the first scan line; the fan-out line is connected to the source of the fourth TFT switch, and the drain of the fourth TFT switch is connected to the fifth TFT a drain of the switch is connected, a drain of the fifth TFT switch is connected to a drain of the sixth TFT switch, a drain of the sixth TFT switch is connected to a second scan line, and a fan-out line is connected to a source of the seventh TFT switch,
  • the drain of the seven TFT switch is connected to the drain of the eighth TFT switch, the drain of the eighth TFT switch is connected to the drain of the ninth TFT switch, and the drain of the ninth TFT switch is connected to the third scan line.
  • the first control line when the fan-out line outputs a high-level signal in the first clock cycle, the second clock cycle, and the third clock cycle, the first control line outputs a high-level signal, a second clock cycle, and a third clock in the first clock cycle.
  • the second control line Periodically outputting a low level signal, the second control line outputs a low level signal in the first clock cycle and the third clock cycle, a high level signal in the second clock cycle, and the third control line is in the first clock cycle and the second
  • the clock cycle outputs a low level signal, and outputs a high level signal during the third clock cycle, so that the first scan line is turned on in the first clock cycle, turned off in the second clock cycle and the third clock cycle, and the second scan line is in the One clock cycle is turned off, turned on in the second clock cycle, and turned off in the third clock cycle, and the third scan line is turned off in the first clock cycle and the second clock cycle, and is turned on in the third clock cycle.
  • a display panel including a plurality of gate driving chips and a scan driving circuit
  • the scan driving circuit includes a plurality of scan driving units.
  • Each scan driving unit includes a fan-out line, a plurality of groups of switches, a plurality of control lines, and a plurality of scan lines, and the number of switches, the number of switches in each group of switches, and the number of control lines and scan lines are the same;
  • the plurality of control lines are respectively connected to at least one of the switches of the plurality of switches;
  • the fan-out line is connected to the plurality of scan lines by the plurality of switches, and the plurality of switches correspond to the plurality of scan lines one by one to enable the plurality of scans
  • the line is in an open state under the control of the fan-out line and the plurality of control lines;
  • the plurality of gate driving chips are respectively connected to the fan-out lines of the plurality of scan driving units, and the plurality of gate driving chips are respectively corresponding to the
  • the plurality of switches includes a first group of switches and a second group of switches, the first group of switches includes a first TFT switch and a second TFT switch, and the second group of switches includes a third TFT switch and a fourth TFT switch, and a plurality of control lines A first control line and a second control line are included, and the plurality of scan lines include a first scan line and a second scan line.
  • the plurality of control lines are respectively connected to at least one of the switches of the plurality of switches, wherein the first control line is connected to the gate of the first TFT switch and the source of the second TFT switch, and the second control line is connected. Connected to the gate of the second TFT switch; the first control line is connected to the gate of the fourth TFT switch, and the second control line is connected to the gate of the third TFT switch and the source of the fourth TFT switch.
  • the fan-out line is connected to the plurality of scan lines through the plurality of switches, wherein the fan-out line is connected to the source of the first TFT switch, the drain of the first TFT switch is connected to the drain of the second TFT switch, and the second TFT switch is connected.
  • the drain is connected to the first scan line; the fan-out line is connected to the source of the third TFT switch, the drain of the third TFT switch is connected to the drain of the fourth TFT switch, and the drain and the second scan of the fourth TFT switch Wire connection.
  • the first control line when the fan-out line outputs a high-level signal in the first clock cycle and the second clock cycle, the first control line outputs a high-level signal in the first clock cycle, and outputs a low-level signal in the second clock cycle, and the second control The line outputs a low level signal in a first clock cycle and a high level signal in a second clock cycle such that the first scan line is turned on in the first clock cycle, turned off in the second clock cycle, and the second scan line is in the first The clock cycle is turned off and turned on in the second clock cycle.
  • the plurality of switches includes a first group switch, a second group switch, and a third group switch
  • the first group switch includes a first TFT switch, a second TFT switch, and a third TFT switch
  • the second group switch includes a fourth TFT switch a fifth TFT switch and a sixth TFT switch
  • the third group switch includes a seventh TFT switch, an eighth TFT switch, and a ninth TFT switch
  • the plurality of control lines include a first control line, a second control line, and a third control line
  • the plurality of scan lines include a first scan line, a second scan line, and a third scan line.
  • the plurality of control lines are respectively connected to at least one of the switches of the plurality of switches, wherein the first control line is connected to the gate of the first TFT switch and the source of the second TFT switch, and the second control line is connected. Connected to the gate of the second TFT switch and the source of the third TFT switch, the third control line is connected to the gate of the third TFT switch; the first control line is connected to the gate of the fifth TFT switch, and the second control line Connected to the gate of the fourth TFT switch, the source of the fifth TFT switch, and the source of the sixth TFT switch, and the third control line is connected to the gate of the sixth TFT switch; the first control line and the ninth TFT switch The gate is connected, the second control line is connected to the gate of the eighth TFT switch, and the third control line is connected to the gate of the seventh TFT switch, the source of the eighth TFT switch, and the source of the ninth TFT switch.
  • the fan-out line is connected to the plurality of scan lines through the plurality of switches, wherein the fan-out line is connected to the source of the first TFT switch, the drain of the first TFT switch is connected to the drain of the second TFT switch, and the second TFT switch is connected.
  • the drain is connected to the drain of the third TFT switch, the drain of the third TFT switch is connected to the first scan line; the fan-out line is connected to the source of the fourth TFT switch, and the drain of the fourth TFT switch is connected to the fifth TFT a drain of the switch is connected, a drain of the fifth TFT switch is connected to a drain of the sixth TFT switch, a drain of the sixth TFT switch is connected to a second scan line, and a fan-out line is connected to a source of the seventh TFT switch,
  • the drain of the seven TFT switch is connected to the drain of the eighth TFT switch, the drain of the eighth TFT switch is connected to the drain of the ninth TFT switch, and the drain of the ninth TFT switch is connected to the third scan line.
  • the first control line when the fan-out line outputs a high-level signal in the first clock cycle, the second clock cycle, and the third clock cycle, the first control line outputs a high-level signal, a second clock cycle, and a third clock in the first clock cycle.
  • the second control line Periodically outputting a low level signal, the second control line outputs a low level signal in the first clock cycle and the third clock cycle, a high level signal in the second clock cycle, and the third control line is in the first clock cycle and the second
  • the clock cycle outputs a low level signal, and outputs a high level signal during the third clock cycle, so that the first scan line is turned on in the first clock cycle, turned off in the second clock cycle and the third clock cycle, and the second scan line is in the One clock cycle is turned off, turned on in the second clock cycle, and turned off in the third clock cycle, and the third scan line is turned off in the first clock cycle and the second clock cycle, and is turned on in the third clock cycle.
  • the scan driving circuit and the display panel of the present invention are respectively connected to at least one switch of each group of switches through a plurality of control lines, and the fan-out line passes through multiple sets of switches and multiple strips.
  • the scan lines are connected so that the plurality of scan lines are turned on under the control of the fan-out line and the plurality of control lines, thereby implementing one fan-out line to drive the plurality of scan lines, thereby reducing the number of gate drive chips used in the fan-out area.
  • the routing space of the fan-out line thereby achieving the narrow bezel design of the display panel.
  • FIG. 1 is a schematic structural view of a display panel in the prior art
  • FIG. 2 is a schematic structural view of a scan driving circuit according to a first embodiment of the present invention
  • FIG. 3 is a circuit schematic diagram of a scan driving circuit of a second embodiment of the present invention.
  • Figure 4 is an operational waveform diagram of the scan driving unit shown in Figure 3;
  • Figure 5 is a circuit schematic diagram of a scan driving circuit of a third embodiment of the present invention.
  • Fig. 6 is a view showing an operation waveform of the scan driving unit shown in Fig. 5.
  • the scan driving circuit includes a plurality of scan driving units 10, each of which includes a fan-out line 11, a plurality of sets of switches 12, a plurality of control lines 13, and a plurality of scan lines 14, wherein the plurality of sets The number of sets of the switches 12 and the number of switches in each set of switches 12 are the same as the number of control lines 13 and scan lines 14. Among them, the plurality of control lines 13 of each of the scan driving units 10 are in communication with each other.
  • the plurality of control lines 13 are respectively connected to at least one of the switches of the plurality of switches 12, and the fan-out line 11 is connected to the plurality of scan lines 14 through the plurality of sets of switches 12, so that the plurality of scan lines 14 are on the fan-out line 11 and The interval under the control of the plurality of control lines 13 is in an on state.
  • the plurality of sets of switches 12 are in one-to-one correspondence with the plurality of scan lines 14.
  • FIG. 3 is a circuit schematic diagram of a scan driving circuit of a second embodiment of the present invention.
  • the scan driving circuit includes a plurality of scan driving units 20, each of which includes a fan-out line Fanout, a first TFT switch K1, a second TFT switch K2, a third TFT switch K3, and a fourth TFT.
  • the switch K4 the first control line L1, the second control line L2, the first scan line G1, and the second scan line G2.
  • the first control line L1 and the second control line L2 of each scan driving unit 20 are in communication with each other.
  • the number of switches, the number of switches in each group of switches, and the number of control lines and scan lines are the same, both being 2.
  • the first TFT switch K1 and the second TFT switch K2 form a first group of switches
  • the third TFT switch K3 and the fourth TFT switch K4 form a second group of switches.
  • the first control line L1 is connected to the gate of the first TFT switch K1 and the source of the second TFT switch K2, and the second control line L2 is connected to the gate of the second TFT switch K2, and the fanout line Fanout Connected to the source of the first TFT switch K1, the drain of the first TFT switch K1 is connected to the drain of the second TFT switch K2, and the drain of the second TFT switch K2 is connected to the first scan line G1.
  • the first control line L1 is connected to the gate of the fourth TFT switch K4, and the second control line L2 is connected to the gate of the third TFT switch K3 and the source of the fourth TFT switch K4, and the fanout line Fanout Connected to the source of the third TFT switch K3, the drain of the third TFT switch K3 is connected to the drain of the fourth TFT switch K4, and the drain of the fourth TFT switch K4 is connected to the second scan line G2.
  • FIG. 4 is an operation waveform diagram of the scan driving unit shown in FIG. 3.
  • the fan-out line Fanout of the scan driving unit 20 outputs a high level in the first clock cycle T1 and the second clock cycle T2, and the first control line L1 outputs a high-level signal in the first clock cycle T1.
  • the two clock cycle T2 outputs a low level signal
  • the second control line L2 outputs a low level signal at the first clock cycle T1 and a high level signal at the second clock cycle T2.
  • the first TFT switch K1 and the fourth TFT switch K4 are turned on, that is, the first TFT switch K1.
  • the source and the drain of the fourth TFT switch K4 are turned on, and the second TFT switch K2 and the third TFT switch K3 are turned off, that is, the source and drain of the second TFT switch K1 and the third TFT switch K4 are turned off.
  • the first TFT switch K1 When the first TFT switch K1 is turned on, since the source of the first TFT switch K1 is connected to the fan-out line Fanout, and the fan-out line Fanout outputs a high-level signal in the first clock cycle T1, the first TFT switch K1 is used.
  • the drain-connected first scan line G1 outputs a high-level signal, that is, the first scan line G1 is in an on state.
  • the fourth TFT switch K4 When the fourth TFT switch K4 is turned on, since the source of the fourth TFT switch K4 is connected to the second control line L2, and the second control line L2 outputs a low level signal during the first clock period T1, the fourth TFT switch is The second scan line G2 connected to the drain of K4 outputs a low level signal, that is, the second scan line G2 is in a off state.
  • the second control line L2 since the first control line L1 outputs a low level signal, the second control line L2 outputs a high level signal, the first TFT switch K1 and the fourth TFT switch K4 are turned off, and the second TFT switch K2 and the The three TFT switch K3 is turned on.
  • the second TFT switch K2 since the source of the second TFT switch K1 is connected to the first control line L1, and the first control line L1 outputs a low level signal in the second clock cycle T2, then the second The first scan line G1 connected to the drain of the TFT switch K2 outputs a low level signal, that is, the first scan line G1 is in a closed state.
  • the drain of the third TFT switch K3 is The connected second scanning line G2 outputs a high level signal, that is, the second scanning line G2 is in an on state.
  • the fan-out line Fanout of the scan driving unit 20 is set to output a low level at the third clock period T3 and the fourth clock period T4, and the first control line L1 repeats the signal states of the first clock period T1 and the second clock period T2, That is, the high-level signal is outputted in the third clock cycle T3, the low-level signal is outputted in the fourth clock cycle T4, and the second control line L2 repeats the signal state of the first clock cycle T1 and the second clock cycle T2, that is, in the first The three-clock period T3 outputs a low-level signal, and the fourth clock period T4 outputs a high-level signal, and the first scan line G1 and the second scan line G2 simultaneously output a low-level signal, that is, the first scan line G1 and the first The two scanning lines G2 are simultaneously turned off.
  • the fan-out lines Fanout of the plurality of scan driving units 20 are sequentially disposed to output a high-level signal of two clock cycles, and the first control line L1 is set to be first in two clock cycles. The output high level then outputs a low level, and the second control line L2 first outputs a low level and then outputs a high level for two clock cycles and switches in two clock cycles, thereby realizing the scanning line interval in the scan driving circuit. It is on. Specifically, taking two scan driving units 20 and four clock cycles as an example, the fan-out line Fanout of the first scan driving unit 20 is set to output a high-level signal in the first clock cycle and the second clock cycle.
  • the third clock cycle and the fourth clock cycle output a low-level signal
  • the fan-out line Fanout of the second scan driving unit 20 is set to output a low-level signal in the first clock cycle and the second clock cycle, in the third clock cycle, and Four clock cycles output a high level signal
  • the first control line L1 is set to output a high level signal in the first clock cycle, a low level signal in the second clock cycle, and a high level in the third clock cycle.
  • the signal outputs a low level signal in the fourth clock cycle, sets the second control line L2 to output a low level signal in the first clock cycle, outputs a high level signal in the second clock cycle, and outputs a low level in the third clock cycle.
  • the signal outputs a high level signal in the fourth clock cycle, and in the first clock cycle, only the first scan line G1 of the first scan driving unit 20 outputs a high level signal, in the second clock cycle. Only the second scan line G2 of the first scan driving unit 20 outputs a high level signal, and in the third clock cycle, only the first scan line G1 of the second scan driving unit 20 outputs a high level signal, in the fourth clock cycle. Only the second scan line G2 of the second scan driving unit 20 outputs a high level signal, thereby realizing that the four scanning line intervals in the scan driving circuit are in an on state.
  • FIG. 5 is a circuit schematic diagram of a scan driving circuit of a third embodiment of the present invention.
  • the scan driving circuit includes a plurality of scan driving units 30, each of which includes a fan-out line Fanout, a first TFT switch K1, a second TFT switch K2, a third TFT switch K3, and a fourth TFT.
  • the first control line L1, the second control line L2, and the third control line L3 of each scan driving unit 30 are in communication with each other.
  • the number of switches, the number of switches in each group of switches, and the number of control lines and scan lines are the same, both being 3.
  • the first TFT switch K1, the second TFT switch K2, and the third TFT switch K3 form a first group switch
  • the fourth TFT switch K4 the fifth TFT switch K5, and the sixth TFT switch K6 form a second group switch
  • the TFT switch K7, the eighth TFT switch K8, and the ninth TFT switch K9 form a third group of switches.
  • the first control line L1 is connected to the gate of the first TFT switch K1 and the source of the second TFT switch K2, the second control line L2 and the gate of the second TFT switch K2 and the third TFT switch
  • the source of K3 is connected
  • the third control line L3 is connected to the gate of the third TFT switch K3
  • the fan-out line Fanout is connected to the source of the first TFT switch K1, the drain of the first TFT switch K1 and the second TFT switch K2
  • the drain of the second TFT switch K2 is connected to the drain of the third TFT switch K3, and the drain of the third TFT switch K3 is connected to the first scan line G1.
  • the first control line L1 is connected to the gate of the fifth TFT switch K5, the second control line L2 and the gate of the fourth TFT switch K4, the source of the fifth TFT switch K5, and the sixth TFT switch
  • the source of K6 is connected
  • the third control line L3 is connected to the gate of the sixth TFT switch K6
  • the fan-out line Fanout is connected to the source of the fourth TFT switch K4
  • the drain of the fourth TFT switch K4 and the fifth TFT switch K5 are connected.
  • the drain is connected, the drain of the fifth TFT switch K5 is connected to the drain of the sixth TFT switch K6, and the drain of the sixth TFT switch K6 is connected to the second scan line G2.
  • the first control line L1 is connected to the gate of the ninth TFT switch K9
  • the second control line L2 is connected to the gate of the eighth TFT switch K8, and the third control line L3 and the seventh TFT switch K7 are connected.
  • the gate, the source of the eighth TFT switch K8 and the source of the ninth TFT switch K9 are connected
  • the fan-out line Fanout is connected to the source of the seventh TFT switch K7
  • the drain of the seventh TFT switch K7 and the eighth TFT switch K8 The drain is connected
  • the drain of the eighth TFT switch K8 is connected to the drain of the ninth TFT switch K9
  • the drain of the ninth TFT switch K9 is connected to the third scan line G3.
  • FIG. 6 is an operation waveform diagram of the scan driving unit shown in FIG. 5.
  • the fan-out line Fanout of the scan driving unit 30 outputs a high level in the first clock cycle T1, the second clock cycle T2, and the third clock cycle T3, and the first control line L1 outputs a high value in the first clock cycle T1.
  • the level signal outputs a low level signal at the second clock period T2 and the third clock period T3, and the second control line L2 outputs a high level signal at the second clock period T2, at the first clock period T1 and the third clock period T3 outputs a low level signal, and the third control line L3 outputs a high level signal at the third clock period T3, and outputs a low level signal at the first clock period T1 and the second clock period T2.
  • the first TFT switch K1 and the fifth TFT are turned on, and the second TFT switch K2, the third TFT switch K3, the fourth TFT switch K4, the sixth TFT switch K6, the seventh TFT switch K7, and the eighth TFT switch K8 are turned off.
  • the first TFT switch K1 When the first TFT switch K1 is turned on, since the source of the first TFT switch K1 is connected to the fan-out line Fanout, and the fan-out line Fanout outputs a high-level signal in the first clock cycle T1, the first TFT switch K1 is used.
  • the drain-connected first scan line G1 outputs a high-level signal, that is, the first scan line G1 is in an on state.
  • the fifth TFT switch is turned on, since the source of the fifth TFT switch K5 is connected to the second control line L2, and the second control line L2 outputs a low level signal in the first clock cycle T1, the fifth TFT switch K5 is connected.
  • the second scan line G2 connected to the drain outputs a low level signal, that is, the second scan line G2 is in a closed state.
  • the ninth TFT switch K9 is turned on, since the source of the ninth TFT switch K9 is connected to the third control line L3, and the third control line L3 outputs a low level signal at the first clock period T1, the ninth TFT switch is The third scan line G3 connected to the drain of K9 outputs a low level signal, that is, the third scan line G3 is in a closed state.
  • the second TFT switch K2 and the fourth TFT are outputted because the first control line L1 outputs a low level signal, the second control line L2 outputs a high level signal, and the third control line L3 outputs a low level signal.
  • the switch K4 and the eighth TFT switch K8 are turned on, and the first TFT switch K1, the third TFT switch K3, the fifth TFT switch K5, the sixth TFT switch K6, the seventh TFT switch K7, and the ninth TFT switch K9 are turned off.
  • the second TFT switch K2 when the second TFT switch K2 is turned on, since the source of the second TFT switch K2 is connected to the first control line L1, and the first control line L1 outputs a low level signal in the second clock cycle T2, then the second The first scan line G1 connected to the drain of the TFT switch K2 outputs a low level signal, that is, the first scan line G1 is in a closed state.
  • the drain of the fourth TFT switch K4 is used.
  • the connected second scanning line G2 outputs a high level signal, that is, the second scanning line G2 is in an on state.
  • the eighth TFT switch K8 is turned on, since the source of the eighth TFT switch K8 is connected to the third control line L3, and the third control line L3 outputs a low level signal in the second clock period T2, the eighth TFT switch is The third scan line G3 connected to the drain of K8 outputs a low level signal, that is, the third scan line G3 is turned off.
  • the third TFT switch K3 In the third clock cycle T3, since the first control line L1 outputs a low level signal, the second control line L2 outputs a low level signal, and the third control line L3 outputs a high level signal, the third TFT switch K3, the sixth TFT The switch K6 and the seventh TFT switch K7 are turned on, and the first TFT switch K1, the second TFT switch K2, the fourth TFT switch K4, the fifth TFT switch K5, the eighth TFT switch K8, and the ninth TFT switch K9 are turned off.
  • the third TFT switch K3 when the third TFT switch K3 is turned on, since the source of the third TFT switch K3 is connected to the second control line L2, and the second control line L2 outputs a low level signal in the third clock period T3, then the third The first scan line G1 connected to the drain of the TFT switch K3 outputs a low level signal, that is, the first scan line G1 is in a closed state.
  • the sixth TFT switch K6 is turned on, since the source of the sixth TFT switch K6 is connected to the second control line L2, and the second control line L2 outputs a low level signal in the third clock period T3, the sixth TFT switch is used.
  • the second scan line G2 connected to the drain of K6 outputs a low level signal, that is, the second scan line G2 is turned off.
  • the seventh TFT switch K7 is turned on, since the source of the seventh TFT switch K7 is connected to the fan-out line Fanout, and the fan-out line Fanout outputs a high-level signal at the third clock cycle T3, the drain of the seventh TFT switch K7 is connected.
  • the connected third scanning line G3 outputs a high level signal, that is, the third scanning line G3 is in an on state.
  • the fan-out line Fanout of the scan driving unit 20 is set to output a low level in the fourth clock cycle T4, the fifth clock cycle T5, and the sixth clock cycle T6, and the first control line L1 repeats the first clock cycle T1 and the second clock cycle.
  • the signal, the third control line L3 repeats the signal states of the first clock cycle T1, the second clock cycle T2, and the third clock cycle T3, that is, outputs a high-level signal at the sixth clock cycle T6, and at the fourth clock cycle T4.
  • the fifth clock period T5 outputs a low level signal
  • the first scan line G1 and the second scan line G2 simultaneously output a low level signal in the fourth clock period T4, the fifth clock period T5, and the sixth clock period T6, that is, First scan line G1, Scanning lines G2 and G3 while the third scan line in a closed state.
  • the fan-out lines Fanout of the plurality of scan driving units 20 are sequentially disposed to output a high-level signal of three clock cycles, and the first control line L1 is set to be first in three clock cycles.
  • the output high level then outputs a low level of two clock cycles
  • the second control line L2 first outputs a low level
  • the third control line L3 first outputs two periods of low power.
  • the fan-out line Fanout of the first scan driving unit 30 is set to output high in the first clock cycle, the second clock cycle, and the third clock cycle.
  • the level signal outputs a low level signal in the fourth clock period, the fifth clock period, and the sixth clock period, and sets the fan out line Fanout of the second scan driving unit 30 in the first clock period, the second clock period, and the third
  • the clock cycle outputs a low level signal, and outputs a high level signal in the fourth clock cycle, the fifth clock cycle, and the sixth clock cycle, and at the same time, sets the first control line L1 to output a high level signal in the first clock cycle, Outputting a low level signal in a second clock cycle, outputting a low level signal in a third clock cycle, and setting a level state of the first clock cycle to the third clock cycle from a fourth clock cycle to a sixth clock cycle, setting a second
  • the control line L2 outputs a low level signal in a first clock cycle, a high
  • the second embodiment shown in FIG. 3 and the third embodiment shown in FIG. 5 respectively describe two scanning lines and three scanning lines by one fan-out line, respectively, based on a similar principle.
  • a fan-out line driving four scan lines and more scan lines will also fall within the scope of the present invention.
  • the TFT switch in the second embodiment shown in FIG. 3 and the third embodiment shown in FIG. 5 operates in an open or closed state, and the source and the drain thereof can be interchanged and then connected to the scan driving circuit.
  • the invention is not limited thereto.
  • the present invention further provides a display panel including a plurality of gate driving chips and the above scanning driving circuit, wherein the plurality of gate driving chips are respectively connected to fan-out lines of the plurality of scanning driving units, and the plurality of gate driving chips One-to-one correspondence with multiple fan-out lines.
  • the scan driving circuit and the display panel of the present invention are respectively connected to at least one switch of each group of switches through a plurality of control lines, and the fan-out line passes through multiple sets of switches and multiple strips.
  • the scan lines are connected so that the plurality of scan lines are turned on under the control of the fan-out line and the plurality of control lines, thereby implementing one fan-out line to drive the plurality of scan lines, thereby reducing the number of gate drive chips used in the fan-out area.
  • the routing space of the fan-out line thereby achieving the narrow bezel design of the display panel.

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Abstract

一种扫描驱动电路，该扫描驱动电路包括多个扫描驱动单元（10），每一扫描驱动单元（10）包括一条扇出线（11）、多组开关（12）、多条控制线（13）和多条扫描线（14），多条控制线（13）分别与各组开关（12）中的至少一个开关连接，扇出线（11）通过多组开关（12）与多条扫描线（14）连接，以使多条扫描线（14）在扇出线（11）和多条控制线（13）的控制下间隔处于开启状态。该扫描驱动电路能够实现一条扇出线（11）驱动多条扫描线（14），从而减少扇出区中栅极驱动芯片的使用数量以及扇出线（11）的走线空间。还提供了一种包括上述扫描驱动电路的显示面板。

Description

一种扫描驱动电路及显示面板
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种扫描驱动电路及显示面板。
【背景技术】
图1是现有技术中显示面板的结构示意图。如图1所示，显示面板中每个像素点由一条扫描线（Gate Line）和一条数据线（Data Line）控制。一个解析度为M×N的显示面板，将会有M条扫描线Gn(n=1，2…，M)和3N条数据线Dn(n=1，2…，3N)。
随着显示面板的解析度的提高，扫描线的数量也会随之增多，与扫描线对应的扇出线的数量也随之增多，当采用单栅极（Single Gate）驱动方式驱动扫描线时，与扇出线对应的栅极驱动芯片（Gate IC）的数量也会随之增加，从而导致显示面板的扇出区占用的面积变大，从而无法实现窄边框的设计。另外，若保持显示面板的扇出区的面积不变，则随着显示面板的解析度的提高，扇出区中与每条扫描线对应的扇出线的线宽会随之减少，从而导致扇出线的线宽过小而出现断线或者信号延迟的问题。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及显示面板，能够减少扇出区中栅极驱动芯片的使用数量以及扇出线的走线空间，从而实现显示面板的窄边框设计。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，该扫描驱动电路包括多个扫描驱动单元，其中，每一扫描驱动单元包括一条扇出线、多组开关、多条控制线和多条扫描线，开关的组数、每组开关中开关的个数与控制线和扫描线的条数相同；多条控制线分别与多组开关中各组开关中的至少一个开关连接；扇出线通过多组开关与多条扫描线连接，多组开关与多条扫描线一一对应，以使多条扫描线在扇出线和多条控制线的控制下间隔处于开启状态；其中，多组开关包括第一组开关和第二组开关，第一组开关包括第一TFT开关和第二TFT开关，第二组开关包括第三TFT开关和第四TFT开关，多条控制线包括第一控制线和第二控制线，多条扫描线包括第一扫描线和第二扫描线；其中，每个扫描驱动单元的第一控制线和第二控制线相互连通。
其中，多条控制线分别与多组开关中各组开关中的至少一个开关连接具体为：第一控制线与第一TFT开关的栅极和第二TFT开关的源极连接，第二控制线与第二TFT开关的栅极连接；第一控制线与第四TFT开关的栅极连接，第二控制线与第三TFT开关的栅极和第四TFT开关的源极连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种扫描驱动电路，该扫描驱动电路包括多个扫描驱动单元，其中，每一扫描驱动单元包括一条扇出线、多组开关、多条控制线和多条扫描线，开关的组数、每组开关中开关的个数与控制线和扫描线的条数相同；多条控制线分别与多组开关中各组开关中的至少一个开关连接；扇出线通过多组开关与多条扫描线连接，多组开关与多条扫描线一一对应，以使多条扫描线在扇出线和多条控制线的控制下间隔处于开启状态。
其中，多组开关包括第一组开关和第二组开关，第一组开关包括第一TFT开关和第二TFT开关，第二组开关包括第三TFT开关和第四TFT开关，多条控制线包括第一控制线和第二控制线，多条扫描线包括第一扫描线和第二扫描线。
其中，多条控制线分别与多组开关中各组开关中的至少一个开关连接具体为：第一控制线与第一TFT开关的栅极和第二TFT开关的源极连接，第二控制线与第二TFT开关的栅极连接；第一控制线与第四TFT开关的栅极连接，第二控制线与第三TFT开关的栅极和第四TFT开关的源极连接。
其中，扇出线通过多组开关与多条扫描线连接具体为：扇出线与第一TFT开关的源极连接，第一TFT开关的漏极与第二TFT开关的漏极连接，第二TFT开关的漏极与第一扫描线连接；扇出线与第三TFT开关的源极连接，第三TFT开关的漏极与第四TFT开关的漏极连接，第四TFT开关的漏极与第二扫描线连接。
其中，扇出线在第一时钟周期和第二时钟周期输出高电平信号时，第一控制线在第一时钟周期输出高电平信号、在第二时钟周期输出低电平信号，第二控制线在第一时钟周期输出低电平信号、在第二时钟周期输出高电平信号，以使第一扫描线在第一时钟周期开启、在第二时钟周期关闭，第二扫描线在第一时钟周期关闭、在第二时钟周期开启。
其中，多组开关包括第一组开关、第二组开关和第三组开关，第一组开关包括第一TFT开关、第二TFT开关和第三TFT开关，第二组开关包括第四TFT开关、第五TFT开关和第六TFT开关，第三组开关包括第七TFT开关、第八TFT开关和第九TFT开关，多条控制线包括第一控制线、第二控制线和第三控制线，多条扫描线包括第一扫描线、第二扫描线和第三扫描线。
其中，多条控制线分别与多组开关中各组开关中的至少一个开关连接具体为：第一控制线与第一TFT开关的栅极和第二TFT开关的源极连接，第二控制线与第二TFT开关的栅极和第三TFT开关的源极连接，第三控制线与第三TFT开关的栅极连接；第一控制线与第五TFT开关的栅极连接，第二控制线与第四TFT开关的栅极、第五TFT开关的源极和第六TFT开关的源极连接，第三控制线与第六TFT开关的栅极连接；第一控制线与第九TFT开关的栅极连接，第二控制线与第八TFT开关的栅极连接，第三控制线与第七TFT开关的栅极、第八TFT开关的源极和第九TFT开关的源极连接。
其中，扇出线通过多组开关与多条扫描线连接具体为：扇出线与第一TFT开关的源极连接，第一TFT开关的漏极与第二TFT开关的漏极连接，第二TFT开关的漏极与第三TFT开关的漏极连接，第三TFT开关的漏极与第一扫描线连接；扇出线与第四TFT开关的源极连接，第四TFT开关的漏极与第五TFT开关的漏极连接，第五TFT开关的漏极与第六TFT开关的漏极连接，第六TFT开关的漏极与第二扫描线连接；扇出线与第七TFT开关的源极连接，第七TFT开关的漏极与第八TFT开关的漏极连接，第八TFT开关的漏极与第九TFT开关的漏极连接，第九TFT开关的漏极与第三扫描线连接。
其中，扇出线在第一时钟周期、第二时钟周期和第三时钟周期输出高电平信号时，第一控制线在第一时钟周期输出高电平信号、在第二时钟周期和第三时钟周期输出低电平信号，第二控制线在第一时钟周期和第三时钟周期输出低电平信号、在第二时钟周期输出高电平信号，第三控制线在第一时钟周期和第二时钟周期输出低电平信号、在第三时钟周期输出高电平信号，以使第一扫描线在第一时钟周期开启、在第二时钟周期和第三时钟周期关闭，第二扫描线在第一时钟周期关闭、在第二时钟周期开启、在第三时钟周期关闭，第三扫描线在第一时钟周期和第二时钟周期关闭、在第三时钟周期开启。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示面板，该显示面板包括多个栅极驱动芯片和扫描驱动电路，其中，该扫描驱动电路包括多个扫描驱动单元，其中，每一扫描驱动单元包括一条扇出线、多组开关、多条控制线和多条扫描线，开关的组数、每组开关中开关的个数与控制线和扫描线的条数相同；多条控制线分别与多组开关中各组开关中的至少一个开关连接；扇出线通过多组开关与多条扫描线连接，多组开关与多条扫描线一一对应，以使多条扫描线在扇出线和多条控制线的控制下间隔处于开启状态；多个栅极驱动芯片分别与多个扫描驱动单元中的扇出线连接，多个栅极驱动芯片与多个扇出线一一对应。
其中，多组开关包括第一组开关和第二组开关，第一组开关包括第一TFT开关和第二TFT开关，第二组开关包括第三TFT开关和第四TFT开关，多条控制线包括第一控制线和第二控制线，多条扫描线包括第一扫描线和第二扫描线。
其中，多条控制线分别与多组开关中各组开关中的至少一个开关连接具体为：第一控制线与第一TFT开关的栅极和第二TFT开关的源极连接，第二控制线与第二TFT开关的栅极连接；第一控制线与第四TFT开关的栅极连接，第二控制线与第三TFT开关的栅极和第四TFT开关的源极连接。
其中，扇出线通过多组开关与多条扫描线连接具体为：扇出线与第一TFT开关的源极连接，第一TFT开关的漏极与第二TFT开关的漏极连接，第二TFT开关的漏极与第一扫描线连接；扇出线与第三TFT开关的源极连接，第三TFT开关的漏极与第四TFT开关的漏极连接，第四TFT开关的漏极与第二扫描线连接。
其中，扇出线在第一时钟周期和第二时钟周期输出高电平信号时，第一控制线在第一时钟周期输出高电平信号、在第二时钟周期输出低电平信号，第二控制线在第一时钟周期输出低电平信号、在第二时钟周期输出高电平信号，以使第一扫描线在第一时钟周期开启、在第二时钟周期关闭，第二扫描线在第一时钟周期关闭、在第二时钟周期开启。
其中，多组开关包括第一组开关、第二组开关和第三组开关，第一组开关包括第一TFT开关、第二TFT开关和第三TFT开关，第二组开关包括第四TFT开关、第五TFT开关和第六TFT开关，第三组开关包括第七TFT开关、第八TFT开关和第九TFT开关，多条控制线包括第一控制线、第二控制线和第三控制线，多条扫描线包括第一扫描线、第二扫描线和第三扫描线。
其中，多条控制线分别与多组开关中各组开关中的至少一个开关连接具体为：第一控制线与第一TFT开关的栅极和第二TFT开关的源极连接，第二控制线与第二TFT开关的栅极和第三TFT开关的源极连接，第三控制线与第三TFT开关的栅极连接；第一控制线与第五TFT开关的栅极连接，第二控制线与第四TFT开关的栅极、第五TFT开关的源极和第六TFT开关的源极连接，第三控制线与第六TFT开关的栅极连接；第一控制线与第九TFT开关的栅极连接，第二控制线与第八TFT开关的栅极连接，第三控制线与第七TFT开关的栅极、第八TFT开关的源极和第九TFT开关的源极连接。
其中，扇出线通过多组开关与多条扫描线连接具体为：扇出线与第一TFT开关的源极连接，第一TFT开关的漏极与第二TFT开关的漏极连接，第二TFT开关的漏极与第三TFT开关的漏极连接，第三TFT开关的漏极与第一扫描线连接；扇出线与第四TFT开关的源极连接，第四TFT开关的漏极与第五TFT开关的漏极连接，第五TFT开关的漏极与第六TFT开关的漏极连接，第六TFT开关的漏极与第二扫描线连接；扇出线与第七TFT开关的源极连接，第七TFT开关的漏极与第八TFT开关的漏极连接，第八TFT开关的漏极与第九TFT开关的漏极连接，第九TFT开关的漏极与第三扫描线连接。
其中，扇出线在第一时钟周期、第二时钟周期和第三时钟周期输出高电平信号时，第一控制线在第一时钟周期输出高电平信号、在第二时钟周期和第三时钟周期输出低电平信号，第二控制线在第一时钟周期和第三时钟周期输出低电平信号、在第二时钟周期输出高电平信号，第三控制线在第一时钟周期和第二时钟周期输出低电平信号、在第三时钟周期输出高电平信号，以使第一扫描线在第一时钟周期开启、在第二时钟周期和第三时钟周期关闭，第二扫描线在第一时钟周期关闭、在第二时钟周期开启、在第三时钟周期关闭，第三扫描线在第一时钟周期和第二时钟周期关闭、在第三时钟周期开启。
本发明的有益效果是：区别于现有技术的情况，本发明的扫描驱动电路及显示面板通过多条控制线分别与各组开关中的至少一个开关连接，扇出线通过多组开关与多条扫描线连接，以使多条扫描线在扇出线和多条控制线的控制下间隔处于开启状态，从而实现一条扇出线驱动多条扫描线，进而减少扇出区中栅极驱动芯片的使用数量以及扇出线的走线空间，进而可以实现显示面板的窄边框设计。
【附图说明】
图1是现有技术中显示面板的结构示意图；
图2是本发明第一实施例的扫描驱动电路的结构示意图；
图3是本发明第二实施例的扫描驱动电路的电路原理图；
图4是图3所示的扫描驱动单元的工作波形图；
图5是本发明第三实施例的扫描驱动电路的电路原理图；
图6是图5所示的扫描驱动单元的工作波形图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图2是本发明第一实施例的扫描驱动电路的结构示意图。如图2所示，扫描驱动电路包括多个扫描驱动单元10，每个扫描驱动单元10包括一条扇出线11、多组开关12、多条控制线13和多条扫描线14，其中，多组开关12的组数、每组开关12中开关的个数与控制线13和扫描线14的条数相同。其中，每个扫描驱动单元10的多条控制线13相互连通。
多条控制线13分别与多组开关12中各组开关中的至少一个开关连接，扇出线11通过多组开关12与多条扫描线14连接，以使多条扫描线14在扇出线11和多条控制线13的控制下间隔处于开启状态。其中，多组开关12与多条扫描线14一一对应。
图3是本发明第二实施例的扫描驱动电路的电路原理图。如图3所示，扫描驱动电路包括多个扫描驱动单元20，每个扫描驱动单元20包括一条扇出线Fanout、第一TFT开关K1、第二TFT开关K2、第三TFT开关K3、第四TFT开关K4、第一控制线L1、第二控制线L2、第一扫描线G1和第二扫描线G2。其中，每个扫描驱动单元20的第一控制线L1和第二控制线L2相互连通。
其中，开关的组数、每组开关中开关的个数、控制线和扫描线的条数均相同，均为2。
其中，第一TFT开关K1和第二TFT开关K2形成第一组开关，第三TFT开关K3和第四TFT开关K4形成第二组开关。
对于第一组开关，第一控制线L1与第一TFT开关K1的栅极和第二TFT开关K2的源极连接，第二控制线L2与第二TFT开关K2的栅极连接，扇出线Fanout与第一TFT开关K1的源极连接，第一TFT开关K1的漏极与第二TFT开关K2的漏极连接，第二TFT开关K2的漏极与第一扫描线G1连接。
对于第二组开关，第一控制线L1与第四TFT开关K4的栅极连接，第二控制线L2与第三TFT开关K3的栅极和第四TFT开关K4的源极连接，扇出线Fanout与第三TFT开关K3的源极连接，第三TFT开关K3的漏极与第四TFT开关K4的漏极连接，第四TFT开关K4的漏极与第二扫描线G2连接。
请一并参考图4，图4是图3所示的扫描驱动单元的工作波形图。如图4所示，扫描驱动单元20的扇出线Fanout在第一时钟周期T1和第二时钟周期T2输出高电平，第一控制线L1在第一时钟周期T1输出高电平信号、在第二时钟周期T2输出低电平信号，第二控制线L2在第一时钟周期T1输出低电平信号、在第二时钟周期T2输出高电平信号。
在第一时钟周期T1，由于第一控制线L1输出高电平信号、第二控制线L2输出低电平信号，第一TFT开关K1和第四TFT开关K4打开，也即第一TFT开关K1和第四TFT开关K4的源极和漏极导通，第二TFT开关K2和第三TFT开关K3关闭，也即第二TFT开关K1和第三TFT开关K4的源极和漏极截止。其中，当第一TFT开关K1打开时，由于第一TFT开关K1的源极与扇出线Fanout连接，而扇出线Fanout在第一时钟周期T1输出高电平信号，则与第一TFT开关K1的漏极连接的第一扫描线G1输出高电平信号，也即第一扫描线G1处于开启状态。当第四TFT开关K4打开时，由于第四TFT开关K4的源极与第二控制线L2连接，而第二控制线L2在第一时钟周期T1输出低电平信号，则与第四TFT开关K4的漏极连接的第二扫描线G2输出低电平信号，也即第二扫描线G2处于关闭状态。
在第二时钟周期T2，由于第一控制线L1输出低电平信号，第二控制线L2输出高电平信号，第一TFT开关K1和第四TFT开关K4关闭，第二TFT开关K2和第三TFT开关K3打开。其中，当第二TFT开关K2打开时，由于第二TFT开关K1的源极与第一控制线L1连接，而第一控制线L1在第二时钟周期T2输出低电平信号，则与第二TFT开关K2的漏极连接的第一扫描线G1输出低电平信号，也即第一扫描线G1处于关闭状态。当第三TFT开关K3打开时，由于第三TFT开关K3的源极与扇出线Fanout连接，而扇出线Fanout在第二时钟周期T2输出高电平信号，则与第三TFT开关K3的漏极连接的第二扫描线G2输出高电平信号，也即第二扫描线G2处于开启状态。
随后，设置扫描驱动单元20的扇出线Fanout在第三时钟周期T3和第四时钟周期T4输出低电平，第一控制线L1重复第一时钟周期T1和第二时钟周期T2的信号状态，也即在第三时钟周期T3输出高电平信号、在第四时钟周期T4输出低电平信号，第二控制线L2重复第一时钟周期T1和第二时钟周期T2的信号状态，也即在第三时钟周期T3输出低电平信号、在第四时钟周期T4输出高电平信号，则第一扫描线G1和第二扫描线G2同时输出低电平信号，也即第一扫描线G1和第二扫描线G2同时处于关闭状态。
当扫描驱动电路中包括多个扫描驱动单元20时，依次设置多个扫描驱动单元20中的扇出线Fanout输出两个时钟周期的高电平信号，设置第一控制线L1在两个时钟周期首先输出高电平随后输出低电平、第二控制线L2首先输出低电平随后输出高电平以两个时钟周期并以两个时钟周期进行切换，即可实现扫描驱动电路中各扫描线间隔处于开启状态。具体来说，以两个扫描驱动单元20、四个时钟周期为例来说，设置第一个扫描驱动单元20的扇出线Fanout在第一时钟周期和第二时钟周期输出高电平信号、在第三时钟周期和第四时钟周期输出低电平信号，设置第二个扫描驱动单元20的扇出线Fanout在第一时钟周期和第二时钟周期输出低电平信号、在第三时钟周期和第四时钟周期输出高电平信号，与此同时，设置第一控制线L1在第一时钟周期输出高电平信号、在第二时钟周期输出低电平信号、在第三时钟周期输出高电平信号、在第四时钟周期输出低电平信号，设置第二控制线L2在第一时钟周期输出低电平信号、在第二时钟周期输出高电平信号、在第三时钟周期输出低电平信号、在第四时钟周期输出高电平信号，则在第一时钟周期，仅仅第一个扫描驱动单元20的第一扫描线G1输出高电平信号，在第二时钟周期，仅仅第一扫描驱动单元20的第二扫描线G2输出高电平信号，在第三时钟周期，仅仅第二个扫描驱动单元20的第一扫描线G1输出高电平信号，在第四时钟周期，仅仅第二扫描驱动单元20的第二扫描线G2输出高电平信号，从而实现扫描驱动电路中四条扫描线间隔处于开启状态。
图5是本发明第三实施例的扫描驱动电路的电路原理图。如图5所示，扫描驱动电路包括多个扫描驱动单元30，每个扫描驱动单元30包括一条扇出线Fanout、第一TFT开关K1、第二TFT开关K2、第三TFT开关K3、第四TFT开关K4、第五TFT开关K5、第六TFT开关K6、第七TFT开关K7、第八TFT开关K8、第九TFT开关K9、第一控制线L1、第二控制线L2、第三控制线L3、第一扫描线G1、第二扫描线G2和第三扫描线G3。其中，每个扫描驱动单元30的第一控制线L1、第二控制线L2和第三控制线L3相互连通。
其中，开关的组数、每组开关中开关的个数、控制线和扫描线的条数均相同，均为3。
其中，第一TFT开关K1、第二TFT开关K2、第三TFT开关K3形成第一组开关，第四TFT开关K4、第五TFT开关K5、第六TFT开关K6形成第二组开关，第七TFT开关K7、第八TFT开关K8、第九TFT开关K9形成第三组开关。
对于第一组开关，第一控制线L1与第一TFT开关K1的栅极和第二TFT开关K2的源极连接，第二控制线L2与第二TFT开关K2的栅极和第三TFT开关K3的源极连接，第三控制线L3与第三TFT开关K3的栅极连接，扇出线Fanout与第一TFT开关K1的源极连接，第一TFT开关K1的漏极与第二TFT开关K2的漏极连接，第二TFT开关K2的漏极与第三TFT开关K3的漏极连接，第三TFT开关K3的漏极与第一扫描线G1连接。
对于第二组开关，第一控制线L1与第五TFT开关K5的栅极连接，第二控制线L2与第四TFT开关K4的栅极、第五TFT开关K5的源极和第六TFT开关K6的源极连接，第三控制线L3与第六TFT开关K6的栅极连接，扇出线Fanout与第四TFT开关K4的源极连接，第四TFT开关K4的漏极与第五TFT开关K5的漏极连接，第五TFT开关K5的漏极与第六TFT开关K6的漏极连接，第六TFT开关K6的漏极与第二扫描线G2连接。
对于第三组开关，第一控制线L1与第九TFT开关K9的栅极连接，第二控制线L2与第八TFT开关K8的栅极连接，第三控制线L3与第七TFT开关K7的栅极、第八TFT开关K8的源极和第九TFT开关K9的源极连接，扇出线Fanout与第七TFT开关K7的源极连接，第七TFT开关K7的漏极与第八TFT开关K8的漏极连接，第八TFT开关K8的漏极与第九TFT开关K9的漏极连接，第九TFT开关K9的漏极与第三扫描线G3连接。
请一并参考图6，图6是图5所示的扫描驱动单元的工作波形图。如图6所示，扫描驱动单元30的扇出线Fanout在第一时钟周期T1、第二时钟周期T2和第三时钟周期T3输出高电平，第一控制线L1在第一时钟周期T1输出高电平信号、在第二时钟周期T2和第三时钟周期T3输出低电平信号，第二控制线L2在第二时钟周期T2输出高电平信号、在第一时钟周期T1和第三时钟周期T3输出低电平信号，第三控制线L3在第三时钟周期T3输出高电平信号、在第一时钟周期T1和第二时钟周期T2输出低电平信号。
在第一时钟周期T1，由于第一控制线L1输出高电平信号、第二控制线L2输出低电平信号、第三控制线L3输出低电平信号，第一TFT开关K1、第五TFT开关K5和第九TFT开关K9打开，第二TFT开关K2、第三TFT开关K3、第四TFT开关K4、第六TFT开关K6、第七TFT开关K7、第八TFT开关K8关闭。其中，当第一TFT开关K1打开时，由于第一TFT开关K1的源极与扇出线Fanout连接，而扇出线Fanout在第一时钟周期T1输出高电平信号，则与第一TFT开关K1的漏极连接的第一扫描线G1输出高电平信号，也即第一扫描线G1处于开启状态。当第五TFT开关打开时，由于第五TFT开关K5的源极与第二控制线L2连接，而第二控制线L2在第一时钟周期T1输出低电平信号，则与第五TFT开关K5的漏极连接的第二扫描线G2输出低电平信号，也即第二扫描线G2处于关闭状态。当第九TFT开关K9打开时，由于第九TFT开关K9的源极与第三控制线L3连接，而第三控制线L3在第一时钟周期T1输出低电平信号，则与第九TFT开关K9的漏极连接的第三扫描线G3输出低电平信号，也即第三扫描线G3处于关闭状态。
在第二时钟周期T2，由于第一控制线L1输出低电平信号、第二控制线L2输出高电平信号、第三控制线L3输出低电平信号，第二TFT开关K2、第四TFT开关K4和第八TFT开关K8打开，第一TFT开关K1、第三TFT开关K3、第五TFT开关K5、第六TFT开关K6、第七TFT开关K7、第九TFT开关K9关闭。其中，当第二TFT开关K2打开时，由于第二TFT开关K2的源极与第一控制线L1连接，而第一控制线L1在第二时钟周期T2输出低电平信号，则与第二TFT开关K2的漏极连接的第一扫描线G1输出低电平信号，也即第一扫描线G1处于关闭状态。当第四TFT开关K4打开时，由于第四TFT开关K4的源极与扇出线Fanout连接，而扇出线Fanout在第二时钟周期T2输出高电平信号，则与第四TFT开关K4的漏极连接的第二扫描线G2输出高电平信号，也即第二扫描线G2处于开启状态。当第八TFT开关K8打开时，由于第八TFT开关K8的源极与第三控制线L3连接，而第三控制线L3在第二时钟周期T2输出低电平信号，则与第八TFT开关K8的漏极连接的第三扫描线G3输出低电平信号，也即第三扫描线G3处于关闭状态。
在第三时钟周期T3，由于第一控制线L1输出低电平信号、第二控制线L2输出低电平信号、第三控制线L3输出高电平信号，第三TFT开关K3、第六TFT开关K6和第七TFT开关K7打开，第一TFT开关K1、第二TFT开关K2、第四TFT开关K4、第五TFT开关K5、第八TFT开关K8、第九TFT开关K9关闭。其中，当第三TFT开关K3打开时，由于第三TFT开关K3的源极与第二控制线L2连接，而第二控制线L2在第三时钟周期T3输出低电平信号，则与第三TFT开关K3的漏极连接的第一扫描线G1输出低电平信号，也即第一扫描线G1处于关闭状态。当第六TFT开关K6打开时，由于第六TFT开关K6的源极与第二控制线L2连接，而第二控制线L2在第三时钟周期T3输出低电平信号，则与第六TFT开关K6的漏极连接的第二扫描线G2输出低电平信号，也即第二扫描线G2处于关闭。当第七TFT开关K7打开时，由于第七TFT开关K7的源极与扇出线Fanout连接，而扇出线Fanout在第三时钟周期T3输出高电平信号，则与第七TFT开关K7的漏极连接的第三扫描线G3输出高电平信号，也即第三扫描线G3处于开启状态。
随后，设置扫描驱动单元20的扇出线Fanout在第四时钟周期T4、第五时钟周期T5、第六时钟周期T6输出低电平，第一控制线L1重复第一时钟周期T1、第二时钟周期T2和第三时钟周期T3的信号状态，也即在第四时钟周期T4输出高电平信号、在第五时钟周期T5和第六时钟周期T6输出低电平信号，第二控制线L2重复第一时钟周期T1、第二时钟周期T2和第三时钟周期T3的信号状态，也即在第五时钟周期T5输出高电平信号、在第四时钟周期T4和第六时钟周期T6输出低电平信号，第三控制线L3重复第一时钟周期T1、第二时钟周期T2和第三时钟周期T3的信号状态，也即在第六时钟周期T6输出高电平信号、在第四时钟周期T4和第五时钟周期T5输出低电平信号，则第一扫描线G1和第二扫描线G2在第四时钟周期T4、第五时钟周期T5、第六时钟周期T6同时输出低电平信号，也即第一扫描线G1、第二扫描线G2和第三扫描线G3同时处于关闭状态。
当扫描驱动电路中包括多个扫描驱动单元30时，依次设置多个扫描驱动单元20中的扇出线Fanout输出三个时钟周期的高电平信号，设置第一控制线L1在三个时钟周期首先输出高电平随后输出两个时钟周期的低电平、第二控制线L2首先输出低电平随后输出高电平再随后输出高电平、第三控制线L3首先输出两个周期的低电平随后输出高电平并以三个时钟周期进行切换，即可实现扫描驱动电路中各扫描线间隔处于开启状态。具体来说，以两个扫描驱动单元30、六个时钟周期为例来说，设置第一个扫描驱动单元30的扇出线Fanout在第一时钟周期、第二时钟周期和第三时钟周期输出高电平信号，在第四时钟周期、第五时钟周期和第六时钟周期输出低电平信号，设置第二个扫描驱动单元30的扇出线Fanout在第一时钟周期、第二时钟周期和第三时钟周期输出低电平信号，在第四时钟周期、第五时钟周期和第六时钟周期输出高电平信号，与此同时，设置第一控制线L1在第一时钟周期输出高电平信号、在第二时钟周期输出低电平信号、在第三时钟周期输出低电平信号、设置第四时钟周期至第六时钟周期重复第一时钟周期至第三时钟周期的电平状态，设置第二控制线L2在第一时钟周期输出低电平信号、在第二时钟周期输出高电平信号、在第三时钟周期输出低电平信号、设置第四时钟周期至第六时钟周期重复第一时钟周期至第三时钟周期的电平状态，设置第三控制线L3在第一时钟周期输出低电平信号、在第二时钟周期输出低电平信号、在第三时钟周期输出高电平信号、设置第四时钟周期至第六时钟周期重复第一时钟周期至第三时钟周期的电平状态，则在第一时钟周期，仅仅第一个扫描驱动单元30的第一扫描线G1输出高电平信号，在第二时钟周期，仅仅第一扫描驱动单元30的第二扫描线G2输出高电平信号，在第三时钟周期，仅仅第一扫描驱动单元30的第三扫描线G3输出高电平信号，在第四时钟周期，仅仅第二个扫描驱动单元30的第一扫描线G1输出高电平信号，在第五时钟周期，仅仅第二个扫描驱动单元30的第二扫描线G2输出高电平信号，在第六时钟周期，仅仅第二个扫描驱动单元20的第三扫描线G3输出高电平信号，从而实现扫描驱动电路中六条扫描线间隔处于开启状态。
本领域的技术人员可以理解，图3所示的第二实施例和图5所示的第三实施例分别以一条扇出线驱动两条扫描线和三条扫描线为例进行说明，基于类似的原理，一条扇出线驱动四条扫描线以及更多的扫描线也将落在本发明的保护范围之内。另外，图3所示的第二实施例和图5所示的第三实施例中的TFT开关工作在打开或者关闭的状态下，其源极和漏极可以相互调换后接入扫描驱动电路中，本发明不以此为限。
本发明进一步提供一种显示面板，包括了多个栅极驱动芯片和上述扫描驱动电路，其中，多个栅极驱动芯片分别与多个扫描驱动单元中的扇出线连接，多个栅极驱动芯片与多个扇出线一一对应。
本发明的有益效果是：区别于现有技术的情况，本发明的扫描驱动电路及显示面板通过多条控制线分别与各组开关中的至少一个开关连接，扇出线通过多组开关与多条扫描线连接，以使多条扫描线在扇出线和多条控制线的控制下间隔处于开启状态，从而实现一条扇出线驱动多条扫描线，进而减少扇出区中栅极驱动芯片的使用数量以及扇出线的走线空间，进而可以实现显示面板的窄边框设计。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种扫描驱动电路，其中，包括：多个扫描驱动单元，其中，每一所述扫描驱动单元包括一条扇出线、多组开关、多条控制线和多条扫描线，所述开关的组数、每组所述开关中开关的个数与所述控制线和所述扫描线的条数相同；
    所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接；
    所述扇出线通过所述多组开关与所述多条扫描线连接，所述多组开关与所述多条扫描线一一对应，以使所述多条扫描线在所述扇出线和所述多条控制线的控制下间隔处于开启状态；
    其中，所述多组开关包括第一组开关和第二组开关，所述第一组开关包括第一TFT开关和第二TFT开关，所述第二组开关包括第三TFT开关和第四TFT开关，所述多条控制线包括第一控制线和第二控制线，所述多条扫描线包括第一扫描线和第二扫描线；
    其中，每个扫描驱动单元的第一控制线和第二控制线相互连通。
  2. 根据权利要求1所述的电路，其中，所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接具体为：
    所述第一控制线与所述第一TFT开关的栅极和所述第二TFT开关的源极连接，所述第二控制线与所述第二TFT开关的栅极连接；
    所述第一控制线与所述第四TFT开关的栅极连接，所述第二控制线与所述第三TFT开关的栅极和所述第四TFT开关的源极连接。
  3. 一种扫描驱动电路，其中，包括：多个扫描驱动单元，其中，每一所述扫描驱动单元包括一条扇出线、多组开关、多条控制线和多条扫描线，所述开关的组数、每组所述开关中开关的个数与所述控制线和所述扫描线的条数相同；
    所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接；
    所述扇出线通过所述多组开关与所述多条扫描线连接，所述多组开关与所述多条扫描线一一对应，以使所述多条扫描线在所述扇出线和所述多条控制线的控制下间隔处于开启状态。
  4. 根据权利要求3所述的电路，其中，所述多组开关包括第一组开关和第二组开关，所述第一组开关包括第一TFT开关和第二TFT开关，所述第二组开关包括第三TFT开关和第四TFT开关，所述多条控制线包括第一控制线和第二控制线，所述多条扫描线包括第一扫描线和第二扫描线。
  5. 根据权利要求4所述的电路，其中，所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接具体为：
    所述第一控制线与所述第一TFT开关的栅极和所述第二TFT开关的源极连接，所述第二控制线与所述第二TFT开关的栅极连接；
    所述第一控制线与所述第四TFT开关的栅极连接，所述第二控制线与所述第三TFT开关的栅极和所述第四TFT开关的源极连接。
  6. 根据权利要求5所述的电路，其中，所述扇出线通过所述多组开关与所述多条扫描线连接具体为：
    所述扇出线与所述第一TFT开关的源极连接，所述第一TFT开关的漏极与所述第二TFT开关的漏极连接，所述第二TFT开关的漏极与所述第一扫描线连接；
    所述扇出线与所述第三TFT开关的源极连接，所述第三TFT开关的漏极与所述第四TFT开关的漏极连接，所述第四TFT开关的漏极与所述第二扫描线连接。
  7. 根据权利要求6所述的电路，其中，所述扇出线在第一时钟周期和第二时钟周期输出高电平信号时，所述第一控制线在所述第一时钟周期输出高电平信号、在所述第二时钟周期输出低电平信号，所述第二控制线在所述第一时钟周期输出低电平信号、在所述第二时钟周期输出高电平信号，以使所述第一扫描线在所述第一时钟周期开启、在所述第二时钟周期关闭，所述第二扫描线在所述第一时钟周期关闭、在所述第二时钟周期开启。
  8. 根据权利要求3所述的电路，其中，所述多组开关包括第一组开关、第二组开关和第三组开关，所述第一组开关包括第一TFT开关、第二TFT开关和第三TFT开关，所述第二组开关包括第四TFT开关、第五TFT开关和第六TFT开关，所述第三组开关包括第七TFT开关、第八TFT开关和第九TFT开关，所述多条控制线包括第一控制线、第二控制线和第三控制线，所述多条扫描线包括第一扫描线、第二扫描线和第三扫描线。
  9. 根据权利要求8所述的电路，其中，所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接具体为：
    所述第一控制线与所述第一TFT开关的栅极和所述第二TFT开关的源极连接，所述第二控制线与所述第二TFT开关的栅极和所述第三TFT开关的源极连接，所述第三控制线与所述第三TFT开关的栅极连接；
    所述第一控制线与所述第五TFT开关的栅极连接，所述第二控制线与所述第四TFT开关的栅极、所述第五TFT开关的源极和所述第六TFT开关的源极连接，所述第三控制线与所述第六TFT开关的栅极连接；
    所述第一控制线与所述第九TFT开关的栅极连接，所述第二控制线与所述第八TFT开关的栅极连接，所述第三控制线与所述第七TFT开关的栅极、所述第八TFT开关的源极和所述第九TFT开关的源极连接。
  10. 根据权利要求9所述的电路，其中，所述扇出线通过所述多组开关与所述多条扫描线连接具体为：
    所述扇出线与所述第一TFT开关的源极连接，所述第一TFT开关的漏极与所述第二TFT开关的漏极连接，所述第二TFT开关的漏极与所述第三TFT开关的漏极连接，所述第三TFT开关的漏极与所述第一扫描线连接；
    所述扇出线与所述第四TFT开关的源极连接，所述第四TFT开关的漏极与所述第五TFT开关的漏极连接，所述第五TFT开关的漏极与所述第六TFT开关的漏极连接，所述第六TFT开关的漏极与所述第二扫描线连接；
    所述扇出线与所述第七TFT开关的源极连接，所述第七TFT开关的漏极与所述第八TFT开关的漏极连接，所述第八TFT开关的漏极与所述第九TFT开关的漏极连接，所述第九TFT开关的漏极与所述第三扫描线连接。
  11. 根据权利要求10所述的电路，其中，所述扇出线在第一时钟周期、第二时钟周期和第三时钟周期输出高电平信号时，所述第一控制线在所述第一时钟周期输出高电平信号、在所述第二时钟周期和所述第三时钟周期输出低电平信号，所述第二控制线在所述第一时钟周期和所述第三时钟周期输出低电平信号、在所述第二时钟周期输出高电平信号，所述第三控制线在所述第一时钟周期和所述第二时钟周期输出低电平信号、在所述第三时钟周期输出高电平信号，以使所述第一扫描线在所述第一时钟周期开启、在所述第二时钟周期和所述第三时钟周期关闭，所述第二扫描线在所述第一时钟周期关闭、在所述第二时钟周期开启、在所述第三时钟周期关闭，所述第三扫描线在所述第一时钟周期和所述第二时钟周期关闭、在所述第三时钟周期开启。
  12. 一种显示面板，其中，所述显示面板包括多个栅极驱动芯片和扫描驱动电路，其中：
    所述扫描驱动电路包括：多个扫描驱动单元，其中，每一所述扫描驱动单元包括一条扇出线、多组开关、多条控制线和多条扫描线，所述开关的组数、每组所述开关中开关的个数与所述控制线和所述扫描线的条数相同；
    所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接；
    所述扇出线通过所述多组开关与所述多条扫描线连接，所述多组开关与所述多条扫描线一一对应，以使所述多条扫描线在所述扇出线和所述多条控制线的控制下间隔处于开启状态；
    所述多个栅极驱动芯片分别与所述多个扫描驱动单元中的所述扇出线连接，所述多个栅极驱动芯片与多个所述扇出线一一对应。
  13. 根据权利要求12所述的显示面板，其中，所述多组开关包括第一组开关和第二组开关，所述第一组开关包括第一TFT开关和第二TFT开关，所述第二组开关包括第三TFT开关和第四TFT开关，所述多条控制线包括第一控制线和第二控制线，所述多条扫描线包括第一扫描线和第二扫描线。
  14. 根据权利要求13所述的显示面板，其中，所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接具体为：
    所述第一控制线与所述第一TFT开关的栅极和所述第二TFT开关的源极连接，所述第二控制线与所述第二TFT开关的栅极连接；
    所述第一控制线与所述第四TFT开关的栅极连接，所述第二控制线与所述第三TFT开关的栅极和所述第四TFT开关的源极连接。
  15. 根据权利要求14所述的显示面板，其中，所述扇出线通过所述多组开关与所述多条扫描线连接具体为：
    所述扇出线与所述第一TFT开关的源极连接，所述第一TFT开关的漏极与所述第二TFT开关的漏极连接，所述第二TFT开关的漏极与所述第一扫描线连接；
    所述扇出线与所述第三TFT开关的源极连接，所述第三TFT开关的漏极与所述第四TFT开关的漏极连接，所述第四TFT开关的漏极与所述第二扫描线连接。
  16. 根据权利要求15所述的显示面板，其中，所述扇出线在第一时钟周期和第二时钟周期输出高电平信号时，所述第一控制线在所述第一时钟周期输出高电平信号、在所述第二时钟周期输出低电平信号，所述第二控制线在所述第一时钟周期输出低电平信号、在所述第二时钟周期输出高电平信号，以使所述第一扫描线在所述第一时钟周期开启、在所述第二时钟周期关闭，所述第二扫描线在所述第一时钟周期关闭、在所述第二时钟周期开启。
  17. 根据权利要求12所述的显示面板，其中，所述多组开关包括第一组开关、第二组开关和第三组开关，所述第一组开关包括第一TFT开关、第二TFT开关和第三TFT开关，所述第二组开关包括第四TFT开关、第五TFT开关和第六TFT开关，所述第三组开关包括第七TFT开关、第八TFT开关和第九TFT开关，所述多条控制线包括第一控制线、第二控制线和第三控制线，所述多条扫描线包括第一扫描线、第二扫描线和第三扫描线。
  18. 根据权利要求17所述的显示面板，其中，所述多条控制线分别与所述多组开关中各组所述开关中的至少一个开关连接具体为：
    所述第一控制线与所述第一TFT开关的栅极和所述第二TFT开关的源极连接，所述第二控制线与所述第二TFT开关的栅极和所述第三TFT开关的源极连接，所述第三控制线与所述第三TFT开关的栅极连接；
    所述第一控制线与所述第五TFT开关的栅极连接，所述第二控制线与所述第四TFT开关的栅极、所述第五TFT开关的源极和所述第六TFT开关的源极连接，所述第三控制线与所述第六TFT开关的栅极连接；
    所述第一控制线与所述第九TFT开关的栅极连接，所述第二控制线与所述第八TFT开关的栅极连接，所述第三控制线与所述第七TFT开关的栅极、所述第八TFT开关的源极和所述第九TFT开关的源极连接。
  19. 根据权利要求18所述的显示面板，其中，所述扇出线通过所述多组开关与所述多条扫描线连接具体为：
    所述扇出线与所述第一TFT开关的源极连接，所述第一TFT开关的漏极与所述第二TFT开关的漏极连接，所述第二TFT开关的漏极与所述第三TFT开关的漏极连接，所述第三TFT开关的漏极与所述第一扫描线连接；
    所述扇出线与所述第四TFT开关的源极连接，所述第四TFT开关的漏极与所述第五TFT开关的漏极连接，所述第五TFT开关的漏极与所述第六TFT开关的漏极连接，所述第六TFT开关的漏极与所述第二扫描线连接；
    所述扇出线与所述第七TFT开关的源极连接，所述第七TFT开关的漏极与所述第八TFT开关的漏极连接，所述第八TFT开关的漏极与所述第九TFT开关的漏极连接，所述第九TFT开关的漏极与所述第三扫描线连接。
  20. 根据权利要求19所述的显示面板，其中，所述扇出线在第一时钟周期、第二时钟周期和第三时钟周期输出高电平信号时，所述第一控制线在所述第一时钟周期输出高电平信号、在所述第二时钟周期和所述第三时钟周期输出低电平信号，所述第二控制线在所述第一时钟周期和所述第三时钟周期输出低电平信号、在所述第二时钟周期输出高电平信号，所述第三控制线在所述第一时钟周期和所述第二时钟周期输出低电平信号、在所述第三时钟周期输出高电平信号，以使所述第一扫描线在所述第一时钟周期开启、在所述第二时钟周期和所述第三时钟周期关闭，所述第二扫描线在所述第一时钟周期关闭、在所述第二时钟周期开启、在所述第三时钟周期关闭，所述第三扫描线在所述第一时钟周期和所述第二时钟周期关闭、在所述第三时钟周期开启。
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