WO2016023305A1 - Transistor à couches minces et son procédé de fabrication, substrat matriciel et dispositif d'affichage - Google Patents

Transistor à couches minces et son procédé de fabrication, substrat matriciel et dispositif d'affichage Download PDF

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Publication number
WO2016023305A1
WO2016023305A1 PCT/CN2014/092908 CN2014092908W WO2016023305A1 WO 2016023305 A1 WO2016023305 A1 WO 2016023305A1 CN 2014092908 W CN2014092908 W CN 2014092908W WO 2016023305 A1 WO2016023305 A1 WO 2016023305A1
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layer
thin film
film transistor
shielding layer
contact region
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PCT/CN2014/092908
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English (en)
Chinese (zh)
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孙建
樊君
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2016023305A1 publication Critical patent/WO2016023305A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • liquid crystal display has become a mainstream product in flat panel display devices due to its small size, low power consumption, and no radiation.
  • a thin film transistor is an indispensable switching device in a liquid crystal display device.
  • the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, and the active layer is usually formed of an amorphous silicon (a-Si) material.
  • a-Si amorphous silicon
  • a polysilicon (p-Si) thin film layer may be formed, and then a polysilicon (p-Si) thin film layer is doped or the like to form an active region, a source contact region, and a drain contact region of the active layer.
  • a polysilicon (p-Si) thin film layer is doped or the like to form an active region, a source contact region, and a drain contact region of the active layer.
  • Polycrystalline silicon includes high temperature polysilicon (HTPS) and low temperature polysilicon (LTPS), wherein a thin film transistor using low temperature polysilicon to form an active layer has high electron mobility and reduced device size, and thus is widely used in liquid crystal display devices.
  • HTPS high temperature polysilicon
  • LTPS low temperature polysilicon
  • a high aperture ratio is achieved, which in turn makes the corresponding display device have the advantages of high brightness and low power consumption.
  • a thin film transistor formed by using a low-temperature polysilicon material to form an active layer has a relatively large leakage current, and a main cause of a large leakage current is a backlight to an active region during display. Irradiation is performed to generate a large photo-leakage current. At present, the leakage current is mainly reduced by preparing a layer of light-shielding metal under the active region. At the same time, the thin-film transistor adopts a double-gate structure to reduce the leakage current to some extent.
  • the light-shielding metal layer under the active region of the double-gate structure thin film transistor is separated (ie, the light-shielding metal layer is divided into two pieces with a small area, and two pieces are spaced apart), in this case Since the facing area between the light-shielding metal layer and the active region is relatively reduced, the parasitic capacitance is reduced, which enables the yield of the product to be higher.
  • a thin film transistor includes a gate, an active region, a source contact region and a drain contact region, the gate is disposed above the active region, and the source contact region and the drain contact are respectively disposed at The opposite sides of the active area.
  • the thin film transistor further includes a non-metal light shielding layer disposed under the active region and at least partially overlapping the active region in a right projection direction, the non-metal light shielding layer capable of The entire visible light from the backlight that is illuminated thereon is occluded.
  • the non-metallic light-shielding layer is formed using a one-dimensional photonic crystal optical film including a first film layer and a second film layer that are alternately stacked.
  • the first film layer and the second film layer that are alternately stacked are one or more groups.
  • the first film layer and the second film layer have different refractive indices, and the first film layer and the second film layer have a refractive index ranging from 1 to 5.
  • the first film layer is made of TiO 2 material
  • the second film layer is made of SiO 2 material.
  • the thickness ratio of the first film layer to the second film layer is 1:1.136.
  • the non-metallic light shielding layer is disposed between the source contact region and a region corresponding to the drain contact region, and at least partially overlaps the gate electrode in a right projection direction.
  • the gate is at least one, and the gate is located in a front projection direction of the non-metallic light shielding layer.
  • a lightly doped drain contact region is disposed in the active region, and the lightly doped drain contact region is disposed between the source contact region and the drain contact region, and is separated The two sides of the area corresponding to the gate.
  • a gate insulating layer is further disposed between the active region and the gate, and a buffer layer is further disposed between the non-metal light shielding layer and the active region.
  • an array substrate is provided.
  • the array substrate includes a thin film transistor as described above.
  • a display device includes the array substrate as described above.
  • a method of fabricating a thin film transistor as described above includes the steps of forming a gate, an active region, a source contact region, and a drain contact region. The method also includes the step of forming a non-metallic light shielding layer.
  • the preparation method includes: Step S1: forming a pattern including the non-metal light shielding layer on a base substrate by using a patterning process; Step S2: sequentially forming a buffer layer on the substrate substrate completing the step S1 and including a pattern of the active region; step S3: sequentially forming a gate insulating layer and a pattern including the gate on the substrate of the step S2; step S4: on the substrate of the step S3
  • the source contact region and the drain contact region are formed, and the source contact region and the drain contact region are formed on opposite sides of the active region by ion implantation.
  • the pattern forming the non-metallic light shielding layer on the substrate by using a patterning process includes:
  • the step of forming the non-metal light shielding layer includes: Step S11: forming a layer on the substrate substrate a first film layer; step S12: forming a second film film on the substrate of the step S11; step S13: forming a pattern including the non-metal light shielding layer by one patterning process;
  • the step of forming the non-metal light shielding layer includes: repeating the step S11 and the step S12 a plurality of times, A pattern including the non-metallic light shielding layer is then formed by one patterning process.
  • step S11 and the step S12 may be interchanged.
  • the step S4 further includes forming a lightly doped drain contact region in the active region by ion implantation.
  • FIG. 1 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the present invention
  • Figure 2 is a cross-sectional view showing the structure of the non-metallic light shielding layer shown in Figure 1;
  • FIG. 3 is a cross-sectional view showing another structure of the non-metal light shielding layer shown in FIG. 1;
  • FIG. 4 is a schematic view showing a step of forming a non-metallic light shielding layer
  • Figure 5 is a schematic view showing the steps of forming a buffer layer and an active region
  • FIG. 6 is a schematic view showing a step of forming a gate insulating layer and a gate
  • FIG. 7 is a schematic diagram of the steps of forming a source contact region, a drain contact region, and a lightly doped drain contact region.
  • a thin film transistor is provided. As shown in FIG. 1, the thin film transistor includes a gate 1, an active region 2, a source contact region 3, and a drain contact region 4.
  • the gate electrode 1 is disposed above the active region 2, and the source contact region 3 and the drain are provided.
  • the pole contact regions 4 are disposed on opposite sides of the active region 2.
  • the active region 2 is made of a low temperature polysilicon material.
  • the thin film transistor according to an embodiment of the present invention further includes a non-metal light shielding layer 5 disposed under the active region 2 and at least partially overlapping the active region 2 in the orthogonal projection direction, and the non-metal light shielding Layer 5 is capable of occluding all visible light from the backlight that is illuminated thereon.
  • the non-metallic light shielding layer 5 is disposed such that a part of the backlight light irradiated onto the active region 2 is blocked, thereby reducing the leakage current of the thin film transistor, and at the same time, since the non-metallic light shielding layer 5 is a non-metal material, it does not Generate parasitic capacitance. Therefore, even for the thin film transistor having a double gate structure, it is not necessary to separate the non-metal light shielding layer 5 into two small pieces, and it is possible to ensure a higher yield of the display product using the thin film transistor.
  • the non-metallic light shielding layer 5 is formed using a one-dimensional photonic crystal optical film including a first film layer 51 and a second film layer 52 which are alternately stacked in a direction perpendicular to the substrate 9.
  • the first film layer 51 and the second film layer 52 which are alternately stacked may be one set (as shown in FIG. 2) or multiple sets (as shown in FIG. 3).
  • the refractive indices of the first film layer 51 and the second film layer 52 are different, and the refractive indices of the first film layer 51 and the second film layer 52 are all in the range of 1-5.
  • One or more sets of first film layer 51 and second film layer The arrangement of 52 can reflect all the visible light from the backlight irradiated thereon, that is, all the visible light from the backlight that is irradiated onto the non-metallic light shielding layer 5 cannot pass through the non-metallic light shielding layer 5, thereby making the non-metallic light shielding layer 5 It has the effect of shading.
  • the first film layer 51 is made of TiO 2 material
  • the second film layer 52 is made of SiO 2 material.
  • the first film layer 51 is made of ZnSe material
  • the second film layer 52 is made of MgF2 material.
  • the thickness ratio of the first film layer 51 and the second film layer 52 may be 1:1 to 1:3.
  • the thickness ratio of the first film layer 51 and the second film layer 52 may be 1:1.136.
  • the material and thickness ratios of the first film layer 51 and the second film layer 52 are not limited, that is, the first film layer 51 and the second film layer 52 may also adopt other materials. Accordingly, the thickness ratio of the first film layer 51 and the second film layer 52 may also be changed as long as the non-metal light shielding layer 5 can be shielded from all visible light from the backlight irradiated thereon.
  • the non-metallic light shielding layer 5 is disposed between the regions corresponding to the source contact region 3 and the drain contact region 4, and at least partially overlaps the gate electrode 1 in the forward projection direction.
  • the non-metal light-shielding layer 5 is at least partially overlapped with the active region 2, and the non-metal light-shielding layer 5 is disposed between the source contact region 3 and the region corresponding to the drain contact region 4, in order to make the non-metal light-shielding layer 5 at least partially
  • a portion of the active area 2 is shielded so that the backlight light that is incident on the active area 2 can be partially blocked, thereby reducing the leakage current of the active area 2.
  • the non-metallic light-shielding layer 5 can also completely overlap the active region 2, so that the non-metallic light-shielding layer 5 completely covers the active region 2, so that the backlight light that is irradiated to the active region 2 is completely covered.
  • the leakage current of the active region 2 can be further reduced.
  • the gate 1 is at least one, and the gate 1 is located in the front projection direction of the non-metal light shielding layer 5.
  • the gate 1 is provided with two, that is, the thin film transistor has a double gate structure.
  • the arrangement of the double gate 1 can buffer the leakage current, thereby functioning to reduce the leakage current of the thin film transistor.
  • the active region 2 is further provided with a lightly doped region 6 disposed between the source contact region 3 and the drain contact region 4 and separated on both sides of the corresponding region of the gate 1.
  • the arrangement of the lightly doped region 6 can buffer the leakage current of the thin film transistor, thereby reducing the leakage current of the thin film transistor.
  • a gate insulating layer 7 is further disposed between the active region 2 and the gate electrode 1, and a buffer layer 8 is further disposed between the non-metal light shielding layer 5 and the active region 2.
  • the arrangement of the gate insulating layer 7 enables the active region 2 and the gate electrode 1 to be insulated from each other.
  • the buffer layer 8 serves to block impurities contained in the substrate substrate 9 from diffusing into the active region 2 of the thin film transistor, thereby preventing characteristics such as threshold voltage and leakage current of the thin film transistor. influences.
  • the buffer layer 8 is provided to prevent excimer The laser annealing causes diffusion of impurities in the base substrate 9, and improves the quality of the thin film transistor formed by the low temperature polysilicon.
  • a thin film transistor according to an embodiment of the present invention further includes a source and a drain (not shown), and a source and a drain are connected to the source contact region 3 and the drain contact region 4, respectively.
  • a passivation layer (not shown) is formed on the gate 1, and the source and the drain are connected to the source contact region 3 and the drain contact region 4 through via holes penetrating the passivation layer and the gate insulating layer 7, respectively.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor, including the steps of forming the gate 1, the active region 2, the source contact region 3, and the drain contact region 4, and further comprising forming a non- The step of the metal light shielding layer 5.
  • the preparation method comprises the following steps.
  • Step S1 A pattern including the non-metal light shielding layer 5 is formed on the base substrate 9 by a patterning process.
  • the step of forming the non-metal light-shielding layer 5 specifically includes:
  • Step S11 forming a first film layer on the base substrate 9 by sputtering or deposition
  • Step S12 forming a second film layer on the base substrate 9 completing step S11 by sputtering or deposition;
  • Step S13 forming a pattern including the non-metal light-shielding layer 5 by one patterning process, that is, performing a single exposure, development, and etching process on the first film layer film and the second film layer film to form the non-metal light-shielding layer 5.
  • the step of forming the non-metal light-shielding layer 5 specifically includes:
  • Steps S11 and S12 are repeated a plurality of times, and then a pattern including the non-metallic light-shielding layer 5 is formed by one patterning process, that is, one exposure, development, and etching processes are performed on the plurality of sets of the first film layer film and the second film layer film.
  • a non-metallic light shielding layer 5 is formed.
  • the patterning process includes: first, forming (such as sputtering, depositing, coating, etc.) a material for forming the non-metal light-shielding layer 5 on the base substrate 9; then, coating a layer on the layer material a photoresist; then, the photoresist is exposed by a mask provided with a pattern including the non-metal light-shielding layer 5; finally, a pattern of the non-metal light-shielding layer 5 is formed after development and etching.
  • the preparation process of the film layer formed by the patterning process is the same as that of the above, and will not be described in detail.
  • Step S2 A buffer layer 8 and a pattern including the active region 2 are sequentially formed on the base substrate 9 on which the step S1 is completed.
  • Step S3 A gate insulating layer 7 and a pattern including the gate electrode 1 are sequentially formed on the base substrate 9 on which the step S2 is completed.
  • Step S4 forming a source contact region 3 and a drain contact region 4 on the base substrate 9 on which the step S3 is completed, and the source contact region 3 and the drain contact region 4 are formed in the opposite sides of the active region 2 by ion implantation. side.
  • the implanted ions are boron ions or phosphorus ions.
  • the buffer layer 8, the active region 2, the gate insulating layer 7, and the gate electrode 1 are all formed by a patterning process, which is similar to the patterning process for forming the non-metal light-shielding layer 5, and the specific process will not be described again.
  • step S4 further includes forming a lightly doped drain contact region 6 in the active region 2 by ion implantation.
  • the implanted ions are also boron ions or phosphorus ions, but only the lightly doped drain contact region 6 is implanted.
  • the amount of ions is less than the amount of ions implanted in the source contact region 3 and the drain contact region 4.
  • the lightly doped drain contact region 6 is formed simultaneously with the source contact region 3 and the drain contact region 4.
  • the thin film transistor and the method of fabricating the same by providing a non-metallic light shielding layer under the active region, a portion of the backlight light that is irradiated onto the active region can be blocked, thereby causing leakage of the thin film transistor.
  • the current is reduced, and since the non-metallic light shielding layer is a non-metal material, parasitic capacitance is not generated, so even for a thin film transistor having a double gate structure, it is not necessary to separate the non-metal light shielding layer into two small pieces having a small area. It is also possible to ensure a higher yield of the display product using the thin film transistor.
  • Embodiments of the present invention also provide an array substrate including the thin film transistor as described above.
  • the array substrate provided by the embodiment of the present invention may be an array substrate of an advanced super-dimensional field conversion display mode (ie, ADS display mode), an array substrate of a twisted nematic display mode (ie, a TN display mode), and any other The array substrate of the thin film transistor.
  • ADS display mode an advanced super-dimensional field conversion display mode
  • TN display mode an array substrate of a twisted nematic display mode
  • any other The array substrate of the thin film transistor any other The array substrate of the thin film transistor.
  • ADS (ADvanced Super Dimension Switch) mode is a planar electric field wide view An angular core technique in which a multi-dimensional electric field is formed by an electric field generated by an edge of a slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals are aligned between the slit electrodes in the liquid crystal cell and directly above the electrode Molecules are capable of rotating, thereby increasing the efficiency of the liquid crystal and increasing the light transmission efficiency.
  • ADS mode switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. .
  • ADS technology has improved high-transmission I-ADS technology, high aperture ratio H-ADS and high-resolution S-ADS technology.
  • the display performance of the array substrate can be further improved.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display performance of the display device is further improved by employing the array substrate as described above.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

L'invention concerne un transistor à couches minces et son procédé de fabrication, un substrat matriciel et un dispositif d'affichage ; le transistor à couches minces comprend une électrode de grille (1), une zone active (2), une zone de contact d'électrode de source (3) et une zone de contact d'électrode de drain (4) ; l'électrode de grille (1) est disposée sur la zone active (2) ; et la zone de contact d'électrode de source (3) et la zone de contact d'électrode de drain (4) sont disposées respectivement au niveau de deux côtés opposés de la zone active (2). Le transistor à couches minces comprend en outre une couche de protection contre la lumière non métallique (5) ; la couche de protection contre la lumière non métallique (5) est disposée au-dessous de la zone active (2), et chevauche au moins partiellement la zone active (2) dans une direction de projection orthographique ; et la couche de protection contre la lumière non métallique (5) bloque toute la lumière visible venant d'un rétroéclairage et incidente sur la couche de protection contre la lumière non métallique (5).
PCT/CN2014/092908 2014-08-13 2014-12-03 Transistor à couches minces et son procédé de fabrication, substrat matriciel et dispositif d'affichage WO2016023305A1 (fr)

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CN201410397694.7A CN104218092B (zh) 2014-08-13 2014-08-13 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN201410397694.7 2014-08-13

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CN111785735A (zh) * 2020-07-02 2020-10-16 Tcl华星光电技术有限公司 阵列基板及其制作方法、显示面板

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CN104795496A (zh) * 2015-04-08 2015-07-22 深圳市华星光电技术有限公司 双栅极器件以及双栅极器件的制造方法
CN104979405B (zh) * 2015-07-22 2019-05-21 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
CN105093679B (zh) * 2015-08-20 2017-12-05 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示面板和显示装置
CN105336745B (zh) * 2015-09-30 2019-01-22 深圳市华星光电技术有限公司 低温多晶硅tft基板
CN105977262B (zh) * 2016-05-27 2019-09-20 深圳市华星光电技术有限公司 一种显示装置、阵列基板及其制造方法
CN106229338A (zh) * 2016-08-24 2016-12-14 深圳市华星光电技术有限公司 一种薄膜晶体管及其制备方法
CN108878537B (zh) * 2017-05-12 2021-02-12 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、显示面板和显示装置
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