WO2016023305A1 - Thin film transistor and manufacturing method thereof, array substrate and display device - Google Patents

Thin film transistor and manufacturing method thereof, array substrate and display device Download PDF

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Publication number
WO2016023305A1
WO2016023305A1 PCT/CN2014/092908 CN2014092908W WO2016023305A1 WO 2016023305 A1 WO2016023305 A1 WO 2016023305A1 CN 2014092908 W CN2014092908 W CN 2014092908W WO 2016023305 A1 WO2016023305 A1 WO 2016023305A1
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layer
thin film
film transistor
shielding layer
contact region
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PCT/CN2014/092908
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French (fr)
Chinese (zh)
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孙建
樊君
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Publication of WO2016023305A1 publication Critical patent/WO2016023305A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • liquid crystal display has become a mainstream product in flat panel display devices due to its small size, low power consumption, and no radiation.
  • a thin film transistor is an indispensable switching device in a liquid crystal display device.
  • the thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, and the active layer is usually formed of an amorphous silicon (a-Si) material.
  • a-Si amorphous silicon
  • a polysilicon (p-Si) thin film layer may be formed, and then a polysilicon (p-Si) thin film layer is doped or the like to form an active region, a source contact region, and a drain contact region of the active layer.
  • a polysilicon (p-Si) thin film layer is doped or the like to form an active region, a source contact region, and a drain contact region of the active layer.
  • Polycrystalline silicon includes high temperature polysilicon (HTPS) and low temperature polysilicon (LTPS), wherein a thin film transistor using low temperature polysilicon to form an active layer has high electron mobility and reduced device size, and thus is widely used in liquid crystal display devices.
  • HTPS high temperature polysilicon
  • LTPS low temperature polysilicon
  • a high aperture ratio is achieved, which in turn makes the corresponding display device have the advantages of high brightness and low power consumption.
  • a thin film transistor formed by using a low-temperature polysilicon material to form an active layer has a relatively large leakage current, and a main cause of a large leakage current is a backlight to an active region during display. Irradiation is performed to generate a large photo-leakage current. At present, the leakage current is mainly reduced by preparing a layer of light-shielding metal under the active region. At the same time, the thin-film transistor adopts a double-gate structure to reduce the leakage current to some extent.
  • the light-shielding metal layer under the active region of the double-gate structure thin film transistor is separated (ie, the light-shielding metal layer is divided into two pieces with a small area, and two pieces are spaced apart), in this case Since the facing area between the light-shielding metal layer and the active region is relatively reduced, the parasitic capacitance is reduced, which enables the yield of the product to be higher.
  • a thin film transistor includes a gate, an active region, a source contact region and a drain contact region, the gate is disposed above the active region, and the source contact region and the drain contact are respectively disposed at The opposite sides of the active area.
  • the thin film transistor further includes a non-metal light shielding layer disposed under the active region and at least partially overlapping the active region in a right projection direction, the non-metal light shielding layer capable of The entire visible light from the backlight that is illuminated thereon is occluded.
  • the non-metallic light-shielding layer is formed using a one-dimensional photonic crystal optical film including a first film layer and a second film layer that are alternately stacked.
  • the first film layer and the second film layer that are alternately stacked are one or more groups.
  • the first film layer and the second film layer have different refractive indices, and the first film layer and the second film layer have a refractive index ranging from 1 to 5.
  • the first film layer is made of TiO 2 material
  • the second film layer is made of SiO 2 material.
  • the thickness ratio of the first film layer to the second film layer is 1:1.136.
  • the non-metallic light shielding layer is disposed between the source contact region and a region corresponding to the drain contact region, and at least partially overlaps the gate electrode in a right projection direction.
  • the gate is at least one, and the gate is located in a front projection direction of the non-metallic light shielding layer.
  • a lightly doped drain contact region is disposed in the active region, and the lightly doped drain contact region is disposed between the source contact region and the drain contact region, and is separated The two sides of the area corresponding to the gate.
  • a gate insulating layer is further disposed between the active region and the gate, and a buffer layer is further disposed between the non-metal light shielding layer and the active region.
  • an array substrate is provided.
  • the array substrate includes a thin film transistor as described above.
  • a display device includes the array substrate as described above.
  • a method of fabricating a thin film transistor as described above includes the steps of forming a gate, an active region, a source contact region, and a drain contact region. The method also includes the step of forming a non-metallic light shielding layer.
  • the preparation method includes: Step S1: forming a pattern including the non-metal light shielding layer on a base substrate by using a patterning process; Step S2: sequentially forming a buffer layer on the substrate substrate completing the step S1 and including a pattern of the active region; step S3: sequentially forming a gate insulating layer and a pattern including the gate on the substrate of the step S2; step S4: on the substrate of the step S3
  • the source contact region and the drain contact region are formed, and the source contact region and the drain contact region are formed on opposite sides of the active region by ion implantation.
  • the pattern forming the non-metallic light shielding layer on the substrate by using a patterning process includes:
  • the step of forming the non-metal light shielding layer includes: Step S11: forming a layer on the substrate substrate a first film layer; step S12: forming a second film film on the substrate of the step S11; step S13: forming a pattern including the non-metal light shielding layer by one patterning process;
  • the step of forming the non-metal light shielding layer includes: repeating the step S11 and the step S12 a plurality of times, A pattern including the non-metallic light shielding layer is then formed by one patterning process.
  • step S11 and the step S12 may be interchanged.
  • the step S4 further includes forming a lightly doped drain contact region in the active region by ion implantation.
  • FIG. 1 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the present invention
  • Figure 2 is a cross-sectional view showing the structure of the non-metallic light shielding layer shown in Figure 1;
  • FIG. 3 is a cross-sectional view showing another structure of the non-metal light shielding layer shown in FIG. 1;
  • FIG. 4 is a schematic view showing a step of forming a non-metallic light shielding layer
  • Figure 5 is a schematic view showing the steps of forming a buffer layer and an active region
  • FIG. 6 is a schematic view showing a step of forming a gate insulating layer and a gate
  • FIG. 7 is a schematic diagram of the steps of forming a source contact region, a drain contact region, and a lightly doped drain contact region.
  • a thin film transistor is provided. As shown in FIG. 1, the thin film transistor includes a gate 1, an active region 2, a source contact region 3, and a drain contact region 4.
  • the gate electrode 1 is disposed above the active region 2, and the source contact region 3 and the drain are provided.
  • the pole contact regions 4 are disposed on opposite sides of the active region 2.
  • the active region 2 is made of a low temperature polysilicon material.
  • the thin film transistor according to an embodiment of the present invention further includes a non-metal light shielding layer 5 disposed under the active region 2 and at least partially overlapping the active region 2 in the orthogonal projection direction, and the non-metal light shielding Layer 5 is capable of occluding all visible light from the backlight that is illuminated thereon.
  • the non-metallic light shielding layer 5 is disposed such that a part of the backlight light irradiated onto the active region 2 is blocked, thereby reducing the leakage current of the thin film transistor, and at the same time, since the non-metallic light shielding layer 5 is a non-metal material, it does not Generate parasitic capacitance. Therefore, even for the thin film transistor having a double gate structure, it is not necessary to separate the non-metal light shielding layer 5 into two small pieces, and it is possible to ensure a higher yield of the display product using the thin film transistor.
  • the non-metallic light shielding layer 5 is formed using a one-dimensional photonic crystal optical film including a first film layer 51 and a second film layer 52 which are alternately stacked in a direction perpendicular to the substrate 9.
  • the first film layer 51 and the second film layer 52 which are alternately stacked may be one set (as shown in FIG. 2) or multiple sets (as shown in FIG. 3).
  • the refractive indices of the first film layer 51 and the second film layer 52 are different, and the refractive indices of the first film layer 51 and the second film layer 52 are all in the range of 1-5.
  • One or more sets of first film layer 51 and second film layer The arrangement of 52 can reflect all the visible light from the backlight irradiated thereon, that is, all the visible light from the backlight that is irradiated onto the non-metallic light shielding layer 5 cannot pass through the non-metallic light shielding layer 5, thereby making the non-metallic light shielding layer 5 It has the effect of shading.
  • the first film layer 51 is made of TiO 2 material
  • the second film layer 52 is made of SiO 2 material.
  • the first film layer 51 is made of ZnSe material
  • the second film layer 52 is made of MgF2 material.
  • the thickness ratio of the first film layer 51 and the second film layer 52 may be 1:1 to 1:3.
  • the thickness ratio of the first film layer 51 and the second film layer 52 may be 1:1.136.
  • the material and thickness ratios of the first film layer 51 and the second film layer 52 are not limited, that is, the first film layer 51 and the second film layer 52 may also adopt other materials. Accordingly, the thickness ratio of the first film layer 51 and the second film layer 52 may also be changed as long as the non-metal light shielding layer 5 can be shielded from all visible light from the backlight irradiated thereon.
  • the non-metallic light shielding layer 5 is disposed between the regions corresponding to the source contact region 3 and the drain contact region 4, and at least partially overlaps the gate electrode 1 in the forward projection direction.
  • the non-metal light-shielding layer 5 is at least partially overlapped with the active region 2, and the non-metal light-shielding layer 5 is disposed between the source contact region 3 and the region corresponding to the drain contact region 4, in order to make the non-metal light-shielding layer 5 at least partially
  • a portion of the active area 2 is shielded so that the backlight light that is incident on the active area 2 can be partially blocked, thereby reducing the leakage current of the active area 2.
  • the non-metallic light-shielding layer 5 can also completely overlap the active region 2, so that the non-metallic light-shielding layer 5 completely covers the active region 2, so that the backlight light that is irradiated to the active region 2 is completely covered.
  • the leakage current of the active region 2 can be further reduced.
  • the gate 1 is at least one, and the gate 1 is located in the front projection direction of the non-metal light shielding layer 5.
  • the gate 1 is provided with two, that is, the thin film transistor has a double gate structure.
  • the arrangement of the double gate 1 can buffer the leakage current, thereby functioning to reduce the leakage current of the thin film transistor.
  • the active region 2 is further provided with a lightly doped region 6 disposed between the source contact region 3 and the drain contact region 4 and separated on both sides of the corresponding region of the gate 1.
  • the arrangement of the lightly doped region 6 can buffer the leakage current of the thin film transistor, thereby reducing the leakage current of the thin film transistor.
  • a gate insulating layer 7 is further disposed between the active region 2 and the gate electrode 1, and a buffer layer 8 is further disposed between the non-metal light shielding layer 5 and the active region 2.
  • the arrangement of the gate insulating layer 7 enables the active region 2 and the gate electrode 1 to be insulated from each other.
  • the buffer layer 8 serves to block impurities contained in the substrate substrate 9 from diffusing into the active region 2 of the thin film transistor, thereby preventing characteristics such as threshold voltage and leakage current of the thin film transistor. influences.
  • the buffer layer 8 is provided to prevent excimer The laser annealing causes diffusion of impurities in the base substrate 9, and improves the quality of the thin film transistor formed by the low temperature polysilicon.
  • a thin film transistor according to an embodiment of the present invention further includes a source and a drain (not shown), and a source and a drain are connected to the source contact region 3 and the drain contact region 4, respectively.
  • a passivation layer (not shown) is formed on the gate 1, and the source and the drain are connected to the source contact region 3 and the drain contact region 4 through via holes penetrating the passivation layer and the gate insulating layer 7, respectively.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor, including the steps of forming the gate 1, the active region 2, the source contact region 3, and the drain contact region 4, and further comprising forming a non- The step of the metal light shielding layer 5.
  • the preparation method comprises the following steps.
  • Step S1 A pattern including the non-metal light shielding layer 5 is formed on the base substrate 9 by a patterning process.
  • the step of forming the non-metal light-shielding layer 5 specifically includes:
  • Step S11 forming a first film layer on the base substrate 9 by sputtering or deposition
  • Step S12 forming a second film layer on the base substrate 9 completing step S11 by sputtering or deposition;
  • Step S13 forming a pattern including the non-metal light-shielding layer 5 by one patterning process, that is, performing a single exposure, development, and etching process on the first film layer film and the second film layer film to form the non-metal light-shielding layer 5.
  • the step of forming the non-metal light-shielding layer 5 specifically includes:
  • Steps S11 and S12 are repeated a plurality of times, and then a pattern including the non-metallic light-shielding layer 5 is formed by one patterning process, that is, one exposure, development, and etching processes are performed on the plurality of sets of the first film layer film and the second film layer film.
  • a non-metallic light shielding layer 5 is formed.
  • the patterning process includes: first, forming (such as sputtering, depositing, coating, etc.) a material for forming the non-metal light-shielding layer 5 on the base substrate 9; then, coating a layer on the layer material a photoresist; then, the photoresist is exposed by a mask provided with a pattern including the non-metal light-shielding layer 5; finally, a pattern of the non-metal light-shielding layer 5 is formed after development and etching.
  • the preparation process of the film layer formed by the patterning process is the same as that of the above, and will not be described in detail.
  • Step S2 A buffer layer 8 and a pattern including the active region 2 are sequentially formed on the base substrate 9 on which the step S1 is completed.
  • Step S3 A gate insulating layer 7 and a pattern including the gate electrode 1 are sequentially formed on the base substrate 9 on which the step S2 is completed.
  • Step S4 forming a source contact region 3 and a drain contact region 4 on the base substrate 9 on which the step S3 is completed, and the source contact region 3 and the drain contact region 4 are formed in the opposite sides of the active region 2 by ion implantation. side.
  • the implanted ions are boron ions or phosphorus ions.
  • the buffer layer 8, the active region 2, the gate insulating layer 7, and the gate electrode 1 are all formed by a patterning process, which is similar to the patterning process for forming the non-metal light-shielding layer 5, and the specific process will not be described again.
  • step S4 further includes forming a lightly doped drain contact region 6 in the active region 2 by ion implantation.
  • the implanted ions are also boron ions or phosphorus ions, but only the lightly doped drain contact region 6 is implanted.
  • the amount of ions is less than the amount of ions implanted in the source contact region 3 and the drain contact region 4.
  • the lightly doped drain contact region 6 is formed simultaneously with the source contact region 3 and the drain contact region 4.
  • the thin film transistor and the method of fabricating the same by providing a non-metallic light shielding layer under the active region, a portion of the backlight light that is irradiated onto the active region can be blocked, thereby causing leakage of the thin film transistor.
  • the current is reduced, and since the non-metallic light shielding layer is a non-metal material, parasitic capacitance is not generated, so even for a thin film transistor having a double gate structure, it is not necessary to separate the non-metal light shielding layer into two small pieces having a small area. It is also possible to ensure a higher yield of the display product using the thin film transistor.
  • Embodiments of the present invention also provide an array substrate including the thin film transistor as described above.
  • the array substrate provided by the embodiment of the present invention may be an array substrate of an advanced super-dimensional field conversion display mode (ie, ADS display mode), an array substrate of a twisted nematic display mode (ie, a TN display mode), and any other The array substrate of the thin film transistor.
  • ADS display mode an advanced super-dimensional field conversion display mode
  • TN display mode an array substrate of a twisted nematic display mode
  • any other The array substrate of the thin film transistor any other The array substrate of the thin film transistor.
  • ADS (ADvanced Super Dimension Switch) mode is a planar electric field wide view An angular core technique in which a multi-dimensional electric field is formed by an electric field generated by an edge of a slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals are aligned between the slit electrodes in the liquid crystal cell and directly above the electrode Molecules are capable of rotating, thereby increasing the efficiency of the liquid crystal and increasing the light transmission efficiency.
  • ADS mode switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. .
  • ADS technology has improved high-transmission I-ADS technology, high aperture ratio H-ADS and high-resolution S-ADS technology.
  • the display performance of the array substrate can be further improved.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display performance of the display device is further improved by employing the array substrate as described above.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

A thin film transistor and manufacturing method thereof, array substrate and display device; the thin film transistor comprises a gate electrode (1), an active area (2), a source electrode contact area (3) and a drain electrode contact area (4); the gate electrode (1) is provided on the active area (2); and the source electrode contact area (3) and the drain electrode contact area (4) are respectively provided at two opposite sides of the active area (2). The thin film transistor further comprises a non-metal light-shielding layer (5); the non-metal light-shielding layer (5) is provided below the active area (2), and at least partially overlaps with the active area (2) in an orthographic projection direction; and the non-metal light-shielding layer (5) shields all visible light coming from a backlight and irradiated onto the non-metal light-shielding layer (5).

Description

薄膜晶体管及其制备方法、阵列基板和显示装置Thin film transistor and preparation method thereof, array substrate and display device 技术领域Technical field
本发明的实施例涉及一种薄膜晶体管及其制备方法、阵列基板和显示装置。Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
背景技术Background technique
目前，液晶显示装置(LCD：Liquid Crystal Display)因其体积小、功耗低、无辐射等特点已成为平板显示装置中的主流产品。At present, liquid crystal display (LCD) has become a mainstream product in flat panel display devices due to its small size, low power consumption, and no radiation.
薄膜晶体管是液晶显示装置中必不可少的开关器件，薄膜晶体管包括栅极、栅绝缘层、有源层、源极与漏极，有源层通常采用非晶硅(a-Si)材料形成。A thin film transistor is an indispensable switching device in a liquid crystal display device. The thin film transistor includes a gate electrode, a gate insulating layer, an active layer, a source and a drain, and the active layer is usually formed of an amorphous silicon (a-Si) material.
随着显示技术的发展，出现了采用多晶硅(p-Si)材料形成有源层的方式。具体的，可形成多晶硅(p-Si)薄膜层，然后对多晶硅(p-Si)薄膜层进行掺杂等工艺，从而形成有源层的有源区、源极接触区与漏极接触区。研究显示，采用多晶硅(p-Si)材料形成有源层的薄膜晶体管的性能比采用非晶硅材料形成有源层的薄膜晶体管的性能高100多倍。多晶硅包括高温多晶硅(HTPS)和低温多晶硅(LTPS)，其中，采用低温多晶硅形成有源层的薄膜晶体管具有较高的电子迁移率，缩小的器件尺寸，因此被广泛应用于液晶显示装置中，既实现了高开口率，又使得相应的显示装置具有高亮度、低耗电的优点。With the development of display technology, a way of forming an active layer using a polysilicon (p-Si) material has emerged. Specifically, a polysilicon (p-Si) thin film layer may be formed, and then a polysilicon (p-Si) thin film layer is doped or the like to form an active region, a source contact region, and a drain contact region of the active layer. Studies have shown that the performance of a thin film transistor in which an active layer is formed using a polysilicon (p-Si) material is more than 100 times higher than that of a thin film transistor in which an active silicon layer is formed using an amorphous silicon material. Polycrystalline silicon includes high temperature polysilicon (HTPS) and low temperature polysilicon (LTPS), wherein a thin film transistor using low temperature polysilicon to form an active layer has high electron mobility and reduced device size, and thus is widely used in liquid crystal display devices. A high aperture ratio is achieved, which in turn makes the corresponding display device have the advantages of high brightness and low power consumption.
与采用非晶硅材料形成有源层的薄膜晶体管相比，采用低温多晶硅材料形成有源层的薄膜晶体管工作时漏电流比较大，而漏电流较大的主要原因是显示时背光对有源区进行照射，从而产生了较大的光致漏电流。目前主要是通过在有源区下面制备一层遮光金属来降低漏电流，同时，薄膜晶体管采用双栅结构也能从一定程度上降低漏电流。在实际制备中，双栅结构的薄膜晶体管的有源区下面的遮光金属层通过分隔开(即遮光金属层被分隔为面积较小的两片，且两片间隔设置)，在此情形下由于遮光金属层与有源区之间的正对面积相对减小，所以寄生电容减小，这能使产品的良率更高。 Compared with a thin film transistor in which an active layer is formed by using an amorphous silicon material, a thin film transistor formed by using a low-temperature polysilicon material to form an active layer has a relatively large leakage current, and a main cause of a large leakage current is a backlight to an active region during display. Irradiation is performed to generate a large photo-leakage current. At present, the leakage current is mainly reduced by preparing a layer of light-shielding metal under the active region. At the same time, the thin-film transistor adopts a double-gate structure to reduce the leakage current to some extent. In actual preparation, the light-shielding metal layer under the active region of the double-gate structure thin film transistor is separated (ie, the light-shielding metal layer is divided into two pieces with a small area, and two pieces are spaced apart), in this case Since the facing area between the light-shielding metal layer and the active region is relatively reduced, the parasitic capacitance is reduced, which enables the yield of the product to be higher.
但随着液晶显示装置越来越往高PPI(像素密度)发展，想把薄膜晶体管有源区下面的遮光金属层分开越来越困难。因此，采用遮光金属层来降低漏电流的方案无法同时实现使寄生电容更小的要求，导致最终显示产品的良率并不是很高。However, as liquid crystal display devices are increasingly moving toward higher PPI (pixel density), it is increasingly difficult to separate the light-shielding metal layers under the active regions of the thin film transistors. Therefore, the scheme of using a light-shielding metal layer to reduce the leakage current cannot simultaneously achieve the requirement of making the parasitic capacitance smaller, resulting in that the yield of the final display product is not very high.
发明内容Summary of the invention
根据本发明的实施例，提供一种薄膜晶体管。该薄膜晶体管包括栅极、有源区、源极接触区和漏极接触区，所述栅极设置在所述有源区的上方，所述源极接触区和所述漏极接触区分设在所述有源区的相对两侧。所述薄膜晶体管还包括非金属遮光层，所述非金属遮光层设置在所述有源区的下方，且在正投影方向上与所述有源区至少部分重叠，所述非金属遮光层能对照射到其上的来自背光的全部可见光进行遮挡。According to an embodiment of the present invention, a thin film transistor is provided. The thin film transistor includes a gate, an active region, a source contact region and a drain contact region, the gate is disposed above the active region, and the source contact region and the drain contact are respectively disposed at The opposite sides of the active area. The thin film transistor further includes a non-metal light shielding layer disposed under the active region and at least partially overlapping the active region in a right projection direction, the non-metal light shielding layer capable of The entire visible light from the backlight that is illuminated thereon is occluded.
例如，所述非金属遮光层采用一维光子晶体光学薄膜形成，所述一维光子晶体光学薄膜包括交替堆叠的第一膜层和第二膜层。For example, the non-metallic light-shielding layer is formed using a one-dimensional photonic crystal optical film including a first film layer and a second film layer that are alternately stacked.
例如，交替堆叠的所述第一膜层和所述第二膜层为一组或多组。For example, the first film layer and the second film layer that are alternately stacked are one or more groups.
例如，所述第一膜层和所述第二膜层的折射率不同，所述第一膜层和所述第二膜层的折射率范围均为1-5。For example, the first film layer and the second film layer have different refractive indices, and the first film layer and the second film layer have a refractive index ranging from 1 to 5.
例如，所述第一膜层采用TiO2材料，所述第二膜层采用SiO2材料。For example, the first film layer is made of TiO 2 material, and the second film layer is made of SiO 2 material.
例如，所述第一膜层和所述第二膜层的厚度比为1:1.136。For example, the thickness ratio of the first film layer to the second film layer is 1:1.136.
例如，所述非金属遮光层设置在所述源极接触区和所述漏极接触区对应的区域之间，且在正投影方向上与所述栅极至少部分重叠。For example, the non-metallic light shielding layer is disposed between the source contact region and a region corresponding to the drain contact region, and at least partially overlaps the gate electrode in a right projection direction.
例如，所述栅极为至少一个，所述栅极位于所述非金属遮光层的正投影方向上。For example, the gate is at least one, and the gate is located in a front projection direction of the non-metallic light shielding layer.
例如，所述有源区中还设置有轻掺杂漏极接触区，所述轻掺杂漏极接触区设置在所述源极接触区和所述漏极接触区之间，且分居在所述栅极对应的区域的两侧。For example, a lightly doped drain contact region is disposed in the active region, and the lightly doped drain contact region is disposed between the source contact region and the drain contact region, and is separated The two sides of the area corresponding to the gate.
例如，在所述有源区与所述栅极之间还设置有栅绝缘层，在所述非金属遮光层与所述有源区之间还设置有缓冲层。For example, a gate insulating layer is further disposed between the active region and the gate, and a buffer layer is further disposed between the non-metal light shielding layer and the active region.
根据本发明的实施例，提供一种阵列基板。该阵列基板包括如上所述的薄膜晶体管。 According to an embodiment of the present invention, an array substrate is provided. The array substrate includes a thin film transistor as described above.
根据本发明的实施例，提供一种显示装置。该显示装置包括如上所述的阵列基板。According to an embodiment of the present invention, a display device is provided. The display device includes the array substrate as described above.
根据本发明的实施例，提供一种如上所述的薄膜晶体管的制备方法。该方法包括形成栅极、有源区、源极接触区和漏极接触区的步骤。所述方法还包括形成非金属遮光层的步骤。According to an embodiment of the present invention, a method of fabricating a thin film transistor as described above is provided. The method includes the steps of forming a gate, an active region, a source contact region, and a drain contact region. The method also includes the step of forming a non-metallic light shielding layer.
例如，所述制备方法包括：步骤S1：采用构图工艺在衬底基板上形成包括所述非金属遮光层的图形；步骤S2：在完成步骤S1的所述衬底基板上先后形成缓冲层和包括所述有源区的图形；步骤S3：在完成步骤S2的所述衬底基板上先后形成栅绝缘层和包括所述栅极的图形；步骤S4：在完成步骤S3的所述衬底基板上形成所述源极接触区和所述漏极接触区，所述源极接触区和所述漏极接触区采用离子注入方式形成于所述有源区的相对两侧。For example, the preparation method includes: Step S1: forming a pattern including the non-metal light shielding layer on a base substrate by using a patterning process; Step S2: sequentially forming a buffer layer on the substrate substrate completing the step S1 and including a pattern of the active region; step S3: sequentially forming a gate insulating layer and a pattern including the gate on the substrate of the step S2; step S4: on the substrate of the step S3 The source contact region and the drain contact region are formed, and the source contact region and the drain contact region are formed on opposite sides of the active region by ion implantation.
例如，所述采用构图工艺在衬底基板上形成包括所述非金属遮光层的图形包括：For example, the pattern forming the non-metallic light shielding layer on the substrate by using a patterning process includes:
当所述非金属遮光层为采用一组交替堆叠的第一膜层和第二膜层形成时，形成所述非金属遮光层的步骤包括：步骤S11：在所述衬底基板上形成一层第一膜层膜；步骤S12：在完成步骤S11的所述衬底基板上形成一层第二膜层膜；步骤S13：通过一次构图工艺形成包括所述非金属遮光层的图形；When the non-metallic light shielding layer is formed by using a set of the first film layer and the second film layer which are alternately stacked, the step of forming the non-metal light shielding layer includes: Step S11: forming a layer on the substrate substrate a first film layer; step S12: forming a second film film on the substrate of the step S11; step S13: forming a pattern including the non-metal light shielding layer by one patterning process;
当所述非金属遮光层为采用多组交替堆叠的第一膜层和第二膜层形成时，形成所述非金属遮光层的步骤包括：多次重复所述步骤S11和所述步骤S12，然后通过一次构图工艺形成包括所述非金属遮光层的图形。When the non-metallic light shielding layer is formed by using a plurality of sets of the first film layer and the second film layer which are alternately stacked, the step of forming the non-metal light shielding layer includes: repeating the step S11 and the step S12 a plurality of times, A pattern including the non-metallic light shielding layer is then formed by one patterning process.
例如，所述步骤S11和所述步骤S12的先后顺序可互换。For example, the order of the step S11 and the step S12 may be interchanged.
例如，所述步骤S4还包括采用离子注入方式在所述有源区中形成轻掺杂漏极接触区。For example, the step S4 further includes forming a lightly doped drain contact region in the active region by ion implantation.
附图说明DRAWINGS
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .
图1为根据本发明实施例的薄膜晶体管的结构剖视图；1 is a cross-sectional view showing the structure of a thin film transistor according to an embodiment of the present invention;
图2为图1所示的非金属遮光层的结构剖视图； Figure 2 is a cross-sectional view showing the structure of the non-metallic light shielding layer shown in Figure 1;
图3为图1所示的非金属遮光层的另一结构剖视图；3 is a cross-sectional view showing another structure of the non-metal light shielding layer shown in FIG. 1;
图4为形成非金属遮光层的步骤的示意图；4 is a schematic view showing a step of forming a non-metallic light shielding layer;
图5为形成缓冲层和有源区的步骤的示意图；Figure 5 is a schematic view showing the steps of forming a buffer layer and an active region;
图6为形成栅绝缘层和栅极的步骤的示意图；6 is a schematic view showing a step of forming a gate insulating layer and a gate;
图7为形成源极接触区、漏极接触区和轻掺杂漏极接触区的步骤的示意图。7 is a schematic diagram of the steps of forming a source contact region, a drain contact region, and a lightly doped drain contact region.
具体实施方式detailed description
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.
根据本发明的实施例，提供一种薄膜晶体管。如图1所示，该薄膜晶体管包括栅极1、有源区2、源极接触区3和漏极接触区4，栅极1设置在有源区2的上方，源极接触区3和漏极接触区4分设在有源区2的相对两侧。例如，有源区2采用低温多晶硅材料。另外，根据本发明实施例的薄膜晶体管还包括非金属遮光层5，非金属遮光层5设置在有源区2的下方，且在正投影方向上与有源区2至少部分重叠，非金属遮光层5能对照射其上的来自背光的全部可见光进行遮挡。According to an embodiment of the present invention, a thin film transistor is provided. As shown in FIG. 1, the thin film transistor includes a gate 1, an active region 2, a source contact region 3, and a drain contact region 4. The gate electrode 1 is disposed above the active region 2, and the source contact region 3 and the drain are provided. The pole contact regions 4 are disposed on opposite sides of the active region 2. For example, the active region 2 is made of a low temperature polysilicon material. In addition, the thin film transistor according to an embodiment of the present invention further includes a non-metal light shielding layer 5 disposed under the active region 2 and at least partially overlapping the active region 2 in the orthogonal projection direction, and the non-metal light shielding Layer 5 is capable of occluding all visible light from the backlight that is illuminated thereon.
非金属遮光层5的设置，能使照射到有源区2上的一部分背光光线被遮住，从而使薄膜晶体管的漏电流降低，同时，由于非金属遮光层5为非金属材料，所以不会产生寄生电容。因此，即使针对双栅结构的薄膜晶体管，也不需要将非金属遮光层5分隔为两个小片，能够确保采用该薄膜晶体管的显示产品的良率更高。The non-metallic light shielding layer 5 is disposed such that a part of the backlight light irradiated onto the active region 2 is blocked, thereby reducing the leakage current of the thin film transistor, and at the same time, since the non-metallic light shielding layer 5 is a non-metal material, it does not Generate parasitic capacitance. Therefore, even for the thin film transistor having a double gate structure, it is not necessary to separate the non-metal light shielding layer 5 into two small pieces, and it is possible to ensure a higher yield of the display product using the thin film transistor.
例如，非金属遮光层5采用一维光子晶体光学薄膜形成，一维光子晶体光学薄膜包括在垂直于基板9的方向上交替堆叠的第一膜层51和第二膜层52。交替堆叠的第一膜层51和第二膜层52可以为一组(如图2所示)或多组(如图3所示)。第一膜层51和第二膜层52的折射率不同，第一膜层51和第二膜层52的折射率范围均为1-5。一组或多组第一膜层51和第二膜层 52的设置，能够对照射其上的来自背光的全部可见光进行反射，即照射到非金属遮光层5上的、来自背光的全部可见光不能通过非金属遮光层5，从而使非金属遮光层5起到了遮光的作用。For example, the non-metallic light shielding layer 5 is formed using a one-dimensional photonic crystal optical film including a first film layer 51 and a second film layer 52 which are alternately stacked in a direction perpendicular to the substrate 9. The first film layer 51 and the second film layer 52 which are alternately stacked may be one set (as shown in FIG. 2) or multiple sets (as shown in FIG. 3). The refractive indices of the first film layer 51 and the second film layer 52 are different, and the refractive indices of the first film layer 51 and the second film layer 52 are all in the range of 1-5. One or more sets of first film layer 51 and second film layer The arrangement of 52 can reflect all the visible light from the backlight irradiated thereon, that is, all the visible light from the backlight that is irradiated onto the non-metallic light shielding layer 5 cannot pass through the non-metallic light shielding layer 5, thereby making the non-metallic light shielding layer 5 It has the effect of shading.
例如，第一膜层51采用TiO2材料，第二膜层52采用SiO2材料。例如，第一膜层51采用ZnSe材料，第二膜层52采用MgF2材料。For example, the first film layer 51 is made of TiO 2 material, and the second film layer 52 is made of SiO 2 material. For example, the first film layer 51 is made of ZnSe material, and the second film layer 52 is made of MgF2 material.
例如，第一膜层51和第二膜层52的厚度比可为1:1至1：3。例如，第一膜层51和第二膜层52的厚度比可为1:1.136。For example, the thickness ratio of the first film layer 51 and the second film layer 52 may be 1:1 to 1:3. For example, the thickness ratio of the first film layer 51 and the second film layer 52 may be 1:1.136.
需要说明的是，在本发明实施例中，对第一膜层51和第二膜层52的材料和厚度比不做限定，即第一膜层51和第二膜层52还可以采用其他材料，相应地，第一膜层51和第二膜层52的厚度比也可以发生变化，只要确保非金属遮光层5能够对照射其上的来自背光的全部可见光进行遮挡即可。It should be noted that, in the embodiment of the present invention, the material and thickness ratios of the first film layer 51 and the second film layer 52 are not limited, that is, the first film layer 51 and the second film layer 52 may also adopt other materials. Accordingly, the thickness ratio of the first film layer 51 and the second film layer 52 may also be changed as long as the non-metal light shielding layer 5 can be shielded from all visible light from the backlight irradiated thereon.
例如，非金属遮光层5设置在源极接触区3和漏极接触区4对应的区域之间，且在正投影方向上与栅极1至少部分重叠。非金属遮光层5与有源区2至少部分重叠，且非金属遮光层5设置在源极接触区3与漏极接触区4对应的区域之间，目的是为了使非金属遮光层5至少要遮住有源区2的一部分区域，从而使照射到有源区2的背光光线能够被遮住一部分，进而降低有源区2的漏电流。当然，非金属遮光层5也可以与有源区2完全重叠，这样，非金属遮光层5就将有源区2完全遮住，从而使照射到有源区2的背光光线被全部遮住，能够更进一步地降低有源区2的漏电流。For example, the non-metallic light shielding layer 5 is disposed between the regions corresponding to the source contact region 3 and the drain contact region 4, and at least partially overlaps the gate electrode 1 in the forward projection direction. The non-metal light-shielding layer 5 is at least partially overlapped with the active region 2, and the non-metal light-shielding layer 5 is disposed between the source contact region 3 and the region corresponding to the drain contact region 4, in order to make the non-metal light-shielding layer 5 at least partially A portion of the active area 2 is shielded so that the backlight light that is incident on the active area 2 can be partially blocked, thereby reducing the leakage current of the active area 2. Of course, the non-metallic light-shielding layer 5 can also completely overlap the active region 2, so that the non-metallic light-shielding layer 5 completely covers the active region 2, so that the backlight light that is irradiated to the active region 2 is completely covered. The leakage current of the active region 2 can be further reduced.
例如，栅极1为至少一个，栅极1位于非金属遮光层5的正投影方向上。在图1中，栅极1设置有两个，即该薄膜晶体管为双栅结构。双栅极1的设置能够对漏电流形成缓冲，从而起到减小薄膜晶体管的漏电流的作用。For example, the gate 1 is at least one, and the gate 1 is located in the front projection direction of the non-metal light shielding layer 5. In FIG. 1, the gate 1 is provided with two, that is, the thin film transistor has a double gate structure. The arrangement of the double gate 1 can buffer the leakage current, thereby functioning to reduce the leakage current of the thin film transistor.
例如，有源区2中还设置有轻掺杂区6，轻掺杂区6设置在源极接触区3和漏极接触区4之间，且分居在栅极1对应的区域的两侧。轻掺杂区6的设置能够使薄膜晶体管的漏电流形成缓冲，从而起到降低薄膜晶体管的漏电流的作用。For example, the active region 2 is further provided with a lightly doped region 6 disposed between the source contact region 3 and the drain contact region 4 and separated on both sides of the corresponding region of the gate 1. The arrangement of the lightly doped region 6 can buffer the leakage current of the thin film transistor, thereby reducing the leakage current of the thin film transistor.
例如，有源区2与栅极1之间还设置有栅绝缘层7，在非金属遮光层5与有源区2之间还设置有缓冲层8。栅绝缘层7的设置能够使有源区2与栅极1之间相互绝缘。缓冲层8用于阻挡衬底基板9中所含的杂质扩散进入薄膜晶体管的有源区2中，防止对薄膜晶体管的阈值电压和漏电流等特性产生 影响。同时，在有源区2采用低温多晶硅材料形成在衬底基板9上的情形下，由于低温多晶硅通常是采用准分子激光退火的方法形成在衬底基板9上，设置缓冲层8能防止准分子激光退火造成衬底基板9中的杂质扩散，提高低温多晶硅形成的薄膜晶体管的质量。For example, a gate insulating layer 7 is further disposed between the active region 2 and the gate electrode 1, and a buffer layer 8 is further disposed between the non-metal light shielding layer 5 and the active region 2. The arrangement of the gate insulating layer 7 enables the active region 2 and the gate electrode 1 to be insulated from each other. The buffer layer 8 serves to block impurities contained in the substrate substrate 9 from diffusing into the active region 2 of the thin film transistor, thereby preventing characteristics such as threshold voltage and leakage current of the thin film transistor. influences. Meanwhile, in the case where the active region 2 is formed on the base substrate 9 using a low-temperature polysilicon material, since the low-temperature polysilicon is usually formed on the base substrate 9 by excimer laser annealing, the buffer layer 8 is provided to prevent excimer The laser annealing causes diffusion of impurities in the base substrate 9, and improves the quality of the thin film transistor formed by the low temperature polysilicon.
例如，根据本发明实施例的薄膜晶体管还包括源极和漏极(未示出)，源极和漏极分别连接到源极接触区3和漏极接触区4。例如，在栅极1上形成有钝化层(未示出)，源极和漏极通过贯通钝化层与栅绝缘层7的过孔分别连接到源极接触区3和漏极接触区4。For example, a thin film transistor according to an embodiment of the present invention further includes a source and a drain (not shown), and a source and a drain are connected to the source contact region 3 and the drain contact region 4, respectively. For example, a passivation layer (not shown) is formed on the gate 1, and the source and the drain are connected to the source contact region 3 and the drain contact region 4 through via holes penetrating the passivation layer and the gate insulating layer 7, respectively. .
基于薄膜晶体管的上述结构，本发明实施例还提供一种薄膜晶体管的制备方法，包括形成栅极1、有源区2、源极接触区3和漏极接触区4的步骤，还包括形成非金属遮光层5的步骤。Based on the above structure of the thin film transistor, the embodiment of the present invention further provides a method for fabricating a thin film transistor, including the steps of forming the gate 1, the active region 2, the source contact region 3, and the drain contact region 4, and further comprising forming a non- The step of the metal light shielding layer 5.
如图4-图7所示，该制备方法包括如下步骤。As shown in Figures 4-7, the preparation method comprises the following steps.
步骤S1：采用构图工艺在衬底基板9上形成包括非金属遮光层5的图形。Step S1: A pattern including the non-metal light shielding layer 5 is formed on the base substrate 9 by a patterning process.
在该步骤中，当非金属遮光层5为采用一组交替堆叠的第一膜层51和第二膜层52形成时，形成非金属遮光层5的步骤具体包括：In this step, when the non-metallic light-shielding layer 5 is formed by using a set of the first film layer 51 and the second film layer 52 which are alternately stacked, the step of forming the non-metal light-shielding layer 5 specifically includes:
步骤S11：采用溅射或沉积的方法在衬底基板9上形成一层第一膜层膜；Step S11: forming a first film layer on the base substrate 9 by sputtering or deposition;
步骤S12：采用溅射或沉积的方法在完成步骤S11的衬底基板9上形成一层第二膜层膜；Step S12: forming a second film layer on the base substrate 9 completing step S11 by sputtering or deposition;
步骤S13：通过一次构图工艺形成包括非金属遮光层5的图形，即对第一膜层膜和第二膜层膜进行一次曝光、显影和刻蚀工艺即可形成非金属遮光层5。Step S13: forming a pattern including the non-metal light-shielding layer 5 by one patterning process, that is, performing a single exposure, development, and etching process on the first film layer film and the second film layer film to form the non-metal light-shielding layer 5.
当非金属遮光层5为采用多组交替堆叠的第一膜层51和第二膜层52形成时，形成非金属遮光层5的步骤具体包括：When the non-metallic light-shielding layer 5 is formed by using a plurality of sets of the first film layer 51 and the second film layer 52 which are alternately stacked, the step of forming the non-metal light-shielding layer 5 specifically includes:
多次重复步骤S11和步骤S12，然后通过一次构图工艺形成包括非金属遮光层5的图形，即对多组第一膜层膜和第二膜层膜进行一次曝光、显影和刻蚀工艺即可形成非金属遮光层5。Steps S11 and S12 are repeated a plurality of times, and then a pattern including the non-metallic light-shielding layer 5 is formed by one patterning process, that is, one exposure, development, and etching processes are performed on the plurality of sets of the first film layer film and the second film layer film. A non-metallic light shielding layer 5 is formed.
例如，所述构图工艺包括：首先，在衬底基板9上形成(如溅射、沉积或涂覆等)用于形成非金属遮光层5的材料；接着，在该层材料上涂覆一层光刻胶；然后，用设置有包括非金属遮光层5的图形的掩模板对光刻胶进行曝光；最后经过显影、刻蚀后形成非金属遮光层5的图形。在根据本发明实 施例的薄膜晶体管的制备方法中，涉及到通过构图工艺形成的膜层的制备工艺与此相同，不再详细赘述。For example, the patterning process includes: first, forming (such as sputtering, depositing, coating, etc.) a material for forming the non-metal light-shielding layer 5 on the base substrate 9; then, coating a layer on the layer material a photoresist; then, the photoresist is exposed by a mask provided with a pattern including the non-metal light-shielding layer 5; finally, a pattern of the non-metal light-shielding layer 5 is formed after development and etching. In accordance with the present invention In the preparation method of the thin film transistor of the embodiment, the preparation process of the film layer formed by the patterning process is the same as that of the above, and will not be described in detail.
需要说明的是，上述步骤S11和步骤S12的先后顺序可互换。即第一膜层膜和第二膜层膜形成的先后顺序可以互换，也即第一膜层51和第二膜层52的位置可以互换。It should be noted that the order of the above steps S11 and S12 is interchangeable. That is, the order in which the first film layer and the second film layer are formed may be interchanged, that is, the positions of the first film layer 51 and the second film layer 52 may be interchanged.
步骤S2：在完成步骤S1的衬底基板9上先后形成缓冲层8和包括有源区2的图形。Step S2: A buffer layer 8 and a pattern including the active region 2 are sequentially formed on the base substrate 9 on which the step S1 is completed.
步骤S3：在完成步骤S2的衬底基板9上先后形成栅绝缘层7和包括栅极1的图形。Step S3: A gate insulating layer 7 and a pattern including the gate electrode 1 are sequentially formed on the base substrate 9 on which the step S2 is completed.
步骤S4：在完成步骤S3的衬底基板9上形成源极接触区3和漏极接触区4，源极接触区3和漏极接触区4采用离子注入方式形成于有源区2的相对两侧。Step S4: forming a source contact region 3 and a drain contact region 4 on the base substrate 9 on which the step S3 is completed, and the source contact region 3 and the drain contact region 4 are formed in the opposite sides of the active region 2 by ion implantation. side.
例如，注入的离子为硼离子或磷离子。For example, the implanted ions are boron ions or phosphorus ions.
上述步骤中，缓冲层8、有源区2、栅绝缘层7和栅极1均通过构图工艺形成，与形成非金属遮光层5的构图工艺过程相似，具体过程不再赘述。In the above steps, the buffer layer 8, the active region 2, the gate insulating layer 7, and the gate electrode 1 are all formed by a patterning process, which is similar to the patterning process for forming the non-metal light-shielding layer 5, and the specific process will not be described again.
例如，步骤S4还包括采用离子注入方式在有源区2中形成轻掺杂漏极接触区6，例如，注入的离子也为硼离子或磷离子，只是形成轻掺杂漏极接触区6注入的离子的量少于形成源极接触区3和漏极接触区4注入的离子的量。例如，轻掺杂漏极接触区6与源极接触区3和漏极接触区4同时形成。For example, step S4 further includes forming a lightly doped drain contact region 6 in the active region 2 by ion implantation. For example, the implanted ions are also boron ions or phosphorus ions, but only the lightly doped drain contact region 6 is implanted. The amount of ions is less than the amount of ions implanted in the source contact region 3 and the drain contact region 4. For example, the lightly doped drain contact region 6 is formed simultaneously with the source contact region 3 and the drain contact region 4.
在根据本发明实施例的薄膜晶体管及其制备方法中，通过在有源区的下方设置非金属遮光层，能使照射到有源区上的部分背光光线被遮挡住，从而使薄膜晶体管的漏电流降低，同时，由于非金属遮光层为非金属材料，所以不会产生寄生电容，因此即使针对双栅结构的薄膜晶体管，也不需要将非金属遮光层分隔为面积较小的两个小片，还能够确保采用该薄膜晶体管的显示产品的良率更高。In the thin film transistor and the method of fabricating the same according to embodiments of the present invention, by providing a non-metallic light shielding layer under the active region, a portion of the backlight light that is irradiated onto the active region can be blocked, thereby causing leakage of the thin film transistor. The current is reduced, and since the non-metallic light shielding layer is a non-metal material, parasitic capacitance is not generated, so even for a thin film transistor having a double gate structure, it is not necessary to separate the non-metal light shielding layer into two small pieces having a small area. It is also possible to ensure a higher yield of the display product using the thin film transistor.
本发明的实施例还提供一种阵列基板，包括如上所述的薄膜晶体管。Embodiments of the present invention also provide an array substrate including the thin film transistor as described above.
本发明实施例所提供的阵列基板可以是高级超维场转换显示方式(即ADS显示方式)的阵列基板、扭曲向列型显示方式(即TN显示方式)的阵列基板以及其他任何能够采用如上所述的薄膜晶体管的阵列基板。The array substrate provided by the embodiment of the present invention may be an array substrate of an advanced super-dimensional field conversion display mode (ie, ADS display mode), an array substrate of a twisted nematic display mode (ie, a TN display mode), and any other The array substrate of the thin film transistor.
其中，ADS(ADvanced Super Dimension Switch)模式是平面电场宽视 角核心技术，其中通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。ADS模式的开关技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。针对不同应用，ADS技术的改进技术有高透过率I-ADS技术、高开口率H-ADS和高分辨率S-ADS技术等。Among them, ADS (ADvanced Super Dimension Switch) mode is a planar electric field wide view An angular core technique in which a multi-dimensional electric field is formed by an electric field generated by an edge of a slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals are aligned between the slit electrodes in the liquid crystal cell and directly above the electrode Molecules are capable of rotating, thereby increasing the efficiency of the liquid crystal and increasing the light transmission efficiency. ADS mode switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. . For different applications, ADS technology has improved high-transmission I-ADS technology, high aperture ratio H-ADS and high-resolution S-ADS technology.
通过采用如上所述的薄膜晶体管，能进一步提高阵列基板的显示性能。By using the thin film transistor as described above, the display performance of the array substrate can be further improved.
本发明的实施例还提供一种显示装置，包括如上所述的阵列基板。Embodiments of the present invention also provide a display device including the array substrate as described above.
通过采用如上所述的阵列基板，使显示装置的显示性能得到了进一步提高。The display performance of the display device is further improved by employing the array substrate as described above.
上述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。The display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.
本申请要求于2014年8月13日递交的第201410397694.7号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。 The present application claims the priority of the Japanese Patent Application No. 20141039769, filed on Aug. 13, 2014, the entire disclosure of which is hereby incorporated by reference.

Claims (17)

  1. 一种薄膜晶体管，包括栅极、有源区、源极接触区和漏极接触区，所述栅极设置在所述有源区的上方，所述源极接触区和所述漏极接触区分设在所述有源区的相对两侧，其中所述薄膜晶体管还包括非金属遮光层，所述非金属遮光层设置在所述有源区的下方，且在正投影方向上与所述有源区至少部分重叠，所述非金属遮光层能对照射到其上的来自背光的全部可见光进行遮挡。A thin film transistor including a gate, an active region, a source contact region, and a drain contact region, the gate being disposed above the active region, the source contact region and the drain contact distinguishing Provided on opposite sides of the active region, wherein the thin film transistor further includes a non-metal light shielding layer disposed under the active region and in the forward projection direction The source regions at least partially overlap, and the non-metallic light shielding layer can block all visible light from the backlight that is irradiated thereon.
  2. 根据权利要求1所述的薄膜晶体管，其中所述非金属遮光层采用一维光子晶体光学薄膜形成，所述一维光子晶体光学薄膜包括交替堆叠的第一膜层和第二膜层。The thin film transistor according to claim 1, wherein said non-metallic light shielding layer is formed using a one-dimensional photonic crystal optical film comprising a first film layer and a second film layer which are alternately stacked.
  3. 根据权利要求2所述的薄膜晶体管，其中交替堆叠的所述第一膜层和所述第二膜层为一组或多组。The thin film transistor according to claim 2, wherein the first film layer and the second film layer which are alternately stacked are one or more groups.
  4. 根据权利要求2所述的薄膜晶体管，其中所述第一膜层和所述第二膜层的折射率不同，所述第一膜层和所述第二膜层的折射率范围均为1-5。The thin film transistor according to claim 2, wherein a refractive index of said first film layer and said second film layer are different, and said first film layer and said second film layer have a refractive index range of 1 - 5.
  5. 根据权利要求2所述的薄膜晶体管，其中所述第一膜层采用TiO2材料，所述第二膜层采用SiO2材料；或者所述第一膜层采用ZnSe材料，所述第二膜层采用MgF2材料。The thin film transistor according to claim 2, wherein said first film layer is made of TiO 2 material, said second film layer is made of SiO 2 material; or said first film layer is made of ZnSe material, said second film layer Use MgF2 material.
  6. 根据权利要求2所述的薄膜晶体管，其中所述第一膜层和所述第二膜层的厚度比为1:1.136。The thin film transistor according to claim 2, wherein a thickness ratio of said first film layer to said second film layer is 1:1.136.
  7. 根据权利要求1所述的薄膜晶体管，其中所述非金属遮光层设置在所述源极接触区和所述漏极接触区对应的区域之间，且在正投影方向上与所述栅极至少部分重叠。The thin film transistor according to claim 1, wherein said non-metal light shielding layer is disposed between said source contact region and a region corresponding to said drain contact region, and at least said gate electrode in a right projection direction Partial overlap.
  8. 根据权利要求1所述的薄膜晶体管，其中所述栅极为至少一个，所述栅极位于所述非金属遮光层的正投影方向上。The thin film transistor according to claim 1, wherein said gate electrode is at least one, and said gate electrode is located in a front projection direction of said non-metal light shielding layer.
  9. 根据权利要求1所述的薄膜晶体管，其中所述有源区中还设置有轻掺杂漏极接触区，所述轻掺杂漏极接触区设置在所述源极接触区和所述漏极接触区之间，且分居在所述栅极对应的区域的两侧。The thin film transistor according to claim 1, wherein a lightly doped drain contact region is further disposed in said active region, said lightly doped drain contact region being disposed in said source contact region and said drain Between the contact regions, and separated on both sides of the corresponding region of the gate.
  10. 根据权利要求1所述的薄膜晶体管，其中在所述有源区与所述栅极之间还设置有栅绝缘层，在所述非金属遮光层与所述有源区之间还设置有缓 冲层。The thin film transistor according to claim 1, wherein a gate insulating layer is further disposed between the active region and the gate, and a buffer is disposed between the non-metal light shielding layer and the active region Punch layer.
  11. 一种阵列基板，包括权利要求1-10任意一项所述的薄膜晶体管。An array substrate comprising the thin film transistor according to any one of claims 1 to 10.
  12. 一种显示装置，包括权利要求11所述的阵列基板。A display device comprising the array substrate of claim 11.
  13. 一种如权利要求1-10任意一项所述的薄膜晶体管的制备方法，包括形成栅极、有源区、源极接触区和漏极接触区的步骤，其中还包括形成非金属遮光层的步骤。A method of fabricating a thin film transistor according to any one of claims 1 to 10, comprising the steps of forming a gate electrode, an active region, a source contact region and a drain contact region, further comprising forming a non-metal light shielding layer step.
  14. 根据权利要求13所述的薄膜晶体管的制备方法，其中所述制备方法包括：The method of fabricating a thin film transistor according to claim 13, wherein the preparation method comprises:
    步骤S1：采用构图工艺在衬底基板上形成包括所述非金属遮光层的图形；Step S1: forming a pattern including the non-metal light shielding layer on the base substrate by using a patterning process;
    步骤S2：在完成步骤S1的所述衬底基板上先后形成缓冲层和包括所述有源区的图形；Step S2: forming a buffer layer and a pattern including the active region on the substrate of the step S1;
    步骤S3：在完成步骤S2的所述衬底基板上先后形成栅绝缘层和包括所述栅极的图形；Step S3: sequentially forming a gate insulating layer and a pattern including the gate on the substrate of the step S2;
    步骤S4：在完成步骤S3的所述衬底基板上形成所述源极接触区和所述漏极接触区，所述源极接触区和所述漏极接触区采用离子注入方式形成于所述有源区的相对两侧。Step S4: forming the source contact region and the drain contact region on the substrate of the step S3, wherein the source contact region and the drain contact region are formed by ion implantation The opposite sides of the active area.
  15. 根据权利要求14所述的薄膜晶体管的制备方法，其中所述采用构图工艺在衬底基板上形成包括所述非金属遮光层的图形包括：The method of fabricating a thin film transistor according to claim 14, wherein the patterning comprising the non-metallic light-shielding layer on the substrate substrate by using a patterning process comprises:
    当所述非金属遮光层为采用一组交替堆叠的第一膜层和第二膜层形成时，形成所述非金属遮光层的步骤包括：When the non-metallic light shielding layer is formed by using a set of the first film layer and the second film layer which are alternately stacked, the step of forming the non-metal light shielding layer includes:
    步骤S11：在所述衬底基板上形成一层第一膜层膜；Step S11: forming a first film layer on the substrate;
    步骤S12：在完成步骤S11的所述衬底基板上形成一层第二膜层膜；Step S12: forming a second film layer on the substrate of the step S11;
    步骤S13：通过一次构图工艺形成包括所述非金属遮光层的图形；Step S13: forming a pattern including the non-metal light shielding layer by one patterning process;
    当所述非金属遮光层为采用多组交替堆叠的第一膜层和第二膜层形成时，形成所述非金属遮光层的步骤包括：When the non-metallic light shielding layer is formed by using a plurality of sets of the first film layer and the second film layer which are alternately stacked, the step of forming the non-metal light shielding layer includes:
    多次重复所述步骤S11和所述步骤S12，然后通过一次构图工艺形成包括所述非金属遮光层的图形。The step S11 and the step S12 are repeated a plurality of times, and then a pattern including the non-metallic light shielding layer is formed by one patterning process.
  16. 根据权利要求15所述的薄膜晶体管的制备方法，其中所述步骤S11和所述步骤S12的先后顺序可互换。 The method of fabricating a thin film transistor according to claim 15, wherein the order of said step S11 and said step S12 are interchangeable.
  17. 根据权利要求14所述的薄膜晶体管的制备方法，其中所述步骤S4还包括采用离子注入方式在所述有源区中形成轻掺杂漏极接触区。 The method of fabricating a thin film transistor according to claim 14, wherein said step S4 further comprises forming a lightly doped drain contact region in said active region by ion implantation.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111524916A (en) * 2020-04-28 2020-08-11 深圳市华星光电半导体显示技术有限公司 Photoelectric conversion device, manufacturing method thereof and display device
CN111785735A (en) * 2020-07-02 2020-10-16 Tcl华星光电技术有限公司 Array substrate, manufacturing method thereof and display panel

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795496A (en) * 2015-04-08 2015-07-22 深圳市华星光电技术有限公司 Bigrid device and manufacturing method thereof
CN104979405B (en) * 2015-07-22 2019-05-21 京东方科技集团股份有限公司 A kind of thin film transistor (TFT), array substrate and display device
CN105093679B (en) * 2015-08-20 2017-12-05 京东方科技集团股份有限公司 A kind of display base plate and preparation method thereof, display panel and display device
CN105336745B (en) * 2015-09-30 2019-01-22 深圳市华星光电技术有限公司 Low temperature polycrystalline silicon TFT substrate
CN105977262B (en) * 2016-05-27 2019-09-20 深圳市华星光电技术有限公司 A kind of display device, array substrate and its manufacturing method
CN106229338A (en) * 2016-08-24 2016-12-14 深圳市华星光电技术有限公司 A kind of thin film transistor (TFT) and preparation method thereof
CN108878537B (en) * 2017-05-12 2021-02-12 京东方科技集团股份有限公司 Thin film transistor, preparation method thereof, display panel and display device
CN108258143A (en) * 2018-01-12 2018-07-06 京东方科技集团股份有限公司 A kind of display panel and preparation method thereof, display device
CN109283734A (en) * 2018-11-20 2019-01-29 京东方科技集团股份有限公司 Color membrane substrates and display device
CN109754710B (en) * 2019-02-28 2021-08-03 昆山国显光电有限公司 Light-shielding layer and display device
CN114002887B (en) * 2021-11-01 2022-10-04 武汉华星光电技术有限公司 Array substrate and display panel

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102016703A (en) * 2008-04-25 2011-04-13 夏普株式会社 Liquid crystal display device
CN102023424A (en) * 2009-09-09 2011-04-20 北京京东方光电科技有限公司 TFT-LCD array substrate and manufacture method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03290622A (en) * 1990-04-09 1991-12-20 Nippon Telegr & Teleph Corp <Ntt> Thin film transistor
TWI244571B (en) * 2002-01-30 2005-12-01 Sanyo Electric Co Semiconductor display device
JP4419577B2 (en) * 2004-01-19 2010-02-24 セイコーエプソン株式会社 Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus
JP5037808B2 (en) * 2005-10-20 2012-10-03 キヤノン株式会社 Field effect transistor using amorphous oxide, and display device using the transistor
US9239484B2 (en) * 2010-11-10 2016-01-19 Sharp Kabushiki Kaisha Display device substrate and method for fabricating same, and display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102016703A (en) * 2008-04-25 2011-04-13 夏普株式会社 Liquid crystal display device
CN102023424A (en) * 2009-09-09 2011-04-20 北京京东方光电科技有限公司 TFT-LCD array substrate and manufacture method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111524916A (en) * 2020-04-28 2020-08-11 深圳市华星光电半导体显示技术有限公司 Photoelectric conversion device, manufacturing method thereof and display device
CN111785735A (en) * 2020-07-02 2020-10-16 Tcl华星光电技术有限公司 Array substrate, manufacturing method thereof and display panel

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