WO2016019520A1 - Tft-lcd阵列基板及其制造方法 - Google Patents

Tft-lcd阵列基板及其制造方法 Download PDF

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Publication number
WO2016019520A1
WO2016019520A1 PCT/CN2014/083773 CN2014083773W WO2016019520A1 WO 2016019520 A1 WO2016019520 A1 WO 2016019520A1 CN 2014083773 W CN2014083773 W CN 2014083773W WO 2016019520 A1 WO2016019520 A1 WO 2016019520A1
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insulating layer
gate line
tft
array substrate
lcd array
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PCT/CN2014/083773
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US14/382,331 priority Critical patent/US20160033832A1/en
Publication of WO2016019520A1 publication Critical patent/WO2016019520A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a TFT-LCD array substrate and a method of fabricating the same.
  • the image display panel displays a progressive scan matrix array of M x N dots, which includes an array substrate for controlling the light source.
  • the driver of the array substrate mainly includes a gate driver, that is, a scan driver, and a data driver, wherein the gate driver inputs the clock
  • the signal is converted by the shift register and applied to the gate line of the liquid crystal display panel.
  • the capacitor is essential as a basic unit of the shift register, and at least one capacitor is required, and at least several picofarads (pF) to several sizes are required.
  • Ten skin methods which usually occupy an area of 1000 ⁇ 2 to 1000000 ⁇ 2 .
  • the shift register of the gate driver of the TFT-LCD is used, one electrode of the capacitor is used as the TFT gate layer, and the other electrode is fabricated using the TFT source and drain layers.
  • a pixel unit structure on a TFT-LCD array substrate comprising: a TFT switch, a storage capacitor and a liquid crystal capacitor, wherein the storage capacitor is generally composed of an overlap region between a Com electrode formed by the first gate metal and the pixel electrode ITO, Since the Com electrode is made of a metal material and is opaque, the storage capacitor region is an opaque region, so that the aperture ratio of the pixel region and the storage capacitor form a contradiction.
  • FIG. 1 is a schematic structural view of a conventional TFT-LCD array substrate in which a storage capacitor formed by an overlap region between a Com metal layer 102 and an ITO layer 105 on a glass substrate 101 is a G-SiNx layer and a P-
  • the SiNx layer 104 has two insulating layers with a large distance, so that the storage capacitance per unit area in the prior art TFT-LCD array substrate is small.
  • the technical problem to be solved by the present invention is to provide a TFT-LCD array substrate and a method of fabricating the same, which can reduce the distance between the storage capacitor plates to increase the storage capacitance per unit area.
  • the present invention provides a method for fabricating a TFT-LCD array substrate, comprising: sequentially forming a gate line and a first insulating layer including a first via hole on a glass substrate; a connection electrode, a source electrode, a drain electrode, and a data line, wherein the first connection electrode is connected to the gate line through the first via hole, and is also connected to the data line; the second insulating layer and the pixel electrode are sequentially disposed; wherein the first via hole is formed On the gate line, and passing through the first insulating layer to expose the gate line; the second insulating layer has a thickness smaller than the thickness of the first insulating layer.
  • the overlapping area of the pixel electrode and the gate line forms a storage capacitor, wherein the second insulating layer forms a dielectric layer of the storage capacitor.
  • the present invention provides a TFT-LCD array substrate including a gate line and a data line.
  • a pixel electrode and a thin film transistor are formed in a pixel region defined by the gate line and the data line, and a pixel region is further disposed in the pixel region.
  • a connection electrode, the first connection electrode is connected to the gate line through the first via hole, and is also connected to the data line.
  • a first insulating layer is disposed on the gate line, and the first via hole passes through the first insulating layer to expose the gate line.
  • the first connection electrode is disposed on the gate line through the first via hole.
  • the first connecting electrode is provided with a second insulating layer, and the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.
  • the second insulating layer has a thickness of 1000 to 2500A.
  • the present invention further provides a method for fabricating a TFT-LCD array substrate, comprising: sequentially forming a gate line and a first insulating layer including a first via hole on a glass substrate; and providing a first connection electrode, a source electrode, a drain electrode and a data line, wherein the first connection electrode is connected to the gate line through the first via hole, and is also connected to the data line; the second insulating layer and the pixel electrode are sequentially disposed.
  • the first via is formed on the gate line and passes through the first insulating layer to expose the gate line.
  • the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.
  • the overlapping area of the pixel electrode and the gate line forms a storage capacitor, wherein the second insulating layer forms a dielectric layer of the storage capacitor.
  • the TFT-LCD array substrate includes a gate line and a data line, a pixel electrode and a thin film transistor are formed in a pixel region defined by the gate line and the data line, and the pixel region is further provided with a first Connecting the electrodes, the first connection electrode is connected to the gate line through the first via hole, and is also connected to the data line, so that the distance between the two electrodes of the storage capacitor is reduced, thereby increasing the unit surface The storage capacitor value.
  • FIG. 1 is a schematic structural view of a prior art TFT-LCD array substrate
  • FIG. 2 is a plan view showing a planar structure of a TFT-LCD array substrate according to a first embodiment of the present invention
  • FIG. 3 is a cross-sectional view taken along line A1-A1 of FIG.
  • FIG. 4 is a flow chart showing a method of manufacturing a TFT-LCD array substrate according to a first embodiment of the present invention. ⁇ detailed description ⁇
  • Fig. 2 is a plan view showing the planar structure of a TFT-LCD array substrate according to a first embodiment of the present invention.
  • the TFT-LCD array substrate 20 includes a gate line 201 and a data line 202.
  • a pixel electrode 203 and a thin film transistor 204 are formed in a pixel region defined by the gate line 201 and the data line 202.
  • a first connection electrode 205 is further disposed in the pixel region, and the first connection electrode 205 is connected to the gate line 201 through the first via 206, and is also connected to the data line 202, that is, the first connection electrode is a source drain line.
  • the thin film transistor 204 includes a source 207, a drain 208, and a gate 209. The first connection electrode 205 and the data line 202 and the source 207 and the drain 208 are formed in the same patterning process.
  • FIG. 3 is a schematic cross-sectional view taken along line A1-A1 of Figure 2; As shown in FIG. 3, a first insulating layer 210 is disposed on the gate line 201, and the first via 206 passes through the first insulating layer 210 to expose the gate line 201.
  • the first connection electrode 205 is disposed on the gate line 201 through the first via 206.
  • the gate line 201 is disposed on the glass substrate 200.
  • a second insulating layer 211 is disposed on the first connection electrode 205.
  • a pixel electrode 203 is disposed on the second insulating layer 211, and an overlapping region of the pixel electrode 203 and the gate line 201 forms a storage capacitor, wherein the second insulating layer 211 forms a dielectric layer of the storage capacitor.
  • the dielectric constant, k is the constant force of the electrostatic force.
  • the first insulating layer 210 is preferably a G-SiNx layer having a thickness of preferably 4000 to 5000 A
  • the second insulating layer 211 is preferably a P-SiNx layer having a thickness of preferably 1000 to 2500 ⁇ .
  • the thickness of the second insulating layer 211 is smaller than the thickness of the first insulating layer 210.
  • the distance between the two electrodes of the storage capacitor is reduced to the thickness of the second insulating layer 211, and the distance is small, and the storage capacitance per unit area is increased.
  • the TFT-LCD array substrate of this embodiment is suitable for TN type, VA type and IPS type liquid crystal display modes.
  • FIG. 4 is a schematic flow chart of a method of fabricating a TFT-LCD array substrate according to a first embodiment of the present invention.
  • the manufacturing method of the TFT-LCD array substrate includes: Step S10: sequentially forming a gate line and a first insulating layer including the first via hole on the glass substrate.
  • the first via is formed on the gate line and passes through the first insulating layer to expose the gate line.
  • Step S11 The first connection electrode, the source electrode, the drain electrode and the data line are disposed, wherein the first connection electrode is connected to the gate line through the first via hole, and the data line is also connected.
  • the first connection electrode is an S/D line.
  • Step S12 The second insulating layer and the pixel electrode are sequentially disposed.
  • the pixel electrode is covered on the second insulating layer.
  • the first insulating layer is preferably a G-SiNx layer, and the thickness thereof is preferably 4000 ⁇ 5000 A.
  • the second insulating layer is preferably a P-SiNx layer, and the thickness thereof is preferably 1000 ⁇ 2500 A. . It can be seen that the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.
  • the overlapping area of the pixel electrode and the gate line forms a storage capacitor, wherein the second insulating layer forms a dielectric layer of the storage capacitor.
  • the TFT-LCD array substrate of the present invention includes a gate line and a data line, a pixel electrode and a thin film transistor are formed in a pixel region defined by the gate line and the data line, and a first connection electrode is further disposed in the pixel region, A connection electrode is connected to the gate line through the first via hole, and the data line is also connected, so that the distance between the two electrodes of the storage capacitor is reduced, thereby increasing the storage capacitance value per unit area.

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Abstract

一种ＴＦＴ-ＬＣＤ阵列基板及其制造方法，包括：栅线（201）和数据线（202），栅线（201）和数据线（202）限定的像素区域内形成有像素电极（203）和薄膜晶体管（204），像素区域内还设置有第一连接电极（205），第一连接电极（205）通过第一过孔（206）与栅线（201）连接，同时还连接数据线（202）。通过上述方式，能够使得存储电容的两个电极之间的距离减小，从而增大了单位面积储存电容值。

Description

TFT-LCD阵列基 jfel及其制造方法
【技术领域】
本发明涉及液晶显示领域， 特别是涉及一种 TFT-LCD阵列基板及其制造方 法。
【背景技术】
图像显示面板釆用 M x N点排列的逐行扫描矩阵显示， 其包括用于控制发 光源的阵列基板。 以薄膜场效应晶体管液晶显示器 (Thin Film Transistor Liquid Crystal Display, 简称 TFT-LCD) 为例， 阵列基板的驱动器主要包括栅极驱动器， 即 扫描驱动器， 和数据驱动器， 其中， 栅极驱动器将输入的时钟信号通过移 位寄存器转换后加在液晶显示面板的栅线上。
目前已有很多种现有技术用于优化减少 TFT 的个数， 而电容作为移位寄存 器的必须基本单元， 必不可少， 而且电容至少需要一个， 大小至少需要几个皮 法 (pF) 到几十个皮法， 即通常所占面积由 1000 μ ιη2到 1000000 μ ιη2。 通常在做 TFT-LCD 的栅极驱动器的移位寄存器时， 会把电容的一个电极作为 TFT栅极 层， 另一电极使用 TFT 源漏层制造。
TFT-LCD阵列基板上的像素单元结构， 其中包括： 一个 TFT开关、 一个存 储电容和一个液晶电容， 通常存储电容由第一层栅金属形成的 Com电极与像素 电极 ITO之间的重叠区域构成， 由于 Com电极由金属材料构成， 不透光， 因此 存储电容区域为不透光区， 使得像素区开口率与存储电容构成一对矛盾体。 图 1 是现有技术 TFT-LCD阵列基板的结构示意图， 其中由玻璃基板 101上的 Com 金属层 102与 ITO层 105间的重叠区形成的存储电容， 介电物质为 G-SiNx层 和 P-SiNx层 104两层绝缘层， 距离较大， 使得现有技术 TFT-LCD 阵列基板中 单位面积存储电容较小。
【发明内容】
本发明解决的技术问题是， 提供一种 TFT-LCD阵列基板及其制造方法， 能 够减少存储电容极板间距离， 以增大单位面积储存电容值。
为解决上述技术问题， 本发明提供了一种 TFT-LCD阵列基板的制造方法， 包括： 在玻璃基板上依次形成栅线和包括第一过孔的第一绝缘层； 设置第一连 接电极、 源电极、 漏电极和数据线， 其中第一连接电极通过第一过孔与栅线连 接， 同时还连接数据线； 依次设置第二绝缘层和像素电极； 其中， 第一过孔形 成在栅线上， 并穿过第一绝缘层以露出栅线； 第二绝缘层厚度小于第一绝缘层 厚度。
其中， 像素电极和栅线的重叠区域形成存储电容， 其中第二绝缘层形成存 储电容的介质层。
为解决上述技术问题， 本发明提供了一种 TFT-LCD阵列基板， 包括栅线和 数据线， 栅线和数据线限定的像素区域内形成有像素电极和薄膜晶体管， 像素 区域内还设置有第一连接电极， 第一连接电极通过第一过孔与栅线连接， 同时 还连接数据线。
其中， 栅线上设置第一绝缘层， 第一过孔穿过第一绝缘层， 露出栅线。 其中， 第一连接电极通过第一过孔设置在栅线上。
其中， 第一连接电极上设置第二绝缘层， 第二绝缘层厚度小于第一绝缘层 厚度。
其中， 第二绝缘层上设置像素电极， 像素电极和栅线的重叠区域形成存储 电容， 其中第二绝缘层形成存储电容的介质层， 存储电容的电容值为： C=e-S/½kd; 其中 S是重叠区域的面积， d是第二绝缘层的厚度， ε是第二绝缘 层的介电常量， k是静电力恒量。
其中， 第二绝缘层的厚度为 1000〜2500A。
为解决上述技术问题，本发明还提供了一种 TFT-LCD阵列基板的制造方法， 包括： 在玻璃基板上依次形成栅线和包括第一过孔的第一绝缘层； 设置第一连 接电极、 源电极、 漏电极和数据线， 其中第一连接电极通过第一过孔与栅线连 接， 同时还连接数据线； 依次设置第二绝缘层和像素电极。
其中， 第一过孔形成在栅线上， 并穿过第一绝缘层以露出栅线。
其中， 第二绝缘层厚度小于第一绝缘层厚度。
其中， 像素电极和栅线的重叠区域形成存储电容， 其中第二绝缘层形成存 储电容的介质层。
通过上述方案， 本发明的有益效果是： 通过 TFT-LCD阵列基板包括栅线和 数据线， 栅线和数据线限定的像素区域内形成有像素电极和薄膜晶体管， 像素 区域内还设置有第一连接电极， 第一连接电极通过第一过孔与栅线连接， 同时 还连接数据线， 使得存储电容的两个电极之间的距离减小， 从而增大了单位面 积储存电容值。
【附图说明】
图 1是现有技术 TFT-LCD阵列基板的结构示意图；
图 2是本发明第一实施例的 TFT-LCD阵列基板的平面结构示意图； 图 3是图 2中 A1-A1向的剖面示意图；
图 4是本发明第一实施例的 TFT-LCD阵列基板的制造方法的流程示意图。 【具体实施方式】
请参阅图 2, 图 2是本发明第一实施例的 TFT-LCD阵列基板的平面结构示 意图。如图 2所示， TFT-LCD阵列基板 20包括栅线 201和数据线 202。栅线 201 和数据线 202限定的像素区域内形成有像素电极 203和薄膜晶体管 204。像素区 域内还设置有第一连接电极 205, 第一连接电极 205通过第一过孔 206与栅线 201连接， 同时还连接数据线 202, 即第一连接电极为源漏线。 薄膜晶体管 204 包括源极 207、 漏极 208以及栅极 209 , 第一连接电极 205与数据线 202以及源 极 207、 漏极 208是在同一次构图工艺中形成的。
图 3为图 2中 A1-A1向的剖面示意图。 如图 3所示， 栅线 201上设置第一 绝缘层 210, 第一过孔 206穿过第一绝缘层 210, 露出栅线 201。 第一连接电极 205通过第一过孔 206设置在栅线 201上。其中栅线 201设置在玻璃基板 200上。 第一连接电极 205上设置第二绝缘层 211。第二绝缘层 211上设置像素电极 203 , 像素电极 203和栅线 201的重叠区域形成存储电容， 其中第二绝缘层 211形成 存储电容的介质层。 存储电容的电容值为： C=s，S/½kd; 其中 S是像素电极 203 和栅线 201的重叠区域的面积， d是第二绝缘层 211的厚度， ε是所述第二绝缘 层 211的介电常量， k是静电力恒量。 而在本实施例中， 第一绝缘层 210优选为 G-SiNx层， 其厚度优选为 4000〜5000A, 第二绝缘层 211优选为 P-SiNx层， 其 厚度优选为 1000〜2500 A。可见，第二绝缘层 211厚度小于第一绝缘层 210厚度。 本实施例使存储电容的两个电极之间的距离减小为第二绝缘层 211 的厚度， 距 离较小，增大了单位面积储存电容值。本实施例的 TFT-LCD阵列基板适用于 TN 型， VA型与 IPS型液晶显示模式。
请参阅图 4, 图 4是本发明第一实施例的 TFT-LCD阵列基板的制造方法的 流程示意图。 如图 4所示， TFT-LCD阵列基板的制造方法包括： 步骤 S10: 在玻璃基板上依次形成栅线和包括第一过孔的第一绝缘层。
其中第一过孔形成在栅线上， 并穿过第一绝缘层以露出栅线。
步骤 S11 : 设置第一连接电极、 源电极、 漏电极和数据线， 其中第一连接电 极通过第一过孔与栅线连接， 同时还连接数据线。
其中， 第一连接电极为 S/D线。
步骤 S12: 依次设置第二绝缘层和像素电极。
其中像素电极覆盖在第二绝缘层上， 第一绝缘层优选为 G-SiNx层， 其厚度 优选为 4000〜5000 A,第二绝缘层优选为 P-SiNx层，其厚度优选为 1000〜2500 A。 可见， 第二绝缘层厚度小于第一绝缘层厚度。 像素电极和栅线的重叠区域形成 存储电容， 其中第二绝缘层形成存储电容的介质层。 存储电容的电容值为： C=e-S/½kd; 其中 S是像素电极和栅线的重叠区域的面积， d是第二绝缘层的厚 度， ε是所述第二绝缘层的介电常量， k是静电力恒量。 如此使得存储电容的两 个电极之间的距离减小为第二绝缘层的厚度， 从而增大了单位面积储存电容值。
综上所述， 本发明的 TFT-LCD阵列基板包括栅线和数据线， 栅线和数据线 限定的像素区域内形成有像素电极和薄膜晶体管， 像素区域内还设置有第一连 接电极， 第一连接电极通过第一过孔与栅线连接， 同时还连接数据线， 使得存 储电容的两个电极之间的距离减小， 从而增大了单位面积储存电容值。
以上所述仅为本发明的实施例， 并非因此限制本发明的专利范围， 凡是利 用本发明说明书及附图内容所作的等效结构或等效流程变换， 或直接或间接运 用在其他相关的技术领域， 均同理包括在本发明的专利保护范围内。

Claims

权利 要求
1. 一种 TFT-LCD阵列基板的制造方法， 其特征在于， 包括：
在玻璃基板上依次形成栅线和包括第一过孔的第一绝缘层；
设置第一连接电极、 源电极、 漏电极和数据线， 其中所述第一连接电极通 过所述第一过孔与所述栅线连接， 同时还连接所述数据线；
依次设置第二绝缘层和像素电极；
其中， 所述第一过孔形成在所述栅线上， 并穿过所述第一绝缘层以露出所 述栅线； 所述第二绝缘层厚度小于所述第一绝缘层厚度。
2. 根据权利要求 1所述的制造方法， 其特征在于， 所述像素电极和所述栅 线的重叠区域形成存储电容， 其中所述第二绝缘层形成所述存储电容的介质层。
3. 一种 TFT-LCD阵列基板， 其特征在于， 包括栅线和数据线， 所述栅线和 所述数据线限定的像素区域内形成有像素电极和薄膜晶体管， 所述像素区域内 还设置有第一连接电极， 所述第一连接电极通过第一过孔与所述栅线连接， 同 时还连接所述数据线。
4. 根据权利要求 3所述的 TFT-LCD阵列基板， 其特征在于， 所述栅线上设 置第一绝缘层， 所述第一过孔穿过所述第一绝缘层， 露出所述栅线。
5. 根据权利要求 4所述的 TFT-LCD阵列基板， 其特征在于， 所述第一连接 电极通过所述第一过孔设置在所述栅线上。
6. 根据权利要求 5所述的 TFT-LCD阵列基板， 其特征在于， 所述第一连接 电极上设置所述第二绝缘层， 所述第二绝缘层厚度小于所述第一绝缘层厚度。
7. 根据权利要求 6所述的 TFT-LCD阵列基板， 其特征在于， 所述第二绝缘 层上设置所述像素电极， 所述像素电极和所述栅线的重叠区域形成存储电容， 其中所述第二绝缘层形成所述存储电容的介质层， 所述存储电容的电容值为： C=e-S/½kd;
其中 S是所述重叠区域的面积， d是所述第二绝缘层的厚度， ε是所述第二 绝缘层的介电常量， k是静电力恒量。
8. 根据权利要求 7所述的 TFT-LCD阵列基板， 其特征在于， 所述第二绝缘 层的厚度为 1000〜2500A。
9. 一种 TFT-LCD阵列基板的制造方法， 其特征在于， 包括： 在玻璃基板上依次形成栅线和包括第一过孔的第一绝缘层；
设置第一连接电极、 源电极、 漏电极和数据线， 其中所述第一连接电极通 过所述第一过孔与所述栅线连接， 同时还连接所述数据线；
依次设置第二绝缘层和像素电极。
10. 根据权利要求 9所述的制造方法， 其特征在于， 所述第一过孔形成在所 述栅线上， 并穿过所述第一绝缘层以露出所述栅线。
11. 根据权利要求 9所述的制造方法， 其特征在于， 所述第二绝缘层厚度小 于所述第一绝缘层厚度。
12. 根据权利要求 10所述的制造方法， 其特征在于， 所述像素电极和所述 栅线的重叠区域形成存储电容， 其中所述第二绝缘层形成所述存储电容的介质 层。
PCT/CN2014/083773 2014-08-04 2014-08-06 Tft-lcd阵列基板及其制造方法 WO2016019520A1 (zh)

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