WO2016015273A1 - 液晶显示面板及其制造方法、阵列基板 - Google Patents

液晶显示面板及其制造方法、阵列基板 Download PDF

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Publication number
WO2016015273A1
WO2016015273A1 PCT/CN2014/083400 CN2014083400W WO2016015273A1 WO 2016015273 A1 WO2016015273 A1 WO 2016015273A1 CN 2014083400 W CN2014083400 W CN 2014083400W WO 2016015273 A1 WO2016015273 A1 WO 2016015273A1
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Prior art keywords
layer
electrode
liquid crystal
electrode layer
substrate
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PCT/CN2014/083400
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English (en)
French (fr)
Inventor
郝思坤
邱钟毅
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深圳市华星光电技术有限公司
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Priority to US14/379,029 priority Critical patent/US20160246121A1/en
Publication of WO2016015273A1 publication Critical patent/WO2016015273A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to the field of liquid crystal display technology based on a transverse electric field mode, and more particularly to a liquid crystal display panel and an array substrate thereof, and a method of manufacturing the liquid crystal display panel.
  • TN Transmission Nematic, Twisted Out
  • MVA Multi-domain Vertical Alignment, multi-quadrant vertical alignment type, etc.
  • IPS In-plane
  • a liquid crystal display panel of a transverse electric field mode, such as switching, planar conversion type, is provided with electrodes only on one substrate or substrate.
  • FFS Flexible Field
  • IPS mode Switching, edge electric field switching type liquid crystal display panel is provided with a layer of electrodes spaced below the pixel electrodes.
  • the boundary electric field generated when the driving voltage is applied causes the liquid crystal molecules to deflect inside the surface of the electrode, thereby improving the penetration of the backlight and realizing a large viewing angle display.
  • a parasitic capacitance is inevitably formed between the pixel electrode and the layer electrode disposed under the pixel electrode. If the parasitic capacitance is too large, the charging rate of the pixel unit of the liquid crystal display panel is affected, thereby greatly affecting the display of the liquid crystal display panel. Effect and quality.
  • the industry generally reduces the parasitic capacitance by increasing the thickness of the insulating layer between the pixel electrode and the underlying electrode.
  • an increase in the thickness of the insulating layer inevitably leads to an increase in the driving voltage, and an increase in the driving voltage inevitably increases the power consumption of the driving circuit, thereby reducing the operating time of the display terminal using the liquid crystal display panel.
  • the technical problem to be solved by the embodiments of the present invention is to provide a liquid crystal display panel, a manufacturing method thereof, and an array substrate, which can reduce the driving voltage, save power consumption, and improve the working time of the display terminal using the liquid crystal display panel.
  • a technical solution adopted by the present invention is to provide a liquid crystal display panel having a first substrate and a second substrate and a plurality of pixel units disposed at a relatively spaced interval, each of the pixel units including: a liquid crystal layer between a substrate and a second substrate, and a first electrode layer, a second electrode layer and an insulating layer disposed on a side of the first substrate facing the liquid crystal layer, the first electrode layer being disposed adjacent to the first substrate, and insulating The layer is sandwiched between the first electrode layer and the second electrode layer; wherein the second electrode layer is provided with an electrode pattern, and the region of the insulating layer corresponding to the second electrode layer where the electrode pattern is not disposed is provided with a groove, wherein the electrode pattern a plurality of spaced strip structures, the insulating layer is provided with a groove corresponding to a region between two adjacent strip structures, the first electrode layer includes a common electrode, the second electrode layer includes a pixel electrode, and the electrode pattern includes
  • the depth of the groove is 0 to 6000 angstroms.
  • the first substrate of the liquid crystal display panel is an array substrate.
  • a technical solution adopted by the present invention is to provide a liquid crystal display panel having a first substrate and a second substrate and a plurality of pixel units disposed at a relatively spaced interval, each of the pixel units including: a liquid crystal layer between a substrate and a second substrate, and a first electrode layer, a second electrode layer and an insulating layer disposed on a side of the first substrate facing the liquid crystal layer, the first electrode layer being disposed adjacent to the first substrate, and insulating The layer is sandwiched between the first electrode layer and the second electrode layer; wherein the second electrode layer is provided with an electrode pattern, and a region of the insulating layer corresponding to the second electrode layer where the electrode pattern is not disposed is provided with a groove.
  • the electrode pattern is a plurality of spaced strip structures, and the insulating layer is provided with a groove corresponding to a region between two adjacent strip structures.
  • the depth of the groove is 0 to 6000 angstroms.
  • the first electrode layer includes a common electrode
  • the second electrode layer includes a pixel electrode
  • the electrode pattern includes a pixel electrode pattern.
  • another technical solution adopted by the present invention is to provide a method for manufacturing a liquid crystal display panel, comprising: coating a substrate on which a first electrode layer, an insulating layer, and a second electrode layer are sequentially deposited; a photoresist layer; performing a first etching on the second electrode layer not covered by the photoresist layer to form an electrode pattern on the second electrode layer, and exposing a surface of the insulating layer corresponding to a region not covered by the photoresist layer And performing a second etching on the exposed surface of the insulating layer to form a region of the insulating layer corresponding to the second electrode layer where the electrode pattern is not disposed; removing the photoresist layer.
  • the first etching is wet etching
  • the second etching is dry etching
  • the formed electrode pattern is a plurality of strip structures arranged at intervals, and the insulating layer is provided with a groove corresponding to an area between adjacent two strip structures.
  • the groove formed has a depth of 0 to 6000 angstroms.
  • the first electrode layer includes a common electrode
  • the second electrode layer includes a pixel electrode
  • the electrode pattern includes a pixel electrode pattern.
  • an array substrate for a liquid crystal display panel having a liquid crystal layer and a plurality of pixel units comprising: a substrate and a substrate disposed on the liquid crystal layer a first electrode layer, a second electrode layer and an insulating layer, the first electrode layer is disposed adjacent to the substrate, and the insulating layer is sandwiched between the first electrode layer and the second electrode layer; wherein the second electrode layer is disposed There is an electrode pattern, and a region of the insulating layer corresponding to the second electrode layer where the electrode pattern is not provided is provided with a groove.
  • the electrode pattern is a plurality of spaced strip structures, and the insulating layer is provided with a groove corresponding to a region between two adjacent strip structures, and the depth of the groove is 0 to 6000 angstroms.
  • the first electrode layer includes a common electrode
  • the second electrode layer includes a pixel electrode
  • the electrode pattern includes a pixel electrode pattern.
  • the beneficial effects of the embodiments of the present invention are: the embodiment of the present invention provides a groove on the insulating layer sandwiched between the first electrode layer and the second electrode layer, and the groove corresponds to the second
  • the region where the electrode layer is not provided with the electrode pattern can not only reduce the parasitic capacitance formed when the driving voltage is applied to the first electrode layer and the second electrode layer, but also does not increase the thickness of the insulating layer, and can lower the driving voltage compared to the prior art.
  • the power consumption is saved, thereby improving the working time of the display terminal using the liquid crystal display panel.
  • FIG. 1 is a cross-sectional view showing the structure of a liquid crystal display panel in accordance with a preferred embodiment of the present invention
  • Figure 2 is a cross-sectional view showing the structure of a pixel unit in accordance with a preferred embodiment of the present invention
  • FIG. 3 is a schematic diagram of a corresponding transmittance of a pixel unit in which no recess is provided in the prior art when a driving voltage is applied;
  • FIG. 4 is a schematic diagram of a corresponding transmittance of a pixel unit in a preferred embodiment of the present invention when a driving voltage is applied;
  • FIG. 5 is a schematic diagram of corresponding transmittances of a pixel unit in which no recess is provided in the prior art when another driving voltage is applied;
  • FIG. 6 is a schematic diagram of a corresponding transmittance of a pixel unit in a preferred embodiment of the present invention when another driving voltage is applied;
  • FIGS. 5 and 6 are schematic diagrams showing the correspondence relationship between the azimuth angle and the vertical curve test when the pixel unit shown in FIGS. 5 and 6 is applied with the same driving voltage;
  • FIG. 8 is a schematic diagram showing a correspondence relationship between a driving voltage and a transmission coefficient applied when a pixel unit of a preferred embodiment of the present invention sets grooves of different depths;
  • FIG. 9 is a flow chart showing a method of manufacturing a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 10 is a schematic view showing deposition of a first electrode layer, an insulating layer, and a second electrode layer on a substrate in an embodiment of a method of fabricating a liquid crystal display panel of the present invention
  • FIG. 11 is a schematic view showing a photoresist layer applied to a second electrode layer in an embodiment of a method of fabricating a liquid crystal display panel of the present invention
  • FIG. 12 is a schematic view showing exposure of a photoresist layer in an embodiment of a method of fabricating a liquid crystal display panel of the present invention
  • FIG. 13 is a schematic view showing a first etching of a second electrode layer in an embodiment of a method of fabricating a liquid crystal display panel of the present invention
  • FIG. 14 is a schematic view showing a second etching of an insulating layer in an embodiment of a method of fabricating a liquid crystal display panel of the present invention
  • 15 is a schematic view showing the removal of a photoresist layer in an embodiment of a method of fabricating a liquid crystal display panel of the present invention.
  • FIG. 1 is a cross-sectional view showing the structure of a liquid crystal display panel in accordance with a preferred embodiment of the present invention.
  • the liquid crystal display panel 10 of the present embodiment includes a first substrate 11, a second substrate 12, a liquid crystal layer 13, and a plurality of pixel units (not shown).
  • the first substrate 11 and the second substrate 12 are relatively spaced apart, wherein the first substrate 11 is a TFT (Thin Film) Transistor, thin film transistor) array substrate, the first substrate 11 includes a transparent substrate and various wirings and pixel electrodes disposed on the transparent substrate, and the second substrate 12 is CF (color Filter, color filter) color film substrate.
  • TFT Thin Film
  • CF color Filter, color filter
  • the liquid crystal layer 13 is filled and sandwiched between the first substrate 11 and the second substrate 12.
  • the liquid crystal layer 13 preferably includes dielectric anisotropy (Dielectric).
  • Anisotropy is a negative liquid crystal molecule 131 and a plurality of reactive monomers 132 mixed in the liquid crystal molecules 131.
  • the liquid crystal molecules 131 are liquid crystal materials having a deflection orientation characteristic which is generated in a specific direction by application of a driving voltage, which achieves a different deflection orientation by a threshold value of an applied driving voltage.
  • the reactive monomer 132 is a polymerizable monomer including an acrylate resin monomer molecule, a methacrylate resin monomer molecule, a vinyl resin monomer molecule, a vinyloxy resin monomer molecule, and an epoxy resin monomer. Any combination of molecules and the like.
  • each pixel unit in the liquid crystal display panel 10 includes three pixels of R, G, and B, and the structure of each pixel unit is similar, one of the pixel units 20 will be described below as an example.
  • the pixel unit 20 of the present embodiment includes a liquid crystal layer 13 corresponding to a region, and a first electrode layer 21 and a second electrode layer 22 disposed on a side of the first substrate 11 facing the liquid crystal layer 13. And an insulating layer 23. among them:
  • the first electrode layer 21 is disposed adjacent to the first substrate 11, and the insulating layer 23 is sandwiched between the first electrode layer 21 and the second electrode layer 22 such that the first electrode layer 21 and the second electrode layer 22 are relatively spaced apart
  • the second electrode layer 22 is disposed adjacent to the liquid crystal layer 13.
  • the second electrode layer 22 of the present embodiment is provided with a (pixel) electrode pattern, and the region of the insulating layer 23 corresponding to the second electrode layer 22 where the electrode pattern is not provided is provided with grooves 221a, 221b, 221c, and 221d.
  • the electrode pattern includes a plurality of spaced strip structures 222a, 222b, 222c, 222d, and 222e, and each of the grooves is disposed between the adjacent two strip structures, that is, as shown in FIG.
  • the groove 221a is disposed between the strip structure 222a and the strip structure 222b
  • the groove 221b is disposed between the strip structure 222b and the strip structure 222c
  • the groove 221c is disposed between the strip structure 222c and the strip structure 222d
  • the groove 221d is disposed between the strip structure 222d and the strip structure 222e.
  • the pixel unit 20 corresponds to the display area of the liquid crystal display panel 10, and accordingly, the first electrode layer 21 is a common electrode, the second electrode layer 22 is a pixel electrode, and the electrode pattern disposed thereon is a pixel electrode. pattern. Further, the first electrode layer 21 and the second electrode layer 22 are both transparent electrode layers, and the manufacturing materials of the two electrodes may be the same or different, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like. Any combination of materials that are light transmissive and electrically conductive.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • a parasitic capacitance C is formed between the first electrode layer 21 and the second electrode layer 22, that is, a plurality of parasitism is formed between the pixel electrode pattern and the first electrode layer 21. Capacitor C. Further, the driving voltage causes a deflection electric field or an alignment electric field of the liquid crystal layer 13 to be formed between the electrode patterns (strip structures 222a, 222b, 222c, 222d, 222e) of the second electrode layer 22 and the first electrode layer 21.
  • the alignment electric field it is preferable to irradiate the first substrate 11 and the second substrate 12 with a light source of an ultraviolet light band, so that the reactive monomer 132 can be sequentially arranged according to the electric field caused by the given driving voltage, thereby completing the liquid crystal display panel.
  • the thickness of the insulating layer 23 of the portions of the grooves 221a, 221b, 221c, 221d is small, so that the deflection electric field generated by the driving voltage has a large electric field intensity component in the z-axis direction in the three-dimensional coordinate system. Therefore, the torsional power of the liquid crystal molecules 131 can be greatly increased, and the deflection angle of the liquid crystal molecules 131 can be increased, that is, the azimuth angle of the pixel unit 20 can be increased (Azimuth). Angle), thereby achieving a wide viewing angle, and improving the transmittance of the backlight, and reducing the aperture ratio of the liquid crystal display panel 10.
  • the display brightness of the pixel unit 20 is increased when the same driving voltage is applied, in other words, to achieve the same display brightness, the driving voltage to be applied in this embodiment is small, thereby saving power consumption. Thereby, the working time of the display terminal using the liquid crystal display panel 10 is improved.
  • the grooves 221a, 221b, 221c, and 221d have a depth of 0 to 6000 ⁇ ( ⁇ ) and cannot be 0 ⁇ .
  • the depths between the grooves 221a, 221b, 221c, and 221d may be the same or different.
  • the depths of the grooves 221a, 221b, 221c, and 221d are both 6000 angstroms, and compared with the case where no groove is provided (that is, the depth of the groove is 0 angstrom). Description:
  • the linear distance between the peaks and valleys of the curves L1 and L2 and the second electrode layer 22 indicates the corresponding transmittance, and it is known that the depth is set to 6000.
  • the pixel unit 20 of the grooves 221a, 221b, 221c, and 221d of the angstroms has a transmittance L2 corresponding to a transmittance L1 corresponding to a pixel unit having a depth of 0 of the groove.
  • the linear distance between the peaks and valleys of the curves L3 and L4 and the second electrode layer 22 indicates the corresponding transmittance
  • the set depth is
  • the pixel unit 20 of the 6000 ⁇ grooves 221a, 221b, 221c, and 221d has a transmittance L4 corresponding to a transmittance L3 corresponding to a pixel unit having a groove depth of 0.
  • the corresponding driving rate of the drive voltage of 3.0 volts is greater than the applied driving voltage of 2.0 volts.
  • the penetration rate is L1.
  • the curves A1, B1, and C1 represent the azimuth angles of the pixel units whose groove depth is 0 angstrom (azimuth). Angle) and vertical curve test (Vertical The relationship of the position, the curves A2, B3 and C3 represent the relationship between the azimuth corresponding to the pixel unit 20 of the groove depth of 6000 angstroms and the vertical curve test.
  • the azimuth angle of the liquid crystal molecules 131 of the pixel unit 20 of the present embodiment is increased compared with the pixel unit of the prior art, and the increase of the azimuth angle causes the brightness of the pixel unit 20 to increase, that is, To achieve the same brightness, the driving voltage to be applied by the pixel unit 20 of the present embodiment is small.
  • the curve V1 indicates the relationship between the driving voltage and the transmittance transmitted when the depth of the groove is 0 angstrom
  • the curve V2 indicates the depth of the grooves 221a, 221b, 221c, and 221d.
  • the curve V3 indicates the relationship between the driving voltage and the transmission coefficient when the depths of the grooves 221a, 221b, 221c, and 221d are both 4000 angstroms
  • the curve V4 indicates the groove 221a
  • the relationship between the driving voltage and the transmission coefficient when the depths of 221b, 221c, and 221d are both 6000 angstroms.
  • the initial voltage Vth when the liquid crystal layer 13 is driven and the operating voltage Vmax when the maximum brightness is reached are reduced, and the grooves 221a, 221b, 221c
  • the starting voltage Vth is 1.8 volts
  • the operating voltage Vmax is 5.5 volts
  • the starting voltage Vth is 1.5 volts
  • the operating voltage Vmax is 5 volts
  • the starting voltage Vth is 1.4 volts
  • the operating voltage Vmax is 4.5 volts
  • the depth of the grooves 221a, 221b, 221c, 221d is 6000 angstroms.
  • the starting voltage Vth was 1.3 volts and the operating voltage Vmax was 4.25 volts. That is, when the depth of the grooves 221a, 221b, 221c, 221d is increased from 0 angstroms to 6000 angstroms, the starting voltage Vth is lowered from 1.8 volts to 1.3 volts, and the operating voltage Vmax is lowered from 5.5 volts to 4.25 volts.
  • the depth of the grooves 221 a , 221 b , 221 c , and 221 d is larger, and the transmittance of the corresponding pixel unit 20 is higher, and the display brightness of the liquid crystal display panel 10 is higher.
  • the driving voltage to be applied by the pixel unit 20 of the present embodiment is much smaller than the driving voltage to be applied by the pixel unit of the prior art, thereby saving power consumption and improving the use of the liquid crystal display panel 10 compared with the prior art.
  • the operating time of the terminal is displayed, and the parasitic capacitance C formed when the driving voltage is applied to the first electrode layer 21 and the second electrode layer 22 can be reduced, and the thickness of the insulating layer 23 is not increased as compared with the prior art.
  • FIG. 9 is a flow chart showing a method of fabricating a liquid crystal display panel in accordance with a preferred embodiment of the present invention. As shown in FIG. 9, the manufacturing method of the liquid crystal display panel of this embodiment includes the following steps:
  • Step S101 depositing a first electrode layer, an insulating layer and a second electrode layer on the substrate in sequence.
  • the substrate 111 can be a glass substrate, a plastic substrate, or a flexible substrate.
  • the first electrode layer 112 is an indium tin oxide ITO glass layer, and silicon oxide, silicon nitride or a combination thereof may also be used.
  • the insulating layer 113 may be formed of a dielectric material such as a silicon nitride layer, a silicon oxide layer or silicon oxynitride, and deposited by chemical vapor deposition or other thin film techniques.
  • the second electrode layer 114 may be the same material or different material as the first electrode layer 112.
  • Step S102 coating a photoresist layer on the substrate on which the first electrode layer, the insulating layer and the second electrode layer are sequentially deposited.
  • the photoresist layer 115 is coated on the second electrode layer 114.
  • the first photomask process can be performed on the photoresist layer 115 by using an exposure technique based on a mask (ie, a photomask) to form an exposed portion D and not required for the photomask process.
  • the portion E is exposed, wherein the exposed portion D corresponds to a groove to be formed, and the unexposed portion E corresponds to an electrode pattern to be formed, that is, a plurality of spaced strip structures.
  • Step S103 performing a first etching on the second electrode layer not covered by the photoresist layer to form an electrode pattern on the second electrode layer, and exposing a surface of the insulating layer corresponding to the region not covered by the photoresist layer.
  • the first etching performed on the second electrode layer 114 not covered by the photoresist layer 115 is a wet etching using the photoresist layer 115 as an etch mask. Since the electrode pattern to be formed includes a plurality of strip structures spaced apart, the surface of the insulating layer 113 corresponding to the region (corresponding to the exposed portion D) that is not covered by the photoresist layer 115 is exposed after the first etching.
  • Step S104 performing a second etching on the exposed surface of the insulating layer, so that a region of the insulating layer corresponding to the second electrode layer where the electrode pattern is not formed forms a groove.
  • the second etching performed on the surface of the insulating layer 112 exposed by the photoresist layer 115 is dry etching using the photoresist layer 115 as an etch mask.
  • a plurality of grooves 116 are formed in a region corresponding to the exposed portion D, wherein the plurality of grooves 116 have a depth of 0 to 6000 angstroms and cannot be 0 angstroms. In addition, the depth between the plurality of grooves 116 may be the same or different.
  • Step S105 removing the photoresist layer.
  • the photoresist layer 115 remaining (corresponding to the unexposed portion E) is completely exposed by a conventional mask process, thereby removing the photoresist layer 115.
  • the array substrate produced by the method for fabricating a liquid crystal display panel of the present embodiment has the same structure as the pixel unit 20 of the embodiment shown in FIG. 2, and thus has the same technical effect.
  • the embodiment of the present invention is designed to provide a groove on the insulating layer sandwiched between the first electrode layer and the second electrode layer, and the groove corresponds to the region where the electrode pattern is not disposed on the second electrode layer,
  • the parasitic capacitance formed by the first electrode layer and the second electrode layer when the driving voltage is applied can be reduced, and the thickness of the insulating layer is not increased compared with the prior art, thereby reducing the driving voltage and saving compared to the prior art. Power consumption, thereby increasing the working time of the display terminal using the liquid crystal display panel.

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Abstract

一种液晶显示面板及其制造方法、阵列基板。该液晶显示面板的像素单元（20）包括：夹持于第一基板和第二基板之间的液晶层（13），以及设置于第一基板朝向液晶层（13）一侧的第一电极层（21）、第二电极层（22）和绝缘层（23），第一电极层（21）与第一基板相邻设置，绝缘层（23）夹持于第一电极层（21）和第二电极层（22）之间，第二电极层（22）上设置有电极图案，绝缘层（23）的对应第二电极层（22）未设置电极图案的区域设置有凹槽（221a）。通过上述方式，能够在确保显示画质的前提下降低液晶显示面板的驱动电压，节省功耗，从而提升使用该液晶显示面板的显示终端的工作时间。

Description

液晶显示面板及其制造方法、阵列基板
【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及基于横向电场模式的液晶显示技术领域，特别是涉及一种液晶显示面板及其阵列基板，以及该液晶显示面板的制造方法。
【背景技术】
与基于TN（Twisted Nematic，扭曲向外型）以及MVA（Multi-domain Vertical Alignment，多象限垂直配向型）等纵向电场模式的液晶显示面板不同，采用IPS（In-plane switching，平面转换型）等横向电场模式的液晶显示面板，仅在一个基板或衬底上设置有电极。
例如，作为IPS模式衍生出来的FFS（Fringe Field Switching，边缘电场切换型）模式的液晶显示面板，其像素电极的下方间隔设置一层电极。施加驱动电压时产生的边界电场使得液晶分子在电极表层内部发生偏转，从而提高背光的穿透，实现大视角显示。然而，施加驱动电压时像素电极与其下方间隔设置的层电极之间必然会形成寄生电容，如果寄生电容过大则会影响液晶显示面板的像素单元的充电率，进而极大地影响液晶显示面板的显示效果与画质。
当前，业界普遍通过增加位于像素电极与该下层电极之间的绝缘层的厚度，减小寄生电容。但是，绝缘层厚度的增加必然导致驱动电压的增大，而驱动电压的增大则必然会增加驱动电路的功耗，从而降低使用该液晶显示面板的显示终端的工作时间。
【发明内容】
有鉴于此，本发明实施例所要解决的技术问题是提供一种液晶显示面板及其制造方法、阵列基板，能够降低驱动电压，节省功耗，提升使用该液晶显示面板的显示终端的工作时间。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示面板，具有相对间隔设置的第一基板和第二基板以及多个像素单元，每一像素单元包括：夹持于第一基板和第二基板之间的液晶层，以及设置于第一基板朝向液晶层一侧的第一电极层、第二电极层和绝缘层，第一电极层与第一基板相邻设置，绝缘层夹持于第一电极层和第二电极层之间；其中，第二电极层上设置有电极图案，绝缘层的对应第二电极层未设置电极图案的区域设置有凹槽，其中电极图案为多个间隔设置的条状结构，绝缘层对应相邻两个条状结构之间的区域设置有凹槽，第一电极层包括公共电极，第二电极层包括像素电极，电极图案包括像素电极图案。
其中，凹槽的深度为0~6000埃。
其中，液晶显示面板的第一基板为阵列基板。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示面板，具有相对间隔设置的第一基板和第二基板以及多个像素单元，每一像素单元包括：夹持于第一基板和第二基板之间的液晶层，以及设置于第一基板朝向液晶层一侧的第一电极层、第二电极层和绝缘层，第一电极层与第一基板相邻设置，绝缘层夹持于第一电极层和第二电极层之间；其中，第二电极层上设置有电极图案，绝缘层的对应第二电极层未设置电极图案的区域设置有凹槽。
其中，电极图案为多个间隔设置的条状结构，绝缘层对应相邻两个条状结构之间的区域设置有凹槽。
其中，凹槽的深度为0~6000埃。
其中，第一电极层包括公共电极，第二电极层包括像素电极，电极图案包括像素电极图案。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示面板的制造方法，包括：在依次沉积有第一电极层、绝缘层以及第二电极层的基体上涂布一光阻层；对未被光阻层遮盖的第二电极层进行第一次蚀刻，以在第二电极层上形成电极图案，并且使绝缘层的对应未被光阻层遮盖的区域的表面曝露；对绝缘层的表面曝露的区域进行第二次蚀刻，以使绝缘层的对应第二电极层未设置电极图案的区域形成凹槽；移除光阻层。
其中，第一次蚀刻为湿法刻蚀，第二次蚀刻为干法刻蚀。
其中，形成的电极图案为多个间隔设置的条状结构，绝缘层对应相邻两个条状结构之间的区域设置凹槽。
其中，形成的凹槽的深度为0~6000埃。
其中，第一电极层包括公共电极，第二电极层包括像素电极，电极图案包括像素电极图案。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种阵列基板，用于具有液晶层以及多个像素单元的液晶显示面板，阵列基板包括：基体以及设置于基体朝向液晶层一侧的第一电极层、第二电极层和绝缘层，第一电极层与基体相邻设置，绝缘层夹持于第一电极层和第二电极层之间；其中，第二电极层上设置有电极图案，绝缘层的对应第二电极层未设置电极图案的区域设置有凹槽。
其中，电极图案为多个间隔设置的条状结构，绝缘层对应相邻两个条状结构之间的区域设置有凹槽，凹槽的深度为0~6000埃。
其中，第一电极层包括公共电极，第二电极层包括像素电极，电极图案包括像素电极图案。
通过上述技术方案，本发明实施例产生的有益效果是：本发明实施例通过在夹持于第一电极层和第二电极层之间的绝缘层上设置凹槽，且凹槽对应于第二电极层未设置电极图案的区域，不仅能够减小第一电极层和第二电极层在施加驱动电压时形成的寄生电容，而且没有增加绝缘层的厚度，相比较于现有技术能够降低驱动电压，节省功耗，从而提升使用该液晶显示面板的显示终端的工作时间。
【附图说明】
图1是本发明优选实施例的液晶显示面板的结构剖视图；
图2是本发明优选实施例的像素单元的结构剖视图；
图3是现有技术中未设置凹槽的像素单元在施加一驱动电压时对应的穿透率的示意图；
图4是本发明优选实施例的像素单元在施加一驱动电压时对应的穿透率的示意图；
图5是现有技术中未设置凹槽的像素单元在施加另一驱动电压时对应的穿透率的示意图；
图6是本发明优选实施例的像素单元在施加另一驱动电压时对应的穿透率的示意图；
图7是图5和图6所示像素单元在施加相同的驱动电压时方位角与竖曲线测试的对应关系的示意图；
图8是本发明优选实施例的像素单元在设置不同深度的凹槽时施加的驱动电压与透射系数的对应关系的示意图；
图9是本发明优选实施例的液晶显示面板的制造方法的流程图；
图10是本发明液晶显示面板的制造方法的实施例中在基体上沉积第一电极层、绝缘层以及第二电极层的示意图；
图11是本发明液晶显示面板的制造方法的实施例中在第二电极层涂布光阻层的示意图；
图12是本发明液晶显示面板的制造方法的实施例中对光阻层进行曝光的示意图；
图13是本发明液晶显示面板的制造方法的实施例中对第二电极层进行第一次刻蚀的示意图；
图14是本发明液晶显示面板的制造方法的实施例中对绝缘层进行第二次刻蚀的示意图；
图15是本发明液晶显示面板的制造方法的实施例中去除光阻层的示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，本发明以下所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
图1是本发明优选实施例的液晶显示面板的结构剖视图。请参阅图1所示，本实施例的液晶显示面板10包括第一基板11、第二基板12、液晶层13以及多个像素单元（未图示）。
第一基板11和第二基板12相对间隔设置，其中第一基板11为TFT（Thin Film Transistor，薄膜晶体管）阵列基板，第一基板11包括透明基体以及设置于透明基体上的各种配线和像素电极等，第二基板12为CF（color filter，彩色滤光片）彩膜基板。
液晶层13填充夹持于第一基板11和第二基板12之间，本实施例优选液晶层13包括介电各向异性（Dielectric Anisotropy）为负的液晶分子131以及混合于液晶分子131之中的多个反应单体132。其中，液晶分子131为具有通过施加驱动电压即在特定方向上发生偏转取向特性的液晶材料，其通过施加的驱动电压的阀值以实现不同的偏转取向。反应单体132为聚合性单体，其包括丙烯酸酯类树脂单体分子、甲基丙烯酸酯类树脂单体分子、乙烯基树脂单体分子、乙烯氧基树脂单体分子、环氧树脂单体分子等的任意组合。
图2是本发明优选实施例的像素单元的结构剖视图。鉴于液晶显示面板10中每个像素单元包括R、G、B三个像素，且每个像素单元的结构是类似的，下文以其中一个像素单元20为例进行说明。
请结合图1和图2所示，本实施例的像素单元20包括对应区域的液晶层13，以及设置于第一基板11朝向液晶层13一侧的第一电极层21、第二电极层22和绝缘层23。其中：
第一电极层21与第一基板11相邻设置，绝缘层23夹持于第一电极层21和第二电极层22之间，以使得第一电极层21和第二电极层22相对间隔设置，第二电极层22与液晶层13相邻设置。
本实施例的第二电极层22上设置有（像素）电极图案，绝缘层23的对应第二电极层22未设置电极图案的区域设置有凹槽221a、221b、221c、221d。具体而言，优选电极图案包括多个间隔设置的条状结构222a、222b、222c、222d、222e，且每一凹槽对应设置于相邻两个条状结构之间，即图2中所示的凹槽221a设置于条状结构222a与条状结构222b之间，凹槽221b设置于条状结构222b与条状结构222c之间，凹槽221c设置于条状结构222c与条状结构222d之间，凹槽221d设置于条状结构222d与条状结构222e之间。
在本实施例中，像素单元20对应液晶显示面板10的显示区域，因此对应地，第一电极层21为公共电极，第二电极层22为像素电极，其上设置的电极图案即为像素电极图案。并且，第一电极层21和第二电极层22均为透明电极层，两者的制造材料可以相同也可以不相同，例如为氧化铟锡（ITO）、氧化铟锌（IZO）或者是其他同时具有透光性和导电性的材料的任意组合。
当由第一基板11一侧接通并施加驱动电压时，第一电极层21和第二电极层22之间形成寄生电容C，即像素电极图案与第一电极层21之间形成多个寄生电容C。并且，驱动电压使得第二电极层22的电极图案（条状结构222a、222b、222c、222d、222e）与第一电极层21之间形成液晶层13的偏转电场或配向电场。
在形成配向电场时，优选对第一基板11和第二基板12施以紫外光波段的光源照射，使反应单体132能按照给予的驱动电压所造成的电场依序排列，进而完成液晶显示面板10中液晶分子131的配向及偏转。具体而言，当施加驱动电压并施以紫外光波段的光照射时，反应单体132产生聚合作用以形成用以取向液晶分子131的高分子聚合物，并使液晶分子131相对于第一基板11形成85~95度的预倾角。
在形成偏转电场时，凹槽221a、221b、221c、221d部分的绝缘层23的厚度较小，使得驱动电压所产生的偏转电场在三维坐标系中的z轴方向有较大的电场强度分量，因此可以大幅提升液晶分子131的扭转动力，增大液晶分子131的偏转角度，即增大像素单元20的方位角（Azimuth Angle），从而实现广视角，并且提升背光的透过率，降低液晶显示面板10的开口率。另外，与现有技术相比，在施加相同的驱动电压时像素单元20的显示亮度提升，换言之，要达到相同的显示亮度，本实施例所要施加的驱动电压较小，因此能够节省功耗，从而提升使用液晶显示面板10的显示终端的工作时间。
本实施例优选凹槽221a、221b、221c、221d的深度为0~6000埃（Å），且不能为0埃。另外，凹槽221a、221b、221c、221d之间的深度可以相同，也可以不相同。下面进一步结合附图3~图8所示，以凹槽221a、221b、221c、221d的深度均为6000埃为例，并与不设置凹槽（即凹槽的深度为0埃）相比较进行说明：
请参阅图3和图4，当施加相同的驱动电压为2.0伏时，曲线L1和L2的峰谷与第二电极层22之间的直线距离表示对应的穿透率，可知设置有深度为6000埃的凹槽221a、221b、221c、221d的像素单元20对应的穿透率L2大于凹槽的深度为0的像素单元对应的穿透率L1。
同理，请参阅图5和图6，当施加相同的驱动电压3.0伏时，曲线L3和L4的峰谷与第二电极层22之间的直线距离表示对应的穿透率，可知设置深度为6000埃的凹槽221a、221b、221c、221d的像素单元20对应的穿透率L4大于凹槽的深度为0的像素单元对应的穿透率L3。
请参阅图4和图6，当设置的凹槽221a、221b、221c、221d的深度相同均为6000埃时，施加的驱动电压3.0伏时对应的穿透率L4大于施加的驱动电压2.0伏时对应的穿透率L2。
同理，请参阅图3和图5所示，当设置的凹槽的深度相同均为0埃时，施加的驱动电压3.0伏时对应的穿透率L3大于施加的驱动电压2.0伏时对应的穿透率L1。
另外，请参阅图5、图6和图7所示，当施加相同的驱动电压为3.0伏时，曲线A1、B1和C1表示凹槽的深度为0埃的像素单元对应的方位角（azimuth angle）与竖曲线测试（Vertical Location）的关系，曲线A2、B3和C3表示凹槽的深度为6000埃的像素单元20对应的方位角与竖曲线测试的关系。可知，施加相同的驱动电压时，与现有技术的像素单元相比，本实施例的像素单元20的液晶分子131的方位角增大，方位角的增大使得像素单元20的亮度提升，即，实现相同的亮度，本实施例像素单元20所要施加的驱动电压较小。
进一步地，请参阅图8所示，曲线V1表示凹槽的深度均为0埃时施加的驱动电压与透射系数（transmittance）的关系，曲线V2表示凹槽221a、221b、221c、221d的深度均为2000埃时施加的驱动电压与透射系数的关系，曲线V3表示凹槽221a、221b、221c、221d的深度均为4000埃时施加的驱动电压与透射系数的关系，曲线V4表示凹槽221a、221b、221c、221d的深度均为6000埃时施加的驱动电压与透射系数的关系。由此可知，随着凹槽221a、221b、221c、221d的深度增加，液晶层13驱动时的起始电压Vth和达到最大亮度时的操作电压Vmax均减小，并且凹槽221a、221b、221c、221d的深度为0埃时，起始电压Vth为1.8伏，操作电压Vmax为5.5伏；凹槽221a、221b、221c、221d的深度为2000埃时，起始电压Vth为1.5伏，操作电压Vmax为5伏；凹槽221a、221b、221c、221d的深度为4000埃时，起始电压Vth为1.4伏，操作电压Vmax为4.5伏；凹槽221a、221b、221c、221d的深度为6000埃时，起始电压Vth为1.3伏，操作电压Vmax为4.25伏。也就是说，凹槽221a、221b、221c、221d的深度由0埃增加到6000埃时，起始电压Vth由1.8伏降低到1.3伏，操作电压Vmax由5.5伏降低到4.25伏。
结合图4~图8可知，施加相同的驱动电压时，凹槽221a、221b、221c、221d的深度越大，其对应的像素单元20的穿透率越高，液晶显示面板10的显示亮度越高；并且，凹槽221a、221b、221c、221d的深度相同时，施加的驱动电压越大，对应的像素单元20的穿透率越高，液晶显示面板10的显示亮度越高，即，实现相同的亮度，本实施例的像素单元20所要施加的驱动电压远远小于现有技术的像素单元所要施加的驱动电压，从而相比较于现有技术能够节省功耗，提升使用液晶显示面板10的显示终端的工作时间，另外还能够减小第一电极层21和第二电极层22在施加驱动电压时形成的寄生电容C，且相比较于现有技术也没有增加绝缘层23的厚度。
图9是本发明优选实施例的液晶显示面板的制造方法的流程图。如图9所示，本实施例的液晶显示面板的制造方法包括如下步骤：
步骤S101：依序在基体上沉积第一电极层、绝缘层以及第二电极层。
如图10所示，基体111可为玻璃基体、塑料基体或可挠式基体。第一电极层112为氧化铟锡ITO玻璃层，也可以采用氧化硅、氮化硅或上述组合。绝缘层113可由氮化硅层、氧化硅层或氮氧化硅等介电材料构成，由化学气相沉积或其它薄膜技术沉积形成。第二电极层114可以与第一电极层112相同的材质也可以不相同。
步骤S102：在依次沉积有第一电极层、绝缘层以及第二电极层的基体上涂布一光阻层。
该光阻层115涂布于第二电极层114上。如图11和图12所示，对光阻层115可采用基于掩模板（即俗称的光罩）的曝光技术进行第一次光罩制程，以形成光罩制程所需要的曝光部分D和未曝光部分E，其中曝光部分D对应所要形成的凹槽，未曝光部分E对应所要形成的电极图案，即多个间隔设置的条状结构。
步骤S103：对未被光阻层遮盖的第二电极层进行第一次蚀刻，以在第二电极层上形成电极图案，并且使绝缘层的对应未被光阻层遮盖的区域的表面曝露。
如图13所示，以光阻层115为刻蚀屏蔽，对未被光阻层115遮盖的第二电极层114进行的第一次蚀刻为湿法刻蚀。由于所要形成的电极图案包括多个间隔设置的条状结构，因此第一次蚀刻之后绝缘层113的对应未被光阻层115遮盖的（对应曝光部分D）区域的表面曝露。
步骤S104：对绝缘层的表面曝露的区域进行第二次蚀刻，以使绝缘层的对应第二电极层未设置电极图案的区域形成凹槽。
如图14所示，以光阻层115为刻蚀屏蔽，对未被光阻层115遮盖的绝缘层112的表面曝露的（对应曝光部分D）区域进行的第二次蚀刻为干法刻蚀。并且，在对应曝光部分D的区域形成多个凹槽116，其中多个凹槽116的深度为0~6000埃，且不能为0埃。另外，多个凹槽116之间的深度可以相同，也可以不相同。
步骤S105：移除光阻层。
如图15所示，采用普通光罩制程，对剩余（对应未曝光部分E）的光阻层115进行完全曝光，从而将光阻层115移除。
本实施例的液晶显示面板的制造方法制得的阵列基板，其像素单元具有与图2所示实施例的像素单元20相同的结构，因此具有与其相同的技术效果。
综上所述，本发明实施例设计在夹持于第一电极层和第二电极层之间的绝缘层上设置凹槽，且凹槽对应于第二电极层未设置电极图案的区域，不仅能够减小第一电极层和第二电极层在施加驱动电压时形成的寄生电容，而且相比较于现有技术也没有增加绝缘层的厚度，从而相比较于现有技术能够降低驱动电压，节省功耗，从而提升使用该液晶显示面板的显示终端的工作时间。
再次说明，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种液晶显示面板，具有相对间隔设置的第一基板和第二基板以及多个像素单元，其特征在于，每一所述像素单元包括：
    夹持于所述第一基板和所述第二基板之间的液晶层，以及设置于所述第一基板朝向所述液晶层一侧的第一电极层、第二电极层和绝缘层，所述第一电极层与所述第一基板相邻设置，所述绝缘层夹持于所述第一电极层和所述第二电极层之间；
    其中，所述第二电极层上设置有电极图案，所述绝缘层的对应所述第二电极层未设置所述电极图案的区域设置有凹槽，其中所述电极图案为多个间隔设置的条状结构，所述绝缘层对应相邻两个所述条状结构之间的区域设置有所述凹槽，所述第一电极层包括公共电极，所述第二电极层包括像素电极，所述电极图案包括像素电极图案。
  2. 根据权利要求1所述的液晶显示面板，其特征在于，所述凹槽的深度为0~6000埃。
  3. 根据权利要求1所述的液晶显示面板，其特征在于，所述液晶显示面板的所述第一基板为阵列基板。
  4. 一种液晶显示面板，具有相对间隔设置的第一基板和第二基板以及多个像素单元，其特征在于，每一所述像素单元包括：
    夹持于所述第一基板和所述第二基板之间的液晶层，以及设置于所述第一基板朝向所述液晶层一侧的第一电极层、第二电极层和绝缘层，所述第一电极层与所述第一基板相邻设置，所述绝缘层夹持于所述第一电极层和所述第二电极层之间；
    其中，所述第二电极层上设置有电极图案，所述绝缘层的对应所述第二电极层未设置所述电极图案的区域设置有凹槽。
  5. 根据权利要求4所述的液晶显示面板，其特征在于，所述电极图案为多个间隔设置的条状结构，所述绝缘层对应相邻两个所述条状结构之间的区域设置有所述凹槽。
  6. 根据权利要求5所述的液晶显示面板，其特征在于，所述凹槽的深度为0~6000埃。
  7. 根据权利要求4所述的液晶显示面板，其特征在于，所述第一电极层包括公共电极，所述第二电极层包括像素电极，所述电极图案包括像素电极图案。
  8. 一种液晶显示面板的制造方法，其特征在于，所述制造方法包括：
    在依次沉积有第一电极层、绝缘层以及第二电极层的基体上涂布一光阻层；
    对未被所述光阻层遮盖的所述第二电极层进行第一次蚀刻，以在所述第二电极层上形成电极图案，并且使所述绝缘层的对应未被所述光阻层遮盖的区域的表面曝露；
    对所述绝缘层的表面曝露的区域进行第二次蚀刻，以使所述绝缘层的对应所述第二电极层未设置所述电极图案的区域形成凹槽；
    移除所述光阻层。
  9. 根据权利要求8所述的制造方法，其特征在于，所述第一次蚀刻为湿法刻蚀，所述第二次蚀刻为干法刻蚀。
  10. 根据权利要求8所述的制造方法，其特征在于，形成的所述电极图案为多个间隔设置的条状结构，所述绝缘层对应相邻两个所述条状结构之间的区域设置所述凹槽。
  11. 根据权利要求10所述的制造方法，其特征在于，形成的所述凹槽的深度为0~6000埃。
  12. 根据权利要求8所述的制造方法，其特征在于，所述第一电极层包括公共电极，所述第二电极层包括像素电极，所述电极图案包括像素电极图案。
  13. 一种阵列基板，用于具有液晶层以及多个像素单元的液晶显示面板，其特征在于，所述阵列基板包括：
    基体以及设置于所述基体朝向所述液晶层一侧的第一电极层、第二电极层和绝缘层，所述第一电极层与所述基体相邻设置，所述绝缘层夹持于所述第一电极层和所述第二电极层之间；
    其中，所述第二电极层上设置有电极图案，所述绝缘层的对应所述第二电极层未设置所述电极图案的区域设置有凹槽。
  14. 根据权利要求13所述的阵列基板，其特征在于，所述电极图案为多个间隔设置的条状结构，所述绝缘层对应相邻两个所述条状结构之间的区域设置有所述凹槽，所述凹槽的深度为0~6000埃。
  15. 根据权利要求13所述的阵列基板，其特征在于，所述第一电极层包括公共电极，所述第二电极层包括像素电极，所述电极图案包括像素电极图案。
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