CN103064224A - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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CN103064224A
CN103064224A CN2013100312901A CN201310031290A CN103064224A CN 103064224 A CN103064224 A CN 103064224A CN 2013100312901 A CN2013100312901 A CN 2013100312901A CN 201310031290 A CN201310031290 A CN 201310031290A CN 103064224 A CN103064224 A CN 103064224A
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林允植
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BOE Technology Group Co Ltd
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Abstract

本发明涉及显示技术领域，提供了一种阵列基板及显示装置。该阵列基板包括：依次设置在基板上的薄膜晶体管、像素电极层、第一钝化层、数据线、第二钝化层和公共电极层；其中，所述第二钝化层仅形成在所述数据线与公共电极之间。本发明中，通过调整进入像素电极层与公共电极层之间的第一钝化层的厚度，提高了像素电极的寄生电容值，维持VHR在一定标准之上，在动态降低驱动频率时也不会因VHR过低而造成屏幕闪烁。由于本发明中不存在控制寄生电容的器件和线路，因而对开口率没有影响，保证了显示效果。最后，在本发明中，通过第二钝化层将数据线与公共电极分隔开一定距离，使两者间的电容影响尽可能减小，保证了数据线的正常工作。

Description

阵列基板及显示装置
技术领域
本发明涉及显示技术领域，提供了一种阵列基板及显示装置。
背景技术
现有技术中，为满足对动态影像的显示需求，普通LCD（LiquidCrystal Display，液晶显示）器件的帧频率通常在60Hz以上（即每秒刷新60帧以上）。较高的帧频率使得驱动电路必须为LCD面板的像素单元提供高频驱动信号，为保证有效的高频驱动，电路中需要使用较高的驱动电压，长期使用高频高压的驱动信号除可能损害器件之外，也会使显示器件功耗较大，不利于节能环保。
为了实现低电力驱动，现有技术中出现了根据显示内容来调整驱动频率的技术。具体地，在显示动态画面时，采用正常的60Hz以上频率进行驱动；而当显示静止画面时，将驱动频率相应降低。上述方式可以通过改动驱动电路来实现，但是在实际的使用过程中，由于低电压和低频率造成像素单元的电压保持率VHR（Voltage Holding Ratio，指像素单元充电后，随时间变化电压降低幅度的比值）较低，使得屏幕闪烁（Flicker）情况变得严重。
考虑到VHR的通用计算公式为：
VHR = 100 % × ( 1 - I leak × t frame C st + C LC )
其中Ileak表示电路中的漏电流、tframe表示一帧画面的显示时间、Cst表示像素电极的存储电容、CLC表示液晶电容。当帧频率变化时，首先发生变化的就是tframe，比如帧频率在60Hz时，tframe为16.7ms，当帧频率降至30Hz时，tframe会变至33.4ms。可以看出，如果要维持VHR，只需相应地动态调整(Cst+CLC)的值即可。
如图1所示，现有技术中，采用了动态调整存储电容Cst的像素结构。其中，薄膜晶体管TFT101为驱动TFT，公共电极线103与像素电极105之间形成寄生电容Cst1。当显示静止状态的画面时，降低LCD的驱动频率，并在普通的像素内驱动专用的寄生电容TFT102，即打开TFT102，使电极104与公共电极线103连通，增加像素电极产生寄生电容区域的面积，电极104与像素电极105之间形成寄生电容Cst2，从而提高寄生电容Cst=Cst1+Cst2，使VHR维持在正常水平。但是，现有技术的上述应用中，如果要根据频率调整寄生电容大小，必须在电路中加入控制可变Cst的TFT102并为相关驱动提供专门的信号线布线，在像素区域中增加的这些部件明显会影响背光的透过率，从而会使面板的开口率降低，影响显示效果。
发明内容
（一）要解决的技术问题
针对上述缺点，本发明为了解决现有技术中动态可变Cst会降低开口率的问题，提供了一种阵列基板及显示装置。
（二）技术方案
为解决上述问题，本发明提供了一种阵列基板，包括：设置在基板之上的薄膜晶体管、由所述薄膜晶体管驱动的像素电极层、数据线、第一钝化层和公共电极层，所述数据线用于驱动薄膜晶体管，所述第一钝化层位于所述像素电极层和公共电极层之间，还包括：设置在所述公共电极层和数据线间且位于数据线对应区域的第二钝化层。
其中，所述第一钝化层位于所述薄膜晶体管、像素电极层和数据线之上，第二钝化层设置在所述第一钝化层之上且位于数据线对应区域上方，所述公共电极层位于所述第一钝化层和第二钝化层之上。
其中，所述公共电极层直接覆盖于基板之上，第一钝化层位于公共电极层之上，所述薄膜晶体管、像素电极层和数据线位于第一钝化层之上，第二钝化层设置在数据线对应区域的数据线和公共电极层之间。
其中，所述第一钝化层的厚度小于
Figure BDA00002783241300031
其中，所述第二钝化层的厚度
Figure BDA00002783241300032
其中，所述第二钝化层由树脂或者硅的氮化物形成。
本发明还提供了一种显示装置，包括上述任一项所述的阵列基板。
（三）有益效果
在本发明的技术方案中，通过调整像素电极层与公共电极层之间的第一钝化层的厚度，提高了像素电极和公共电极的存储电容值，从而维持了像素单元的VHR在一定标准之上，因而在动态降低LCD的驱动频率时也不会因VHR过低而造成屏幕闪烁。由于本发明中不存在控制存储电容的器件和线路，因而对开口率没有影响，保证了显示效果。最后，在本发明中，通过第二钝化层将数据线与公共电极分隔开一定距离，使两者间的电容影响尽可能减小，保证了数据线的正常工作。
附图说明
图1为现有技术中动态增大存储电容的阵列基板的剖面结构图；
图2为本发明一个实施例中阵列基板的剖面结构图；
图3为本发明另一个实施例中阵列基板的剖面结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明中，为了在不影响开口率的情况下保证VHR尽可能的大，基板中未增加额外的控制TFT及信号线。在本发明的实施例中，考虑到VHR主要受寄生电容的影响，要使VHR尽可能大，尽量提高寄生电容值即可。在此情况下，如图2所示的阵列基板剖面图中，本发明以H-ADS（ADvanced Super Dimension Switch）模式的阵列基板结构（也可以是FFS模式的阵列基板）为例进行说明，该阵列基板包括：设置在基板201上的薄膜晶体管202、由薄膜晶体管202驱动的像素电极层203、栅线（图中未示出）、数据线206（和薄膜晶体管的源漏电极同时形成）、第一钝化层204、第二钝化层207和公共电极层205。本实施例中，公共电极层205由条状的公共电极组成且位于像素电极层203上方。栅线用于驱动薄膜晶体管202的通断，数据线206的信号通过薄膜晶体管202传输至像素电极层203，第一钝化层204位于薄膜晶体管202和像素电极层203之上。第二钝化层207设置在第一钝化层204之上且位于数据线206对应区域上方。
优选地，所述基板为玻璃基板；所述像素电极层及所述公共电极层是透明氧化物薄膜，如ITO（氧化铟锡）、IZO（氧化铟锌）等。所述像素电极层及所述公共电极层的图案及位置按现有的H-ADS模式设置，即所述公共电极覆盖于数据线之上，屏蔽数据线与所述像素电极之间的电场，从而提高开口率。所述TFT包括栅极Gate、源极S和漏极D，所述TFT的源极S电连接至像素电极，所述TFT的栅极Gate与栅线电连接。
如图2的阵列基板结构，为了得到大的存储电容，可以将所述第一钝化层204厚度根据需要的存储电容值的情况进行预先设置，即对像素电极层203与公共电极层205之间的第一钝化层204的厚度，根据所期望的频率，将其从目前的
Figure BDA00002783241300041
对应进行变更。从而使像素电极和公共电极的存储电容变大；但是，在第一钝化层204厚度变化时，由于数据线206与公共电极层205之间距离变小，数据线206与公共电极层205间会形成一个较大的寄生电容，影响了数据线206的正常工作。在此情况下，为了减小数据线206与公共电极层205间的寄生电容，在数据线206与公共电极层205之间设置了第二钝化层207，通过第二钝化层207将数据线206与公共电极层205分隔开一定距离，使两者间的电容影响尽可能减小，这样，形成在所述像素电极和所述公共电极之间形成存储电容的大小，可以通过控制第一钝化层的厚度实现，而控制公共电极与数据线之间的寄生电容可以通过控制第二钝化层实现，且第一钝化层和第二钝化层均是可以单独控制其厚度的。设计人员可以根据具体产品的性能进行个性化设计。优选地，所述第二钝化层由树脂或者硅的氮化物（SiNx）形成。
对于其他典型的ADS型阵列基板结构，例如：如图3所示的结构，公共电极层305直接覆盖于基板301之上，第一钝化层304位于公共电极层305之上，所述薄膜晶体管302（顶栅结构）和像素电极层303位于第一钝化层304之上。第二钝化层307设置在第一钝化层304之上且位于数据线306对应区域下方（当然第二钝化层307也设置在数据线306对应区域的第一钝化层304和公共电极层305之间）。
本发明还提供了一种显示装置，包括上述的阵列基板，所述显示装置可以为：液晶面板、电子纸、OLED面板、等离子体面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
在本发明的技术方案中，通过调整进入像素电极层与公共电极层之间的第一钝化层的厚度，提高了像素电极的寄生电容值，从而维持了像素单元的VHR在一定标准之上，因而在动态降低LCD的驱动频率时也不会因VHR过低而造成屏幕闪烁。由于本发明中不存在控制寄生电容的器件和线路，因而对开口率没有影响，保证了显示效果。最后，在本发明中，通过第二钝化层将数据线与公共电极分隔开一定距离，使两者间的电容影响尽可能减小，保证了数据线的正常工作。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (7)

1.一种阵列基板，包括：设置在基板之上的薄膜晶体管、由所述薄膜晶体管驱动的像素电极层、数据线、第一钝化层和公共电极层，所述数据线用于驱动薄膜晶体管，所述第一钝化层位于所述像素电极层和公共电极层之间，其特征在于，还包括：设置在所述公共电极层和数据线间且位于数据线对应区域的第二钝化层。
2.根据权利要求1所述的阵列基板，其特征在于，所述第一钝化层位于所述薄膜晶体管、像素电极层和数据线之上，第二钝化层设置在所述第一钝化层之上且位于数据线对应区域上方，所述公共电极层位于所述第一钝化层和第二钝化层之上。
3.根据权利要求1所述的阵列基板，其特征在于，所述公共电极层直接覆盖于基板之上，第一钝化层位于公共电极层之上，所述薄膜晶体管、像素电极层和数据线位于第一钝化层之上，第二钝化层设置在数据线对应区域的数据线和公共电极层之间。
4.根据权利要求1~3中任一项所述的阵列基板，其特征在于，所述第一钝化层的厚度小于
Figure FDA00002783241200011
5.根据权利要求1~3中任一项所述的阵列基板，其特征在于，所述第二钝化层的厚度
Figure FDA00002783241200012
6.根据权利要求1~3中任一项所述的阵列基板，其特征在于，所述第二钝化层由树脂或者硅的氮化物形成。
7.一种显示装置，其特征在于，所述显示装置包括：如权利要求1~6中任一项所述的阵列基板。
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