WO2016006032A1 - オペアンプ回路及びバイアス電流供給方法 - Google Patents
オペアンプ回路及びバイアス電流供給方法 Download PDFInfo
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- WO2016006032A1 WO2016006032A1 PCT/JP2014/068146 JP2014068146W WO2016006032A1 WO 2016006032 A1 WO2016006032 A1 WO 2016006032A1 JP 2014068146 W JP2014068146 W JP 2014068146W WO 2016006032 A1 WO2016006032 A1 WO 2016006032A1
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- differential pair
- field effect
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- operational amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
- H03F1/0233—Continuous control by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
- H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
- H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
- H03F3/3022—CMOS common source output SEPP amplifiers
- H03F3/3028—CMOS common source output SEPP amplifiers with symmetrical driving of the end stage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/4521—Complementary long tailed pairs having parallel inputs and being supplied in parallel
- H03F3/45219—Folded cascode stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/261—Amplifier which being suitable for instrumentation applications
Definitions
- the present invention relates to an operational amplifier circuit, and more particularly to a technique of an operational amplifier circuit having a plurality of differential pairs.
- a so-called fully differential amplifier circuit has been used that improves S / N by obtaining a signal amplitude that is twice the power supply voltage by maximizing the signal amplitude through signal differentiation.
- the output impedance of a sensor element that captures natural world information such as light, acceleration, and sound as an analog signal into a circuit is generally high (several M ⁇ or more). For this reason, in order to connect to such a sensor element, it is necessary to connect a non-inverting amplifier circuit capable of obtaining a high input impedance of several G ⁇ or more.
- FIG. 15 shows a conventional single-ended operational amplifier circuit.
- the instrumentation amplifier (instrumentation) shown in FIG. 14 configured by using two single-ended operational amplifiers shown in FIG. ⁇ Amplifier, Non-Patent Document 1) Configuration and configurations shown as symbols of operational amplifiers in FIGS. 10 and 11 (Non-Patent Document 2).
- the operation of the conventional differential amplifier circuit (for example, FIG. 14) will be briefly described.
- the potentials of the inverting input terminal and the inverting input terminal are the same as VINP. Since the distinction is clear, no particular explanation will be given.
- G is a voltage gain of the amplifier circuit. For simplification, the gain of the operational amplifier is infinite.
- the instrumentation amplifier includes two single-ended operational amplifiers shown in FIG. 15 and a resistor network including resistors R100, R200, and R201.
- R200 R201 (3)
- a differential output can be obtained by the equation (2).
- a configuration using a double differential pair type operational amplifier exhibits the same operation.
- 10 and 11 show symbols of the double differential pair type operational amplifier.
- G 1 (5)
- R100 R101 (6)
- R200 R201 (7)
- G (R100 + R200) / R100 (8) It becomes.
- the instrumentation amplifier shown in FIG. 10 unlike the inverting amplifier circuit in which the input terminal of the operational amplifier is virtually grounded and becomes a constant voltage, a signal is input to the input terminal of the operational amplifier in the non-inverting amplifier circuit. There is no voltage.
- the signal amplitude may be wide.
- the differential pair may be turned off as will be described later.
- PMOS differential pairs D30 and D40 are connected in parallel to the two NMOS differential pairs D10 and D20, respectively.
- at least one of the NMOS type differential pair and the PMOS type differential pair operates even with a wide range of input voltages in the range from the ground potential to the power supply potential. Therefore, according to this configuration (rail-to-rail), a differential amplification operation is possible in the entire range from the ground potential to the power supply potential.
- a PMOS differential pair D30 is connected in parallel to the NMOS differential pair D10.
- This configuration is also a rail-to-rail configuration, and differential signal amplification operation is possible in the entire range from the ground potential to the power supply potential.
- the mutual conductance of the NMOS type differential pair is gmn
- the mutual conductance of the PMOS type differential pair is Assuming gmp
- gmdiff gmn + gmp (10) Will decrease.
- the mutual conductance of the differential pair of the operational amplifier varies greatly depending on the input voltage. Further, when any one of the differential pairs is turned OFF, the current flowing through the active loads AL101 (FIG. 15) and AL100 (FIG. 13) also changes, and the slew rate degradation and the bandwidth degradation of the operational amplifier occur.
- Patent Document 1 in order to suppress the influence of fluctuations in the operating state of the differential pair due to the input voltage on the circuit characteristics, a transistor for securing a current path when the differential pair is turned off is provided in parallel for the single-ended operational amplifier. Connecting. A configuration has been proposed in which the current flowing through the active load does not change even when the input voltage is such that the differential pair is turned off by this transistor.
- Patent Document 2 when a transistor through which a spare current flows is connected in parallel to a differential pair, and one of the NMOS type differential pair and the PMOS type differential pair is turned off, the difference that is turned on. There has been proposed a configuration in which the current of the dynamic pair is increased to suppress the variation in the mutual conductance of the entire differential pair.
- Patent Document 2 it is possible to suppress fluctuations in mutual conductance in a state where any one of the differential pairs is turned off. However, if all the differential pairs are turned on, There is a problem that the current consumption increases by the current flowing through the transistor.
- the operational amplifier circuit of the present invention is A first differential pair composed of two field effect transistors having the same channel type of the N channel type and the P channel type, and two field effect transistors different in channel type from the first differential pair, A first parallel portion including a second differential pair connected in parallel to the first differential pair; A third differential pair consisting of two field effect transistors of the same channel type as the first differential pair, and two field effect transistors of the same channel type as the second differential pair, A second parallel portion including a fourth differential pair connected in parallel to the third differential pair; A first current source for supplying a bias current to the first differential pair and the third differential pair; One second current source for supplying a bias current to the second differential pair and the fourth differential pair is provided.
- the present invention it is possible to keep the current flowing through the active load constant and suppress fluctuations in mutual conductance without increasing the power consumption of the circuit and increasing the circuit scale.
- FIG. 3 is a diagram of the first embodiment and is a schematic diagram of a circuit of an operational amplifier circuit 1000; 3 is a diagram of the first embodiment and is a circuit diagram illustrating a specific example of an operational amplifier circuit 1000.
- FIG. FIG. 11 is a diagram of the first embodiment, and is a circuit diagram in the case where an operational amplifier circuit 1000 is applied to the differential amplifier circuit of FIG. 10.
- FIG. 5 is a diagram of a second embodiment and is a schematic diagram of a circuit of a differential amplifier circuit 2001;
- FIG. 6 is a diagram of a second embodiment and is a circuit diagram illustrating a specific example of a differential amplifier circuit 2001;
- FIG. 10 is a diagram of Embodiment 3, and is a schematic diagram of a circuit of a differential amplifier circuit 3001.
- FIG. 5 is a diagram of a second embodiment and is a schematic diagram of a circuit of a differential amplifier circuit 2001
- FIG. 6 is a diagram of a second embodiment and is a circuit diagram illustrating a specific example
- FIG. 9 is a diagram of Embodiment 3, and is a circuit diagram illustrating a specific example of a differential amplifier circuit 3001.
- FIG. 5 is a diagram of a fourth embodiment, and is a schematic diagram of a circuit of a differential amplifier circuit 4001.
- FIG. 5 is a diagram of Embodiment 4, and is a circuit diagram illustrating a specific example of a differential amplifier circuit 4001.
- the circuit diagram which shows another example of the differential amplifier circuit using an operational amplifier symbol.
- the figure which shows a prior art and is a circuit diagram which shows a double differential operational amplifier. It is a figure which shows a prior art and is a circuit diagram showing an example of the conventional instrumentation amplifier. It is a figure which shows a prior art and is a circuit diagram showing the specific example of the operational amplifier for comprising the conventional instrumentation amplifier.
- an NMOS transistor N11 that is an N-channel MOS transistor is referred to as a transistor N11.
- a PMOS transistor P31 which is a P-channel MOS transistor is referred to as a transistor P31. The same applies to other NMOS transistors and PMOS transistors.
- FIG. 1 is a circuit diagram of an operational amplifier circuit 1000 constituting a differential amplifier circuit.
- FIG. 2 is a circuit diagram showing a specific example of the operational amplifier circuit 1000.
- FIG. 2 is a diagram describing a circuit configuration of the active load AL100 of FIG.
- the operational amplifier circuit 1000 can be applied to the differential amplifier circuit shown in FIGS. That is, the operational amplifier circuit 1000 may be incorporated in the double differential operational amplifier A100 shown as the operational amplifier symbol in FIGS.
- the operational amplifier circuit 1000 includes a differential pair D10 (first differential pair), a differential pair D20 (third differential pair), a differential pair D30 (second differential pair), and a differential pair D40 (first differential pair). 4 differential pairs).
- the differential pair D10, D20, D30, and D40 as in the case of FIG. 13, the differential pair D30 is connected in parallel to the differential pair D10, and the differential pair D40 is connected in parallel to the differential pair D20.
- the differential pair D10 and the differential pair D30 constitute a first parallel part PC101
- the differential pair D20 and the differential pair D40 constitute a second parallel part PC102.
- the differential pair D10 includes transistors N11 and N12. Transistors N11 and N12 have their gate terminals connected to a first inverting input terminal VI1M arranged as an inverting input terminal and a first non-inverting input terminal VI1P arranged as a non-inverting input terminal, respectively.
- the differential pair D20 includes transistors N21 and N22. Transistors N21 and N22 have their gate terminals connected to a second inverting input terminal VI2M arranged as an inverting input terminal and a second non-inverting input terminal VI2P arranged as a non-inverting input terminal, respectively.
- the differential pair D30 includes transistors P31 and P32.
- Transistors P31 and P32 have gate terminals connected to a first inverting input terminal VI1M arranged as an inverting input terminal and a first non-inverting input terminal VI1P arranged as a non-inverting input terminal, respectively.
- the differential pair D40 includes transistors P41 and P42.
- Transistors P41 and P42 have their gate terminals connected to a second inverting input terminal VI2M arranged as an inverting input terminal and a second non-inverting input terminal VI2P arranged as a non-inverting input terminal, respectively.
- the differential pair D10 and D20 is supplied with a bias current from one transistor N10 (first current source). As shown in FIG. 1, the source terminals of the transistor N11 and the transistor N12 are connected to each other. The source terminals of the transistors N21 and N22 are connected to each other. The source terminals of the differential pair D10 and the differential pair D20 are short-circuited.
- the transistor N10 which is a current source, supplies a bias current from the drain to the source terminals of the shorted differential pair D10 and the differential pair D20.
- the transistors N10 and N100 are NMOS transistors that constitute a current mirror for bias current of the NMOS type differential pair D10 and D20.
- a current source IR1 is connected to the drain of the transistor N100.
- the source of the transistor N100 is grounded.
- a connection path that connects the drain and gate of the transistor N100 is formed, and the middle of this connection path is connected to the gate of the transistor N10.
- the source of the transistor N10 is grounded.
- the drains of the transistors N11 and N21 are short-circuited, and these drains are connected to the first input terminal T1 of the active load AL100. Further, in the differential pair D10 and D20, the drains of the transistors N12 and N22 are short-circuited, and these drains are connected to the second input terminal T2 of the active load AL100.
- the differential pair D30 and D40 is supplied with a bias current from one transistor P30 (second current source). As shown in FIG. 1, the source terminals of the transistor P31 and the transistor P32 are connected to each other. The source terminals of the transistor P41 and the transistor P42 are connected to each other. The source terminals of the differential pair D30 and the differential pair D40 are short-circuited.
- the transistor P30 which is a current source, supplies a bias current from the drain to the source terminals of the shorted differential pair D30 and the differential pair D40.
- the transistors P30 and P101 are PMOS transistors that constitute a current mirror for bias current of the PMOS differential pair D30 and D40.
- a current source IR2 is connected to the drain of the transistor P101.
- a connection path that connects the drain and gate of the transistor P101 is formed, and the middle of the connection path is connected to the gate of the transistor P30.
- the drains are short-circuited, and these drains are connected to the third input terminal T3 of the active load AL100. Further, in the transistors P32 and P42, the drains are short-circuited, and these drains are connected to the fourth input terminal T4 of the active load AL100.
- the active load AL100 has an inverting output terminal VOM and a non-inverting output terminal VOP.
- the active load AL100 has the following in accordance with voltages input to the first inverting input terminal VI1M, the first non-inverting input terminal VI1P, the second inverting input terminal VI2M, and the second non-inverting input terminal VI2P.
- the differential output voltage VOUT expressed by the equation is output.
- VOUT AP ⁇ VP + AM ⁇ VM (12) here,
- VOUT VOP-VOM (13)
- VP VI1P-VI1M (14)
- VM VI2P-VI2M (15) It is.
- a bias current is supplied from the transistor N10 which is one current source to the differential pair D10 and D20, and a transistor P30 which is one current source to the differential pair D30 and D40.
- a bias current is supplied from With this configuration, when a voltage at which one of the differential pair D10 and D20 or one of the differential pair D30 and D40 is OFF is input from the first inverting input terminal VI1M or the like, the other is not OFF. Bias current flows through the differential pair. For example, when the differential pair D10 of the differential pairs D10 and D20 is turned off, all the bias currents of the transistor N10 flow to the differential pair D20 that is not turned off.
- FIG. 2 shows an embodiment of the active load AL100 using an NMOS transistor and a PMOS transistor.
- the active load AL100 adds the signal currents obtained from the respective differential pairs, and converts the added current into a voltage signal.
- the active load AL100 includes cascode-connected transistors P51, P52, P61, and P62, and cascode-connected transistors N71, N72, N81, and N82.
- the cascode-connected transistors P51, P52, P61, and P62 constitute a first load unit L101.
- the cascode-connected transistors N71, N72, N81, and N82 constitute a second load unit L102.
- Transistors P51 and P52, and transistors P61 and P62 are supplied with gate voltages V3 and V4 by transistors P50 and P60 biased by current source IR3 and resistor R1, respectively.
- Transistors N71 and N72 are supplied with gate voltage V5 by transistor N70 biased by current source IR4.
- the gate control voltage V6 is supplied to the transistors N81 and N82 by the common mode feedback circuit CMFB.
- the common mode feedback circuit CMFB monitors the output common mode voltage of the output terminals VOP and VOM, and outputs the gate control voltage V6 so that the output common mode voltage becomes equal to the predetermined input voltage VCOM.
- the operational amplifier circuit 1000 shown in FIGS. 1 and 2 can be applied to the differential amplifier circuit shown in FIG.
- FIG. 3 is a circuit diagram when the operational amplifier circuit 1000 is applied to the differential amplifier circuit shown in FIG.
- the non-inverting input voltage VINP and the inverting input voltage VINM are input to the first non-inverting input terminal VI1P and the second inverting input terminal VI2M.
- the non-inverted output voltage VOP and the inverted output voltage VOM are the non-inverted output VOUTP and the inverted output VOUTM of the differential amplifier circuit, respectively.
- the difference between the non-inverted output voltage VOP and the inverted output voltage VOM is output as the differential output voltage VOUT. Further, the non-inverting output voltage VOUTP (VOP in FIG. 2) is fed back to the first inverting input terminal VI1M, and the inverting output signal VOUTM (VOM in FIG. 2) is fed back to the second non-inverting input terminal VI2P.
- the circuit of FIG. 3 supplies a bias current from the transistor N10, which is one current source, to the differential pair D10 and D20, and bias current from the transistor P30, which is one current source, to the differential pair D30 and D40.
- Supply Conventionally, the circuit of FIG. 13 has been incorporated in the differential amplifier circuit of FIG. That is, in the conventional differential amplifier circuit of FIG. 10, the differential pairs D10, D20, D30, and D40 are biased from the current sources of the transistors N10, N20, P30, and P40 as shown in FIG. Current was being supplied. In the case of this configuration, when one input voltage becomes the power supply potential and the other input potential becomes the ground potential, the P channel and the N channel of the two P channel differential pairs and the two N channel differential pairs.
- a bias current is supplied from one current source to the differential pairs D10 and D20, and a bias current is supplied from one current source to the differential pairs D30 and D40.
- the input voltage VINP is the power supply potential
- the input voltage VINM is the ground potential
- the differential pair D20 and the differential pair D30 are turned off, as shown in FIG.
- the supplied bias current flows to the output stage via the differential pair D10
- the bias current supplied from the current source transistor P30 flows to the output stage via the differential pair D40. Therefore, even when the differential pair D20 and the differential pair D30 are turned off, the circuit current is kept constant, and fluctuations in frequency characteristics can be suppressed.
- FIG. 11 shows a non-inverting amplifier circuit using a resistor network. With the configuration of FIG. 11, it is possible to amplify a signal.
- a differential signal is input as a non-inverted signal and an inverted signal from the first non-inverted input terminal VI1P (VINP) and the second inverted input terminal VI2M (VINM), respectively.
- the voltage difference between the non-inverting output terminal (VOP) and the inverting output terminal (VOM) of the operational amplifier circuit 1000 is taken out as a differential output signal.
- the output of the inverting output terminal VOM (VOUTM) is fed back to the second non-inverting input terminal VI2P, and the output of the non-inverting output terminal VOP (VOUTP) is fed back to the first inverting input terminal VI1M.
- the resistor 200 (first resistor element) is arranged in a path that feeds back from the non-inverting output terminal VOP to the first inverting input terminal VI1M.
- the resistor R201 (second resistor element) is disposed in a path that feeds back from the inverting output terminal VOM to the second non-inverting input terminal VI2P.
- the resistor R100 is arranged on a path connecting from the first common voltage terminal VCOM arranged as a common voltage terminal to the resistor R200 and the first inverting input terminal VI1M.
- the resistor R101 (fourth resistor element) is arranged on a path connected from the second common voltage terminal VCOM arranged as a common voltage terminal to the resistor R201 and the second non-inverting input terminal VI2P.
- the operational amplifier circuit 1000 in FIG. 1 may be applied to the differential amplifier circuit shown in FIG.
- the operational amplifier circuit in FIG. 1 is assumed to be built in the operational amplifier A100 in FIG.
- differential signals are input as a non-inverted signal and an inverted signal from the first non-inverted input terminal VI1P (VINP) and the second inverted input terminal VI2M (VINM), respectively.
- the voltage difference between the non-inverting output terminal (VOP) and the inverting output terminal (VOM) of the operational amplifier circuit 1000 is taken out as a differential output signal.
- the output of the inverting output terminal VOM (VOUTM) is fed back to the second non-inverting input terminal VI2P, and the output of the non-inverting output terminal VOP (VOUTP) is fed back to the first inverting input terminal VI1M.
- the resistor R100 is disposed in a path connecting the first inverting input terminal VI1M and the second non-inverting input terminal VI2P.
- the resistor R200 is disposed in a path that feeds back from the non-inverting output terminal VOP to the first inverting input terminal VI1M.
- the resistor R201 is disposed in a path that feeds back from the inverting output terminal VOM to the second non-inverting input terminal VI2P.
- the gate control voltage V6 of the common mode feedback circuit CMFB is applied to the gate voltages of the transistors N81 and N82.
- the present invention is not limited to the transistors N81 and N82, and may be configured to be provided to one or more of the transistors P51 and P52, the transistor N10, and the transistor P30.
- the transistors P61 and P62 and the transistors N71 and N72 may have a gain boost cascode configuration in which the source potential is monitored and the gate voltage is controlled so that the source potential becomes constant. Further, the transistors N10 and P30 of the current source may be cascode connected.
- the bias current is supplied from one current source to the differential pair D10 and D20 and the differential pair D30 and D40, so that the current flowing through the active load is kept constant. Therefore, it is possible to suppress fluctuations in mutual conductance.
- FIG. 4 is a schematic diagram showing a differential amplifier circuit 2001 (op-amp circuit) according to the second embodiment.
- FIG. 5 is a circuit diagram illustrating a specific example of the differential amplifier circuit 2001 according to the second embodiment.
- FIG. 5 is a diagram showing a circuit configuration of the active load AL100 and the output amplifier OA100 of FIG.
- the differential amplifier circuit 2001 of the second embodiment has a configuration in which a voltage amplifier circuit (output amplifier OA100) is connected to the output section of the active load AL100 of the operational amplifier circuit 1000 of the first embodiment.
- a voltage amplifier circuit output amplifier OA100
- FIG. 5 shows a configuration in which an OA 100 that is a voltage amplification circuit is connected to the circuit configuration of the operational amplifier circuit 1000 in FIG.
- the inverting output terminal T5 (output voltage VM) and the non-inverting output terminal T6 (output voltage VP) of the active load AL100 are connected to the inverting output terminal and the non-inverting input terminal of the output amplifier OA100, respectively.
- the output amplifier OA100 includes transistors NO11, NO12, PO21, and PO22.
- Output amplifier OA100 has NO11 that receives and amplifies output voltage VM of active load AL100 at its gate, and NO12 that receives and amplifies output voltage VP at its gate.
- the output amplifier OA100 includes PO21 and PO22 that receive a predetermined voltage at the gate and supply a bias current to the transistors NO11 and NO12.
- the output amplifier OA100 is a common source amplifier circuit.
- the configuration of FIG. 5 to which the output amplifier OA100 is connected improves the gain of the differential amplifier circuit 2001 and enables a more accurate amplification operation. Further, in the configuration of FIG. 5, as described in the first embodiment, since the variation of the mutual conductance of the differential pair due to the input voltage is suppressed, the capacitance value used for the phase compensation network is set to be smaller than the conventional one. can do. Therefore, a reduction in bandwidth due to phase compensation is suppressed, and a wider bandwidth is possible.
- the output amplifier OA100 is configured as a class A amplifier circuit with transistors NO11 and NO12 biased by transistors PO21 and PO22 connected in a current mirror, but this configuration is an example.
- a configuration of the output amplifier OA100 it is needless to say that a class A amplifier circuit using a PMOS transistor may be used, or a class AB amplifier circuit may be used.
- the output amplifier OA100 is a single-stage amplifier circuit, but it may be a multistage connection type.
- FIG. 6 is a schematic diagram of a differential amplifier circuit 3001 (an operational amplifier circuit) according to the third embodiment.
- FIG. 7 shows a specific example of the circuit of the differential amplifier circuit 3001 of the third embodiment.
- FIG. 7 is a diagram showing a circuit configuration of the active loads AL200 and AL201 of FIG. In the third embodiment, only the difference from the first embodiment will be described.
- the third embodiment is different from the first embodiment in that the active load AL100 of the first embodiment includes an active load AL200 for inverting output (first active load) and an active load AL201 for non-inverting output (first). 2 active loads).
- the active load AL200 adds the signal currents obtained by the differential pairs D10 and D30, and converts the added signal current into a voltage signal.
- the active load AL201 adds the signal currents obtained by the differential pairs D20 and D40, and converts the added signal current into a voltage signal.
- the drains of the transistors N11, N12, P31, and P32 of the differential pair D10 and D30 are connected to the active load AL200.
- the drains of the transistors N21, N22, P41, and P42 of the differential pair D20 and D40 are connected to the active load AL201.
- the active load AL200 includes cascode-connected transistors P51, P52, P61, and P62 and cascode-connected N71, N72, M81, and N82.
- the active load AL201 includes cascode-connected P53, P54, P63, and P64 and cascode-connected N73, N74, N83, and N84.
- the active load AL200 has a first connection part L201 and a second connection part L202.
- the active load AL201 has a third connection portion L203 and a fourth connection portion L204.
- the first connection L201 is connected to the drains of the transistors N11 and N12 of the differential pair D10
- the second connection L202 is connected to the drains of the transistors P31 and P32 of the differential pair D30.
- the third connection L203 is connected to the drains of the transistors N21 and N22 of the differential pair D20
- the fourth connection L204 is connected to the drains of the transistors P41 and P42 of the differential pair D40.
- the third embodiment has a configuration of two single-ended operational amplifiers that share only the current sources of the differential pairs D10 and D20 and the differential pairs D30 and D40. 6 and 7, even in the configuration of the conventional instrumentation amplifier in FIG. 14, it is possible to suppress the fluctuation of the mutual conductance of the operational amplifier due to the input voltage, and it is necessary in the first and second embodiments.
- the circuit design can be facilitated by eliminating the common mode feedback circuit.
- FIG. 8 is a schematic diagram of a differential amplifier circuit 4001 (an operational amplifier circuit) according to the fourth embodiment.
- FIG. 9 shows a specific example of the differential amplifier circuit 4001 of the fourth embodiment.
- FIG. 9 is a diagram showing a circuit configuration of the active loads AL200 and AL201, output amplifiers OA200 and OA201 of FIG. In the fourth embodiment, only the difference from the third embodiment will be described.
- voltage amplification circuits (output amplifier OA200 and output amplifier OA201) are connected to the output sections of active loads AL200 and AL201 described in the third embodiment, respectively. That is, the output amplifiers OA200 and OA201 are arranged between the active load AL200 and the output terminal VOP and between the active load AL201 and the output terminal VOM, respectively.
- the output amplifier OA200 (first voltage amplification circuit) is configured by transistors NO11 and PO12
- the output amplifier OA201 (second voltage amplification circuit) is configured by transistors NO21 and PO22. Yes.
- the output amplifier OA200 is connected to the output terminal T7 of the active load AL200, and the output amplifier OA201 is connected to the output terminal T8 of the active load AL201.
- the output amplifier OA200 amplifies the voltage output from the output terminal T7, and the output amplifier OA201 amplifies the voltage output from the output terminal T8.
- the output amplifier OA200 is a common source amplifier circuit having NO11 for receiving and amplifying the output voltage of the output terminal T7 of the active load AL200 at the gate and PO12 for receiving a predetermined voltage at the gate and supplying a bias current to N011. is there.
- the output amplifier OA201 is a common-source amplifier circuit having NO21 that receives and amplifies the output voltage of the output terminal T8 of the active load AL201 at the gate and PO22 that receives a predetermined voltage at the gate and supplies a bias current to the NO21. is there.
- the configuration of FIG. 9 improves the gain as a differential amplifier circuit and enables a more accurate amplification operation. Further, in the configuration of FIG. 9, as described in the first embodiment, since the variation in the mutual conductance of the differential pair due to the input voltage is suppressed, the capacitance value used for the phase compensation network should be set smaller than the conventional one. Can do. Therefore, a reduction in bandwidth due to phase compensation is suppressed, and a wider bandwidth is possible.
- the output amplifier OA200 and the output amplifier OA201 which are voltage amplification circuits, are configured as a class A amplification circuit composed of transistors NO11 and NO21 biased by transistors PO12 and PO22 that are current mirror connected, respectively. It is. It goes without saying that the output amplifier OA200 and the output amplifier OA201 may be configured as a class A amplifier circuit using PMOS transistors, or may be a class AB amplifier circuit. In FIG. 9, the voltage amplifier circuit is a single-stage amplifier circuit, but it may be a multistage connection type.
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Abstract
Description
VIN=VINP-VINM (1)
VINに対する差動出力電圧を、
VOUT=G・VIN=VOUTP-VOUTM (2)
とする。
ここで、Gは増幅回路の電圧利得である。尚、簡略化のため、オペアンプの利得は無限大とする。
R200=R201 (3)
とすると、その利得Gは、
G=(R100+2・R200)/R100 (4)
となり、式(2)により差動出力が得られる。
図10、図11は、2重差動対型オペアンプの記号を示す。
図10に対しては、
G=1 (5)
また、図11に対しては、
R100=R101 (6)
R200=R201 (7)
とすると、
G=(R100+R200)/R100 (8)
となる。
gmdiff=gmn+gmp (9)
となる。
しかし、たとえばグランド電位付近の電圧が入力された場合、NMOS型差動対がOFFし、動作できなくなることでgmn≒0となり、
gmdiff≒gmp (10)
に減少してしまう。
gmdiff≒gmn (11)
となる。
Nチャネル型とPチャネル型とのうちチャネル型を同じくする2つの電界効果トランジスタからなる第1の差動対と、前記第1の差動対と異なるチャネル型の2つの電界効果トランジスタからなり、前記第1の差動対に並列に接続される第2の差動対とを含む第1の並列部と、
前記第1の差動対と同一のチャネル型の2つの電界効果トランジスタからなる第3の差動対と、前記第2の差動対と同一のチャネル型の2つの電界効果トランジスタからなり、前記第3の差動対に並列に接続される第4の差動対とを含む第2の並列部と、
前記第1の差動対と前記第3の差動対とにバイアス電流を供給する一つの第1の電流源と、
前記第2の差動対と前記第4の差動対とにバイアス電流を供給する一つの第2の電流源と
を備えたことを特徴とする。
図1は、差動増幅回路を構成するオペアンプ回路1000の回路図である。
図2は、オペアンプ回路1000の具体例を示す回路図である。図2は図1の能動負荷AL100の回路構成を記載した図である。後述するが、オペアンプ回路1000は、図10、図11、図12に示す差動増幅回路に適用できる。つまり、図10、図11、図12でオペアンプ記号として示した2重差動型オペアンプA100には、オペアンプ回路1000が組み込まれてもよい。
オペアンプ回路1000は、差動対D10(第1の差動対)、差動対D20(第3の差動対)、差動対D30(第2の差動対)、差動対D40(第4の差動対)を備える。差動対D10、D20、D30,D40は、図13の場合と同様に、差動対D10に対し差動対D30が並列に接続し、差動対D20に対し差動対D40が並列に接続する。差動対D10と差動対D30とは第1の並列部PC101を構成し、差動対D20と差動対D40とは第2の並列部PC102を構成する。
(1)差動対D10は、トランジスタN11、N12からなる。トランジスタN11、N12は、それぞれ、反転入力端子として配置された第1の反転入力端子VI1M、非反転入力端子として配置された第1の非反転入力端子VI1Pに、ゲート端子が接続されている。
(2)差動対D20は、トランジスタN21、N22からなる。トランジスタN21、N22は、それぞれ、反転入力端子として配置された第2の反転入力端子VI2M、非反転入力端子として配置された第2の非反転入力端子VI2Pに、ゲート端子が接続されている。
(3)差動対D30は、トランジスタP31、P32からなる。トランジスタP31、P32は、それぞれ、反転入力端子として配置された第1の反転入力端子VI1M、非反転入力端子として配置された第1の非反転入力端子VI1Pに、ゲート端子が接続されている。
(4)差動対D40は、トランジスタP41、P42からなる。トランジスタP41、P42は、それぞれ、反転入力端子として配置された第2の反転入力端子VI2M、非反転入力端子として配置された第2の非反転入力端子VI2Pに、ゲート端子が接続されている。
差動対D10及びD20は、1つのトランジスタN10(第1の電流源)からバイアス電流が供給される。図1のように、トランジスタN11とトランジスタN12とのソース端子どうしは接続されている。トランジスタN21とトランジスタN22とのソース端子どうしも接続されている。差動対D10と差動対D20のソース端子どうしはショートされている。電流源であるトランジスタN10は、ショートされた差動対D10と差動対D20とのソース端子に、ドレインからバイアス電流を供給する。
トランジスタN10、N100は、NMOS型の差動対D10、D20のバイアス電流用のカレントミラーを構成するNMOSトランジスタである。トランジスタN100のドレインに電流源IR1が接続する。トランジスタN100のソースは接地されている。トランジスタN100のドレインとゲートとを接続する接続経路が形成され、この接続経路の途中とトランジスタN10のゲートとが接続される。トランジスタN10のソースは接地されている。
差動対D10及びD20は、トランジスタN11及びN21のドレインがショートされており、これらのドレインは、能動負荷AL100の第1の入力端子T1に接続される。更に、差動対D10及びD20では、トランジスタN12及びN22のドレインがショートされており、これらのドレインは、能動負荷AL100の第2の入力端子T2に接続される。
差動対D30及びD40は、1つのトランジスタP30(第2の電流源)からバイアス電流が供給される。図1のように、トランジスタP31とトランジスタP32とのソース端子どうしは接続されている。トランジスタP41とトランジスタP42とのソース端子どうしも接続されている。差動対D30と差動対D40のソース端子どうしはショートされている。電流源であるトランジスタP30は、ショートされた差動対D30と差動対D40とのソース端子に、ドレインからバイアス電流を供給する。
トランジスタP30、P101は、PMOS型の差動対D30、D40のバイアス電流用のカレントミラーを構成するPMOSトランジスタである。トランジスタP101のドレインに電流源IR2が接続する。トランジスタP101のドレインとゲートとを接続する接続経路が形成され、この接続経路の途中とトランジスタP30のゲートとが接続される。
また、トランジスタP31及びP41では、ドレインがショートされて、これらのドレインは、能動負荷AL100の第3の入力端子T3に接続される。更に、トランジスタP32及びP42では、ドレインがショートされて、これらのドレインは、能動負荷AL100の第4の入力端子T4に接続される。
VOUT=AP・VP+AM・VM (12)
ここで、
VOUT=VOP-VOM (13)
VP=VI1P-VI1M (14)
VM=VI2P-VI2M (15)
である。
更に、差動対D10、D20、D30、D40の相互コンダクタンスをgm10、gm20、gm30、gm40とおき、
gmP=gm10+gm30 (16)
gmM=gm20+gm40 (17)
と定義する。この場合、式(12)において、電圧利得AP及びAMは、
AP=gmP・Zout (18)
AM=gmM・Zout (19)
と表される。
尚、式(18)、式(19)のZoutは、能動負荷AL100の、電流・電圧変換ノードにおける出力インピーダンスである。
gmP=gm10+gm30
のうちgm10=0となったとしても、トランジスタN10のすべてのバイアス電流が差動対D20に流れるので、
式(17)において、
gmM=gm20+gm40
のうち、gm20が増大する。
よって、式(12)の
VOUT=AP・VP+AM・VM
におけるVOUTの変動を抑制できる。また回路電流は一定に保たれるので周波数特性の変動を抑えることができる。
能動負荷AL100は、カスコード接続されたトランジスタP51、P52、P61、P62、及びカスコード接続されたトランジスタN71、N72、N81、N82で構成される。カスコード接続されたトランジスタP51、P52、P61、P62は、第1の負荷部L101を構成する。カスコード接続されたトランジスタN71、N72、N81、N82は、第2の負荷部L102を構成する。トランジスタP51とP52、トランジスタP61とP62は、それぞれ、電流源IR3によりバイアスされたトランジスタP50、P60、抵抗R1により、ゲート電圧V3及びV4が供給される。トランジスタN71とN72とは、電流源IR4によりバイアスされたトランジスタN70により、ゲート電圧V5が供給される。トランジスタN81とN82とは、ゲート制御電圧V6が、コモンモード・フィードバック回路CMFBにより供給される。コモンモード・フィードバック回路CMFBは、出力端子VOP及びVOMの出力コモンモード電圧をモニタし、出力コモンモード電圧が所定の入力電圧VCOMと等しくなるようゲート制御電圧V6を出力する。
図1、図2に示すオペアンプ回路1000を図10に示す差動増幅回路に適用することができる。
図3は、オペアンプ回路1000を図10に示す差動増幅回路に適用する場合の回路図である。図3に示す差動増幅回路は、非反転入力電圧VINP及び反転入力電圧VINMが、第1の非反転入力端子VI1P及び第2の反転入力端子VI2Mに入力される。非反転出力電圧VOP及び反転出力電圧VOMは、それぞれ、差動増幅回路の非反転出力VOUTP及び反転出力VOUTMとする。また、差動増幅回路では、非反転出力電圧VOPと反転出力電圧VOMとの差分が、差動出力電圧VOUTとして出力される。更に非反転出力電圧VOUTP(図2のVOP)は第1の反転入力端子VI1Mに帰還され、反転出力信号VOUTM(図2のVOM)は、第2の非反転入力端子VI2Pに帰還される。
その場合、VI1PとVI1M、VI2PとVI2Mが、それぞれイマジナリ・ショートされて同電位となる。
出力電圧として、
VOUT=VOUTP-VOUTM=VINP-VINM (20)
が得られる。すなわち、オペアンプ回路1000を適用した図3の差動増幅回路は、差動信号に対する電圧バッファとして動作する。図10はボルテージフォロワの場合を示す。
また、図1のオペアンプ回路1000は、図11の差動増幅回路に適用してもよい。図11は、抵抗ネットワークを用いた非反転増幅回路である。図11の構成により、信号を増幅することが可能である。
また、図1のオペアンプ回路1000は、図12に示す差動増幅回路に適用してもよい。図1のオペアンプ回路は図12のオペアンプA100に内蔵されているものとする。
R200=R201 (21)
とすると、
式(2)における利得Gは、
G=(R100+2・R200)/R100 (22)
となり、コモン電圧VCOMを用いず、より簡素な構成で増幅回路を構成することが可能である。
図4、図5を参照して実施の形態2を説明する。
図4は、実施の形態2の差動増幅回路2001(オペアンプ回路)を示す概略図である。
図5は、実施の形態2の差動増幅回路2001の具体例を示す回路図である。図5は図4の能動負荷AL100、出力アンプOA100の回路構成を示す図である。
実施の形態2の差動増幅回路2001は、実施の形態1のオペアンプ回路1000の能動負荷AL100の出力部に、電圧増幅回路(出力アンプOA100)を接続した構成である。
図6、図7を参照して実施の形態3を説明する。
図6は、実施の形態3の差動増幅回路3001(オペアンプ回路)の概略図である。
図7は、実施の形態3の差動増幅回路3001の回路の具体例を示す。図7は図6の能動負荷AL200、AL201の回路構成を示す図である。実施の形態3では、実施の形態1との差分にのみ注目し説明を行う。
図6、図7の構成により、図14の従来の計装アンプの構成においても、入力電圧によるオペアンプの相互コンダクタンスの変動を抑制することが可能になるとともに、実施の形態1及び2で必要とされるコモンモード・フィードバック回路を不用とすることで回路設計の容易化を図ることが可能である。
図8、図9を参照して実施の形態4を説明する。
図8は、実施の形態4の差動増幅回路4001(オペアンプ回路)の概略図である。
図9は、実施の形態4の差動増幅回路4001の具体例を示す。図9は図8の能動負荷AL200、AL201,出力アンプOA200、OA201の回路構成を示す図である。実施の形態4では、実施の形態3との差分にのみ注目し説明を行う。
Claims (15)
- Nチャネル型とPチャネル型とのうちチャネル型を同じくする2つの電界効果トランジスタからなる第1の差動対と、前記第1の差動対と異なるチャネル型の2つの電界効果トランジスタからなり、前記第1の差動対に並列に接続される第2の差動対とを含む第1の並列部と、
前記第1の差動対と同一のチャネル型の2つの電界効果トランジスタからなる第3の差動対と、前記第2の差動対と同一のチャネル型の2つの電界効果トランジスタからなり、前記第3の差動対に並列に接続される第4の差動対とを含む第2の並列部と、
前記第1の差動対と前記第3の差動対とにバイアス電流を供給する一つの第1の電流源と、
前記第2の差動対と前記第4の差動対とにバイアス電流を供給する一つの第2の電流源と
を備えたことを特徴とするオペアンプ回路。 - 前記第1の差動対は、
2つの前記電界効果トランジスタのソース端子どうしが短絡され、
前記第3の差動対は、
2つの前記電界効果トランジスタのソース端子どうしが短絡され、
前記第1の電流源は、
短絡されたそれぞれの前記ソース端子に前記バイアス電流を供給し、
前記第2の差動対は、
2つの前記電界効果トランジスタのソース端子どうしが短絡され、
前記第4の差動対は、
2つの前記電界効果トランジスタのソース端子どうしが短絡され、
前記第2の電流源は、
短絡されたそれぞれの前記ソース端子に前記バイアス電流を供給することを特徴とする請求項1に記載のオペアンプ回路。 - 前記第1の電流源は、
前記第1の差動対と前記第3の差動対とに前記バイアス電流を供給する一つのトランジスタを備え、
前記第2の電流源は、
前記第2の差動対と前記第4の差動対とに前記バイアス電流を供給する一つのトランジスタを備えることを特徴とする請求項1または2に記載のオペアンプ回路。 - 前記オペアンプ回路は、
前記第1の並列部と、前記第2の並列部とが接続する能動負荷を備え、
前記第1の並列部は、
それぞれの差動対を構成する一方の電界効果トランジスタのゲート端子が反転入力端子として配置された第1の反転入力端子に接続され、それぞれの差動対を構成する他方の電界効果トランジスタのゲート端子が非反転入力端子として配置された第1の非反転入力端子に接続され、
前記第2の並列部は、
それぞれの差動対を構成する一方の電界効果トランジスタのゲート端子が反転入力端子として配置された第2の反転入力端子に接続され、それぞれの差動対を構成する他方の電界効果トランジスタのゲート端子が非反転入力端子として配置された第2の非反転入力端子に接続され、
前記第1の並列部と前記第2の並列部とは、
前記第1の差動対の前記一方の電界効果トランジスタのドレインと、前記第3の差動対の前記一方の電界効果トランジスタのドレインとが短絡されて前記能動負荷に接続し、
前記第1の差動対の前記他方の電界効果トランジスタのドレインと、前記第3の差動対の前記他方の電界効果トランジスタのドレインとが短絡されて前記能動負荷に接続し、
前記第2の差動対の前記一方の電界効果トランジスタのドレインと、前記第4の差動対の前記一方の電界効果トランジスタのドレインとが短絡されて前記能動負荷に接続し、
前記第2の差動対の前記他方の電界効果トランジスタのドレインと、前記第4の差動対の前記他方の電界効果トランジスタのドレインとが短絡されて前記能動負荷に接続する
ことを特徴とする請求項1~3のいずれかに記載のオペアンプ回路。 - 前記第1の差動対と前記第3の差動対とは、
Nチャネル型の電界効果トランジスタからなり、
前記第2の差動対と前記第4の差動対とは、
Pチャネル型の電界効果トランジスタからなり、
前記能動負荷は、
カスコード接続された4つのPチャネル型の電界効果トランジスタを有し、前記第1の差動対及び前記第3の差動対が接続する第1の負荷部と、
カスコード接続された4つのNチャネル型の電界効果トランジスタを有し、前記第2の差動対及び前記第4の差動対が接続する第2の負荷部と
を備えたことを特徴とする請求項4に記載のオペアンプ回路。 - 前記オペアンプ回路は、さらに、
前記能動負荷の出力端子に接続する電圧増幅回路を備えたことを特徴とする請求項4または5のいずれかに記載のオペアンプ回路。 - 前記能動負荷は、
反転出力電圧を出力する反転出力端子と、非反転出力電圧を出力する非反転出力端子とを備え、
前記電圧増幅回路は、
前記反転出力端子の前記反転出力電圧がゲート端子に印加され、ソース端子が接地された電界効果トランジスタと、前記非反転出力端子の前記反転出力電圧がゲート端子に印加され、ソース端子が接地された電界効果トランジスタとを備えたソース接地型の電圧増幅回路であることを特徴とする請求項6に記載のオペアンプ回路。 - 前記オペアンプ回路は、
前記第1の並列部が接続する第1の能動負荷と、
前記第2の並列部が接続する第2の能動負荷と
を備え、
前記第1の並列部は、
それぞれの差動対を構成する一方の電界効果トランジスタのゲート端子が第1の反転入力端子に接続され、それぞれの差動対を構成する他方の電界効果トランジスタのゲート端子が第1の非反転入力端子に接続され、
前記第2の並列部は、
それぞれの差動対を構成する一方の電界効果トランジスタのゲート端子が第2の反転入力端子に接続され、それぞれの差動対を構成する他方の電界効果トランジスタのゲート端子が第2の非反転入力端子に接続され、
前記第1の並列部は、
前記第1の差動対と前記第2の差動対との前記電界効果トランジスタのドレインが前記第1の能動負荷に接続し、
前記第2の並列部は、
前記第3の差動対と前記第4の差動対との前記電界効果トランジスタのドレインが前記第2の能動負荷に接続する
ことを特徴とする請求項1~3のいずれかに記載のオペアンプ回路。 - 前記第1の能動負荷は、
カスコード接続された4つの電界効果トランジスタを有し、前記第1の差動対の前記一方の電界効果トランジスタのドレインと、前記第1の差動対の前記他方の電界効果トランジスタのドレインとが接続する第1の接続部と、
カスコード接続された4つの電界効果トランジスタを有し、前記第2の差動対の前記一方の電界効果トランジスタのドレインと、前記第2の差動対の前記他方の電界効果トランジスタのドレインが接続する第2の接続部とを備え、
第2の能動負荷は、
カスコード接続された4つの電界効果トランジスタを有し、前記第3の差動対の前記一方の電界効果トランジスタのドレインと、前記第3の差動対の前記他方の電界効果トランジスタのドレインとが接続する第3の接続部と、
カスコード接続された4つの電界効果トランジスタを有し、前記第4の差動対の前記一方の電界効果トランジスタのドレインと、前記第4の差動対の前記他方の電界効果トランジスタのドレインとが接続する第4の接続部とを備えた
ことを備えたことを特徴とする請求項8に記載のオペアンプ回路。 - 前記オペアンプ回路は、
前記第1の能動負荷の出力端子に接続する第1の電圧増幅回路と、
前記第2の能動負荷の出力端子に接続する第2の電圧増幅回路と
を備えたことを特徴とする請求項8に記載のオペアンプ回路。 - 前記第1の電圧増幅回路は、
前記第1の能動負荷の前記出力端子から出力される電圧がゲート端子に印加され、ソース端子が接地された電界効果トランジスタを備えたソース接地型の電圧増幅回路であり、
前記第2の電圧増幅回路は、
前記第2の能動負荷の前記出力端子から出力される電圧がゲート端子に印加され、ソース端子が接地された電界効果トランジスタを備えたソース接地型の電圧増幅回路であることを特徴とする請求項10に記載のオペアンプ回路。 - 前記能動負荷は、
反転出力端子と、非反転出力端子とを備え、
前記反転出力端子の出力を前記第2の非反転入力端子に帰還し、
前記非反転出力端子の出力を前記第1の反転入力端子に帰還することを特徴とする請求項4に記載のオペアンプ回路。 - 前記能動負荷は、
反転出力端子と、非反転出力端子とを備え、
前記反転出力端子の出力を前記第2の非反転入力端子に帰還し、
前記非反転出力端子の出力を前記第1の反転入力端子に帰還し、
前記オペアンプ回路は、さらに、
前記非反転出力端子から前記第1の反転入力端子に帰還する経路に配置された第1の抵抗要素と、
前記反転出力端子から前記第2の非反転入力端子に帰還する経路に配置された第2の抵抗要素と、
コモン電圧端子として配置された第1のコモン電圧端子から、前記第1の抵抗要素と前記第1の反転入力端子との間に接続する経路に配置された第3の抵抗要素と、
コモン電圧端子として配置された第2のコモン電圧端子から、前記第2の抵抗要素と前記第2の非反転入力端子との間に接続する経路に配置された第4の抵抗要素と
を備えたことを特徴とする請求項4に記載のオペアンプ回路。 - 前記能動負荷は、
反転出力端子と、非反転出力端子とを備え、
前記反転出力端子の出力を前記第2の非反転入力端子に帰還し、
前記非反転出力端子の出力を前記第1の反転入力端子に帰還し、
前記オペアンプ回路は、さらに、
前記第1の反転入力端子と前記第2の非反転入力端子とを接続する経路に配置された抵抗要素と、
前記非反転出力端子から前記第1の反転入力端子に帰還する経路に配置された抵抗要素と、
前記反転出力端子から前記第2の非反転入力端子に帰還する経路に配置された抵抗要素と
を備えたことを特徴とする請求項4に記載のオペアンプ回路。 - Nチャネル型とPチャネル型とのうちチャネル型を同じくする2つの電界効果トランジスタからなる第1の差動対と、前記第1の差動対と異なるチャネル型の2つの電界効果トランジスタからなり、前記第1の差動対に並列に接続される第2の差動対とを含む第1の並列部と、
前記第1の差動対と同一のチャネル型の2つの電界効果トランジスタからなる第3の差動対と、前記第2の差動対と同一のチャネル型の2つの電界効果トランジスタからなり、前記第3の差動対に並列に接続される第4の差動対とを含む第2の並列部と
に対して、
一つの第1の電流源が、
前記第1の差動対と前記第3の差動対とにバイアス電流を供給し、
一つの第2の電流源が、
前記第2の差動対と前記第4の差動対とにバイアス電流を供給することを特徴とするバイアス電流供給方法。
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EP14897045.2A EP3168987B1 (en) | 2014-07-08 | 2014-07-08 | Operational amplifier circuit and bias current supply method |
US15/305,462 US9923522B2 (en) | 2014-07-08 | 2014-07-08 | Operational amplifier circuit and bias current supply method |
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JPH0993052A (ja) * | 1995-09-25 | 1997-04-04 | Sony Corp | 多入力差動増幅回路 |
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US5561396A (en) | 1995-04-27 | 1996-10-01 | Philips Electronics North America Corporation | Rail-to-rail input stages with gm -control by multiple input pairs |
US5734297A (en) | 1996-03-29 | 1998-03-31 | Philips Electronics North America Corporation | Rail-to-rail input stages with constant gm and constant common-mode output currents |
US5929705A (en) | 1997-04-15 | 1999-07-27 | Fairchild Semiconductor Corporation | CMOS rail-to-rail input/output amplifier |
JP2001085958A (ja) | 1999-09-10 | 2001-03-30 | Toshiba Corp | 増幅回路 |
KR20020035324A (ko) | 2000-11-06 | 2002-05-11 | 김덕중 | 차동 증폭기 |
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JP2009033230A (ja) | 2007-07-24 | 2009-02-12 | Sony Corp | 増幅器及びそれを備えた液晶駆動回路 |
US8004361B2 (en) * | 2010-01-08 | 2011-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Constant transconductance operational amplifier and method for operation |
CN103825598B (zh) * | 2012-11-19 | 2018-11-13 | 恩智浦美国有限公司 | 轨间差分缓冲器输入级 |
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