WO2015192526A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2015192526A1
WO2015192526A1 PCT/CN2014/087521 CN2014087521W WO2015192526A1 WO 2015192526 A1 WO2015192526 A1 WO 2015192526A1 CN 2014087521 W CN2014087521 W CN 2014087521W WO 2015192526 A1 WO2015192526 A1 WO 2015192526A1
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Prior art keywords
main
common electrode
array substrate
connecting portion
hole
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PCT/CN2014/087521
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English (en)
French (fr)
Inventor
龙跃
李凡
王杨
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US14/654,141 priority Critical patent/US9966389B2/en
Publication of WO2015192526A1 publication Critical patent/WO2015192526A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate,
  • a method of manufacturing an array substrate and a display device including the array substrate is a method of manufacturing an array substrate and a display device including the array substrate.
  • FIG. 1 Shown in FIG. 1 is an array substrate including a common electrode 10, a common electrode line 20, a thin film transistor 30, and a pixel electrode 40, and the common electrode 10 is electrically connected to the common electrode line 20.
  • An etch stop layer 31 and a passivation layer 50 are further disposed between the layer where the common electrode 10 is located and the layer where the common electrode line 20 is located.
  • the common electrode line 20 may be disposed above the common electrode line 20.
  • the via hole 60 is disposed, and a common electrode material is also formed on the sidewall of the via hole 60 and the bottom wall (ie, the upper surface of the common electrode line 20) while the common electrode 10 is deposited, and the via hole 60 is also formed.
  • the common electrode material is formed as a connection portion 70 that electrically connects the common electrode line 20 and the common electrode 10. Since the passivation layer 50 and the etch stop layer 31 have a relatively large thickness, when the connection portion 70 is formed, a gap is easily formed on the sidewall of the via hole 60, resulting in the common electrode line 20 and the common electrode 10 Poor connection.
  • An object of the present invention is an array substrate, a method of fabricating the array substrate, and a display device including the array substrate.
  • the array substrate there is a reliable electrical connection between the common electrode line and the common electrode line.
  • an array substrate includes a common electrode line, a thin film transistor, and a common electrode, and the common electrode line is spaced apart from an active layer of the thin film transistor.
  • a main via hole is disposed above the common electrode line, wherein the common electrode is electrically connected to the common electrode line through a main connection portion at least partially disposed in the main via hole,
  • the main connecting portion includes an upper main connecting portion and a lower main connecting portion, the lower main connecting portion including a main body and a flange disposed on the main body and extending in a direction away from a center of the main transfer hole, the upper portion A lower end of the main connecting portion is connected to the flange, and an upper end of the upper main connecting portion is connected to the common electrode.
  • the main transfer hole includes an upper main transfer hole and a lower main transfer hole, and a width of the upper main transfer hole is larger than a width of the lower main transfer hole, and the main body is disposed at the In the lower main transfer hole, the flange is disposed at a connection between the upper main transfer hole and the lower main transfer hole, and the upper main connection portion is disposed in the upper main transfer hole,
  • the main connecting portion is formed integrally with the common electrode.
  • the main transfer hole includes an upper main transfer hole and a lower main transfer hole
  • the flange extends from an upper end of the lower main transfer hole to an outside of the main transfer hole.
  • the lower main connecting portion is formed in synchronization with a pixel electrode of the array substrate, and the upper main connecting portion is formed integrally with the common electrode
  • a secondary transfer hole is disposed above the flange, and the common electrode is electrically connected to the flange through a secondary connection portion provided in the auxiliary transfer hole.
  • the active layer of the thin film transistor is made of a metal oxide
  • the array substrate further includes an etch barrier layer disposed over the active layer of the thin film transistor, the flange being disposed at the Above the etch barrier.
  • a passivation layer is disposed between the etch barrier layer and the common electrode.
  • a method of manufacturing an array substrate comprising:
  • the method further includes the following steps:
  • the main transfer hole is located above the common electrode line, and reaches the common electrode line;
  • the active layer of the thin film transistor is made of a metal oxide, wherein
  • the step S14 includes:
  • step S14-2 after the step S15, forming an upper main via hole on the etch barrier layer corresponding to the lower main via hole, and removing the deposition in the lower main via hole
  • the passivation layer material, the upper main via hole and the lower main via hole penetrate to form the main via hole.
  • the width of the upper main transfer hole is larger than the width of the lower main transfer hole
  • the step S16 and the step S17 are performed synchronously
  • the upper main connection portion formed in the step S16 is located In the upper main transfer hole
  • the main body of the lower main connecting portion is located in the lower main transfer hole
  • the flange is located at a joint of the upper main transfer hole and the lower main transfer hole And the flange is located on the etch stop layer.
  • the width of the upper main transfer hole is greater than or equal to the width of the lower main transfer hole, and the step S16 includes:
  • the step S16-1 is performed between the step S14-1 and the step S15, and a pixel electrode is formed over the etch barrier layer in the step S16-1, the step S16-2 This is performed in synchronization with the step S17.
  • the manufacturing method further includes:
  • a secondary connecting portion that electrically connects the common electrode and the flange is disposed in the auxiliary via hole.
  • the step S19 is performed in synchronization with the step S17.
  • a display device comprising an array substrate, wherein the array substrate is the above array substrate provided by the present invention.
  • the vertical length of the upper main connecting portion is smaller than the total depth of the main via hole, and the lower main connecting portion is The vertical length of the main body is smaller than the total depth of the main transfer hole. Therefore, when the main connecting portion is formed, the upper connecting portion of the main connecting portion and the lower connecting portion of the main connecting portion are less likely to be notched. And the metal layer forming the main connection portion is continuously uniform, thereby reducing the probability of occurrence of an open circuit in the main connection portion. In other words, in the array substrate provided by the present invention, there is a reliable electrical connection between the common electrode line and the common electrode line. Therefore, the display device including the array substrate can display a picture better.
  • the complexity of the manufacturing method is not increased. That is, when the array substrate is manufactured by the manufacturing method provided by the present invention, high production efficiency can be obtained.
  • 1 is a schematic view of a conventional array substrate
  • FIG. 2 is a schematic view of a first embodiment of an array substrate provided by the present invention.
  • FIG. 3 is a schematic view of a second embodiment of an array substrate provided by the present invention.
  • FIG. 4 is a flow chart for fabricating the array substrate shown in FIG. 2 by the manufacturing method provided by the present invention
  • Figure 5 is a flow chart for preparing the array substrate shown in Figure 3 by the manufacturing method provided by the present invention.
  • gate insulating layer 40 pixel electrode
  • main transfer hole 62 auxiliary transfer hole
  • connecting portion 71 upper main connecting portion
  • an array substrate includes a common electrode line 20, a thin film transistor 30, a common electrode 10, and a common electrode line 20 is active in the thin film transistor 30.
  • a main via hole 61 is disposed above the common electrode line 20.
  • the common electrode 10 passes at least partially
  • the main connection portion provided in the main transfer hole 61 is electrically connected to the common electrode line 20, and the main connection portion includes an upper main connection portion 71 and a lower main connection portion 72.
  • the lower main connecting portion 72 includes a main body 72a and a flange 72b provided on the main body 72a and extending in a direction away from the center of the main transfer hole 61.
  • the lower end of the upper main connecting portion 71 is connected to the flange 72b, and the upper main connecting portion 71 is The upper end is connected to the common electrode 10.
  • the vertical length of the upper main connecting portion 71 is smaller than the total depth of the main transfer hole 61, and the vertical direction of the main body 72a of the lower main connecting portion 72 is increased.
  • the length is smaller than the total depth of the main through-hole 61. Therefore, when the main connecting portion is formed, the upper connecting portion 71 of the main connecting portion and the lower connecting portion 72 of the main connecting portion are less likely to be formed in a gap.
  • the metal layer of the main connecting portion is continuously uniform, thereby reducing the probability of occurrence of an open circuit in the main connecting portion. In other words, in the array substrate provided by the present invention, there is a reliable electrical connection between the common electrode line and the common electrode line.
  • the "common electrode line 20 is spaced apart from the active layer 32 of the thin film transistor 30" as described above means that the layer in which the common electrode line 20 is located and the layer in which the active layer 32 of the thin film transistor 30 is located There are also other layers disposed therebetween (for example, in the embodiment shown in FIGS. 2 and 3, an etch barrier is provided between the layer in which the common electrode line 20 is located and the layer in which the active layer 32 of the thin film transistor 30 is located. Layer 31, gate insulating layer 36 and passivation layer 50).
  • the thin film transistor 30 has a bottom gate structure, that is, the gate electrode 35 of the thin film transistor 30 is disposed under the active layer 32.
  • the arrangement of the source 33 and the drain 34 of the thin film transistor 30 is the same as that of the prior art, and will not be described herein.
  • the main transfer hole 61 includes an upper main transfer hole 61a and a lower main transfer hole 61b, and the width of the upper main transfer hole 61a is larger than the lower
  • the width of the main transfer hole 61b (the width described here refers to the size of the upper main transfer hole 61a and the lower main transfer hole 61b in the left-right direction in FIG. 2), that is, the main transfer hole 61 is formed as a stepped hole .
  • the main body 72a of the lower main connecting portion 72 is disposed in the lower main transfer hole 61b, and the flange 72b is disposed at the joint of the upper main transfer hole 61a and the lower main transfer hole 61b (ie, on the step of the stepped hole), the upper main The connecting portion 71 is disposed on In the main transfer hole 61a, the main connection portion is formed integrally with the common electrode 10.
  • connection between the upper main transfer hole 61a and the lower main transfer hole 61b may be a flat surface or an inclined surface.
  • the main transfer hole 61 includes an upper main transfer hole 61a and a lower main transfer hole 61b, and the flange 72b extends from the upper end of the lower main transfer hole 61b to The outside of the main transfer hole.
  • the lower end surface of the upper main connecting portion 71 may completely conform to the upper surface of the flange 72b, and therefore, in this embodiment, the common electrode 10 and the common electrode line 20 are The electrical connection between the two is more reliable.
  • the lower main connecting portion 72 may be formed while forming the pixel electrode 40, and preferably, the upper main connecting portion 71 is formed integrally with the common electrode 10, and when the common electrode 10 is formed, the upper main body may be formed synchronously Connection portion 71. It should be understood that the flange 72b cannot be connected to the pixel electrode 40.
  • the active layer of the thin film transistor 30 is made of a metal oxide, in which case the array substrate further includes an engraving disposed above the active layer 32 of the thin film transistor.
  • the etch stop layer 31, the flange 72b is disposed above the etch stop layer 31.
  • a passivation layer is disposed between the etch barrier layer 31 and the common electrode 10.
  • FIG. 4 Shown in FIG. 4 is a process flow diagram when the array substrate shown in FIG. 2 is fabricated. As shown in the drawing, the manufacturing method includes:
  • a hole having the etching stopper layer 31 and the gate insulating layer 36 may be formed by a patterning process such as printing or transfer. In order to save cost, it is preferable that a hole penetrating the etching stopper layer 31 and the gate insulating layer 36 can be formed using a conventional photolithography process. And a source 33 and a drain 34 are formed in the source/drain contact hole.
  • a step of forming a pixel electrode on the etch barrier layer 31 is further included between step S13 and step S14-1.
  • serial number is added before each step for the convenience of description, but the serial number before each step does not really represent the order in which the step is performed.
  • the lower main via hole 61b and the source may be formed by a photolithography process using the first mask 91 in step S14-1. Pole 33, drain 34. Forming a passivation layer and an etch stop layer Thereafter, the upper main via hole 61a may be formed by a photolithography process using the second mask 92 in step S14-2.
  • the width of the upper main transfer hole 61a is larger than the width of the lower main transfer hole 61b.
  • the hole 61b has a size in the left-right direction in FIG.
  • the step S16 and the step S17 are performed simultaneously (i.e., the common electrode 10 and the main connection portion are formed in the same step).
  • the upper main connecting portion 71 formed in the step S16 is located in the upper main transfer hole 61a
  • the main body 72a of the lower main connecting portion 72 is located in the lower main transfer hole 61b
  • the flange 72b is located above.
  • the junction of the main via hole 61a and the lower main via hole 61b, and the flange 72b is located on the etch barrier layer 31.
  • the method of preparing the array substrate provided by the present invention does not increase the complexity of preparing the array substrate as compared with the prior art described in the background art. It will be readily understood that in Figure 4, the direction of the arrows is the sequence of the various preparation steps in the manufacturing method provided by the present invention.
  • the manufacturing method includes:
  • a hole having the etching stopper layer 31 and the gate insulating layer 36 may be formed by a patterning process such as printing or transfer.
  • a hole penetrating the etch stop layer 31 and the gate insulating layer 36 can be formed using a conventional photolithography process.
  • a source 33 and a drain 34 are formed in the source/drain contact hole.
  • a lower main connecting portion 72 is formed at the lower main through-hole 61b.
  • the lower main connecting portion 72 has the same configuration as that of the lower main connecting portion 72 in the embodiment of FIG.
  • a body 72a and a flange 72b are also included, wherein the body 72a is connected to the common electrode line and the flange 72b of the lower main connection 72 is located on the etch stop layer 31.
  • a pattern of the common electrode 10 is formed on the passivation layer 50, and the common electrode 10 is connected to the upper end of the upper main connection portion 71.
  • a pixel electrode is also formed in S16-1, and the step S16-2 and the step S17 can be simultaneously performed.
  • the lower main connecting portion 72 is formed while the pixel electrode 40 is formed, and the upper main connecting portion 71 is formed while forming the common electrode 10, and thus, compared with the prior art described in the background art
  • the method of preparing the array substrate provided by the present invention does not increase the complexity of preparing the array substrate. It will be readily understood that in Figure 5, the direction of the arrows is the sequence of the various preparation steps in the manufacturing method provided by the present invention.
  • the manufacturing method further comprises the step of forming a secondary via hole in the substrate.
  • the manufacturing method further includes:
  • a secondary connecting portion 80 that electrically connects the common electrode 10 and the flange 72b is provided in the auxiliary via hole 62.
  • the step S19 is performed in synchronization with the step S17. That is, the auxiliary connecting portion 80 is formed in the same step as the common electrode 10.
  • the width of the upper main via hole 61a is formed to be equal to the width of the lower main via hole 61b in step S14-2 in this embodiment, it is merely exemplary and may also be The width of the upper main transfer hole 61a is formed to be larger than the width of the lower main transfer hole 61b, which is not shown in the drawing.
  • the complexity of the manufacturing method is not increased. That is, when the array substrate is manufactured by the manufacturing method provided by the present invention, high production efficiency can be obtained.
  • a display device comprising an array substrate, wherein the array substrate is the above array substrate provided by the present invention.
  • the display device further includes a color filter substrate formed by pairing the array substrate with the array substrate.
  • the display device provided by the present invention may be an electronic device such as a liquid crystal panel, a television, a mobile phone, or a tablet computer.
  • the vertical length of the upper main connecting portion is smaller than the total depth of the main via hole, and the lower main connecting portion is The vertical length of the main body is smaller than the total depth of the main transfer hole, and therefore, when the main connecting portion is formed, a notch or discontinuity is less likely to occur, that is, the probability of occurrence of an open circuit in the main connecting portion is reduced.
  • the display device including the array substrate can display a picture better.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种阵列基板以及阵列基板的制造方法和包括阵列基板的显示装置，该阵列基板包括公共电极线（20）、薄膜晶体管（30）、公共电极（10），公共电极线（20）位于薄膜晶体管（30）的有源层（32）下方，公共电极线（20）上方设置有主转接孔（61），其中，公共电极（10）通过至少部分地设置在主转接孔（61）中的主连接部与公共电极线（20）电连接，主连接部包括上主连接部（71）和下主连接部（72），下主连接部（72）包括主体（72a）和设置在主体（72a）上且朝向远离主转接孔（61）中心的方向延伸的凸缘（72b），上主连接部（71）的下端与凸缘（72b）相连，上主连接部（71）的上端与公共电极（10）相连。在阵列基板中，公共电极（10）与公共电极线（20）之间具有可靠的电连接。因此，包括阵列基板的显示装置可以更好地显示画面。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明涉及显示技术领域，具体地，涉及一种阵列基板、该
阵列基板的制造方法和包括所述阵列基板的显示装置。
背景技术
图1中所示的是一种阵列基板，该阵列基板包括公共电极10、公共电极线20、薄膜晶体管30和像素电极40，公共电极10与公共电极线20电连接。公共电极10所在的层与公共电极线20所在的层之间还设置有刻蚀阻挡层31和钝化层50，为了将公共电极10与公共电极线20电连接，可以在公共电极线20上方设置转接孔60，在沉积形成公共电极10的同时，转接孔60的侧壁以及底壁(即，公共电极线20的上表面)上也形成一层公共电极材料，转接孔60内的公共电极材料形成为将公共电极线20与公共电极10电连接的连接部70。由于钝化层50和刻蚀阻挡层31具有相对较大的厚度，因此，在形成连接部70时，容易在转接孔60的侧壁上产生缺口，导致公共电极线20与公共电极10之间连接不良。
因此，如何防止公共电极线20与公共电极10之间连接不良成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于一种阵列基板、该阵列基板的制造方法和包括所述阵列基板的显示装置。在所述阵列基板中，公共电极线与公共电极线之间具有可靠的电连接。
为了实现上述目的，作为本发明的一个方面，提供一种阵列基板，该阵列基板包括公共电极线、薄膜晶体管、公共电极，所述公共电极线与所述薄膜晶体管的有源层间隔设置，所述公共电极线上方设置有主转接孔，其中，所述公共电极通过至少部分地设置在所述主转接孔中的主连接部与所述公共电极线电连接，所 述主连接部包括上主连接部和下主连接部，所述下主连接部包括主体和设置在所述主体上且朝向远离所述主转接孔中心的方向延伸的凸缘，所述上主连接部的下端与所述凸缘相连，所述上主连接部的上端与所述公共电极相连。
优选地，所述主转接孔包括上主转接孔和下主转接孔，且所述上主转接孔的宽度大于所述下主转接孔的宽度，所述主体设置在所述下主转接孔中，所述凸缘设置在所述上主转接孔与所述下主转接孔的连接处，所述上主连接部设置在所述上主转接孔中，所述主连接部与所述公共电极形成为一体。
优选地，所述主转接孔包括上主转接孔和下主转接孔，所述凸缘从所述下主转接孔的上端延伸至所述主转接孔的外部。
优选地，所述下主连接部与所述阵列基板的像素电极同步形成，所述上主连接部与所述公共电极形成为一体
优选地，所述凸缘上方设置有辅转接孔，所述公共电极通过设置在所述辅转接孔中的辅连接部与所述凸缘电连接。
优选地，所述薄膜晶体管的有源层由金属氧化物制成，所述阵列基板还包括设置在所述薄膜晶体管的有源层上方的刻蚀阻挡层，所述凸缘设置在所述刻蚀阻挡层上方。
优选地，所述刻蚀阻挡层与所述公共电极之间设置有钝化层。
作为本发明的另一个方面，提供一种阵列基板的制造方法，其中，所述制造方法包括：
S10、在基板上形成包括公共电极线和薄膜晶体管的栅极的图形；
S11、在包括公共电极线和薄膜晶体管的栅极的图形上方形成栅绝缘层；
S12、在所述栅绝缘层上且栅极的上方形成薄膜晶体管的有源层；
S13、在所述薄膜晶体管的有源层上方形成刻蚀阻挡层；
S15、在所述刻蚀阻挡层上方形成钝化层；以及
其中，所述方法还包括如下步骤：
S14、形成主转接孔，所述主转接孔位于所述公共电极线的上方，并到达所述公共电极线；
S16、形成包括主连接部的图形，所述主连接部至少部分地设置在所述主转接孔中，所述主连接部包括上主连接部和下主连接部，所述下主连接部包括主体和设置在所述主体上且朝向远离所述主转接孔中心的方向延伸的凸缘，所述上主连接部的下端与所述凸缘相连，并且所述主体与所述公共电极线相连；以及
S17、形成包括所述公共电极的图形，所述公共电极与所述上主连接部的上端相连。
优选地，所述薄膜晶体管的有源层由金属氧化物制成，其中，
所述步骤S14包括：
S14-1、在所述步骤S13之后形成下主转接孔，该下主转接孔贯穿所述刻蚀阻挡层和栅绝缘层到达所述公共电极线；以及
S14-2、在所述步骤S15之后，在所述刻蚀阻挡层上与所述下主转接孔对应的位置形成上主转接孔，并去除沉积在所述下主转接孔中的钝化层材料，所述上主转接孔与所述下主转接孔贯通，形成所述主转接孔。
优选地，所述上主转接孔的宽度大于所述下主转接孔的宽度，所述步骤S16和所述步骤S17同步进行，且所述步骤S16中形成的所述上主连接部位于所述上主转接孔中，所述下主连接部的主***于所述下主转接孔中，所述凸缘位于所述上主转接孔和所述下主转接孔的连接处，且所述凸缘位于所述刻蚀阻挡层上。
优选地，所述上主转接孔的宽度大于或等于所述下主转接孔的宽度，所述步骤S16包括：
S16-1、形成所述下主连接部，所述凸缘位于所述刻蚀阻挡层上；
S16-2、形成所述上主连接部；其中，
所述步骤S16-1在所述步骤S14-1和所述步骤S15之间进行，并且，在所述步骤S16-1中在所述刻蚀阻挡层上方形成像素电极，所述步骤S16-2与所述步骤S17同步进行。
优选地，所述制造方法还包括：
S18、形成位于所述凸缘上方的辅转接孔；
S19、在所述辅转接孔中设置将所述公共电极和所述凸缘电连接的辅连接部。
优选地，所述步骤S19与所述步骤S17同步进行。
作为本发明的再一个方面，提供一种显示装置，该显示装置包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
在本发明所提供的阵列基板中，增加了朝向远离主转接孔中心的方向延伸的凸缘之后，上主连接部的竖直长度比主转接孔的总深度小，下主连接部的主体的竖直长度比主转接孔的总深度小，因此，在形成所述主连接部时，该主连接部的上连接部和所述主连接部的下连接部上均不易产生缺口，并且形成主连接部的金属层连续均匀，从而降低了主连接部中产生断路的几率。换言之，在本发明所提供的阵列基板中，公共电极线与公共电极线之间具有可靠的电连接。因此，包括所述阵列基板的显示装置可以更好地显示画面。
此外，利用本发明所提供的制造方法制造本发明所提供的阵列基板时，并没有增加制造方法的复杂程度。即，在利用本发明所提供的制造方法制造所述阵列基板时，可以获得较高的生产效率。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是现有的阵列基板的示意图；
图2是本发明所提供的阵列基板的第一种实施方式的示意图；
图3是本发明所提供的阵列基板的第二种实施方式的示意 图；
图4是利用本发明所提供的制造方法制备图2中所示的阵列基板的流程图；
图5是利用本发明所提供的制造方法制备图3中所示的阵列基板的流程图。
附图标记说明
10：公共电极           20：公共电极线
30：薄膜晶体管         31：刻蚀阻挡层
32：有源层             33：源极
34：漏极               35：栅极
36：栅绝缘层           40：像素电极
50：钝化层             60：转接孔
61：主转接孔           62：辅转接孔
70：连接部             71：上主连接部
72：下主连接部         80：辅连接部
91：第一掩膜板         92：第二掩膜板
61a：上主转接孔        61b：下主转接孔
72a：主体              72b：凸缘
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
应当理解的是，在说明书中所使用的方位词“上、下”均是指附图中的“上、下”方向。
如图2和图3中所示，作为本发明的一个方面，一种阵列基板，该阵列基板包括公共电极线20、薄膜晶体管30、公共电极10，公共电极线20位于薄膜晶体管30的有源层32下方，公共电极线20上方设置有主转接孔61。其中，公共电极10通过至少部分地 设置在主转接孔61中的主连接部与公共电极线20电连接，所述主连接部包括上主连接部71和下主连接部72。下主连接部72包括主体72a和设置在主体72a上且朝向远离主转接孔61中心的方向延伸的凸缘72b，上主连接部71的下端与凸缘72b相连，上主连接部71的上端与公共电极10相连。
增加了朝向远离主转接孔61中心的方向延伸的凸缘72b之后，上主连接部71的竖直长度比主转接孔61的总深度小，下主连接部72的主体72a的竖直长度比主转接孔61的总深度小，因此，在形成所述主连接部时，该主连接部的上连接部71和所述主连接部的下连接部72上均不易产生缺口，形成所述主连接部的金属层连续均匀，因此，降低了所述主连接部中产生断路的几率。换言之，在本发明所提供的阵列基板中，公共电极线与公共电极线之间具有可靠的电连接。
应当理解的是，上文中所述的“公共电极线20与薄膜晶体管30的有源层32间隔设置”是指，公共电极线20所在的层与薄膜晶体管30的有源层32所在的层之间还设置有其他层(例如，在图2和图3中所示的具体实施方式中，公共电极线20所在的层与薄膜晶体管30的有源层32所在的层之间设置有刻蚀阻挡层31、栅绝缘层36和钝化层50)。
在图2和图3中所示的阵列基板中，薄膜晶体管30具有底栅结构，即，薄膜晶体管30的栅极35设置在有源层32下方。薄膜晶体管30的源极33和漏极34的设置方式与现有技术中的设置方式相同，这里不再赘述。
作为本发明的一种具体实施方式，优选地，如图2所示，主转接孔61包括上主转接孔61a和下主转接孔61b，且上主转接孔61a的宽度大于下主转接孔61b的宽度(此处所述的宽度是指上主转接孔61a和下主转接孔61b沿图2中左右方向的尺寸)，即，主转接孔61形成为阶梯孔。下主连接部72的主体72a设置在下主转接孔61b中，凸缘72b设置在上主转接孔61a与下主转接孔61b的连接处(即，阶梯孔的台阶上)，上主连接部71设置在上 主转接孔61a中，所述主连接部与公共电极10形成为一体。
上主转接孔61a与下主转接孔61b之间的连接处可以是平面，也可以是倾斜面。
作为本发明的另一种实施方式，如图3所示，主转接孔61包括上主转接孔61a和下主转接孔61b，凸缘72b从下主转接孔61b的上端延伸至所述主转接孔的外部。
在图3中所示的实施方式中，上主连接部71的下端面可以完全贴合在凸缘72b的上表面上，因此，在这种实施方式中，公共电极10与公共电极线20之间的电连接更加可靠。
为了便于制造，可以在形成像素电极40的同时形成下主连接部72，并且优选地，将上主连接部71与公共电极10形成为一体，在形成公共电极10时，可以同步地形成上主连接部71。应当理解的是，凸缘72b不能与像素电极40相连。
为了进一步提高公共电极10与公共电极线20之间的连接的可靠性，优选地，可以在凸缘72b上方设置辅转接孔62，公共电极10通过设置在辅转接孔62中的辅连接部80与凸缘72b电连接。
作为本发明的一种具体实施方式，薄膜晶体管30的有源层由金属氧化物制成，在这种情况中，所述阵列基板还包括设置在所述薄膜晶体管的有源层32上方的刻蚀阻挡层31，凸缘72b设置在刻蚀阻挡层31的上方。当薄膜晶体管的有源层为金属氧化物时，设置刻蚀阻挡层的优点是本领域所公知的，这里不再赘述。
如上文中所述，作为本发明的一种具体实施方式，刻蚀阻挡层31与公共电极10之间设置有钝化层。
作为本发明的另一个方面，提供本发明所提供的上述阵列基板的制造方法。图4中所示的是制作图2中所示的阵列基板时的工艺流程图，如图中所示，所述制造方法包括：
S10、在基板上形成包括公共电极线20和薄膜晶体管30的栅极35的图形；
S11、在包括公共电极线20和薄膜晶体管30的栅极35的图形上方形成栅绝缘层36；
S12、在所述栅极35上方的所述栅绝缘层36上形成薄膜晶体管的有源层32；
S13、在所述薄膜晶体管的有源层32和栅绝缘层36上方形成刻蚀阻挡层31；
S14-1、形成下主转接孔61b和源漏接触孔，所述下主转接孔61b位于所述公共电极线20的上方，且所述下主转接孔61b暴露出所述公共电极线20的上表面；其中，所述下主转接孔61b贯穿所述刻蚀阻挡层31和栅绝缘层36。可以通过诸如打印、转印的构图工艺形成具有贯通所述刻蚀阻挡层31和栅绝缘层36的孔。为了节约成本，优选地，可以利用传统的光刻工艺形成贯通所述刻蚀阻挡层31和栅绝缘层36的孔。并且在所述源漏接触孔中形成源极33和漏极34。
S15、形成位于刻蚀阻挡层31上方的钝化层50；
S14-2、在与下主转接孔61b对应的位置形成上主转接孔61a，并去除沉积在所述下主转接孔61b中的钝化层材料，上主转接孔61a贯穿钝化层50而与下主转接孔61b贯通，以形成主转接孔61。
S16、在所述主转接孔61处形成包括主连接部的图形，所述主连接部至少部分地设置在所述主转接孔中，所述主连接部包括上主连接部71和下主连接部72，所述下主连接部72包括主体72a和设置在所述主体上且朝向远离所述主转接孔中心的方向延伸的凸缘72b，所述上主连接部71的下端与所述凸缘72b相连；
S17、形成包括所述公共电极10的图形，所述公共电极10与所述上主连接部71的上端相连。
此外，在步骤S13和步骤S14-1之间还包括在刻蚀阻挡层31上形成像素电极的步骤。
容易理解的是，为了便于描述在各个步骤前添加了序号，但是，各步骤前的序号并不是真正代表执行该步骤的顺序。
如图4中所示，在形成覆盖基板的刻蚀阻挡层31(步骤S13)之后，在步骤S14-1中可以利用第一掩膜板91通过光刻工艺形成下主转接孔61b和源极33、漏极34。形成了钝化层和刻蚀阻挡层 之后，可以在步骤S14-2中利用第二掩膜板92通过光刻工艺形成上主转接孔61a。
如图4所示，上主转接孔61a的宽度大于下主转接孔61b的宽度，应当理解的是，此处所述的“宽度”是指上主转接孔61a和下主转接孔61b沿图4中左右方向的尺寸。在这种实施方式中，所述步骤S16和所述步骤S17同步进行(即，在同一步骤中形成公共电极10和所述主连接部)。如上文中所述，所述步骤S16中形成的上主连接部71位于所述上主转接孔61a中，下主连接部72的主体72a位于下主转接孔61b中，凸缘72b位于上主转接孔61a和下主转接孔61b的连接处，且凸缘72b位于刻蚀阻挡层31上。
由于步骤S16和所述步骤S17同步进行，因此，与背景技术中描述的现有技术相比，制备本发明所提供的阵列基板的方法并没有增加制备阵列基板的复杂程度。容易理解的是，在图4中，箭头的方向即为本发明所提供的制造方法中各个制备步骤的顺序。
在制备图3中所示的阵列基板的实施例中，如图5所示，所述制造方法包括：
S10、形成包括公共电极线20和薄膜晶体管30的栅极35的图形；
S11、在包括公共电极线20和薄膜晶体管30的栅极35的图形上方形成栅绝缘层36；
S12、在所述栅极35上方的所述栅绝缘层36上形成薄膜晶体管的有源层32；
S13、在所述薄膜晶体管的有源层32和栅绝缘层36上方形成刻蚀阻挡层31；
S14-1、形成下主转接孔61b和源漏接触孔，所述下主转接孔61b位于所述公共电极线20的上方，且所述下主转接孔61b暴露出所述公共电极线20的上表面；其中，所述下主转接孔61b贯穿所述刻蚀阻挡层31和栅绝缘层36。可以通过诸如打印、转印的构图工艺形成具有贯通所述刻蚀阻挡层31和栅绝缘层36的孔。为 了节约成本，优选地，可以利用传统的光刻工艺形成贯通所述刻蚀阻挡层31和栅绝缘层36的孔。并且在所述源漏接触孔中形成源极33和漏极34。
S16-1、在所述下主转接孔61b处形成下主连接部72，在该实施例中，下主连接部72与参照图4的实施例中的下主连接部72的构造相同，也包括主体72a和凸缘72b，其中所述主体72a与公共电极线相连并且下主连接部72的凸缘72b位于所述刻蚀阻挡层31上。
S15、形成位于刻蚀阻挡层31上方的钝化层50，并且钝化层50覆盖部分凸缘72b，如图5所示；
S14-2、在与下主转接孔61b对应的位置形成上主转接孔61a，其中上主转接孔61a的宽度等于下主转接孔61b的宽度，并去除沉积在所述下主转接孔61b中的钝化层材料，上主转接孔61a和下主转接孔61b贯通，以形成主转接孔61。
S16-2、在所述上主转接孔61a处形成上主连接部71，所述上主连接部71与所述凸缘72b相连；以及
S17，在所述钝化层50上形成公共电极10的图形，所述公共电极10与所述上主连接部71的上端相连。
S16-1中还形成像素电极，并且所述步骤S16-2与所述步骤S17可同时进行。
如图5中所示，在形成像素电极40的同时形成了下主连接部72，在形成公共电极10的同时形成了上主连接部71，因此，与背景技术中描述的现有技术相比，制备本发明所提供的阵列基板的方法并没有增加制备阵列基板的复杂程度。容易理解的是，在图5中，箭头的方向即为本发明所提供的制造方法中各个制备步骤的顺序。
优选地，该实施例中，所述制造方法还包括在基板中形成辅转接孔的步骤。具体地，在阵列基板中包括辅转接孔的实施方式中，所述制造方法还包括：
S18、形成位于凸缘72b上方的辅转接孔62；
S19、在辅转接孔62中设置将公共电极10和凸缘72b电连接的辅连接部80。
为了减少制备阵列基板的步骤、提高生产效率，优选地，所述步骤S19与所述步骤S17同步进行。即，辅连接部80与公共电极10在同一步骤中形成。
本领域技术人员应该明白，尽管在该实施例中步骤S14-2中将上主转接孔61a的宽度形成为等于下主转接孔61b的宽度，但是其仅是示例性的，还可以将上主转接孔61a的宽度形成为大于下主转接孔61b的宽度，附图中未示出该情形。
综上所述，利用本发明所提供的制造方法制造本发明所提供的阵列基板时，并没有增加制造方法的复杂程度。即，在利用本发明所提供的制造方法制造所述阵列基板时，可以获得较高的生产效率。
作为本发明的再一个方面，提供一种显示装置，该显示装置包括阵列基板，其中，所述阵列基板为本发明所提供的上述阵列基板。
容易理解的是，所述显示装置还包括与所述阵列基板对盒形成的彩膜基板。
本发明所提供给的显示装置可为液晶面板、电视、手机、平板电脑等电子设备。
在本发明所提供的阵列基板中，增加了朝向远离主转接孔中心的方向延伸的凸缘之后，上主连接部的竖直长度比主转接孔的总深度小，下主连接部的主体的竖直长度比主转接孔的总深度小，因此，在形成所述主连接部时，不容易产生缺口或不连续现象，即，降低了主连接部中产生断路的几率。换言之，在本发明所提供的阵列基板中，公共电极线与公共电极线之间具有可靠的电连接。因此，包括所述阵列基板的显示装置可以更好地显示画面。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况 下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种阵列基板，该阵列基板包括公共电极线、薄膜晶体管、公共电极，所述公共电极线与所述薄膜晶体管的有源层间隔设置，所述公共电极线上方设置有主转接孔，其特征在于，所述公共电极通过至少部分地设置在所述主转接孔中的主连接部与所述公共电极线电连接，所述主连接部包括上主连接部和下主连接部，所述下主连接部包括主体和设置在所述主体上且朝向远离所述主转接孔中心的方向延伸的凸缘，所述上主连接部的下端与所述凸缘相连，所述上主连接部的上端与所述公共电极相连。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述主转接孔包括上主转接孔和下主转接孔，且所述上主转接孔的宽度大于所述下主转接孔的宽度，所述主体设置在所述下主转接孔中，所述凸缘设置在所述上主转接孔与所述下主转接孔的连接处，所述上主连接部设置在所述上主转接孔中，所述主连接部与所述公共电极形成为一体。
  3. 根据权利要求1所述的阵列基板，其特征在于，所述主转接孔包括上主转接孔和下主转接孔，所述凸缘从所述下主转接孔的上端延伸至所述主转接孔的外部。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述下主连接部与所述阵列基板的像素电极同步形成，以及所述上主连接部与所述公共电极形成为一体
  5. 根据权利要求3所述的阵列基板，其特征在于，所述凸缘上方设置有辅转接孔，所述公共电极通过设置在所述辅转接孔中的辅连接部与所述凸缘电连接。
  6. 根据权利要求1至4中任意一项所述的阵列基板，其特征在于，所述薄膜晶体管的有源层由金属氧化物制成，所述阵列基板还包括设置在所述薄膜晶体管的有源层上方的刻蚀阻挡层，以及所述凸缘设置在所述刻蚀阻挡层上方。
  7. 根据权利要求6所述的阵列基板，其特征在于，所述刻蚀阻挡层与所述公共电极之间设置有钝化层。
  8. 一种阵列基板的制造方法，所述制造方法包括：
    S10、在基板上形成包括公共电极线和薄膜晶体管的栅极的图形；
    S11、在包括公共电极线和薄膜晶体管的栅极的图形上方形成栅绝缘层；
    S12、在所述栅极上方的所述栅绝缘层上形成薄膜晶体管的有源层；
    S13、在所述薄膜晶体管的有源层和所述栅绝缘层上方形成刻蚀阻挡层；
    S15、在所述刻蚀阻挡层上方形成钝化层；以及
    其特征在于，所述方法还包括如下步骤：
    S14、形成主转接孔，所述主转接孔位于所述公共电极线的上方，并到达所述公共电极线；
    S16、形成包括主连接部的图形，所述主连接部至少部分地设置在所述主转接孔中，所述主连接部包括上主连接部和下主连接部，所述下主连接部包括主体和设置在所述主体上且朝向远离所述主转接孔中心的方向延伸的凸缘，所述上主连接部的下端与所述凸缘相连，并且所述主体与所述公共电极线相连；以及
    S17、形成包括所述公共电极的图形，所述公共电极与所述上主连接部的上端相连。
  9. 根据权利要求8所述的制造方法，其特征在于，所述薄膜 晶体管的有源层由金属氧化物制成，其中，
    所述步骤S14包括：
    S14-1、在所述步骤S13之后形成下主转接孔，该下主转接孔贯穿所述刻蚀阻挡层和栅绝缘层到达所述公共电极线；以及
    S14-2、在所述步骤S15之后，在所述刻蚀阻挡层上与所述下主转接孔对应的位置形成上主转接孔，并去除沉积在所述下主转接孔中的钝化层材料，所述上主转接孔与所述下主转接孔贯通，形成所述主转接孔。
  10. 根据权利要求9所述的制造方法，其特征在于，所述上主转接孔的宽度大于所述下主转接孔的宽度，所述步骤S16和所述步骤S17同步进行，且所述步骤S16中形成的所述上主连接部位于所述上主转接孔中，所述下主连接部的主***于所述下主转接孔中，所述凸缘位于所述上主转接孔和所述下主转接孔的连接处，且所述凸缘位于所述刻蚀阻挡层上。
  11. 根据权利要求9所述的制造方法，其特征在于，所述上主转接孔的宽度大于或等于所述下主转接孔的宽度，所述步骤S16包括：
    S16-1、形成所述下主连接部，所述凸缘位于所述刻蚀阻挡层上；
    S16-2、形成所述上主连接部；其中，
    所述步骤S16-1在所述步骤S14-1和所述步骤S15之间进行，并且，在所述步骤S16-1中在所述刻蚀阻挡层上方形成像素电极，所述步骤S16-2与所述步骤S17同步进行。
  12. 根据权利要求11所述的制造方法，其特征在于，所述制造方法还包括：
    S18、形成位于所述凸缘上方的辅转接孔；
    S19、在所述辅转接孔中设置将所述公共电极和所述凸缘电连 接的辅连接部。
  13. 根据权利要求12所述的制造方法，其特征在于，所述步骤S19与所述步骤S17同步进行。
  14. 一种显示装置，所述显示装置包括阵列基板，其特征在于，所述阵列基板为权利要求1至7中任意一项所述的阵列基板。
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