WO2017031924A1 - 薄膜晶体管阵列基板、其制作方法及显示装置 - Google Patents

薄膜晶体管阵列基板、其制作方法及显示装置 Download PDF

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Publication number
WO2017031924A1
WO2017031924A1 PCT/CN2016/070257 CN2016070257W WO2017031924A1 WO 2017031924 A1 WO2017031924 A1 WO 2017031924A1 CN 2016070257 W CN2016070257 W CN 2016070257W WO 2017031924 A1 WO2017031924 A1 WO 2017031924A1
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layer
thin film
film transistor
transistor array
transparent electrode
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PCT/CN2016/070257
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English (en)
French (fr)
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冯伟
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/513,172 priority Critical patent/US10209594B2/en
Publication of WO2017031924A1 publication Critical patent/WO2017031924A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • Embodiments of the present invention relate to a thin film transistor array substrate, a method of fabricating the same, and a display device.
  • an advanced super-dimension switch (ADS) thin film transistor liquid crystal display is formed by an electric field generated by the edge of the slit electrode in the same plane and a multi-dimensional electric field between the slit electrode layer and the plate electrode layer. All the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmittance. Therefore, ADS technology can improve the picture quality of the product, with high resolution, high transmittance, low power consumption, wide viewing angle and so on.
  • the ADS technology is to fabricate two layers of Indium Tin Oxide (ITO) materials on a thin film transistor array substrate as a common electrode and a pixel electrode, respectively.
  • ITO Indium Tin Oxide
  • a common electrode is formed on the bottom layer of the base substrate, and a block design is adopted, and the pixel electrode is formed on the uppermost layer, and a slit design is adopted, and has a certain width-to-space ratio.
  • At least one embodiment of the present invention provides a thin film transistor array substrate, a method for fabricating the same, and a display device, which can reduce the residual sand of the electrode layer in the region where the thin film transistor is located, and avoid the phenomenon of unevenness of the picture caused by residual sand.
  • At least one embodiment of the present invention provides a thin film transistor array substrate including: a substrate substrate, a gate disposed on the substrate, a gate insulating layer and an active layer sequentially disposed on the gate a pixel electrode, a common electrode, and a transparent electrode layer disposed on the substrate; wherein the transparent electrode layer and the pixel electrode are of the same material, or the transparent electrode layer and the common electrode are of the same material;
  • the transparent electrode layer is located directly under the gate insulating layer; an orthographic projection of the active layer on the substrate is located in a region where the orthographic projection of the transparent electrode layer is located.
  • the transparent electrode layer is disposed between the base substrate and the gate; or the transparent electrode layer is disposed in the Between the gate and the gate insulating layer.
  • a buffer layer is disposed between the base substrate and the gate; the transparent electrode layer is disposed on the base substrate and the buffer layer between.
  • the thin film transistor array substrate provided in the embodiment of the present invention may further include: a plurality of gate lines disposed on the transparent electrode layer, and a portion of each of the gate lines serves as the gate.
  • an orthographic projection of the gate line on the substrate substrate and an orthographic projection of the transparent electrode layer overlap each other.
  • the pixel electrode in the thin film transistor array substrate is located above the common electrode, wherein the common electrode is a plate electrode.
  • the pixel electrode in the thin film transistor array substrate is located below the common electrode, wherein the pixel electrode is a plate electrode.
  • the material of the transparent electrode layer is one or a combination of indium tin oxide, indium zinc oxide or indium gallium zinc oxide.
  • the transparent electrode layer is a plate electrode having a rectangular shape.
  • the thickness of the transparent electrode layer is to
  • At least one embodiment of the present invention provides a method for fabricating the thin film transistor array substrate provided by the embodiment of the present invention, comprising: forming a pattern of a pixel electrode and a transparent electrode layer on a substrate by the same patterning process, or by the same Forming a pattern of a common electrode and a transparent electrode layer on the base substrate; forming a pattern of the gate on the base substrate; forming a gate insulating layer and an active layer on the base substrate on which the gate pattern is formed a pattern of the layer; the transparent electrode layer pattern is located below the gate insulating layer pattern; an orthographic projection of the active layer pattern on the substrate substrate is located in an area where the orthographic projection of the transparent electrode layer pattern is located .
  • At least one embodiment of the present invention provides a display device including the above-described thin film transistor array substrate provided by the embodiment of the present invention.
  • 1a is a top plan view of a thin film transistor array substrate
  • Figure 1b is a schematic cross-sectional view of the Figure 1a along the A-A' direction;
  • FIG. 2a is a top view of a thin film transistor array substrate according to an embodiment of the present invention.
  • FIG. 2b to 2d are schematic cross-sectional views of the Fig. 2a along the B-B' direction in the respective embodiments;
  • Figure 2e is a schematic cross-sectional view taken along line C-C' of Figure 2a;
  • Figure 2f is a variant of the embodiment shown in Figure 2e;
  • 3a is a top view of a thin film transistor array substrate according to another embodiment of the present invention.
  • Figure 3b is a schematic cross-sectional view of Figure 3a along the C-C' direction;
  • FIG. 4 is a flow chart of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a method for fabricating a thin film transistor array substrate according to an embodiment of the present invention after each step is performed.
  • each film layer in the drawing do not reflect the true proportion of the thin film transistor array substrate. It is only illustrative of the contents of the present invention.
  • the mechanism of the defect is: related to the residual sand of the plate electrode layer (such as the common electrode) (ie, a small amount of electrode layer material remaining after etching), as shown in FIG. 1a and FIG. 1b, the severe residual sand region easily causes the film.
  • the active layer 01 in the transistor is not flattened, causing the thin film transistor characteristic Ioff to be large, and the leakage is severe, causing unevenness of the picture.
  • the thin film transistor array substrate includes: a substrate substrate 1, a gate electrode 20 disposed on the substrate substrate 1, and sequentially disposed. a gate insulating layer 30 on the gate and an active layer 4; as shown, the array substrate includes a plurality of horizontally extending gate lines 2 and a plurality of vertically extending data lines 9 that define a plurality of crossings with each other A pixel unit each including a pixel electrode 12 and a thin film transistor as a switching element.
  • the thin film transistor has a gate, a source, a drain, an active layer, and a gate insulating layer, the gate insulating layer is sandwiched between the gate and the active layer, and the source and the drain are in contact with the active layer, and both A channel region is defined between them, and the channel region corresponds to the gate.
  • the gate may be electrically connected to or be part of the gate line (the embodiment shown in the figure is part of the gate line), one of the source and the drain being electrically connected to the data line or part of the data line as needed, The other is electrically connected to the pixel electrode.
  • the thin film transistor array substrate further includes: a pixel electrode 12 disposed on the base substrate 1, a common electrode 7 and a transparent electrode layer 3; wherein the transparent electrode layer 3 and the pixel electrode are of the same material; or, the transparent electrode The layer 3 and the common electrode are of the same material; the transparent electrode layer 3 is located below the gate insulating layer 30; the orthographic projection of the active layer 4 on the substrate 1 is located in the area where the orthographic projection of the transparent electrode layer 3 is located.
  • the electrode layer of the region where the thin film transistor is located can be reduced. Residual sand smoothes the surface of the active layer to avoid uneven images caused by residual sand.
  • the implementation method is simple, and has little influence on the gate resistance, which can improve product quality.
  • the transparent electrode layer 3 may be disposed between the gate electrode 20 and the substrate substrate 1; or, as shown in FIG. 2c The transparent electrode layer 3 may be disposed between the gate electrode 20 and the gate insulating layer 30.
  • the passivation layer 50 is overlaid on the thin film transistor (including the source 5 and the drain 6).
  • the pixel electrode 12 is formed on the passivation layer 50 (see FIG. 2e), or the pixel electrode may be formed over the gate insulating layer 30 below the passivation layer 50.
  • a buffer layer may be disposed between the substrate and the gate.
  • the transparent electrode layer 3 may be disposed between the base substrate 1 and the buffer layer 40.
  • the position of the transparent electrode layer is not limited to the position referred to in the drawings of the present invention, and is not limited herein.
  • the thin film transistor array substrate further includes: a plurality of gate lines 2 disposed on the transparent electrode layer 3, A portion of each of the gate lines 2 serves as the gate electrode 20 in the thin film transistor, which simplifies the process and saves cost.
  • the orthographic projection of the gate line on the substrate substrate and the orthographic projection of the transparent electrode layer can be overlapped with each other, so that no additional preparation process is required in preparing the thin film transistor array substrate.
  • the pattern of the transparent electrode layer and the gate line can be formed by only one patterning process (such as a semi-transparent mask process or a single slit mask process), thereby simplifying the process. ,cut costs.
  • the transparent electrode layer 3 may be disposed between the gate line 2 and the base substrate 1.
  • the thin film transistor array substrate provided in the embodiment of the present invention can be applied to an advanced-super-dimension switch (ADS) type liquid crystal panel, for example, in a thin film transistor array substrate.
  • ADS advanced-super-dimension switch
  • the common electrode is located as a plate electrode in the lower layer (closer to the substrate), and the pixel electrode is located as the slit electrode in the upper layer (closer to the liquid crystal layer), as shown in FIG. 2e, that is, the pixel electrode 12 is located above the common electrode 7, in the pixel
  • An insulating layer is disposed between the electrode 12 and the common electrode 7; at this time, the common electrode and the transparent electrode layer may be disposed in the same layer.
  • the common electrode layer in the area is left with sand to avoid uneven images caused by residual sand.
  • the above thin film transistor array substrate provided by the embodiment of the present invention It can also be applied to a High Advanced-Super Dimension Switch (HADS) type liquid crystal panel.
  • the pixel electrode in the thin film transistor array substrate is located as a plate electrode in the lower layer (closer to the substrate), and the common electrode As the slit electrode is located in the upper layer (closer to the liquid crystal layer), as shown in FIG. 2f, that is, the pixel electrode 12 is located below the common electrode 7, and an insulating layer is disposed between the pixel electrode 12 and the common electrode 7.
  • HADS High Advanced-Super Dimension Switch
  • the pixel electrode The transparent electrode layer can be disposed in the same layer, so that no additional preparation process is required in the preparation of the thin film transistor array substrate, and only the pattern of the pixel electrode and the transparent electrode layer can be formed by the same patterning process, thereby saving the manufacturing cost and improving
  • the added value of the product can reduce the residual sand of the pixel electrode layer in the region where the thin film transistor is located, and avoid the phenomenon of unevenness of the picture caused by residual sand.
  • the material of the transparent electrode layer may be one or a combination of indium tin oxide, indium zinc oxide or indium gallium zinc oxide.
  • Reasonable selection of the material of the transparent electrode layer can further achieve the effect that the electrode layer does not cause residual sand in the region where the thin film transistor is located.
  • the transparent electrode layer may be provided as a plate-shaped electrode having a rectangular shape, which simplifies the etching process.
  • the shape of the transparent electrode layer may also be set to other regular patterns, and only the orthographic projection of the active layer on the substrate substrate is located in the area where the orthographic projection of the transparent electrode layer is located.
  • the thickness of the transparent electrode layer may be set to to to It is further ensured that the electrode layer does not have residual sand in the region where the thin film transistor is located.
  • the thin film transistor array substrate provided by the embodiment of the present invention generally has other film layer structures such as a gate insulating layer, an ohmic contact layer, and a passivation layer, and a common electrode is also generally formed on the substrate. Structures such as lines and data lines, and the specific structures may be implemented in various manners, which are not limited herein.
  • At least one embodiment of the present invention further provides a method for fabricating the above-mentioned thin film transistor array substrate provided by an embodiment of the present invention. Since the principle of solving the problem is similar to the foregoing thin film transistor array substrate, the implementation of the method can be seen. The implementation of the thin film transistor array substrate will not be repeated here.
  • the method for fabricating the thin film transistor array substrate provided by the embodiment of the present invention, as shown in FIG. 4 includes the following steps, for example:
  • step S401 When the transparent electrode layer is located under the gate, step S401 is performed first, then step S402 is performed; when the transparent electrode layer is located between the gate and the gate insulating layer. First, step S402 is performed, and then step S401 is performed. In step S402, gate lines electrically connected thereto may be formed together while forming the gate.
  • a transparent electrode layer of the same material as the pixel electrode or the common electrode is disposed directly under the active layer in the thin film transistor, and the active layer pattern is
  • the orthographic projection on the substrate is located in the area where the orthographic projection of the transparent electrode layer pattern is located, which can reduce the residual sand of the electrode layer in the region where the thin film transistor is located, and avoid the phenomenon of unevenness of the picture caused by residual sand.
  • the implementation method is simple, and has little influence on the gate resistance, which can improve product quality.
  • Step 1 forming a pattern including a common electrode and a transparent electrode layer on the base substrate by the same patterning process, as shown in FIG. 5a; for example, depositing a thickness on the substrate by sputtering or thermal evaporation to a thickness of about to
  • the electrode layer film the material of the electrode layer film may include indium tin oxide ITO, or indium zinc oxide IZO, or other metals and metal oxides; the common electrode 7 and the transparent electrode layer 3 are formed by one exposure and wet etching processes.
  • the pattern in which the corresponding region of the thin film transistor is required to retain the electrode layer film is used as the transparent electrode layer 3.
  • Step 2 forming a pattern of gate lines on the base substrate on which the common electrode and the transparent electrode layer pattern are formed, as shown in FIG. 5b; for example, depositing a layer on the above substrate by sputtering or thermal evaporation Buffer layer film and metal layer film, the thickness of the buffer layer film is about to
  • the material of the buffer layer film may include metal or alloy such as metal Ta, Cr, Mo, W, Nb, or a transparent conductive film; the thickness of the metal layer film is about to The material may be aluminum or copper, and the metal layer film is coated with a photoresist, exposed, developed, wet etched and stripped to obtain a corresponding pattern of the gate line 2 and the common electrode line 8 (connecting the lower common electrode); A portion of each gate line 2 pattern serves as a gate in the thin film transistor.
  • Step 3 sequentially forming a pattern of a gate insulating layer and an active layer over the gate pattern, as shown in FIG. 5c; for example, sequentially depositing a gate insulating layer by PECVD or the like on the substrate on which the step 2 is completed,
  • the film of the source layer 4 and the ohmic contact layer; the thickness of the gate insulating layer film may specifically be to
  • the material may specifically include a nitride SiNx or an oxynitride SiOxNx, or a composite of a nitride SiNx and a oxynitride SiOxNx; and the thickness of the active layer 4 film may specifically be to
  • the thickness of the ohmic contact layer film may specifically be to
  • the channel of the thin film transistor is then formed by photoresisting, exposing, developing, and dry etching and stripping processes; wherein the orthographic projection area of the active layer 4 on the substrate is slightly smaller than the orthographic area of the transparent electrode layer 3. .
  • Step 4 forming a pattern of source and drain on the base substrate on which the active layer pattern is formed, as shown in FIG. 5d; for example, depositing sequentially by sputtering or thermal evaporation on the substrate substrate on which the step 3 is completed; Upper thickness is about a metal or alloy such as metal Ta, Cr, Mo, W, Nb or a transparent conductive film of 1000 A as a buffer layer; The metal layer (the material may be aluminum or copper), or the source and drain metal layers are formed of a plurality of layers of metal; then the source 5 and the drain 6 are obtained by photoresist, exposure, development, wet etching and lift-off processes. And the graph of the data scan line 9.
  • a metal or alloy such as metal Ta, Cr, Mo, W, Nb or a transparent conductive film of 1000 A as a buffer layer
  • the metal layer the material may be aluminum or copper
  • the source and drain metal layers are formed of a plurality of layers of metal; then the source 5 and the drain 6 are obtained by photoresist
  • Step 5 forming a pattern of a passivation layer having via holes on the base substrate including the source and drain patterns, as shown in FIG. 5e; for example, depositing by a PECVD method or the like on the substrate of the fourth step Thickness is about
  • the passivation layer the material of the passivation layer may specifically include an oxide, a nitride or an oxynitride; and the pixel region is formed in the passivation layer by photoresist, exposure, development, dry etching and lift-off processes;
  • the via hole 10 removing the passivation layer
  • the connection hole 11 removing the passivation layer and the gate insulating layer connecting the upper and lower common electrodes 7 (the common electrode line 8).
  • Step 6 forming a pattern of the pixel electrode on the base substrate on which the passivation layer pattern is formed, as shown in FIG. 5f; for example, depositing a thickness on the substrate of the fifth step by sputtering or thermal evaporation.
  • the material of the transparent conductive layer may specifically include ITO, or IZO, or other metal and metal oxide; then, the pixel electrode 12 is formed by a single exposure and etching process, and the upper and lower common electrodes 7 are connected (the common electrode line 8) The conductive connection layer 13.
  • the above manufacturing process is formed by using six exposure processes, and can also be fabricated by five exposure processes. That is, when step 3 is performed, after the film of the gate insulating layer, the active layer, and the ohmic contact layer is sequentially deposited by a method such as PECVD, the exposure and etching processes are not performed, but the buffer is sequentially deposited by sputtering or thermal evaporation. a layer and a metal layer; subsequently, a halftone or gray tone mask exposure development process may be employed to form a pattern corresponding to the gate insulating layer, the semiconductor layer, the ohmic contact layer, and the source and drain metal layers after multiple etching, such as a thin film transistor Channel, source, drain, and data lines.
  • a method such as PECVD
  • the exposure and etching processes are not performed, but the buffer is sequentially deposited by sputtering or thermal evaporation.
  • a layer and a metal layer; subsequently, a halftone or gray tone mask exposure development process
  • the above-mentioned thin film transistor array substrate provided by at least one embodiment of the present invention has been produced through the above steps 1 to 6.
  • At least one embodiment of the present invention further provides a display device, including the thin film transistor array substrate provided by the above embodiments of the present invention
  • the display device may be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame. , navigation, etc. Any product or component that has a display function.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the invention.
  • the display device refer to the embodiment of the above-mentioned thin film transistor array substrate, and the repeated description is omitted.
  • the present invention provides a thin film transistor array substrate, a manufacturing method thereof, and a display device.
  • the thin film transistor array substrate includes: a substrate substrate, a gate disposed on the substrate substrate, and a gate sequentially disposed on the gate An insulating layer and an active layer, a pixel electrode disposed on the base substrate, a common electrode, and a transparent electrode layer; wherein the transparent electrode layer and the pixel electrode/common electrode are of the same material; the transparent electrode layer is located under the gate insulating layer
  • the orthographic projection of the active layer on the substrate is located in the region of the orthographic projection of the transparent electrode layer.
  • the residual layer of the electrode layer in the region where the thin film transistor is located can be reduced, and the surface of the active layer can be flattened to avoid
  • the phenomenon of uneven picture caused by sand is simple to implement and has little influence on the gate resistance, which can improve product quality.

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Abstract

一种薄膜晶体管阵列基板、其制作方法及显示装置，包括：衬底基板(1)、设置在衬底基板(1)上的栅极(2)、依次设置在栅极(2)上的栅极绝缘层和有源层(4)、设置在衬底基板(1)上的像素电极、公共电极和透明电极层(3)，透明电极层(3)和像素电极/公共电极同层同材质；透明电极层(3)位于栅极绝缘层的下方；有源层(4)在衬底基板(1)上的正投影位于透明电极层(3)的正投影所在区域内。所述薄膜晶体管阵列基板可以减少薄膜晶体管所在区域的电极层残沙，使有源层的表面平整，避免由残沙引起的画面不均的现象，且其实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。

Description

薄膜晶体管阵列基板、其制作方法及显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管阵列基板、其制作方法及显示装置。
背景技术
目前，高级超维场开关(Advanced-super Dimension Switch，简称ADS)薄膜晶体管液晶显示器是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间形成多维电场，使液晶盒内狭缝电极间、电极正上方的所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光率。因此ADS技术可以提高产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角等优点。
例如ADS技术是将两层氧化铟锡(Indium Tin Oxide，简称ITO)材料都制作在薄膜晶体管阵列基板上，分别作为公共电极和像素电极。一种ADS技术中，公共电极制作在衬底基板的最底层，采用块状设计，而像素电极制作在最上层，采用狭缝设计，且具有一定的宽度间隔比。
发明内容
本发明至少一实施例提供一种薄膜晶体管阵列基板、其制作方法及显示装置，可以减少薄膜晶体管所在区域的电极层残沙，避免由残沙引起的画面不均的现象。
本发明至少一实施例提供了一种薄膜晶体管阵列基板，包括：衬底基板、设置在所述衬底基板上的栅极、依次设置在所述栅极上的栅极绝缘层和有源层、设置在所述衬底基板上的像素电极、公共电极和透明电极层；其中，所述透明电极层和像素电极同层同材质，或所述透明电极层和公共电极同层同材质；所述透明电极层位于所述栅极绝缘层的正下方；所述有源层在所述衬底基板上的正投影位于所述透明电极层的正投影所在区域内。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层设置在所述衬底基板和所述栅极之间；或，所述透明电极层设置在所述 栅极和所述栅极绝缘层之间。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述衬底基板和所述栅极之间设置有缓冲层；所述透明电极层设置在所述衬底基板和所述缓冲层之间。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板还可以包括：设置在所述透明电极层上的多条栅线，每条所述栅线的一部分作为所述栅极。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述栅线在所述衬底基板上的正投影与所述透明电极层的正投影相互重叠。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述薄膜晶体管阵列基板中的像素电极位于公共电极的上方，其中，所述公共电极为板状电极。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述薄膜晶体管阵列基板中的像素电极位于公共电极的下方，其中，所述像素电极为板状电极。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层的材料为氧化铟锡、氧化铟锌或氧化铟镓锌其中之一或组合。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层为具有矩形形状的板状电极。
例如，在本发明实施例提供的上述薄膜晶体管阵列基板中，所述透明电极层的厚度为
Figure PCTCN2016070257-appb-000001
至
Figure PCTCN2016070257-appb-000002
本发明至少一实施例还提供了一种本发明实施例提供的上述薄膜晶体管阵列基板的制作方法，包括：通过同一构图工艺在衬底基板上形成像素电极和透明电极层的图形，或通过同一构图工艺在衬底基板上形成公共电极和透明电极层的图形；在衬底基板上形成栅极的图形；在形成有所述栅极图形的衬底基板上依次形成栅极绝缘层和有源层的图形；所述透明电极层图形位于所述栅极绝缘层图形的下方；所述有源层图形在所述衬底基板上的正投影位于所述透明电极层图形的正投影所在区域内。
本发明至少一实施例还提供了一种显示装置，包括本发明实施例提供的上述薄膜晶体管阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为一种薄膜晶体管阵列基板的俯视图；
图1b为图1a沿A-A’方向的剖面结构示意图；
图2a为本发明一实施例提供的一种薄膜晶体管阵列基板的俯视图；
图2b至图2d分别为在各个实施例中图2a沿B-B’方向的剖面结构示意图；
图2e为图2a中沿C-C’方向的剖面结构示意图；
图2f为图2e所示的实施例一种变型；
图3a为本发明另一实施例提供的一种薄膜晶体管阵列基板的俯视图；
图3b为图3a沿C-C’方向的剖面结构示意图；
图4为本发明一实施例提供的一种薄膜晶体管阵列基板的制作方法流程图；
图5a至图5f分别为本发明一实施例提供的薄膜晶体管阵列基板的制作方法在各步骤执行后的结构示意图。
附图标记说明：
1、衬底基板；2、栅线；3、透明电极层；4、有源层；5、源极；6、漏极；7、公共电极；8、公共电极线；9、数据扫描线；10、过孔；11、连接孔；12、像素电极；13、导电连接层；20、栅极；30、栅绝缘层；40、缓冲层；50、钝化层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
附图中各膜层的厚度和形状不反映薄膜晶体管阵列基板的真实比例，目 的只是示意说明本发明内容。
发明人发现，ADS产品在生产过程中易发生污渍状画面不均，严重影响产品的良率。经分析，不良的发生机理为：与板状电极层(如公共电极)残沙(即刻蚀后残留的少量电极层材料)相关，如图1a和图1b所示，残沙严重区域容易引起薄膜晶体管中的有源层01弯曲不平整，造成薄膜晶体管特性Ioff偏大，漏电严重，引起画面不均。
本发明至少一实施例提供了一种薄膜晶体管阵列基板，如图2a至图2d所示，该薄膜晶体管阵列基板包括：衬底基板1、设置在衬底基板1上的栅极20以及依次设置在栅极上的栅极绝缘层30和有源层4；如图所示，该阵列基板包括多条水平延伸的栅线2和多条竖直延伸的数据线9，它们彼此交叉限定了多个像素单元，每个像素单元包括像素电极12和作为开关元件的薄膜晶体管。薄膜晶体管具有栅极、源极、漏极、有源层、栅绝缘层，栅绝缘层夹置在栅极和有源层之间，而源极和漏极与有源层接触，且二者之间限定了沟道区，沟道区与栅极对应。栅极可以与栅线电连接或为栅线的一部分(图中所示的实施例为栅线的一部分)，源极和漏极之一根据需要与数据线电连接或为数据线的一部分，而另一个则与像素电极相电连接。
相应地，该薄膜晶体管阵列基板还包括：设置在衬底基板1上的像素电极12、公共电极7和透明电极层3；其中，透明电极层3和像素电极同层同材质；或，透明电极层3和公共电极同层同材质；透明电极层3位于栅极绝缘层30的下方；该有源层4在衬底基板1上的正投影位于透明电极层3的正投影所在区域内。
在本发明实施例提供的上述薄膜晶体管阵列基板中，由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，可以减少薄膜晶体管所在区域的电极层残沙，使有源层的表面平整，避免由残沙引起的画面不均的现象。该实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，如图2b所示，透明电极层3可以设置在栅极20和衬底基板1之间；或，如图2c所示，透明电极层3可以设置在栅极20和栅极绝缘层30之间。而且，如图2b和2c所示，钝化层50覆盖在薄膜晶体管(包括源极5、漏极6)之上。 例如在该钝化层50上形成像素电极12(参见图2e)，或者像素电极也可以形成在栅极绝缘层30之上而在钝化层50之下。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，为了提高衬底基板与衬底基板上金属膜层的附着性，还可以在衬底基板与栅极之间设置缓冲层，此时，如图2d所示，透明电极层3也可以设置在衬底基板1和缓冲层40之间。在具体实现过程中，所述透明电极层的位置不限于本发明附图中涉及到的位置，在此不作限定。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，如图2a至图2d所示，该薄膜晶体管阵列基板还包括：设置在透明电极层3上的多条栅线2，每条栅线2的一部分作为薄膜晶体管中的栅极20，这样可以简化工艺，节省成本。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，当每条栅线的一部分作为薄膜晶体管中的栅极时，为了减少一次掩膜板进行构图工艺的使用，具体地，如图3a和图3b所示，可以将栅线在衬底基板上的正投影与透明电极层的正投影相互重叠，这样在制备薄膜晶体管阵列基板时不需要增加额外的制备工序，在衬底基板上沉积电极层薄膜和金属层薄膜之后，只需通过一次构图工艺(如半透膜掩膜工艺或单狭缝掩膜工艺)就可以形成透明电极层和栅线的图形，进而可以简化工艺，降低成本。为了不影响显示效果，如图3b所示，透明电极层3可以设置在栅线2和衬底基板1之间。
例如，在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板可以应用于高级超维场开关(Advanced-super Dimension Switch，ADS)型液晶面板中，例如，在薄膜晶体管阵列基板中的公共电极作为板状电极位于下层(更靠近衬底基板)，像素电极作为狭缝电极位于上层(更靠近液晶层)，如图2e所示，即像素电极12位于公共电极7的上方，在像素电极12和公共电极7之间设有绝缘层；此时，公共电极与透明电极层可以同层设置。这样，在制备薄膜晶体管阵列基板时不需要增加额外的制备工序，只需要通过同一构图工艺即可形成公共电极和透明电极层的图形，能够节省制备成本，提升产品附加值，并且可以减少薄膜晶体管所在区域的公共电极层残沙，避免由残沙引起的画面不均的现象。
例如，在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板 还可以应用于超高级超维场开关(High Advanced-super Dimension Switch，HADS)型液晶面板中，在薄膜晶体管阵列基板中的像素电极作为板状电极位于下层(更靠近衬底基板)，公共电极作为狭缝电极位于上层(更靠近液晶层)，如图2f所示，即像素电极12位于公共电极7的下方，在像素电极12和公共电极7之间设有绝缘层；此时，像素电极与透明电极层可以同层设置，这样，在制备薄膜晶体管阵列基板时不需要增加额外的制备工序，只需要通过同一构图工艺即可形成像素电极和透明电极层的图形，能够节省制备成本，提升产品附加值，并且可以减少薄膜晶体管所在区域的像素电极层残沙，避免由残沙引起的画面不均的现象。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，例如，透明电极层的材料可以为氧化铟锡、氧化铟锌或氧化铟镓锌其中之一或组合。合理选择上述透明电极层的材料，可以进一步实现薄膜晶体管所在区域不会产生电极层残沙的作用。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，例如，透明电极层可以设置为具有矩形形状的板状电极，使刻蚀工艺简单化。对于透明电极层的形状也可以设置为其他规则图形，只需满足有源层在衬底基板上的正投影位于透明电极层的正投影所在区域内即可。
在具体实施时，在本发明实施例提供的上述薄膜晶体管阵列基板中，例如，透明电极层的厚度可以设置为
Figure PCTCN2016070257-appb-000003
至
Figure PCTCN2016070257-appb-000004
进一步保证薄膜晶体管所在区域不会产生电极层残沙。
在具体实施时，本发明实施例提供的薄膜晶体管阵列基板中一般还会具有诸如栅绝缘层、欧姆接触层和钝化层等其他膜层结构，以及在衬底基板上还一般形成有公共电极线、数据线等结构，这些具体结构可以有多种实现方式，在此不做限定。
本发明至少一实施例还提供了一种本发明实施例提供的上述薄膜晶体管阵列基板的制作方法，由于该方法解决问题的原理与前述一种薄膜晶体管阵列基板相似，因此该方法的实施可以参见薄膜晶体管阵列基板的实施，重复之处不再赘述。
在具体实施时，本发明实施例提供的薄膜晶体管阵列基板的制作方法，如图4所示，例如包括以下步骤：
S401、通过同一构图工艺在衬底基板上形成像素电极和透明电极层的图形；或，通过同一构图工艺在衬底基板上形成公共电极和透明电极层的图形；
S402、在衬底基板上形成栅极的图形；
S403、在形成有栅极图形的衬底基板上依次形成栅极绝缘层和有源层的图形；透明电极层图形位于栅极绝缘层图形的下方；有源层图形在衬底基板上的正投影位于透明电极层图形的正投影所在区域内。
需要说明的是，上述步骤S401和步骤S402可以互换，当透明电极层位于栅极下方时，首先执行步骤S401，然后执行步骤S402；当透明电极层位于栅极和栅极绝缘层之间时，首先执行步骤S402，然后执行步骤S401。在步骤S402之中，在形成栅极的同时可以一并形成与之电连接的栅线。
在本发明实施例提供的上述薄膜晶体管阵列基板的制作方法中，由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，且有源层图形在衬底基板上的正投影位于透明电极层图形的正投影所在区域内，可以减少薄膜晶体管所在区域的电极层残沙，避免由残沙引起的画面不均的现象。该实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。
下面以一个具体的实例详细的说明本发明实施例提供的薄膜晶体管阵列基板的制作方法，具体步骤如下：
步骤一、通过同一构图工艺在衬底基板上形成包括公共电极和透明电极层的图形，如图5a所示；例如，在衬底基板上通过溅射或热蒸发等方法沉积一层厚度约为
Figure PCTCN2016070257-appb-000005
至
Figure PCTCN2016070257-appb-000006
的电极层薄膜，电极层薄膜的材质可以包括氧化铟锡ITO、或者氧化铟锌IZO、或者其它金属及金属氧化物；通过一次曝光、湿法刻蚀工艺，形成公共电极7和透明电极层3的图形，其中，薄膜晶体管对应的区域需保留电极层薄膜用来作为透明电极层3。
步骤二、在形成有公共电极和透明电极层图形的衬底基板上形成栅线的图形，如图5b所示；例如，在上述衬底基板上通过溅射或热蒸发等方法，沉积一层缓冲层薄膜和金属层薄膜，缓冲层薄膜的厚度约为
Figure PCTCN2016070257-appb-000007
至
Figure PCTCN2016070257-appb-000008
缓冲层薄膜的材质可以包括金属Ta、Cr、Mo、W、Nb等金属或者合金，或者透明导电薄膜；金属层薄膜的厚度约为
Figure PCTCN2016070257-appb-000009
至
Figure PCTCN2016070257-appb-000010
材质可以为铝或者铜，对金属层薄膜进行涂光刻胶、曝光、显影和湿法刻蚀及剥离工艺得 到栅线2和公共电极线8(连接下层公共电极)等对应的图形；其中，每条栅线2图形的一部分作为薄膜晶体管中的栅极。
步骤三、在栅极图形上方依次形成栅极绝缘层和有源层的图形，如图5c所示；例如，在完成步骤二的衬底基板上通过PECVD等方法依次沉积栅极绝缘层、有源层4、欧姆接触层的薄膜；栅绝缘层薄膜的厚度具体可为
Figure PCTCN2016070257-appb-000011
至
Figure PCTCN2016070257-appb-000012
材质具体可以包括氮化物SiNx或者氮氧化合物SiOxNx，或者是氮化物SiNx和氮氧化合物SiOxNx的复合物等；有源层4薄膜的厚度具体可为
Figure PCTCN2016070257-appb-000013
至
Figure PCTCN2016070257-appb-000014
欧姆接触层薄膜的厚度具体可为
Figure PCTCN2016070257-appb-000015
至
Figure PCTCN2016070257-appb-000016
然后通过涂光刻胶、曝光、显影和干法刻蚀及剥离工艺形成薄膜晶体管的沟道；其中，有源层4在衬底基板上的正投影面积稍小于透明电极层3的正投影面积。
步骤四、在形成有源层图形的衬底基板上形成源极和漏极的图形，如图5d所示；例如，在完成步骤三的衬底基板上通过溅射或热蒸发的方法依次沉积上厚度约为
Figure PCTCN2016070257-appb-000017
至1000A的金属Ta、Cr、Mo、W、Nb等金属或合金、或者透明导电薄膜作为缓冲层；然后再沉积厚度约为
Figure PCTCN2016070257-appb-000018
的金属层(材质可以为铝或者铜)，或由多层金属形成源漏极金属层；然后通过涂光刻胶、曝光、显影和湿法刻蚀及剥离工艺得到源极5、漏极6和数据扫描线9的图形。
步骤五、在形成包括源极和漏极图形的衬底基板上形成具有过孔的钝化层的图形，如图5e所示；例如，在完成步骤四的衬底基板上通过PECVD等方法沉积厚度约为
Figure PCTCN2016070257-appb-000019
的钝化层，钝化层的材质具体可以包括氧化物、氮化物或者氧氮化合物等；然后通过涂光刻胶、曝光、显影和干法刻蚀及剥离工艺在钝化层形成像素区域的过孔10(去除钝化层)，以及形成连接上下公共电极7(公共电极线8)的连接孔11(去除钝化层和栅极绝缘层)。
步骤六、在形成钝化层图形的衬底基板上形成像素电极的图形，如图5f所示；例如，在完成步骤五的衬底基板上通过溅射或热蒸发等方法沉积一层厚度约为
Figure PCTCN2016070257-appb-000020
的透明导电层，透明导电层的材质具体可以包括ITO、或者IZO、或者其它金属及金属氧化物；然后通过一次曝光、刻蚀工艺，形成像素电极12以及连接上下公共电极7(公共电极线8)的导电连接层13。
需要说明的是，上述制作工艺采用了六次曝光工艺形成的，此外还可以采用五次曝光工艺制作。即：执行步骤三时，通过形成PECVD等方法依次沉积栅绝缘层、有源层、欧姆接触层的薄膜之后，不进行曝光和刻蚀工艺，而是通过溅射或热蒸发的方法依次沉积缓冲层和金属层；后续，可采用半色调或灰色调掩模板曝光显影工艺，经过多步刻蚀之后形成栅绝缘层、半导体层、欧姆接触层以及源漏极金属层对应的图形，例如薄膜晶体管的沟道、源极、漏极和数据线。
至此，经过上述所述步骤一至六制作出了本发明至少一实施例提供的上述薄膜晶体管阵列基板。
本发明至少一实施例还提供了一种显示装置，包括本发明上述实施例提供的所述薄膜晶体管阵列基板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。该显示装置的实施可以参见上述薄膜晶体管阵列基板的实施例，重复之处不再赘述。
本发明实施例提供的一种薄膜晶体管阵列基板、其制作方法及显示装置，该薄膜晶体管阵列基板包括：衬底基板、设置在衬底基板上的栅极、依次设置在栅极上的栅极绝缘层和有源层、设置在衬底基板上的像素电极、公共电极和透明电极层；其中，透明电极层和像素电极/公共电极同层同材质；透明电极层位于栅极绝缘层的下方；有源层在衬底基板上的正投影位于透明电极层的正投影所在区域内。由于薄膜晶体管中的有源层正下方设置有与像素电极或公共电极同层同材质的透明电极层，可以减少薄膜晶体管所在区域的电极层残沙，使有源层的表面平整，避免由残沙引起的画面不均的现象，实现方法简单，且对栅极电阻的影响较小，可以提升产品品质。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年8月21日递交的中国专利申请第201510518773.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (14)

  1. 一种薄膜晶体管阵列基板，包括：
    衬底基板，
    设置在所述衬底基板上的栅极，
    依次设置在所述栅极上的栅极绝缘层和有源层，以及
    设置在所述衬底基板上的像素电极、公共电极和透明电极层；其中，
    所述透明电极层和像素电极同层同材质，或所述透明电极层和公共电极同层同材质；
    所述透明电极层位于所述栅极绝缘层的下方；
    所述有源层在所述衬底基板上的正投影位于所述透明电极层的正投影所在区域内。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述透明电极层设置在所述衬底基板和所述栅极之间；或，
    所述透明电极层设置在所述栅极和所述栅极绝缘层之间。
  3. 如权利要求1或2所述的薄膜晶体管阵列基板，其中，所述衬底基板和所述栅极之间设置有缓冲层；
    所述透明电极层设置在所述衬底基板和所述缓冲层之间。
  4. 如权利要求1-3任一项所述的薄膜晶体管阵列基板，还包括：设置在所述透明电极层上的多条栅线，每条所述栅线的一部分作为所述栅极。
  5. 如权利要求4所述的薄膜晶体管阵列基板，其中，所述栅线在所述衬底基板上的正投影与所述透明电极层的正投影相互重叠。
  6. 如权利要求1-5任一项所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板中的像素电极位于公共电极的上方，其中，所述公共电极为板状电极。
  7. 如权利要求1-5任一项所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板中的像素电极位于公共电极的下方，其中，所述像素电极为板状电极。
  8. 如权利要求1-7任一项所述的薄膜晶体管阵列基板，其中，所述透明电极层的材料为氧化铟锡、氧化铟锌或氧化铟镓锌其中之一或组合。
  9. 如权利要求1-7任一项所述的薄膜晶体管阵列基板，其中，所述透明电极层为具有矩形形状的板状电极。
  10. 如权利要求1-7任一项所述的薄膜晶体管阵列基板，其中，所述透明电极层的厚度为
    Figure PCTCN2016070257-appb-100001
    至
    Figure PCTCN2016070257-appb-100002
  11. 一种显示装置，包括如权利要求1-10任一项所述的薄膜晶体管阵列基板。
  12. 一种薄膜晶体管阵列基板的制作方法，包括：
    通过同一构图工艺在衬底基板上形成像素电极和透明电极层的图形；或，通过同一构图工艺在衬底基板上形成公共电极和透明电极层的图形；
    在所述衬底基板上形成栅极的图形；
    在形成有所述栅极图形的衬底基板上依次形成栅极绝缘层和有源层的图形；所述透明电极层图形位于所述栅极绝缘层图形的下方；所述有源层图形在所述衬底基板上的正投影位于所述透明电极层图形的正投影所在区域内。
  13. 根据权利要求12的制作方法，还包括：在所述有源层之上形成与所述有源层接触的源极和漏极以及与所述源极和漏极之一电连接的数据线。
  14. 根据权利要求13的制作方法，还包括：形成与所述源极和漏极中另一个电连接的像素电极。
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