WO2020113622A1 - Tft基板的制作方法及tft基板 - Google Patents

Tft基板的制作方法及tft基板 Download PDF

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Publication number
WO2020113622A1
WO2020113622A1 PCT/CN2018/120417 CN2018120417W WO2020113622A1 WO 2020113622 A1 WO2020113622 A1 WO 2020113622A1 CN 2018120417 W CN2018120417 W CN 2018120417W WO 2020113622 A1 WO2020113622 A1 WO 2020113622A1
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layer
gate
active layer
tft substrate
contact region
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PCT/CN2018/120417
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English (en)
French (fr)
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赵振宇
李威
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武汉华星光电半导体显示技术有限公司
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Priority to US16/344,099 priority Critical patent/US20210005757A1/en
Publication of WO2020113622A1 publication Critical patent/WO2020113622A1/zh

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/383—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a gaseous phase
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of display technology, and in particular, to a method for manufacturing a TFT substrate and a TFT substrate.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • the display panel is an important part of LCD and OLED. Whether it is an LCD display panel or an OLED display panel, it usually has a thin film transistor (Thin Film Transistor, TFT) substrate.
  • TFT Thin Film Transistor
  • a LCD display panel mainly includes a TFT substrate, a color filter substrate (Color Filter, CF), and a liquid crystal layer (Liquid) disposed between the two substrates Crystal Layer), its working principle is to control the rotation of liquid crystal molecules in the liquid crystal layer by applying a driving voltage on the TFT substrate and the CF substrate to refract the light of the backlight module to generate the picture.
  • TFT substrates are mainly divided into: Coplanar type, Etch Stop Layer (ESL) type, Back Channel Etch (BCE) type, etc. according to the structure type .
  • ESL Etch Stop Layer
  • BCE Back Channel Etch
  • Indium gallium zinc oxide has become a research hotspot in the field of thin film transistor technology due to its advantages of high mobility, suitable for large-area production, and easy conversion from amorphous silicon (a-Si) process.
  • IGZO active layer in IGZO-TFT is very sensitive to the process and environment. Therefore, IGZO-TFT usually adopts ESL structure. The IGZO active layer is protected by etching the ESL and adding a mask to protect the IGZO active layer.
  • the existing ESL type TFT substrate includes a substrate 100, a gate 200, a gate insulating layer 300, an oxide semiconductor layer 400, an etch barrier 500, a source 610, and a drain that are sequentially disposed on the substrate 100
  • the ESL type TFT substrate shown in FIG. 1 uses an etch barrier layer 500 to avoid channel damage, but the addition of an etch barrier layer 500 also increases the channel length of the TFT.
  • oxide semiconductor materials such as IGZO/IGSO (Indium Gallium Selenium Oxide) are generally used as channel substrates because of their high electron mobility and are suitable for large-scale production. In order to obtain higher resolution, greater aperture ratio, and lower power consumption, the panel is required to obtain a larger OLED drive current at a lower drive turn-on voltage.
  • the object of the present invention is to provide a method for manufacturing a TFT substrate, which adopts a double-gate structure and forms a series structure of TFT channels in the original channel region through the diffusion and doping of hydrogen atoms in the silicon nitride layer to reduce the channels on both sides Impedance, equivalently shorten the original channel length, realize the double TFT structure, save costs, in actual use can effectively save space and optimize the space layout.
  • the object of the present invention is also to provide a TFT substrate with a double gate structure, through the diffusion and doping of hydrogen atoms in the silicon nitride layer, to form a TFT channel series structure in the original channel region, to reduce the channel impedance on both sides, Equivalently shorten the original channel length, realize the double TFT structure, save costs, in actual use can effectively save space and optimize the space layout.
  • the present invention provides a method for manufacturing a TFT substrate, including the following steps:
  • Step S1 providing a base substrate, forming spaced first and second gates on the base substrate, and depositing and forming gates on the first gate, the second gate and the base substrate An electrode insulating layer, deposited and patterned on the gate insulating layer to form an active layer corresponding to the first gate and the second gate;
  • Step S2 an etching barrier layer is deposited on the active layer and the gate insulating layer, the etching barrier layer includes a silicon nitride layer, and when the silicon nitride layer of the etching barrier layer is deposited, the silicon nitride layer Hydrogen atoms in the layer will diffuse into the active layer, thereby reducing the impedance of the active layer;
  • Step S3 deposit and pattern on the etch barrier layer to form a source electrode and a drain electrode.
  • a plasma chemical vapor deposition method is used to deposit a silicon nitride layer forming the etching barrier layer.
  • the active layer is deposited by plating sputtering, and the material of the active layer is a metal oxide semiconductor material.
  • the step S1 further includes performing plasma doping treatment on both sides of the active layer, so that the conductivity of the two sides is enhanced to form a source contact region and a drain contact region at both ends, the source electrode The region between the contact region and the drain contact region is formed as a channel region;
  • the step S2 further includes patterning the etch barrier layer, the etch barrier layer forming a first via hole and a second via hole respectively over the source contact region and the drain contact region corresponding to the active layer hole;
  • the source electrode and the drain electrode are in contact with the source contact region and the drain contact region through the first via hole and the second via hole, respectively.
  • the etch stop layer further includes a silicon oxide layer between the silicon nitride layer and the active layer.
  • the voltages on the first gate and the second gate are independently controlled.
  • the present invention also provides a TFT substrate, including: a base substrate, spaced first and second gates provided on the base substrate, and provided on the first gate and the second gate And the gate insulating layer on the base substrate, the active layer provided on the gate insulating layer and corresponding to the first gate and the second gate, and the etching provided on the active layer A barrier layer and source and drain electrodes provided on the etching barrier layer;
  • the etching barrier layer includes a silicon nitride layer, and hydrogen atoms in the silicon nitride layer will diffuse into the active layer, thereby reducing the impedance of the active layer.
  • the material of the active layer is a metal oxide semiconductor
  • the regions on both sides of the active layer are respectively a source contact region and a drain contact region with enhanced conductivity through plasma doping treatment, and a region between the source contact region and the drain contact region on the active layer Is the channel region;
  • the etch barrier layer is respectively provided with a first via hole and a second via hole corresponding to the source contact region and the drain contact region of the active layer, and the source electrode and the drain electrode respectively pass through the first via hole and the second via hole
  • the two vias are in contact with the source contact region and the drain contact region.
  • the etch stop layer further includes a silicon oxide layer between the silicon nitride layer and the active layer.
  • the voltages on the first gate and the second gate are independently controlled.
  • the method for manufacturing a TFT substrate of the present invention forms a first gate and a second gate separated on a base substrate, and a double gate structure is formed by using the first gate and the second gate, Then, a gate insulating layer, an active layer, an etch barrier layer and a source/drain electrode are sequentially formed.
  • the etch barrier layer includes a silicon nitride layer.
  • the hydrogen atoms in the silicon nitride layer will Diffusion into the active layer, forming doping in the active layer, hydrogen atoms as a donor to provide a large number of electrons, so that the electron mobility of the low-impedance channel region increases and the impedance further decreases, thereby forming a TFT trench in the original channel region
  • the channel series structure reduces the channel impedance on both sides, equivalently shortens the channel length, improves the electron mobility, and reduces power consumption. Without changing the yellow light process equipment, through the ion diffusion doping, the double The TFT structure saves costs. In actual use, it can effectively save space and optimize the space layout.
  • the TFT substrate of the present invention adopts a double-gate structure.
  • a TFT channel series structure is formed in the original channel region, which reduces the channel impedance on both sides and shortens the equivalent
  • the channel length improves the electron mobility and reduces power consumption.
  • the dual TFT structure can be realized by ion diffusion doping without changing the yellow light process equipment, which saves costs. In actual use, it can effectively save space and optimize the space layout. .
  • FIG. 1 is a schematic structural diagram of an existing ESL type TFT substrate
  • FIG. 2 is a schematic flow chart of the method for manufacturing a TFT substrate of the present invention
  • step S1 of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S1 of the method for manufacturing a TFT substrate of the present invention
  • step S2 is a schematic diagram of step S2 of the method for manufacturing a TFT substrate of the present invention.
  • step S3 of the manufacturing method of the TFT substrate of the present invention is a schematic diagram of step S3 of the manufacturing method of the TFT substrate of the present invention and a schematic structural diagram of the TFT substrate of the present invention
  • FIG. 6 is a schematic top view of the TFT substrate of the present invention.
  • FIG. 7 is a circuit diagram of the TFT substrate of the present invention.
  • the present invention first provides a TFT
  • the manufacturing method of the substrate includes the following steps:
  • a base substrate is provided 10 , In the base substrate 10 Forming spaced-apart first gates twenty one And the second gate twenty two , At the first gate twenty one , Second grid twenty two And substrate 10 Deposited on top to form gate insulating layer 30 , In the gate insulating layer 30 Deposited on and patterned corresponding to the first gate twenty one And the second gate twenty two Active layer above 40 , For the active layer 40 The areas on both sides are plasma doped to increase the conductivity of the areas on both sides, forming source contact regions at both ends 41 And drain contact 42 , The source contact area 41 And drain contact 42 The region between them is formed as the channel region 43 .
  • the first gate twenty one And the second gate twenty two The material is a metal material, such as one or more alloys of molybdenum, aluminum, copper, and titanium.
  • the steps S1 In the patterning to form the first gate twenty one , Second grid twenty two And active layer 40 The processes include: a photoresist coating step, an exposure step, a development step, an etching step, and a photoresist removal step; wherein, for the first gate twenty one And the second gate twenty two
  • the etching step is a wet etching step, for the active layer 40
  • the etching step is a dry etching step.
  • the material is indium gallium zinc oxide or metal oxide semiconductor materials such as indium gallium selenium oxide.
  • the gate insulating layer 30 Of materials include silicon oxide ( SiOx ) And silicon nitride ( SiNx ) One or a combination of both.
  • the gate insulating layer 30 The material is silicon oxide.
  • the active layer is deposited by electroplating and sputtering 40 .
  • the steps S1 In the active layer 40 On both sides of the N Type plasma doping treatment, ie the source contact area 41 And drain contact 42 All via N Type plasma doped and conductive n+IGZO region.
  • step S2 As shown 3 As shown in the active layer 40 And gate insulation 30 Deposition to form an etch barrier 50 , The etch barrier 50 Including silicon nitride layer 51 , When depositing the etch barrier 50 Silicon nitride layer 51 The silicon nitride layer 51 The hydrogen atoms in will diffuse into the active layer 40 In order to reduce the active layer 40 The impedance.
  • the steps S2 In the plasma chemical vapor deposition method Plasma Enhanced Chemical Vapor Deposition , PECVD ) Deposition to form the etch barrier 50 Silicon nitride layer 51
  • the silicon nitride layer 51 The hydrogen atoms in will diffuse into the active layer 40 Medium, hydrogen atoms as a donor provide a large number of electrons, making the original low-impedance channel region 43 The electron mobility increases and the impedance further decreases, so that in the original channel region 43 formed TFT
  • the channel series structure is equivalent to reducing the corresponding first gate twenty one And the second gate twenty two
  • the channel impedance is equivalent to shorten the channel length.
  • the steps S2 also includes the etch stop layer 50 Performing a patterning process, the etching barrier layer 50 Corresponding to the active layer 40 Source contact area 41 And drain contact 42
  • the first vias are formed above 501 , Second via 502 .
  • the etching barrier layer 50 also includes the silicon nitride layer 51 Active layer 40 Silicon oxide layer 52 .
  • step S3 As shown 4 As shown in the etch barrier 50 Deposited and patterned to form the source 61 And drain 62 , The source 61 And drain 62 Through the first via 501 And the second via 502 Contact area with source 41 And drain contact 42 Contact.
  • the invention TFT Substrate manufacturing method, first on the base substrate 10 Forming spaced-apart first gates twenty one And the second gate twenty two , Using the first gate twenty one With the second gate twenty two Form a double gate structure, and then make a gate insulating layer in turn 30 Active layer 40 , Etching barrier 50 Source and drain 61/62 , Where the etch barrier 50 Including silicon nitride layer 51 , When deposited to form the silicon nitride layer 51 The silicon nitride layer 51 The hydrogen atoms in will diffuse into the active layer 40 In the active layer 40 Doping in the formation, hydrogen atoms as a donor to provide a large number of electrons, making the original low-impedance channel region 43 The electron mobility increases and the impedance further decreases, so that in the original channel region 43 form TFT
  • the channel series structure reduces the channel impedance on both sides, as shown in the figure 6 As shown, the channel length is equivalently shortened, where L Is the original channel length, d To increase the
  • the present invention also provides a method for manufacturing a substrate TFT Substrate, including: substrate substrate 10 ⁇ Set on the base substrate 10 The first gate on the interval twenty one And the second gate twenty two , Set on the first gate twenty one , Second grid twenty two And substrate 10 Gate insulating layer 30 , Provided on the gate insulating layer 30 On and corresponding to the first gate twenty one And the second gate twenty two Active layer above 40 , Located in the active layer 40 Etch barrier 50 And provided on the etching barrier layer 50 Source 61 And drain 62 ;
  • the active layer 40 Is made of metal oxide semiconductor; the active layer 40 The areas on both sides of are source contact regions with enhanced conductivity through plasma doping 41 And drain contact 42 , The active layer 40 Upper source contact 41 And drain contact 42 Channel region 43 ;
  • Etch barrier 50 Corresponding to the active layer 40 Source contact area 41 And drain contact 42 With first vias 501 , Second via 502 , The source 61 And drain 62 Through the first via 501 And the second via 502 Contact area with source 41 And drain contact 42 Contact
  • Etch barrier 50 Including silicon nitride layer 51 , The silicon nitride layer 51
  • the hydrogen atoms in will diffuse into the active layer 40 Medium, hydrogen atoms as a donor provide a large number of electrons, making the original low-impedance channel region 43
  • the electron mobility increases and the impedance further decreases, as shown in the figure 6
  • the channel series structure is equivalent to reducing the corresponding first gate twenty one And the second gate twenty two Channel impedance, equivalently shorten the channel length, figure 6 in L Is the original channel length, d To increase the double TFT The equivalent channel length after the structure.
  • the active layer 40 Is a metal oxide semiconductor, preferably IGZO .
  • the etching barrier layer 50 also includes the silicon nitride layer 51 Active layer 40 Silicon oxide layer 52 .
  • the active layer 40 Source contact area 41 And drain contact 42 Via N Type plasma doping treatment, ie the source contact area 41 And drain contact 42 All via N Type plasma doped and conductive n+IGZO region.
  • the first gate twenty one , Second grid twenty two Source 61 And drain 62 The materials are all metal materials, such as one or more alloys of molybdenum, aluminum, copper, and titanium.
  • the invention TFT Substrate, using the first grid twenty one With the second gate twenty two Forming a double gate structure and etching the barrier layer 50 Silicon nitride layer 51 , When deposited to form the silicon nitride layer 51 The silicon nitride layer 51 The hydrogen atoms in will diffuse into the active layer 40 In the active layer 40 Doping in the formation, hydrogen atoms as a donor to provide a large number of electrons, making the original low-impedance channel region 43 The electron mobility increases and the impedance further decreases, so that in the original channel region 43 formed TFT The channel series structure reduces the channel impedance on both sides and shortens the channel length equivalently.
  • the present invention TFT
  • the manufacturing method of the substrate is to form a first gate and a second gate spaced apart on the base substrate, the first gate and the second gate are used to form a double gate structure, and then the gate insulating layer and the active Layer, etch barrier layer and source/drain, wherein the etch barrier layer includes a silicon nitride layer, and when deposited to form the silicon nitride layer, hydrogen atoms in the silicon nitride layer will diffuse into the active layer, where active Doping is formed in the layer, and hydrogen atoms serve as donors to provide a large amount of electrons, which increases the electron mobility of the low-impedance channel region and further reduces the impedance, thereby forming in the original channel region TFT
  • the channel series structure reduces the channel impedance on both sides, equivalently shortens the channel length, improves the electron mobility, and reduces power consumption.
  • TFT The substrate adopts a double-gate structure, which is formed in the original channel region by diffusion and doping of hydrogen atoms in the silicon nitride layer TFT
  • the channel series structure reduces the channel impedance on both sides, equivalently shortens the channel length, improves the electron mobility, and reduces power consumption. It can achieve double-diffusion through ion diffusion doping without changing the yellow light process equipment.
  • TFT Structure, cost saving can effectively save space and optimize space layout in actual use.

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Abstract

本发明提供一种TFT基板的制作方法及TFT基板。本发明的TFT基板的制作方法，采用第一栅极与第二栅极组成双栅极结构，并利用氮化硅层制作蚀刻阻挡层，当沉积形成该氮化硅层时，其中的氢原子会扩散至有源层中，在有源层中形成掺杂，氢原子作为供体提供大量电子，使得低阻抗沟道区的电子迁移率增加，阻抗进一步降低，从而在原有沟道区形成TFT沟道串联结构，降低了两侧沟道阻抗，等效缩短了沟道长度，提高了电子迁移率，降低功耗，在无需改变黄光制程设备的情况下，通过离子扩散掺杂，实现了双TFT结构，节约成本，实际使用中可有效节约空间，优化空间布局。

Description

TFT基板的制作方法及TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及TFT基板。
 背景技术
在显示技术领域，液晶显示器（Liquid Crystal Display，LCD）与有机发光二极管显示器（Organic Light Emitting Diode，OLED）等平板显示器已经逐步取代CRT显示器，广泛的应用于液晶电视、手机、个人数字助理、数字相机、计算机屏幕或笔记本电脑屏幕等。
显示面板是LCD、OLED的重要组成部分。不论是LCD的显示面板，还是OLED的显示面板，通常都具有一薄膜晶体管（Thin Film Transistor，TFT）基板。以LCD的显示面板为例，其主要是由一TFT基板、一彩色滤光片基板（Color Filter，CF）、以及配置于两基板间的液晶层（Liquid Crystal Layer）所构成，其工作原理是通过在TFT基板与CF基板上施加驱动电压来控制液晶层中液晶分子的旋转，将背光模组的光线折射出来产生画面。
目前，现有的TFT基板按结构类型主要分为：共平面（Coplanar）型、具有蚀刻阻挡层（Etch Stop Layer，ESL）型、背沟道蚀刻（Back Channel Etch，BCE）型等多种类型。
铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）由于具有高迁移率、适用于大面积生产、易于由非晶硅（a-Si）制程转换等优势，成为目前薄膜晶体管技术领域内的研究热点。但IGZO-TFT中的IGZO有源层对于工艺和环境非常敏感，因此IGZO-TFT通常采用ESL型结构，通过刻蚀阻挡层ESL并增加一道光罩（Mask）对IGZO有源层进行保护，然而这样就不利于TFT制程成本的降低；同时由于源漏极（SD）与刻蚀阻挡层ESL之间的堆叠，使得TFT器件的沟道尺寸较大，从而造成TFT的导电性能下降。
请参阅图1，现有的ESL型TFT基板包括基板100、依次设于基板100上的栅极200、栅极绝缘层300、氧化物半导体层400、蚀刻阻挡层500、源极610、及漏极620，其中，所述源极610和漏极620分别通过第一过孔510和第二过孔520与氧化物半导体层400相接触。
图1所示的ESL型TFT基板采用蚀刻阻挡层500来避免沟道损伤，但是由于增加了一道蚀刻阻挡层500，也使得TFT的沟道长度随之增加。在大尺寸OLED显示面板中，通常使用IGZO/IGSO（铟镓硒氧化物）这类的氧化物半导体材料作为沟道衬底，因为其拥有较高的电子迁移率，适用于大尺寸生产。为了获得更高的分辨力，更大的开口率，以及更低功耗，要求面板在较低的驱动开启电压下获得更大的OLED驱动电流。一般通过缩短TFT沟道长度可以得到更高的漏极电流（Ids），但是考虑到现实制程能力，TFT沟道长度的缩短严格受限，无法显著改善电流驱动能力，因此通过工艺制程缩短TFT通道长度来改善大尺寸OLED面板的电流驱动能力无法满足现实需要，亟待改进。
 技术问题
本发明的目的在于提供一种TFT基板的制作方法，采用双栅极结构，通过氮化硅层中氢原子的扩散掺杂，在原有沟道区形成TFT沟道串联结构，降低两侧沟道阻抗，等效缩短原沟道长度，实现双TFT结构，节约成本，实际使用中可有效节约空间，优化空间布局。
本发明的目的还在于提供一种TFT基板，采用双栅极结构，通过氮化硅层中氢原子的扩散掺杂，在原有沟道区形成TFT沟道串联结构，降低两侧沟道阻抗，等效缩短原沟道长度，实现双TFT结构，节约成本，实际使用中可有效节约空间，优化空间布局。
 技术解决方案
为实现上述目的，本发明提供一种TFT基板的制作方法，包括以下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成相间隔的第一栅极和第二栅极，在所述第一栅极、第二栅极及衬底基板上沉积形成栅极绝缘层，在所述栅极绝缘层上沉积并图案化形成对应于所述第一栅极和第二栅极上方的有源层；
步骤S2、在所述有源层与栅极绝缘层上沉积形成蚀刻阻挡层，所述蚀刻阻挡层包括氮化硅层，当沉积所述蚀刻阻挡层的氮化硅层时，该氮化硅层中的氢原子会扩散至所述有源层中，从而降低所述有源层的阻抗；
步骤S3、在所述蚀刻阻挡层上沉积并图案化形成源极和漏极。
所述步骤S2中采用等离子化学气相沉积法沉积形成所述蚀刻阻挡层的氮化硅层。
所述步骤S1中采用电镀激溅的方法沉积形成所述有源层，所述有源层的材料为为金属氧化物半导体材料。
所述步骤S1还包括对所述有源层的两侧区域进行等离子掺杂处理，而使得该两侧区域的导电性增强，形成位于两端的源极接触区和漏极接触区，该源极接触区和漏极接触区之间的区域形成为沟道区；
所述步骤S2还包括对所述蚀刻阻挡层进行图案化处理，所述蚀刻阻挡层在对应所述有源层的源极接触区和漏极接触区上方分别形成第一过孔、第二过孔；
所述步骤S3中，所述源极和漏极分别通过第一过孔和第二过孔与源极接触区和漏极接触区相接触。
所述蚀刻阻挡层还包括位于所述氮化硅层与有源层之间的氧化硅层。
所述TFT基板在使用时，所述第一栅极和第二栅极上的电压分别独立控制。
本发明还提供一种TFT基板，包括：衬底基板、设于所述衬底基板上的相间隔的第一栅极和第二栅极、设于所述第一栅极、第二栅极及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上且对应于所述第一栅极和第二栅极上方的有源层、设于所述有源层上的蚀刻阻挡层以及设于所述蚀刻阻挡层上的源极和漏极；
其中，所述蚀刻阻挡层包括氮化硅层，该氮化硅层中的氢原子会扩散至所述有源层中，从而降低所述有源层的阻抗。
所述有源层的材料为金属氧化物半导体；
所述有源层的两侧区域分别为经由等离子掺杂处理而导电性增强的源极接触区和漏极接触区，所述有源层上源极接触区和漏极接触区之间的区域为沟道区；
所述蚀刻阻挡层对应所述有源层的源极接触区和漏极接触区分别设有第一过孔、第二过孔，所述的源极和漏极分别通过第一过孔和第二过孔与源极接触区和漏极接触区相接触。
所述蚀刻阻挡层还包括位于所述氮化硅层与有源层之间的氧化硅层。
所述TFT基板在使用时，所述第一栅极和第二栅极上的电压分别独立控制。
 有益效果
本发明的有益效果：本发明的TFT基板的制作方法，在衬底基板上形成相间隔的第一栅极和第二栅极，采用第一栅极与第二栅极组成双栅极结构，然后依次制作栅极绝缘层、有源层、蚀刻阻挡层及源漏极，其中蚀刻阻挡层包括氮化硅层，当沉积形成该氮化硅层时，该氮化硅层中的氢原子会扩散至有源层中，在有源层中形成掺杂，氢原子作为供体提供大量电子，使得低阻抗沟道区的电子迁移率增加，阻抗进一步降低，从而在原有沟道区形成TFT沟道串联结构，降低了两侧沟道阻抗，等效缩短了沟道长度，提高了电子迁移率，降低功耗，在无需改变黄光制程设备的情况下，通过离子扩散掺杂，实现了双TFT结构，节约成本，实际使用中可有效节约空间，优化空间布局。本发明的TFT基板，采用双栅极结构，通过氮化硅层中氢原子的扩散掺杂，在原有沟道区形成了TFT沟道串联结构，降低了两侧沟道阻抗，等效缩短了沟道长度，提高了电子迁移率，降低功耗，能够在无需改变黄光制程设备的情况下，通过离子扩散掺杂实现双TFT结构，节约成本，实际使用中可有效节约空间，优化空间布局。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有一种ESL型TFT基板的结构示意图；
图2为本发明TFT基板的制作方法的流程示意图；
图3为本发明TFT基板的制作方法的步骤S1的示意图；
图4为本发明TFT基板的制作方法的步骤S2的示意图；
图5为本发明TFT基板的制作方法的步骤S3的示意图暨本发明的TFT基板的结构示意图；
图6为本发明TFT基板的俯视示意图；
图7为本发明TFT基板的电路图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图 1 ，本发明首先提供一种 TFT 基板的制作方法，包括如下步骤：
步骤 S1 、如图 2 所示，提供一衬底基板 10 ，在所述衬底基板 10 上形成相间隔的第一栅极 21 和第二栅极 22 ，在所述第一栅极 21 、第二栅极 22 及衬底基板 10 上沉积形成栅极绝缘层 30 ，在所述栅极绝缘层 30 上沉积并图案化形成对应于所述第一栅极 21 和第二栅极 22 上方的有源层 40 ，对所述有源层 40 的两侧区域进行等离子掺杂处理，而使得该两侧区域的导电性增强，形成位于两端的源极接触区 41 和漏极接触区 42 ，该源极接触区 41 和漏极接触区 42 之间的区域形成为沟道区 43 。
具体地，所述第一栅极 21 和第二栅极 22 的材料为金属材料，例如钼、铝、铜、钛中的一种或多种的合金。
具体地，所述步骤 S1 中，图案化形成第一栅极 21 、第二栅极 22 和有源层 40 的过程均具体包括：光阻涂布步骤、曝光步骤、显影步骤、蚀刻步骤、及光阻去除步骤；其中，对于所述第一栅极 21 和第二栅极 22 的蚀刻步骤为湿法蚀刻步骤，对于有源层 40 的蚀刻步骤为干法蚀刻步骤。
具体地，所述步骤 S1 中所形成的有源层 40 的材料为铟镓锌氧化物，也可以为铟镓硒氧化物等金属氧化物半导体材料。
具体的，所述栅极绝缘层 30 的材料包括氧化硅（ SiOx ）与氮化硅（ SiNx ）中的一种或两者的组合。优选的，所述栅极绝缘层 30 的材料为氧化硅。
具体的，所述步骤 S1 中，采用化学气相沉积（ Chemical Vapor Deposition ， CVD ）的方式沉积得到所述栅极绝缘层 30 。
具体地所述步骤 S1 中采用电镀激溅的方法沉积形成所述有源层 40 。
具体地，所述步骤 S1 中，对所述有源层 40 的两侧区域进行 N 型等离子掺杂处理，即该源极接触区 41 和漏极接触区 42 均为经由 N 型等离子掺杂处理而导体化的 n+IGZO 区域。
步骤 S2 、如图 3 所示，在所述有源层 40 与栅极绝缘层 30 上沉积形成蚀刻阻挡层 50 ，所述蚀刻阻挡层 50 包括氮化硅层 51 ，当沉积所述蚀刻阻挡层 50 的氮化硅层 51 时，该氮化硅层 51 中的氢原子会扩散至所述有源层 40 中，从而降低所述有源层 40 的阻抗。
具体地，所述步骤 S2 中，采用等离子化学气相沉积法（ Plasma Enhanced Chemical Vapor Deposition ， PECVD ）沉积形成所述蚀刻阻挡层 50 的氮化硅层 51 ，此过程中，氮化硅层 51 中的氢原子会扩散至所述有源层 40 中，氢原子作为供体提供大量电子，使得低阻抗的原有沟道区 43 的电子迁移率增加，阻抗进一步降低，从而在原有沟道区 43 形成了 TFT 沟道串联结构，相当于降低了两侧的分别对应第一栅极 21 和第二栅极 22 的沟道阻抗，等效缩短了沟道长度。
具体地，所述步骤 S2 还包括对所述蚀刻阻挡层 50 进行图案化处理，所述蚀刻阻挡层 50 在对应所述有源层 40 的源极接触区 41 和漏极接触区 42 上方分别形成第一过孔 501 、第二过孔 502 。
具体地，所述蚀刻阻挡层 50 还包括位于所述氮化硅层 51 与有源层 40 之间的氧化硅层 52 。
步骤 S3 、如图 4 所示，在所述蚀刻阻挡层 50 上沉积并图案化形成源极 61 和漏极 62 ，所述源极 61 和漏极 62 分别通过第一过孔 501 和第二过孔 502 与源极接触区 41 和漏极接触区 42 相接触。
本发明的 TFT 基板的制作方法，首先在衬底基板 10 上形成相间隔的第一栅极 21 和第二栅极 22 ，采用第一栅极 21 与第二栅极 22 组成双栅极结构，然后依次制作栅极绝缘层 30 、有源层 40 、蚀刻阻挡层 50 及源漏极 61/62 ，其中蚀刻阻挡层 50 包括氮化硅层 51 ，当沉积形成该氮化硅层 51 时，该氮化硅层 51 中的氢原子会扩散至有源层 40 中，在有源层 40 中形成掺杂，氢原子作为供体提供大量电子，使得低阻抗的原有沟道区 43 的电子迁移率增加，阻抗进一步降低，从而在原有沟道区 43 形成 TFT 沟道串联结构，降低了两侧沟道阻抗，如图 6 所示，等效缩短了沟道长度，其中 L 为原有沟道长度， d 为增加双 TFT 结构后的等效通道长度，提高了电子迁移率，降低功耗，在无需改变黄光制程设备的情况下，如图 7 所示的电路图，通过离子扩散掺杂，实现了双 TFT 结构，节约成本，同时两侧通道的第一栅极电压 Vg1 、第二栅极电压 Vg2 独立控制，即双 TFT 结构独立控制，实际使用中可有效节约空间，优化空间布局。
请参阅图 5 ，基于上述的 TFT 基板的制作方法，本发明还提供一种 TFT 基板，包括：衬底基板 10 、设于所述衬底基板 10 上的相间隔的第一栅极 21 和第二栅极 22 、设于所述第一栅极 21 、第二栅极 22 及衬底基板 10 上的栅极绝缘层 30 、设于所述栅极绝缘层 30 上且对应于所述第一栅极 21 和第二栅极 22 上方的有源层 40 、设于所述有源层 40 上的蚀刻阻挡层 50 以及设于所述蚀刻阻挡层 50 上的源极 61 和漏极 62 ；
其中，所述有源层 40 的材料为金属氧化物半导体；所述有源层 40 的两侧区域分别为经由等离子掺杂处理而导电性增强的源极接触区 41 和漏极接触区 42 ，所述有源层 40 上源极接触区 41 和漏极接触区 42 之间的区域为沟道区 43 ；
所述蚀刻阻挡层 50 对应所述有源层 40 的源极接触区 41 和漏极接触区 42 分别设有第一过孔 501 、第二过孔 502 ，所述的源极 61 和漏极 62 分别通过第一过孔 501 和第二过孔 502 与源极接触区 41 和漏极接触区 42 相接触；
所述蚀刻阻挡层 50 包括氮化硅层 51 ，该氮化硅层 51 中的氢原子会扩散至所述有源层 40 中，氢原子作为供体提供大量电子，使得低阻抗的原有沟道区 43 的电子迁移率增加，阻抗进一步降低，如图 6 所示，从而在原有沟道区 43 形成了 TFT 沟道串联结构，相当于降低了两侧的分别对应第一栅极 21 和第二栅极 22 的沟道阻抗，等效缩短了沟道长度，图 6 中 L 为原有沟道长度， d 为增加双 TFT 结构后的等效通道长度。
具体地，所述有源层 40 的材料为金属氧化物半导体，优选为 IGZO 。
具体地，所述蚀刻阻挡层 50 还包括位于所述氮化硅层 51 与有源层 40 之间的氧化硅层 52 。
具体地，所述有源层 40 的源极接触区 41 和漏极接触区 42 均经由 N 型等离子掺杂处理，即该源极接触区 41 和漏极接触区 42 均为经由 N 型等离子掺杂处理而导体化的 n+IGZO 区域。
具体地，所述第一栅极 21 、第二栅极 22 、源极 61 和漏极 62 的材料均为金属材料，例如钼、铝、铜、钛中的一种或多种的合金。
本发明的 TFT 基板，采用第一栅极 21 与第二栅极 22 组成双栅极结构，并在蚀刻阻挡层 50 中设置氮化硅层 51 ，当沉积形成该氮化硅层 51 时，该氮化硅层 51 中的氢原子会扩散至有源层 40 中，在有源层 40 中形成掺杂，氢原子作为供体提供大量电子，使得低阻抗的原有沟道区 43 的电子迁移率增加，阻抗进一步降低，从而在原有沟道区 43 形成了 TFT 沟道串联结构，降低了两侧沟道阻抗，等效缩短了沟道长度， d 为增加双 TFT 结构后的等效通道长度，提高了电子迁移率，降低功耗，在无需改变黄光制程设备的情况下，通过离子扩散掺杂，实现了双 TFT 结构，节约成本，同时两侧通道的第一栅极电压 Vg1 、第二栅极电压 Vg2 独立控制，即双 TFT 结构独立控制，实际使用中可有效节约空间，优化空间布局。以下表一为本发明 TFT 基板的双通道控制开启 / 关闭控制逻辑表。
表一
Figure dest_path_image001
综上所述，本发明的 TFT 基板的制作方法，在衬底基板上形成相间隔的第一栅极和第二栅极，采用第一栅极与第二栅极组成双栅极结构，然后依次制作栅极绝缘层、有源层、蚀刻阻挡层及源漏极，其中蚀刻阻挡层包括氮化硅层，当沉积形成该氮化硅层时，该氮化硅层中的氢原子会扩散至有源层中，在有源层中形成掺杂，氢原子作为供体提供大量电子，使得低阻抗沟道区的电子迁移率增加，阻抗进一步降低，从而在原有沟道区形成 TFT 沟道串联结构，降低了两侧沟道阻抗，等效缩短了沟道长度，提高了电子迁移率，降低功耗，在无需改变黄光制程设备的情况下，通过离子扩散掺杂，实现了双 TFT 结构，节约成本，实际使用中可有效节约空间，优化空间布局。本发明的 TFT 基板，采用双栅极结构，通过氮化硅层中氢原子的扩散掺杂，在原有沟道区形成了 TFT 沟道串联结构，降低了两侧沟道阻抗，等效缩短了沟道长度，提高了电子迁移率，降低功耗，能够在无需改变黄光制程设备的情况下，通过离子扩散掺杂实现双 TFT 结构，节约成本，实际使用中可有效节约空间，优化空间布局。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT基板的制作方法，包括以下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成相间隔的第一栅极和第二栅极，在所述第一栅极、第二栅极及衬底基板上沉积形成栅极绝缘层，在所述栅极绝缘层上沉积并图案化形成对应于所述第一栅极和第二栅极上方的有源层；
    步骤S2、在所述有源层与栅极绝缘层上沉积形成蚀刻阻挡层，所述蚀刻阻挡层包括氮化硅层，当沉积所述蚀刻阻挡层的氮化硅层时，该氮化硅层中的氢原子会扩散至所述有源层中，从而降低所述有源层的阻抗；
    步骤S3、在所述蚀刻阻挡层上沉积并图案化形成源极和漏极。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S2中采用等离子化学气相沉积法沉积形成所述蚀刻阻挡层的氮化硅层。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S1中采用电镀激溅的方法沉积形成所述有源层，所述有源层的材料为为金属氧化物半导体材料。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S1还包括对所述有源层的两侧区域进行等离子掺杂处理，而使得该两侧区域的导电性增强，形成位于两端的源极接触区和漏极接触区，该源极接触区和漏极接触区之间的区域形成为沟道区；
    所述步骤S2还包括对所述蚀刻阻挡层进行图案化处理，所述蚀刻阻挡层在对应所述有源层的源极接触区和漏极接触区上方分别形成第一过孔、第二过孔；
    所述步骤S3中，所述源极和漏极分别通过第一过孔和第二过孔与源极接触区和漏极接触区相接触。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述蚀刻阻挡层还包括位于所述氮化硅层与有源层之间的氧化硅层。
  6. 如权利要求1所述的TFT基板的制作方法，其中，所述TFT基板在使用时，所述第一栅极和第二栅极上的电压分别独立控制。
  7. 一种TFT基板，包括：衬底基板、设于所述衬底基板上的相间隔的第一栅极和第二栅极、设于所述第一栅极、第二栅极及衬底基板上的栅极绝缘层、设于所述栅极绝缘层上且对应于所述第一栅极和第二栅极上方的有源层、设于所述有源层上的蚀刻阻挡层以及设于所述蚀刻阻挡层上的源极和漏极；
    其中，所述蚀刻阻挡层包括氮化硅层，该氮化硅层中的氢原子会扩散至所述有源层中，从而降低所述有源层的阻抗。
  8. 如权利要求7所述的TFT基板，其中，所述有源层的材料为金属氧化物半导体；
    所述有源层的两侧区域分别为经由等离子掺杂处理而导电性增强的源极接触区和漏极接触区，所述有源层上源极接触区和漏极接触区之间的区域为沟道区；
    所述蚀刻阻挡层对应所述有源层的源极接触区和漏极接触区分别设有第一过孔、第二过孔，所述的源极和漏极分别通过第一过孔和第二过孔与源极接触区和漏极接触区相接触。
  9. 如权利要求7所述的TFT基板，其中，所述蚀刻阻挡层还包括位于所述氮化硅层与有源层之间的氧化硅层。
  10. 如权利要求7所述的TFT基板，使用时，所述第一栅极和第二栅极上的电压分别独立控制。
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