WO2015180209A1 - 液晶面板的电路结构及液晶面板的驱动方法 - Google Patents

液晶面板的电路结构及液晶面板的驱动方法 Download PDF

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Publication number
WO2015180209A1
WO2015180209A1 PCT/CN2014/079707 CN2014079707W WO2015180209A1 WO 2015180209 A1 WO2015180209 A1 WO 2015180209A1 CN 2014079707 W CN2014079707 W CN 2014079707W WO 2015180209 A1 WO2015180209 A1 WO 2015180209A1
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Prior art keywords
liquid crystal
electrically connected
transistor
source
gate
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PCT/CN2014/079707
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English (en)
French (fr)
Inventor
朱江
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深圳市华星光电技术有限公司
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Priority to US14/374,517 priority Critical patent/US20150348475A1/en
Publication of WO2015180209A1 publication Critical patent/WO2015180209A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management

Definitions

  • the present invention relates to the field of liquid crystal panels, and in particular to a circuit structure of a liquid crystal panel and a driving method of the liquid crystal panel. Background technique
  • a liquid crystal layer having dielectric anisotropy is formed between an upper substrate and a lower substrate. Thereafter, the density of the electric field formed on the liquid crystal layer is controlled to cause the molecular arrangement of the liquid crystal material to change. Thereby, the amount of light transmitted through the upper substrate as the display surface is adjusted to present an ideal image.
  • a liquid crystal display device includes a liquid crystal panel composed of a plurality of pixels displaying an image, a driving circuit for driving the liquid crystal panel, and a backlight unit that projects light to the liquid crystal panel.
  • An equivalent circuit constituting each pixel of the liquid crystal panel includes gate lines and data lines crossing each other, thin film transistors and pixel electrodes respectively disposed at intersections of the gate lines and the data lines, and liquid crystal capacitors arranged based on the pixel unit and Storage capacitors.
  • LCD TVs are widely used because of their light weight and low power consumption. With the development of the economy, large-size, high-resolution LCD TVs are becoming more and more popular, but as the resolution increases, the number of output channels required by the LCD panel is correspondingly increased. More and more High. Therefore, how to achieve higher resolution by using a driver chip with a smaller number of output channels has become an urgent problem to be solved in the field.
  • Tri-gate (3D transistor) and HSD (Half Source Driving) designs can effectively reduce the number of output channels of the data driver chip.
  • Tri-gate technology is a special stacking architecture that adds a "vertical tail structure" on three sides of the tri-gate conductive via to eliminate excess heat and provide longer battery life for mobile devices through high-combination gate insulators and strained silicon. Better performance.
  • these two technologies respectively increase the number of output channels of the scan driver chip, and the impedances of the pixels from the data drive chip to the liquid crystal panel are also greatly different, resulting in a color shift phenomenon, which seriously affects the screen of the liquid crystal panel. quality. Summary of the invention
  • the object of the present invention is to provide a circuit structure of a liquid crystal panel, which sequentially charges the liquid crystal pixel display elements of the M liquid crystal pixel array regions by sequentially triggering M flip-flops, and does not interfere with each other, thereby greatly reducing data driving control.
  • the number of data signal output channels of the chip effectively improves the color shift phenomenon of the liquid crystal panel.
  • Another object of the present invention is to provide a driving method for a liquid crystal panel, which can achieve a higher resolution by using a driving chip with a smaller number of output channels, and P reduces the cost of a driving chip required for the liquid crystal panel, and effectively improves the cost.
  • the color shift phenomenon of the liquid crystal panel is to provide a driving method for a liquid crystal panel, which can achieve a higher resolution by using a driving chip with a smaller number of output channels, and P reduces the cost of a driving chip required for the liquid crystal panel, and effectively improves the cost.
  • the present invention provides a circuit structure of a liquid crystal panel, comprising: a data driving control chip having n data signal output channels (S1 to S(n)), a row driving scanning chip, and M flip-flops (triggering) 1 to the trigger M and the M flip-flops corresponding to the liquid crystal pixel array area (Section 1 ⁇ Section(M) point clock signal (CLK and common voltage (VCOM); each liquid crystal pixel array area includes: (nxN) Liquid crystal pixels (P ⁇ N scanning signal lines
  • the liquid crystal pixel (P) includes a pixel transistor (Tr) and a pixel electrode (A); the pixel transistor (Tr) has a gate (g X source (s ⁇ drain (d); the pixel electrode (A) - the terminal is electrically connected to the drain (d) of the pixel transistor (Tr), the other end is electrically connected to the common voltage (VCOM); the gate (g) of the pixel transistor (Tr) arranged in the same row and the scanning signal line (Scanl ⁇ Scan(N)) is a common connection in which the source (s) of the pixel transistor (Tr) arranged in the same column and one of the liquid crystal pixel data signal lines (Linel ⁇ Li ne ( n )) are connected in common
  • the row driving scanning chip is electrically connected
  • the scan signal line (Scanl-Scan(N)) is based on the stages of the shift register.
  • the output signal becomes active or inactive.
  • the data driver are located in each of the flip-flop Control chip and corresponding liquid crystal pixel data signal line in the liquid crystal pixel array area
  • the M flip-flops (Trigger 1 to Trigger M) are all controlled by a dot clock signal (CLK) and sequentially triggered.
  • Each of the flip-flops controls the liquid crystal pixel data signal lines (Line1 to Line(n)) in the corresponding liquid crystal pixel array region to be in an on state.
  • the flip-flop controls the data drive control chip to charge the liquid crystal pixels (P) of the respective liquid crystal pixel array regions.
  • the flip-flop includes: a trigger control module and a trigger output module electrically connected to the trigger control module; the trigger control module includes a first transistor (M1), a second transistor (M2), and a third transistor ( M3 fourth transistor (M4), and capacitor (C1); said first The transistor (M1) includes a first gate (gl X first source (si) and a first drain (dl), and the second transistor (M2) includes a second gate (g2 second source (s2) And a second drain (d2), the third transistor (M3) includes a third gate (g3 third source (S3) and a third drain (d3), and the fourth transistor (M4) includes a four-gate (g4 fourth source (s4) and a fourth drain (d4); the flip-flop output module includes n output transistors (T1 TT(n)), the output transistors ( ⁇ 1 ⁇ ( ⁇ )) having a gate ( g1 , ⁇ gn, a source ( S1 , ⁇ sn), and a drain (d
  • the drain of the fourth (d4) is electrically connected to a negative power supply (Vss), said second gate (g 2) and the fourth gate (g 4) electrically After the connection, the (m+1)th pulse signal output terminal Out(m+l) is formed, the capacitor The C1)-terminal is electrically connected to the intersection (al) formed by the first drain (dl) electrically connected to the second source (s2) and connected to the third gate (g3), and the capacitance (C1) The other end is electrically connected to the third drain (d3) and the fourth source (s4) to form an mth pulse signal output terminal Out(m), and the gates of the n output crystals T1 to Tn) (gl '-gn' is electrically connected to the mth pulse signal output terminal Out(m), and the sources ( S1 , ⁇ sn, ) of the n output transistors (T1 ⁇ Tn) are correspondingly electrically connected to the data Driving the data signal output channel (S1 to S
  • the invention also provides a circuit structure of a liquid crystal panel, comprising: a data driving control chip with n data signal output channels, a row driving scanning chip, M flip-flops, M liquid crystal pixel arrays corresponding to M flip-flops ⁇ , dot clock signal, and common voltage;
  • Each of the liquid crystal pixel array regions includes: (nxN) liquid crystal pixels, N scanning signal lines, and n liquid crystal pixel data signal lines; the liquid crystal pixels are arranged in a row in the row direction, and N in the column direction;
  • the liquid crystal pixel includes a pixel transistor and a pixel electrode; the pixel transistor has a gate, a source, and a drain; one end of the pixel electrode is electrically connected to a drain of the pixel transistor, and the other end is electrically connected to a common voltage;
  • the gates of the pixel transistors in the same row are connected in common to one of the scanning signal lines, and the sources of the pixel transistors arranged in the same column are connected in common to one of the liquid crystal pixel data signal lines;
  • the row driving scanning chip is electrically connected to the scanning signal line, and the row driving scanning chip selectively activates the scanning signal line;
  • Each of the flip-flops is located between the data driving control chip and the liquid crystal pixel data signal line in the corresponding liquid crystal pixel array region, and is electrically connected to each data signal output channel and the dot clock signal of the data driving control chip. And corresponding liquid crystal pixels in the liquid crystal pixel array region a data signal line; the data signal output channel is electrically connected to the liquid crystal pixel data signal line in the corresponding liquid crystal pixel array area;
  • the M triggers are sequentially connected to each other, and the M triggers are controlled by a dot clock signal, and are sequentially triggered;
  • each of the flip-flops controls the liquid crystal pixel data signal lines in the corresponding liquid crystal pixel array area to be in an on state
  • the trigger control data driving control chip charges the liquid crystal pixels of each liquid crystal pixel array region
  • the trigger includes: a trigger control module and a trigger output module electrically connected to the trigger control module;
  • the trigger control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, And a capacitor;
  • the first transistor includes a first gate, a first source, and a first drain, and the second transistor includes a second gate, a second source, and a second drain, the third transistor a third gate, a third source, and a third drain, the fourth transistor includes a fourth gate, a fourth source, and a fourth drain;
  • the flip-flop output module includes n output transistors, The output transistor has a gate, a source and a drain;
  • the first gate is electrically connected to the first source to form an (m-1)th pulse signal output terminal Out(ml), and the second drain is electrically connected to the power source negative electrode, the third source Electrically connected to the point a clock signal, the fourth drain is electrically connected to the negative pole of the power source, and the second gate is electrically connected to the fourth gate to form an output (M+1) of the (m+1)th pulse signal.
  • One end of the capacitor is electrically connected to an intersection formed by the first drain and the second source being electrically connected to the third gate, and the other end of the capacitor is electrically connected to the third drain and the fourth source.
  • the gates of the n output transistors are electrically connected to the mth pulse signal output terminal Out(m), and the sources of the n output transistors are electrically connected one-to-one.
  • the drains of the n output transistors are electrically connected to the liquid crystal pixel data signal lines in the mth liquid crystal pixel array region.
  • the invention also provides a driving method of a liquid crystal panel, comprising:
  • Step 100 Providing a data driving control chip having n data signal output channels (S1 to S(n)), a row driving scanning chip, and M flip-flops (trigger 1 to flip-flop M corresponding to M flip-flops) M liquid crystal pixel array regions (Section 1 ⁇ Section(M));
  • Each liquid crystal pixel array region includes: (nxN) liquid crystal pixels (P), N scanning signal lines (S C anl ⁇ S C an(N) ), and n liquid crystal pixel data signal lines ( Linel ⁇ Line(n)); the liquid crystal pixels (P) are arranged in a row in the row direction, and N in the column direction; the liquid crystal pixel (P) includes a pixel transistor (Tr) and a pixel electrode (A)
  • the pixel transistor (Tr) has a gate (g X source (s ⁇ drain (d); the pixel electrode (A) one end is electrically connected to the drain (d) of the pixel transistor (Tr), the other end is electrically connected to the common voltage (VC0M); the gate ( g ) and the scanning of the pixel transistor (Tr) arranged in the same row a common connection of the signal lines (Scanl ⁇ Scan(N)), arranged in the same column of pixel transistors
  • a source ( s ) of ( Tr ) is commonly connected to a certain one of the liquid crystal pixel data signal lines ( Linel ⁇ Li ne ( n ) );
  • Step 120 The row driving scan chip is electrically connected to the scan signal line (Scan1 ⁇ Scan(N)), and the row driving scan chip sequentially activates the scan signal affixing Scanl-Scan(N));
  • Each of the flip-flops is located between the data driving control chip and the corresponding liquid crystal pixel data signal lines (Line1 ⁇ Li ne ( n ) ) in the liquid crystal pixel array region, and is electrically connected to each of the data driving control chips.
  • Step 140 M flip-flops (trigger 1 to flip-flop M) are sequentially connected to each other.
  • the M flip-flops (Trigger 1 to Trigger M) are controlled by a dot clock signal (CLK) and are sequentially triggered.
  • Each flip-flop pair of liquid crystal pixel data signal lines in the corresponding liquid crystal pixel array region (Linel ⁇ Line(n)) - Control is turned on.
  • the flip-flop controls the data drive control chip to charge the liquid crystal pixels (P) of the respective liquid crystal pixel array regions.
  • the flip-flop includes: a trigger control module and a trigger output module electrically connected to the trigger control module; the trigger control module includes a first transistor (M1), a second transistor (M2), and a third transistor ( M3 fourth transistor (M4), and capacitor (C1); the first transistor (M1) includes a first gate (gl X first source (si) and a first drain (dl), the second The transistor (M2) includes a second gate (g2 second source (s2) and a second drain (d2), and the third transistor (M3) includes a third gate (g3 third source (S3) and a third drain (d3), the fourth transistor (M4) includes a fourth gate (g4 fourth source (s4) and fourth drain (d4); the flip-flop output module includes n output transistors (Tl ⁇ T(n)), the output transistors ( ⁇ 1 ⁇ ( ⁇ )) have gates ( g1 , ⁇ gn, sources ( S1 , ⁇ sn,) and drains (dl, ⁇ dn, The first
  • the output channels (S1 to S(n)), the drains (d1, dn, ) of the n output transistors (T1 to Tn) are electrically connected to the mth liquid crystal pixel array region (Section (m) Liquid crystal pixel data signal line (Linel ⁇ Line(n) ⁇
  • the present invention provides a circuit structure of a liquid crystal panel and a driving method of the liquid crystal panel.
  • M flip-flops between the liquid crystal pixel data signal line and the data driving control chip, the corresponding liquid crystal panel is divided.
  • the triggers are sequentially triggered, and the liquid crystal pixels of the M liquid crystal pixel array regions can be sequentially charged without mutual interference, and the n data signal output channels of the data driving control chip are realized, and the liquid crystal output channels are realized.
  • the liquid crystal pixel charging in the panel greatly reduces the number of data signal output channels of the data driving control chip, P lowers the production cost of the liquid crystal panel; in addition, the turn-on time of the flip-flop is related to the dot clock signal (CLK), therefore, the data
  • the driving control chip can control the charging time of the liquid crystal pixels in a liquid crystal pixel array area, thereby solving the problem that the liquid crystal panel is inconsistent in charging between the left and right sides and the middle area.
  • the color shift phenomenon can control the charging time of the liquid crystal pixels in a liquid crystal pixel array area, thereby solving the problem that the liquid crystal panel is inconsistent in charging between the left and right sides and the middle area.
  • FIG. 1 is a circuit configuration diagram of a liquid crystal panel of the present invention
  • FIG. 2a is a schematic view showing the design of a flip-flop in the liquid crystal panel shown in FIG. 1;
  • Figure 2b is a timing diagram of the flip-flop shown in Figure 2a;
  • FIG. 3 is a schematic view showing the mutual connection of the triggers in the liquid crystal panel shown in FIG. 1;
  • Fig. 4 is a timing chart of the liquid crystal panel shown in Fig. 1. detailed description
  • the present invention provides a circuit structure of a liquid crystal panel, comprising: a data driving control chip having 1 n data signal output channels (S1 to S(n)), a row driving scanning chip 2, and M flip-flops. 3 (trigger 1 to flip-flop M ⁇ corresponding to M flip-flops of liquid crystal pixel array area 4 (Section 1 ⁇ Section(M)), dot clock signal (CLK), and common voltage (VCOM);
  • Each liquid crystal pixel array region includes: (nxN) liquid crystal pixels (P ⁇ N scanning signal lines (Scanl ⁇ Scan(N)), and n liquid crystal pixel data signal lines (Line1 ⁇ Line(n));
  • the liquid crystal pixels (P) are arranged in a row in the row direction, and N in the column direction;
  • the liquid crystal pixel (P) includes a pixel transistor (Tr) and a pixel electrode (A);
  • the pixel transistor (Tr) has a gate a pole (g X source (s drain (d);
  • the pixel electrode (A)-terminal is electrically connected to the drain (d) of the pixel transistor (Tr), and the other end is electrically connected to a common voltage (VCOM)
  • the gate (g) of the pixel transistor (Tr) arranged in the same row is connected to one of the scanning signal lines (Scanl ⁇ Scan(N)), and is disposed at the source of the pixel transistor (Tr) in the same column (s )
  • the liquid crystal pixel (P) shown in FIG. 1 is a simple diagram, and the liquid crystal pixel in FIG. 3 is seen in detail.
  • the pixel The transistor (Tr) has a gate (g X source (s drain (d); a gate (g) of the pixel transistor (Tr) is electrically connected to a first scan signal line (Scanl), the pixel The source ( s ) of the transistor ( Tr ) is electrically connected to the first liquid crystal pixel data signal line ( Line1 ), and the drain ( d ) of the pixel transistor ( Tr ) is electrically connected to one end of the pixel electrode ( A )
  • An upper plate of the storage capacitor (C) the other end of the pixel electrode (A) is electrically connected to a common voltage (VCOM), and a lower plate of the storage capacitor (C) is electrically connected to a common voltage (VCOM)
  • VCOM common voltage
  • the row driving scanning chip 2 is electrically connected to a scanning signal line (Scanl-Scan(N)), and the row driving scanning chip 2 sequentially selectively activates the scanning signal line (Scanl ⁇ Scan(N) ⁇ specifically,
  • the row drive scan chip 2 has an N-stage shift register.
  • each of the flip-flops is located between the data driving control chip 1 and the liquid crystal pixel data signal line (Linel-Line(n)) in the corresponding liquid crystal pixel array region, and is electrically
  • the M flip-flops 3 are sequentially connected to each other to form an M-stage shift register;
  • the serial data clock terminal of the shift register is supplied with a dot clock signal (CLK); the M flip-flops 3 are controlled by a dot clock signal (CLK) and sequentially triggered.
  • Each of the flip-flops controls the data driving control chip 1 to charge the liquid crystal pixels (P) of the corresponding liquid crystal pixel array regions.
  • FIG. 2 a is a schematic diagram of a design of a flip-flop in the liquid crystal panel shown in FIG. 1 , taking the trigger m as an example.
  • the trigger control module 30 and the trigger output module 32 electrically connected to the trigger control module 30;
  • the flip-flop control module 30 includes a first transistor (M1 second transistor (M2 third transistor (M3 fourth transistor ( M4 and a capacitor (C1);
  • the first transistor (M1) includes a first gate (gl X first source (si) and a first drain (dl)
  • the second transistor (M2) includes a second a gate ( g 2 second source (s2) and a second drain (d2),
  • the fourth transistor (M4) includes a fourth gate (g4 fourth source (s4) and fourth drain (d4)
  • the flip-flop output module 32 includes n output crystals a body tube (T1 ⁇ T
  • the first gate (gl) is electrically connected to the first source (si) to form an (m-1)th pulse signal output terminal Out(ml), and the second drain (d2) is electrically connected to a negative pole of the power supply (Vss), the third source (S3) is electrically connected to the dot clock signal (CLK), and the fourth drain (d4) is electrically connected to the negative pole of the power supply (Vss), the second gate The pole ( g 2 ) is electrically connected to the fourth gate ( g 4 ) to form an (m+1)th pulse signal output terminal Out(m+l), and the capacitor (C1)-terminal is electrically connected to the first The drain (dl) is electrically connected to the second source (s2) and is connected to the third gate (g3) to form an intersection (al), and the other end of the capacitor (C1) and the third drain (d3) And the fourth source (s4) is electrically connected to form an mth pulse signal output terminal Out(m), and the gates (gl '-gn') of
  • FIG. 2b is a timing diagram of the flip-flop shown in FIG. 2a.
  • the working process of the trigger in the invention is: when the (m-1)th trigger (trigger (m-1)) is turned on,
  • the (m-1)th pulse signal output terminal Out(ml) is a high pulse signal, at which time the data drive control chip 1 pairs nxN liquid crystals in the (m-1)th liquid crystal pixel array region (Section (m-1)) Pixel (P) is charged.
  • the working state of the mth flip-flop (trigger m) is: the first transistor (M1) and the third crystal element M3 are turned on, and the mth pulse signal output end Out(m) is low due to the dot clock signal CLK)
  • the level is a low pulse signal, at which time the mth flip-flop (trigger m) is off.
  • the dot clock signal (CLK) is high
  • the output signal of the mth pulse signal Out(m) is a high pulse signal
  • the mth flip-flop (trigger m) is turned on, and the data driving chip 1 is controlled to be m.
  • nxN liquid crystal pixels (P) in the liquid crystal pixel array region (Section (m)) are charged.
  • the second transistor (M2) and the fourth transistor (M4) of the (m-1)th flip-flop (flip-flop (m-1)) It is turned on, so that the (m-1)th pulse signal output terminal Out (m-1) is output as a low pulse signal.
  • the M flip-flops 3 are sequentially turned on, and the control data drive control chip 1 sequentially charges the liquid crystal pixels (P) in the different liquid crystal pixel array regions (Sections 1 to 3).
  • FIG. 3 is a schematic diagram of the mutual connection of the triggers in the liquid crystal panel shown in FIG. 1 , taking the trigger 1 and the flip-flop 2 as an example.
  • the gates ( g l ' ⁇ gn') of the output transistors (T1 ⁇ T(n)) in the flip-flop 1 are electrically connected to the flip-flop a first pulse signal output terminal Out1 of 1;
  • a drain (dl, dn, ) of the output transistors (T1 to T(n)) in the flip-flop 1 is electrically connected
  • Li ne ( n ) ⁇ when the flip-flop 1 is turned on, the flip-flop 2 is turned off, and the data driving control chip 1 charges nxN liquid crystal pixels (P) in the first liquid crystal pixel array region (Section 1); when triggered When the device 2 is turned on, the flip-flop 1 is turned off, and the data driving control chip 1 charges nxN liquid crystal pixels (P) in the second liquid crystal pixel array region (Section 2 ).
  • FIG. 4 is a timing diagram of the liquid crystal panel shown in FIG. 1.
  • Out(ml), Out(m), 01!1(11 +1) are the pulse signal output end of the (11-1)th pulse, the pulse signal output end of the (m)th, and the (m+1)
  • the pulse signal output terminal is used to connect the trigger (ml), the trigger (m) and the trigger (m+1); Section (ml) Data, Section (m) Data, Section (m + l) Data is (m-1) liquid crystal pixel array region (Section (ml)), (m) liquid crystal pixel array region (Section (m)), and (m+1) in the liquid crystal pixel array region 4.
  • Data signal of the liquid crystal pixel array region S eC tkm (m + l) ).
  • the working process of the present invention is: M flip-flops are connected to each other, controlled by a dot clock signal (CLK), and sequentially triggered.
  • CLK dot clock signal
  • the trigger m work, the trigger corresponding to m m-th liquid crystal pixel array region (S eC ticm (m)) of the liquid crystal pixel (P) and the data driving control chip 1 is connected is turned, then the data driving control chip 1 charging the liquid crystal pixel (P) of the mth liquid crystal pixel array region (Section (m)), and other flip-flops (trigger 1 to flip-flop (ml), flip-flop (m+1) to flip-flop (M) ) )
  • the liquid crystal pixels ( P ) in the corresponding liquid crystal pixel array regions Section 1 to Section (ml), Section (m+1) to Section (M) ) are disconnected from the data driving control chip 1 .
  • the corresponding liquid crystal panel is divided into M liquid crystal pixel array regions, and the triggers are sequentially triggered to realize the M liquid crystals.
  • the liquid crystal pixels (P) in the pixel array area are sequentially charged and do not interfere with each other, and the n data signal output channels (S1 to S(n)) of the data driving control chip are realized, and the liquid crystal pixels (P) in the liquid crystal panel are charged.
  • the number of data signal output channels of the data driving control chip is greatly reduced; in addition, the turn-on time of the flip-flop is related to the dot clock signal (CLK), and therefore, the data driving control chip charges the liquid crystal pixel (P) of a liquid crystal pixel array area.
  • CLK dot clock signal
  • the data driving control chip charges the liquid crystal pixel (P) of a liquid crystal pixel array area. The time will become controllable, which can solve the color caused by the inconsistency between the left and right sides and the middle area of the liquid crystal panel. Partial phenomenon.
  • the present invention further provides a driving method for the liquid crystal panel, which mainly comprises:
  • Step 100 providing a data driving control chip having n data signal output channels, a row driving scanning chip, M flip-flops, M liquid crystal pixel array regions corresponding to M flip-flops; Step 110, each liquid crystal the pixel array region comprising: (nxN) liquid crystal pixels, N number of scanning signal lines, and the n pieces of pixel data signal lines of the liquid crystal; the liquid crystal pixels arranged in the row direction of n, the N arranged in the column direction; the liquid crystal
  • the pixel includes a pixel transistor and a pixel electrode; the pixel transistor has a gate, a source and a drain; the pixel electrode is electrically connected to the drain of the pixel transistor, and the other end is electrically connected to the common voltage (VCOM);
  • VCOM common voltage
  • the gates of the pixel transistors in the same row are connected in common to one of the scanning signal lines, and the sources of the pixel transistors arranged in the same column are connected in common to one of the liquid crystal pixel data signal lines;
  • Step 120 The row driving scan chip is electrically connected to the scan signal line, and the row driving scan chip 2 sequentially selectively activates the scan signal line;
  • Step 130 Each of the flip-flops is located between the data driving control chip and the liquid crystal pixel data signal line in the corresponding liquid crystal pixel array area, and is electrically connected to each data signal output channel of the data driving control chip. Liquid crystal pixel data letter in the corresponding liquid crystal pixel array area The data output channel is electrically connected in one-to-one correspondence with the liquid crystal pixel data signal lines in the corresponding liquid crystal pixel array region;
  • Step 140 M triggers are sequentially connected to each other, controlled by a dot clock signal (CLK), and triggered in sequence;
  • CLK dot clock signal
  • Step 150 Each flip-flop controls the liquid crystal pixel data signal lines in the corresponding liquid crystal pixel array area to be in an on state, and each flip-flop controls the data driving control chip to charge the liquid crystal pixels of the corresponding liquid crystal pixel array area.
  • the driving method of the liquid crystal panel can be understood from the above description and Fig. 1, Fig. 2a, Fig. 2b, Fig. 3, and Fig. 4, and will not be described here.
  • the present invention provides a circuit structure of a liquid crystal panel and a driving method of the liquid crystal panel.
  • the liquid crystal panel is divided into M correspondingly.
  • the liquid crystal pixel array area and the triggering of the flip-flops can sequentially charge the liquid crystal pixels of the M liquid crystal pixel array regions without mutual interference, and realize the n data signal output channels of the data driving control chip, in the liquid crystal panel
  • the liquid crystal pixel charging greatly reduces the number of data signal output channels of the data driving control chip, P lowers the production cost of the liquid crystal panel; in addition, the turn-on time of the flip-flop is related to the dot clock signal (CLK), therefore, the data driving control
  • CLK dot clock signal

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Abstract

一种液晶面板的电路结构及液晶面板的驱动方法，该液晶面板的电路结构包括：具有n个数据信号输出通道（S1～S（n））的数据驱动控制芯片（1）、行驱动扫描芯片（2）、M个触发器（3）、与M个触发器（3）相对应的M个液晶像素阵列区（4）、点时钟信号（CLK）、及公共电压（VCOM）；每一液晶像素阵列区包含：（n×N）个液晶像素（P）、N条扫描信号线（Scan1～Scan（N））、以及n条液晶像素数据信号线（Line1～Line（n））；通过触发器的依次触发，实现对M个液晶像素阵列区（4）的液晶像素（P）依次充电，互不干扰。该液晶面板的电路结构及液晶面板的驱动方法，可大幅缩减数据驱动控制芯片的数据信号输出通道数，还可解决液晶面板因左右两边与中间区充电不一致而造成的色偏现象。

Description

液晶面板的电踣结构及液晶面板的驱动方法 技术领域
本发明涉及液晶面板领域，尤其涉及一种液晶面板的电路结构及液晶 面板的驱动方法。 背景技术
常规的液晶显示装置，在上基板与下基板之间形成具有介电各向异性 的液晶层。 之后，控制液晶层上形成的电场密度，使液晶材料的分子排列 转变。 由此，对经由作为显示表面的上基板透射的光量进行调整，呈现出 理想的图像。 这种液晶显示装置包括由显示图像的多个像素构成的液晶面 板、 用于驱动液晶面板的驱动电路和向液晶面板投射光的背光单元。 组成 液晶面板的每个像素的等效电路包括彼此交叉的栅极线和数据线、 分别布 置在栅极线与数据线的交点处的薄膜晶体管和像素电极、 和基于像素单元 排列的液晶电容器和存储电容器。
液晶电视因其重量轻、 功耗小，而被广泛应用。 随着经济的发展，大 尺寸、 高解析度的液晶电视越来越受到人们的欢迎，但随着解析度的升高， 液晶面板所需求的驱动芯片的输出通道数也相应的增多，其成本也越来越 高。 因此，怎样使用较少输出通道数的驱动芯片来实现较高的解析度，已 成为本领域亟待解决的问题。
目前， Tri-gate (三维晶体管 )和 HSD ( Half Source Driving ,半源极驱 动）设计都能有效地减少数据驱动芯片的输出通道数。 Tri-gate技术是一种 特殊的堆叠架构，是在三栅极导电通道三面添加 "垂直尾翼结构"，排除多 余热量，通过高组合栅绝缘体和应变硅，为移动设备提供更长的电池寿命 和更好的性能。 但是，这两种技术均相应地增加了扫描驱动芯片的输出通 道数，而且从数据驱动芯片至液晶面板各列像素的阻抗也相差很大，致使 出现色偏现象，严重影响了液晶面板的画面品质。 发明内容
本发明的目的在于提供一种液晶面板的电路结构，通过 M个触发器的 依次触发，实现对这 M个液晶像素阵列区的液晶像素显示元件依次充电， 互不干扰，大大缩减了数据驱动控制芯片的数据信号输出通道数，有效改 善了液晶面板的色偏现象。
本发明的另一目的在于提供一种液晶面板的驱动方法，能够使用较少 输出通道数的驱动芯片来达到较高的解析度， P牵低了液晶面板所需驱动芯 片的成本，有效改善了液晶面板的色偏现象。 为实现上述目的，本发明提供一种液晶面板的电路结构，包括：具有 n 个数据信号输出通道 ( Sl〜 S(n) )的数据驱动控制芯片、 行驱动扫描芯片、 M个触发器（触发器 1〜触发器 M 与 M个触发器相对应的 Μ个液晶像素 阵列区（ Sectionl〜Section(M) 点时钟信号（ CLK 及公共电压（ VCOM )； 每一液晶像素阵列区包含： ( nxN )个液晶像素（ P λ N条扫描信号线
( Scanl〜Scan(N) )、 以及 n条液晶像素数据信号线 ( Linel〜Line(n) )；所述 液晶像素（ P )沿行方向排列配置 n个，沿列方向排列配置 N个；所述液晶 像素（ P )包括像素晶体管 ( Tr )及像素电极（ A )；所述像素晶体管 ( Tr ) 具有栅极 ( g X 源极（ s λ 漏极 ( d ) ;所述像素电极 ( A )—端电性连接于 像素晶体管 ( Tr )的漏极（ d ) ,另一端电性连接于公共电压 ( VCOM )；配 置在同一行的像素晶体管 ( Tr )的栅极 ( g )与扫描信号线 ( Scanl~Scan(N) ) 的某一条公共连接，配置在同一列的像素晶体管（ Tr )的源极 ( s )与液晶 像素数据信号线（ Linel〜Line(n) )的某一条公共连接。所述行驱动扫描芯片 与扫描信号线 ( Scanl~Scan(N) )电性连接，所述行驱动扫描芯片依次有选 择地激活扫描信号线 ( Scanl~Scan(N) \具体地，所述行驱动扫描芯片具有 N级移位寄存器。 扫描信号线 ( Scanl-Scan(N) )根据移位寄存器的各级的 输出信号，成为激活状态或非激活状态。 所述每一触发器均位于数据驱动 控制芯片与相对应的液晶像素阵列区中的液晶像素数据信号线
( Linel-Line(n) )之间，且电性连接于数据驱动控制芯片的每一数据信号输 出通道（Sl〜S(n) X 点时钟信号（CLK X 及相对应的液晶像素阵列区中的 液晶像素数据信号线 ( Linel~Line(n) )；所述数据信号输出通道 ( S l〜 S(n) ) 与相对应的液晶像素阵列区中的液晶像素数据信号线（ Linel~Line(n) )一一 对应电性连接；所述 M个触发器（触发器 1〜触发器 M )依次相互连接，形 成 M级移位寄存器；对 M级移位寄存器的串行数据时钟端供给时钟信号
( CLK )；
所述 M个触发器（触发器 1〜触发器 M )均由点时钟信号（ CLK )控制， 依次触发。
所述每一触发器对相应的液晶像素阵列区中的液晶像素数据信号线 ( Linel〜Line(n) )—起控制为导通状态。
所述触发器控制数据驱动控制芯片对各个液晶像素阵列区的液晶像素 ( P )充电。
所述触发器包括：触发器控制模块及与触发器控制模块电性连接的触 发器输出模块；所述触发器控制模块包括第一晶体管（ Ml )、 第二晶体管 ( M2 )、 第三晶体管（ M3 第四晶体管（ M4 )、 及电容（ C1 )；所述第一 晶体管 ( Ml )包括第一栅极（ gl X 第一源极 ( si )及第一漏极（ dl ) ,所 述第二晶体管（ M2 )包括第二栅极（ g2 第二源极（ s2 )及第二漏极（ d2 ) , 所述第三晶体管（ M3 )包括第三栅极（ g3 第三源极（ S3 )及第三漏极（ d3 ) , 所述第四晶体管（ M4 )包括第四栅极（ g4 第四源极（ s4 )及第四漏极（ d4 )； 所述触发器输出模块包括 n个输出晶体管（ Tl〜T(n) ) ,所述输出晶体管 ( Τ1〜Τ(η) )具有栅极 ( gl，〜gn， 源极 ( Sl，〜sn， )及漏极（ dl，〜dn， )； 所述第一栅极 ( gl )与第一源极（ si )电性连接后形成第 (m-1)脉冲信 号输出端 Out(m-l) ,所述第二漏极 ( d2 )电性连接于电源负极（ Vss ) ,所 述第三源极 ( S3 )电性连接于点时钟信号（ CLK ) ,所述第四漏极（ d4 )电 性连接于电源负极（ Vss ) ,所述第二栅极（ g2 )与第四栅极（ g4 )电性连 接后形成第 (m+1)脉冲信号输出端 Out(m+l) ,所述电容（ C1 )—端电性连 接于第一漏极 ( dl )与第二源极 ( s2 )电性连接后与第三栅极 ( g3 )连接形 成的交点（ al ) ,所述电容（ C1 )的另一端与第三漏极（ d3 )及第四源极（ s4 ) 电性连接后形成第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体資 Tl〜Tn ) 的栅极 ( gl '-gn' )电性连接于第 m脉冲信号输出端 Out(m) ,所述 n个输出 晶体管 ( Tl〜Tn )的源极 ( Sl，〜sn， )—―对应电性连接于数据驱动控制芯片 1的数据信号输出通道 ( Sl〜S(n) ) ,所述 n个输出晶体管（ Tl〜Tn )的漏极 ( dl，〜dn， )—―对应电性连接于第 m液晶像素阵列区（ Section(m) )中的 液晶像素数据信号线 ( Linel〜Line(n) \
本发明还提供一种液晶面板的电路结构，包括：具有 n个数据信号输 出通道的数据驱动控制芯片、 行驱动扫描芯片、 M个触发器、 与 M个触发 器相对应的 M个液晶像素阵歹眍、 点时钟信号、 及公共电压；
每一液晶像素阵列区包含： ( nxN )个液晶像素、 N条扫描信号线、 以 及 n条液晶像素数据信号线；所述液晶像素沿行方向排列配置 n个，沿列 方向排列配置 N个；所述液晶像素包括像素晶体管及像素电极；所述像素 晶体管具有栅极、 源极、 漏极；所述像素电极一端电性连接于像素晶体管 的漏极，另一端电性连接于公共电压；配置在同一行的像素晶体管的栅极 与扫描信号线的某一条公共连接，配置在同一列的像素晶体管的源极与液 晶像素数据信号线的某一条公共连接；
所述行驱动扫描芯片与扫描信号线电性连接，所述行驱动扫描芯片依 次有选择地激活扫描信号线；
所述每一触发器均位于数据驱动控制芯片与相对应的液晶像素阵列区 中的液晶像素数据信号线之间，且电性连接于数据驱动控制芯片的每一数 据信号输出通道、 点时钟信号、 及相对应的液晶像素阵列区中的液晶像素 数据信号线；所述数据信号输出通道与相对应的液晶像素阵列区中的液晶 像素数据信号线一一对应电性连接；
其中，所述 M个触发器依次相互连接，所述 M个触发器由点时钟信号 控制，依次触发；
其中，所述每一触发器对相应的液晶像素阵列区中的液晶像素数据信 号线一起控制为导通状态；
其中，所述触发器控制数据驱动控制芯片对各个液晶像素阵列区的液 晶像素充电；
其中，所述触发器包括：触发器控制模块及与触发器控制模块电性连 接的触发器输出模块；所述触发器控制模块包括第一晶体管、 第二晶体管、 第三晶体管、 第四晶体管、 及电容；所述第一晶体管包括第一栅极、 第一 源极及第一漏极，所述第二晶体管包括第二栅极、 第二源极及第二漏极， 所述第三晶体管包括第三栅极、 第三源极及第三漏极，所述第四晶体管包 括第四栅极、 第四源极及第四漏极；所述触发器输出模块包括 n个输出晶 体管，所述输出晶体管具有栅极、 源极及漏极；
所述第一栅极与第一源极电性连接后形成第 (m-1)脉冲信号输出端 Out(m-l) ,所述第二漏极电性连接于电源负极，所述第三源极电性连接于点 时钟信号，所述第四漏极电性连接于电源负极，所述第二栅极与第四栅极 电性连接后形成第 (m+1)脉冲信号输出端 Out(m+l) ,所述电容一端电性连接 于第一漏极与第二源极电性连接后与第三栅极连接形成的交点，所述电容 的另一端与第三漏极及第四源极电性连接后形成第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的栅极电性连接于第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的源极一一对应电性连接于数据驱动控制芯 片 1的数据信号输出通道，所述 n个输出晶体管的漏极一一对应电性连接 于第 m液晶像素阵列区中的液晶像素数据信号线。
本发明还提供一种液晶面板的驱动方法，包括：
步骤 100、 提供具有 n个数据信号输出通道 ( Sl〜S(n) )的数据驱动控 制芯片、 行驱动扫描芯片， M个触发器 (触发器 1〜触发器 M 与 M个触 发器相对应的 M个液晶像素阵列区（ Sectionl〜Section(M) )；
步骤 110、 所述每一液晶像素阵列区包含： ( nxN )个液晶像素（ P )、 N 条扫描信号线（ SCanl〜SCan(N) )、 以及 n 条液晶像素数据信号线 ( Linel~Line(n) )；所述液晶像素（ P )沿行方向排列配置 n个，沿列方向 排列配置 N个；所述液晶像素（ P )包括像素晶体管 ( Tr )及像素电极（ A )； 所述像素晶体管（ Tr )具有栅极 ( g X 源极（ s λ 漏极（ d )；所述像素电极 ( A )一端电性连接于像素晶体管 ( Tr )的漏极（ d ) ,另一端电性连接于公 共电压（ VC0M )；配置在同一行的像素晶体管（ Tr )的栅极（ g )与扫描 信号线 ( Scanl~Scan(N) )的某一条公共连接，配置在同一列的像素晶体管
( Tr )的源极 ( s )与液晶像素数据信号线（ Linel〜Line(n) )的某一条公共 连接；
步骤 120、 所述行驱动扫描芯片与扫描信号线 ( Scanl~Scan(N) )电性 连接 ,所述行驱动扫描芯片依次有选择地激活扫描信号缀 Scanl-Scan(N) )； 步骤 130、所述每一触发器均位于数据驱动控制芯片与相对应的液晶像 素阵列区中的液晶像素数据信号线（ Linel〜Line(n) )之间，且电性连接于数 据驱动控制芯片的每一数据信号输出通道（ Sl〜S(n) )与相对应的液晶像素 阵列区中的液晶像素数据信号线（ Linel〜Line(n) ) ;所述数据信号输出通道 ( Sl〜S(n) )与相对应的液晶像素阵列区中的液晶像素数据信号线 ( Linel~Line(n) )——对应电性连接；
步骤 140、 M个触发器 (触发器 1〜触发器 M )依次相互连接。
所述 M个触发器 (触发器 1〜触发器 M )由点时钟信号 ( CLK )控制， 依次触发。
所述每一触发器对相应的液晶像素阵列区中的液晶像素数据信号线 ( Linel〜Line(n) )—起控制为导通状态。
所述触发器控制数据驱动控制芯片对各个液晶像素阵列区的液晶像素 ( P )充电。
所述触发器包括：触发器控制模块及与触发器控制模块电性连接的触 发器输出模块；所述触发器控制模块包括第一晶体管（ Ml )、 第二晶体管 ( M2 )、 第三晶体管（ M3 第四晶体管（ M4 )、 及电容（ C1 )；所述第一 晶体管 ( Ml )包括第一栅极（ gl X 第一源极 ( si )及第一漏极（ dl ) ,所 述第二晶体管（ M2 )包括第二栅极（ g2 第二源极（ s2 )及第二漏极（ d2 ) , 所述第三晶体管（ M3 )包括第三栅极（ g3 第三源极（ S3 )及第三漏极（ d3 ) , 所述第四晶体管（ M4 )包括第四栅极（ g4 第四源极（ s4 )及第四漏极（ d4 )； 所述触发器输出模块包括 n个输出晶体管（ Tl〜T(n) ) ,所述输出晶体管 ( Τ1〜Τ(η) )具有栅极 ( gl，〜gn， 源极 ( Sl，〜sn， )及漏极（ dl，〜dn， )； 所述第一栅极 ( gl )与第一源极（ si )电性连接后形成第 (m-1)脉冲信 号输出端 Out(m-l) ,所述第二漏极 ( d2 )电性连接于电源负极（ Vss ) ,所 述第三源极 ( S3 )电性连接于点时钟信号（ CLK ) ,所述第四漏极（ d4 )电 性连接于电源负极（ Vss ) ,所述第二栅极（ g2 )与第四栅极（ g4 )电性连 接后形成第 (m+1)脉冲信号输出端 Out(m+l) ,所述电容（ C1 )—端电性连 接于第一漏极 ( dl )与第二源极 ( s2 )电性连接后与第三栅极 ( g3 )连接形 成的交点（ al ) ,所述电容（ C1 )的另一端与第三漏极（ d3 )及第四源极（ s4 ) 电性连接后形成第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体資 Tl〜Tn ) 的栅极 ( gl '-gn' )电性连接于第 m脉冲信号输出端 Out(m) ,所述 n个输出 晶体管 ( Tl〜Tn )的源极 ( si，〜sn， )—―对应电性连接于数据驱动控制芯片 1的数据信号输出通道 ( Sl〜S(n) ) ,所述 n个输出晶体管（ Tl〜Tn )的漏极 ( dl，〜dn， )—―对应电性连接于第 m液晶像素阵列区（ Section(m) )中的 液晶像素数据信号线 ( Linel〜Line(n) \
本发明的有益效果：本发明提供一种液晶面板的电路结构及液晶面板 的驱动方法，通过在液晶像素数据信号线与数据驱动控制芯片之间设计 M 个触发器，相对应的将液晶面板分为 M个液晶像素阵列区，触发器的依次 触发，可以实现对这 M个液晶像素阵列区的液晶像素依次充电，互不干扰， 实现了数据驱动控制芯片的 n个数据信号输出通道，对液晶面板中的液晶 像素充电，大大缩减了数据驱动控制芯片的数据信号输出通道数， P牵低了 液晶面板的生产成本；另外，触发器的开启时间与点时钟信号（ CLK )有 关，因此，数据驱动控制芯片对某液晶像素阵列区的液晶像素的充电时间 将变得可控，进而可以解决液晶面板因左右两边与中间区充电不一致而造 成的色偏现象。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1为本发明的液晶面板的电路结构图；
图 2a为图 1所示的液晶面板中触发器的设计示意图；
图 2b为图 2a所示的触发器的时序图；
图 3为图 1所示的液晶面板中触发器相互连接示意图；
图 4为图 1所示的液晶面板的时序图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。 请参阅图 1 ,本发明提供一种液晶面板的电路结构，包括：具有 η个数 据信号输出通道 ( Sl〜 S(n) )的数据驱动控制芯片 1、 行驱动扫描芯片 2、 M个触发器 3 (触发器 1〜触发器 M λ 与 M个触发器相对应的 Μ个液晶像 素阵列区 4 ( Sectionl~Section(M) )、 点时钟信号（ CLK )、 及公共电压 ( VCOM )；
每一液晶像素阵列区包含： ( nxN )个液晶像素（ P λ N条扫描信号线 ( Scanl〜Scan(N) )、 以及 n条液晶像素数据信号线 ( Linel〜Line(n) )；所述 液晶像素（ P )沿行方向排列配置 n个，沿列方向排列配置 N个；所述液晶 像素（ P )包括像素晶体管 ( Tr )及像素电极（ A )；所述像素晶体管（ Tr ) 具有栅极 ( g X 源极（ s 漏极 ( d ) ;所述像素电极 ( A )—端电性连接于 像素晶体管 ( Tr )的漏极（ d ) ,另一端电性连接于公共电压 ( VCOM )；配 置在同一行的像素晶体管 ( Tr )的栅极 ( g )与扫描信号线 ( Scanl~Scan(N) ) 的某一条公共连接，配置在同一列的像素晶体管（ Tr )的源极 ( s )与液晶 像素数据信号线 ( Linel-Line(n) )的某一条公共连接。
其中，图 1中所示的液晶像素（ P )为简易图，详看图 3中的液晶像素
( P ) ,以第一液晶像素整列区（ Sectionl )中第一行第一列的液晶像素（ P ) 为例，包括像素晶体管 ( Tr 像素电极 ( A 及存储电容 ( C ) ;所述像素 晶体管 ( Tr )具有栅极 ( g X 源极（ s 漏极 ( d ) ;所述像素晶体管 ( Tr ) 的栅极 ( g )与第一扫描信号线 ( Scanl )的电性连接，所述像素晶体管（ Tr ) 的源极 ( s )与第一液晶像素数据信号线（ Linel )的电性连接，所述像素晶 体管（ Tr )的漏极（ d )电性连接于像素电极 ( A )一端与存储电容（ C )的 上极板，所述像素电极 ( A )的另一端电性连接于公共电压 ( VCOM ) ,所 述存储电容（ C )的下极板电性连接于公共电压（ VCOM )；所述存储电容
( C )用于保持对像素晶体管（ Tr )施加的信号的状态，直到施加下一个信 号。 所述行驱动扫描芯片 2与扫描信号线 ( Scanl-Scan(N) )电性连接，所 述行驱动扫描芯片 2依次有选择地激活扫描信号线（ Scanl~Scan(N) \具体 地， 所述行驱动扫描芯片 2 具有 N 级移位寄存器。 扫描信号线
( Scanl-Scan(N) )根据移位寄存器的各级的输出信号，成为激活状态或非 激活状态。
在液晶面板的 TFT玻璃基板上，所述每一触发器均位于数据驱动控制 芯片 1 与相对应的液晶像素阵列区中的液晶像素数据信号线 ( Linel-Line(n) )之间，且电性连接于数据驱动控制芯片 1的每一数据信号 输出通道（ Sl〜S(n) λ 点时钟信号（CLK X 及相对应的液晶像素阵列区中 的液晶像素数据信号线 ( Linel-Line(n) )；所述数据输出通道 ( Sl〜S(n) )与 相对应的液晶像素阵列区中的液晶像素数据信号线（ Linel-Line(n) )一一对 应电性连接；所述 M个触发器 3依次相互连接，形成 M级移位寄存器；对 M级移位寄存器的串行数据时钟端供给点时钟信号 ( CLK )；所述 M个触 发器 3由点时钟信号 ( CLK )控制，依次触发。
所述每一触发器对相应的液晶像素阵列区中的液晶像素数据信号线
( Linel〜Line(n) )—起控制为导通状态。
所述每一触发器控制数据驱动控制芯片 1对相应的液晶像素阵列区的 液晶像素（ P )充电。
请参阅图 2a并结合图 1 ,图 2a为图 1所示的液晶面板中触发器的设计 示意图，以触发器 m工作时为例。包括触发器控制模块 30及与触发器控制 模块 30电性连接的触发器输出模块 32；所述触发器控制模块 30包括第一 晶体管 ( Ml 第二晶体管 ( M2 第三晶体管 ( M3 第四晶体管（ M4 及电容 ( C1 )；所述第一晶体管 ( Ml )包括第一栅极 ( gl X 第一源极 ( si ) 及第一漏极（ dl ) ,所述第二晶体管 ( M2 )包括第二栅极（ g2 第二源极 ( s2 )及第二漏极（ d2 ) ,所述第三晶体管（ M3 )包括第三栅极（ g3 λ 第 三源极（ S3 )及第三漏极（ d3 ) ,所述第四晶体管（ M4 )包括第四栅极（ g4 第四源极 ( s4 )及第四漏极 ( d4 ) ;所述触发器输出模块 32包括 n个输出晶 体管（ Tl〜T(n) ) ,所述输出晶体管（ Τ1〜Τ(η) )具有栅极（ gl '〜gn' )、 源极 ( sl，〜sn， )及漏极 ( dl，〜dn， \
所述第一栅极 ( gl )与第一源极（ si )电性连接后形成第 (m-1)脉冲信 号输出端 Out(m-l) ,所述第二漏极 ( d2 )电性连接于电源负极（ Vss ) ,所 述第三源极 ( S3 )电性连接于点时钟信号（ CLK ) ,所述第四漏极（ d4 )电 性连接于电源负极（ Vss ) ,所述第二栅极（ g2 )与第四栅极（ g4 )电性连 接后形成第 (m+1)脉冲信号输出端 Out(m+l) ,所述电容（ C1 )—端电性连 接于第一漏极 ( dl )与第二源极 ( s2 )电性连接后与第三栅极 ( g3 )连接形 成的交点（ al ) ,所述电容（ C1 )的另一端与第三漏极（ d3 )及第四源极（ s4 ) 电性连接后形成第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体資 Tl〜Tn ) 的栅极 ( gl '-gn' )电性连接于第 m脉冲信号输出端 Out(m) ,所述 n个输出 晶体管 ( Tl〜Tn )的源极 ( Sl，〜sn， )—―对应电性连接于数据驱动控制芯片 1的数据信号输出通道 ( Sl〜S(n) ) ,所述 n个输出晶体管（ Tl〜Tn )的漏极 ( dl，〜dn， )—―对应电性连接于第 m液晶像素阵列区（ Section(m) )中的 液晶像素数据信号线 ( Linel〜Line(n) \
请参阅图 2b并结合图 1及图 2a ,图 2b为图 2a所示的触发器的时序图。 本发明中触发器的工作过程为：当第 (m-1)个触发器（触发器 (m-1) )打开时， 第 (m-1)脉冲信号输出端 Out(m-l)为高脉冲信号，这时数据驱动控制芯片 1 对第 (m-1)液晶像素阵列区（ Section (m-1) )中的 nxN个液晶像素（ P )充电。
此时，第 m个触发器 (触发器 m )的工作状态为：第一晶体管 ( Ml ) 与第三晶体資 M3 开 ,第 m脉冲信号输出端 Out(m)因点时钟信 CLK ) 为低电平而为低脉冲信号，此时第 m个触发器 (触发器 m )处于关闭状态。 当点时钟信号 ( CLK )为高电平时，第 m脉冲信号输出端 Out(m)输出为高 脉冲信号，第 m个触发器 (触发器 m )处于开启状态，控制数据驱动芯片 1对第 m液晶像素阵列区（ Section (m) )中的 nxN个液晶像素（ P )充电。
由于第 m脉冲信号输出端 Out(m)输出为高脉冲信号，第 (m-1)个触发器 (触发器 (m-1) )中的第二晶体管（ M2 )与第四晶体管（ M4 )处于开启状 态，致使第 (m-1)脉冲信号输出端 Out (m-1)输出为低脉冲信号。
以上所述， M个触发器 3依次被打开，控制数据驱动控制芯片 1依次 对不同液晶像素阵列区（ Sectionl〜 SectionM )中的液晶像素（ P )充电。
请参阅 3并结合图 1、 图 2a、 及图 2b ,图 3为图 1所示的液晶面板中 触发器相互连接示意图，以触发器 1与触发器 2相互连接为例。 触发器 1 中输出晶体管（ Tl〜T(n) )的源极（ Sr〜sn' )与触发器 2 中输出晶体管 ( Tl〜T(n) )的源极 ( Sl，〜sn， )—―对应连接后与数据驱动控制芯片 1的数 据信号输出通道（ Sl〜S(n) )一一对应电性连接；触发器 1 中输出晶体管 ( Tl〜T(n) )的栅极 ( gl '〜gn' )电性连接于触发器 1的第 1脉冲信号输出端 Outl；触发器 1中输出晶体管 ( Tl〜T(n) )的漏极 ( dl，〜dn， )电性连接于第 1液晶像素阵列区（ Section 1 )的液晶像素数据信号线 ( Linel〜Line(n) )；触 发器 2中输出晶体管 ( Tl〜T(n) )的栅极 ( gl '〜gn' )电性连接于触发器 2的 第 2脉冲信号输出端 0ut2；触发器 2 中输出晶体管（ Tl〜T(n) )的漏极 ( dl，〜dn， )电性连接于第 2液晶像素阵列区（ Section )的液晶像素数据信 号线（ Linel〜Line(n) \ 具体地，当触发器 1打开时，触发器 2关闭，数据 驱动控制芯片 1给第 1液晶像素阵列区（ Section 1 )中的 nxN个液晶像素 ( P )充电；当触发器 2打开时，触发器 1关闭，数据驱动控制芯片 1给第 2液晶像素阵列区（ Section2 )中的 nxN个液晶像素（ P )充电。
请参阅图 4并结合图 1、 图 2a、 图 2b、 及图 3 ,其中图 4为图 1所示 的液晶面板的时序图。 图 3中 Out(m-l)、 Out(m)、 01!1(11 +1)为第(11 -1)的脉 冲信号输出端、 第 (m)的脉冲信号输出端、 及第 (m+1)的脉冲信号输出端， 用于连接触发器 (m-l)、 触发器 (m)及触发器 (m+1)； Section(m-l)Data、 Section(m)Data、 Section(m+l)Data为液晶像素阵列区 4中第 (m-1)液晶像素 阵列区（Section(m-l) )、 第 (m)液晶像素阵列区（ Section(m) )、 及第 (m+1) 液晶像素阵列区（ SeCtkm(m+l) )的数据信号。
由图 4可以看出，本发明的工作过程为： M个触发器相互连接，由点 时钟信号 ( CLK )控制，依次触发。 当触发器 m工作时，触发器 m将相对 应的第 m液晶像素阵列区（ SeCticm(m) )的液晶像素（ P )与数据驱动控制 芯片 1 导通相连，此时数据驱动控制芯片 1 对第 m液晶像素阵列区 ( Section(m) )的液晶像素（ P )充电，而其它的触发器 (触发器 1〜触发器 (m-l)、 触发器（m+1)〜触发器（M) ) 将相对应的液晶像素阵列区 ( Sectionl〜Section(m-l)、 Section(m+l)〜Section(M) )中的液晶像素（ P )与 数据驱动控制芯片 1断开连接。
因此，通过在液晶像素数据信号线与数据驱动控制芯片之间设计 M个 触发器，相对应的将液晶面板分为 M个液晶像素阵列区，触发器的依次触 发，可以实现对这 M个液晶像素阵列区的液晶像素（ P )依次充电，互不 干扰，实现了数据驱动控制芯片的 n个数据信号输出通道（ Sl〜S(n) ) ,对液 晶面板中的液晶像素（ P )充电，大大缩减了数据驱动控制芯片的数据信号 输出通道数；另外，触发器的开启时间与点时钟信号（ CLK )有关，因此， 数据驱动控制芯片对某液晶像素阵列区的液晶像素（ P )的充电时间将变得 可控，进而可以解决液晶面板因左右两边与中间区充电不一致而造成的色 偏现象。
根据本发明液晶面板的电路结构，本发明还相应提供了一种液晶面板 的驱动方法，主要包括：
步骤 100、提供具有 n个数据信号输出通道的数据驱动控制芯片、行驱 动扫描芯片， M个触发器、 与 M个触发器相对应的 M个液晶像素阵列区； 步骤 110、 所述每一液晶像素阵列区包含： ( nxN )个液晶像素、 N条 扫描信号线、 以及 n条液晶像素数据信号线；所述液晶像素沿行方向排列 配置 n个，沿列方向排列配置 N个；所述液晶像素包括像素晶体管及像素 电极；所述像素晶体管具有栅极、 源极、 漏极；所述像素电极一端电性连 接于像素晶体管的漏极，另一端电性连接于公共电压 ( VCOM )；配置在同 一行的像素晶体管的栅极与扫描信号线的某一条公共连接，配置在同一列 的像素晶体管的源极与液晶像素数据信号线的某一条公共连接；
步骤 120、所述行驱动扫描芯片与扫描信号线电性连接，所述行驱动扫 描芯片 2依次有选择地激活扫描信号线；
步骤 130、所述每一触发器均位于数据驱动控制芯片与相对应的液晶像 素阵列区中的液晶像素数据信号线之间，且电性连接于数据驱动控制芯片 的每一数据信号输出通道与相对应的液晶像素阵列区中的液晶像素数据信 号线；所述数据输出通道与相对应的液晶像素阵列区中的液晶像素数据信 号线一一对应电性连接；
步骤 140、 M个触发器依次相互连接，由点时钟信号 ( CLK )控制，依 次触发；
步骤 150、每一触发器对相应的液晶像素阵列区中的液晶像素数据信号 线一起控制为导通状态，每一触发器控制数据驱动控制芯片对相应的液晶 像素阵列区的液晶像素充电。
该液晶面板的驱动方法可以根据前述说明及图 1 ,图 2a、 图 2b、 图 3、 及图 4来理解，在此不再螯述。
综上所述，本发明提供一种液晶面板的电路结构及液晶面板的驱动方 法通过在液晶像素数据信号线与数据驱动控制芯片之间设计 M个触发器， 相对应的将液晶面板分为 M个液晶像素阵列区，触发器的依次触发，可以 实现对这 M个液晶像素阵列区的液晶像素依次充电，互不干扰，实现了数 据驱动控制芯片的 n个数据信号输出通道，对液晶面板中的液晶像素充电， 大大缩减了数据驱动控制芯片的数据信号输出通道数， P牵低了液晶面板的 生产成本；另外，触发器的开启时间与点时钟信号（ CLK )有关，因此， 数据驱动控制芯片对某液晶像素阵列区的液晶像素的充电时间将变得可 控，进而可以解决液晶面板因左右两边与中间区充电不一致而造成的色偏 现象。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

杈 利 要 求
1、 一种液晶面板的电路结构，包括：具有 n个数据信号输出通道的数 据驱动控制芯片、 行驱动扫描芯片、 M个触发器、 与 M个触发器相对应的 M个液晶像素阵列区、 点时钟信号、 及公共电压；
每一液晶像素阵列区包含： ( nxN )个液晶像素、 N条扫描信号线、 以 及 n条液晶像素数据信号线；所述液晶像素沿行方向排列配置 n个，沿列 方向排列配置 N个；所述液晶像素包括像素晶体管及像素电极；所述像素 晶体管具有栅极、 源极、 漏极；所述像素电极一端电性连接于像素晶体管 的漏极，另一端电性连接于公共电压；配置在同一行的像素晶体管的栅极 与扫描信号线的某一条公共连接，配置在同一列的像素晶体管的源极与液 晶像素数据信号线的某一条公共连接；
所述行驱动扫描芯片与扫描信号线电性连接，所述行驱动扫描芯片依 次有选择地激活扫描信号线；
所述每一触发器均位于数据驱动控制芯片与相对应的液晶像素阵列区 中的液晶像素数据信号线之间，且电性连接于数据驱动控制芯片的每一数 据信号输出通道、 点时钟信号、 及相对应的液晶像素阵列区中的液晶像素 数据信号线；所述数据信号输出通道与相对应的液晶像素阵列区中的液晶 像素数据信号线一一对应电性连接。
2、如权利要求 1所述的液晶面板的电路结构，其中，所述 M个触发器 依次相互连接，所述 M个触发器由点时钟信号控制，依次触发。
3、 如权利要求 2所述的液晶面板的电路结构，其中，所述每一触发器 对相应的液晶像素阵列区中的液晶像素数据信号线一起控制为导通状态。
4、 如权利要求 3所述的液晶面板的电路结构，其中，所述触发器控制 数据驱动控制芯片对各个液晶像素阵列区的液晶像素充电。
5、如权利要求 4所述的液晶面板的电路结构，其中，所述触发器包括： 触发器控制模块及与触发器控制模块电性连接的触发器输出模块；所述触 发器控制模块包括第一晶体管、 第二晶体管、 第三晶体管、 第四晶体管、 及电容；所述第一晶体管包括第一栅极、 第一源极及第一漏极，所述第二 晶体管包括第二栅极、 第二源极及第二漏极，所述第三晶体管包括第三栅 极、 第三源极及第三漏极，所述第四晶体管包括第四栅极、 第四源极及第 四漏极；所述触发器输出模块包括 n个输出晶体管，所述输出晶体管具有 栅极、 源极及漏极；
所述第一栅极与第一源极电性连接后形成第 (m-1)脉冲信号输出端 Out(m-l) ,所述第二漏极电性连接于电源负极，所述第三源极电性连接于点 时钟信号，所述第四漏极电性连接于电源负极，所述第二栅极与第四栅极 电性连接后形成第 (m+1)脉冲信号输出端 Out(m+l) ,所述电容一端电性连接 于第一漏极与第二源极电性连接后与第三栅极连接形成的交点，所述电容 的另一端与第三漏极及第四源极电性连接后形成第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的栅极电性连接于第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的源极一一对应电性连接于数据驱动控制芯 片 1的数据信号输出通道，所述 n个输出晶体管的漏极一一对应电性连接 于第 m液晶像素阵列区中的液晶像素数据信号线。
6、 一种液晶面板的电路结构，包括：具有 n个数据信号输出通道的数 据驱动控制芯片、 行驱动扫描芯片、 M个触发器、 与 M个触发器相对应的 M个液晶像素阵列区、 点时钟信号、 及公共电压；
每一液晶像素阵列区包含： ( nxN )个液晶像素、 N条扫描信号线、 以 及 n条液晶像素数据信号线；所述液晶像素沿行方向排列配置 n个，沿列 方向排列配置 N个；所述液晶像素包括像素晶体管及像素电极；所述像素 晶体管具有栅极、 源极、 漏极；所述像素电极一端电性连接于像素晶体管 的漏极，另一端电性连接于公共电压；配置在同一行的像素晶体管的栅极 与扫描信号线的某一条公共连接，配置在同一列的像素晶体管的源极与液 晶像素数据信号线的某一条公共连接；
所述行驱动扫描芯片与扫描信号线电性连接，所述行驱动扫描芯片依 次有选择地激活扫描信号线；
所述每一触发器均位于数据驱动控制芯片与相对应的液晶像素阵列区 中的液晶像素数据信号线之间，且电性连接于数据驱动控制芯片的每一数 据信号输出通道、 点时钟信号、 及相对应的液晶像素阵列区中的液晶像素 数据信号线；所述数据信号输出通道与相对应的液晶像素阵列区中的液晶 像素数据信号线一一对应电性连接；
其中，所述 M个触发器依次相互连接，所述 M个触发器由点时钟信号 控制，依次触发；
其中，所述每一触发器对相应的液晶像素阵列区中的液晶像素数据信 号线一起控制为导通状态；
其中，所述触发器控制数据驱动控制芯片对各个液晶像素阵列区的液 晶像素充电；
其中，所述触发器包括：触发器控制模块及与触发器控制模块电性连 接的触发器输出模块；所述触发器控制模块包括第一晶体管、 第二晶体管、 第三晶体管、 第四晶体管、 及电容；所述第一晶体管包括第一栅极、 第一 源极及第一漏极，所述第二晶体管包括第二栅极、 第二源极及第二漏极， 所述第三晶体管包括第三栅极、 第三源极及第三漏极，所述第四晶体管包 括第四栅极、 第四源极及第四漏极；所述触发器输出模块包括 n个输出晶 体管，所述输出晶体管具有栅极、 源极及漏极；
所述第一栅极与第一源极电性连接后形成第 (m-1)脉冲信号输出端 Out(m-l) ,所述第二漏极电性连接于电源负极，所述第三源极电性连接于点 时钟信号，所述第四漏极电性连接于电源负极，所述第二栅极与第四栅极 电性连接后形成第 (m+1)脉冲信号输出端 Out(m+l) ,所述电容一端电性连接 于第一漏极与第二源极电性连接后与第三栅极连接形成的交点，所述电容 的另一端与第三漏极及第四源极电性连接后形成第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的栅极电性连接于第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的源极一一对应电性连接于数据驱动控制芯 片 1的数据信号输出通道，所述 n个输出晶体管的漏极一一对应电性连接 于第 m液晶像素阵歹眍中的液晶像素数据信号线。
7、 一种液晶面板的驱动方法，包括：
步骤 100、提供具有 n个数据信号输出通道的数据驱动控制芯片、行驱 动扫描芯片、 M个触发器、 与 M个触发器相对应的 M个液晶像素阵列区； 步骤 110、 所述每一液晶像素阵列区包含： ( nxN )个液晶像素、 N条 扫描信号线、 以及 n条液晶像素数据信号线；所述液晶像素沿行方向排列 配置 n个，沿列方向排列配置 N个；所述液晶像素包括像素晶体管及像素 电极；所述像素晶体管具有栅极、 源极、 漏极；所述像素电极一端电性连 接于像素晶体管的漏极，另一端电性连接于公共电压；配置在同一行的像 素晶体管的栅极与扫描信号线的某一条公共连接，配置在同一列的像素晶 体管的源极与液晶像素数据信号线的某一条公共连接；
步骤 120、所述行驱动扫描芯片与扫描信号线电性连接，所述行驱动扫 描芯片依次有选择地激活扫描信号线；
步骤 130、所述每一触发器均位于数据驱动控制芯片与相对应的液晶像 素阵列区中的液晶像素数据信号线之间，且电性连接于数据驱动控制芯片 的每一数据信号输出通道与相对应的液晶像素阵列区中的液晶像素数据信 号线；所述数据信号输出通道与相对应的液晶像素阵列区中的液晶像素数 据信号线一一对应电性连接；
步骤 140、 M个触发器依次相互连接。
8、如权利要求 7所述的液晶面板的驱动方法，其中，所述 M个触发器 由点时钟信号控制，依次触发。
9、 如权利要求 8所述的液晶面板的驱动方法，其中，所述每一触发器 对相应的液晶像素阵列区中的液晶像素数据信号线一起控制为导通状态。
10、 如权利要求 9所述的液晶面板的驱动方法，其中，所述触发器控 制数据驱动控制芯片对各个液晶像素阵列区的液晶像素充电。
11、 如权利要求 10所述的液晶面板的驱动方法，其中，所述触发器包 括：触发器控制模块及与触发器控制模块电性连接的触发器输出模块；所 述触发器控制模块包括第一晶体管、 第二晶体管、 第三晶体管、 第四晶体 管、 及电容；所述第一晶体管包括第一栅极、 第一源极及第一漏极，所述 第二晶体管包括第二栅极、 第二源极及第二漏极，所述第三晶体管包括第 三栅极、 第三源极及第三漏极，所述第四晶体管包括第四栅极、 第四源极 及第四漏极；所述触发器输出模块包括 n个输出晶体管，所述输出晶体管 具有栅极、 源极及漏极；
所述第一栅极与第一源极电性连接后形成第 (m-1)脉冲信号输出端 Out(m-l) ,所述第二漏极电性连接于电源负极，所述第三源极电性连接于点 时钟信号，所述第四漏极电性连接于电源负极，所述第二栅极与第四栅极 电性连接后形成第 (m+1)脉冲信号输出端 Out(m+l) ,所述电容一端电性连接 于第一漏极与第二源极电性连接后与第三栅极连接形成的交点，所述电容 的另一端与第三漏极及第四源极电性连接后形成第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的栅极电性连接于第 m脉冲信号输出端 Out(m) ,所述 n个输出晶体管的源极一一对应电性连接于数据驱动控制芯 片 1的数据信号输出通道，所述 n个输出晶体管的漏极一一对应电性连接 于第 m液晶像素阵列区中的液晶像素数据信号线。
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