WO2015172472A1 - 薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

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WO2015172472A1
WO2015172472A1 PCT/CN2014/086237 CN2014086237W WO2015172472A1 WO 2015172472 A1 WO2015172472 A1 WO 2015172472A1 CN 2014086237 W CN2014086237 W CN 2014086237W WO 2015172472 A1 WO2015172472 A1 WO 2015172472A1
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Prior art keywords
photoresist
active layer
drain
source
thin film
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PCT/CN2014/086237
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English (en)
French (fr)
Inventor
李延钊
王刚
崔剑
方金钢
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京东方科技集团股份有限公司
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Publication of WO2015172472A1 publication Critical patent/WO2015172472A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • TFT backplane technology is the core technology of modern and future display.
  • the active layer process is one of the core processes of TFT (Thin Film Transistor) backplane technology.
  • the material of the active layer also uses materials such as amorphous silicon and metal oxide semiconductor, and the selectivity in material selection is small, so the space for improvement in process and cost is small.
  • Embodiments of the present invention provide a thin film transistor, a method for fabricating the same, an array substrate, and a display device, and propose a new material suitable for an active layer of a thin film transistor, which can expand the selectivity of the active layer on the material.
  • the improvement in the process and cost of the thin film transistor can be improved based on various alternative materials of the active layer.
  • a thin film transistor including a gate, a gate insulating layer, an active layer, a source, and a drain; wherein the material of the active layer is a high degenerate semiconductor.
  • the active layer has a thickness of 5 to 20 nm.
  • the source and the drain are prepared by the same patterning process as the active layer, and the source and the drain are disposed in different layers from the active layer.
  • the source and the drain are disposed in the same layer and integrated with the active layer; wherein the material of the source and the drain is a high degenerate semiconductor.
  • the high degenerate semiconductor comprises a high degenerate semiconductor of a Group IV element, or a high degenerate semiconductor of a binary compound, or a high degenerate semiconductor of a ternary and above compound.
  • an array substrate including the thin film transistor and electrode structure described above.
  • the electrode structure includes a first electrode electrically connected to a drain of the thin film transistor
  • the first electrode is a pixel electrode, and the array substrate is used to drive a liquid crystal;
  • the first electrode is an anode
  • the array substrate further includes an organic material functional layer and a cathode above the anode.
  • the first electrode and the source of the thin film transistor And the drain is disposed in the same layer and integrated; wherein the material of the first electrode is a high degenerate semiconductor.
  • the array substrate further includes a common electrode.
  • a display device including the above array substrate is provided.
  • a method for fabricating a thin film transistor includes forming a gate, a gate insulating layer, an active layer, a source and a drain on a base substrate; wherein a material of the active layer is high degeneracy semiconductor.
  • the active layer has a thickness of 5 to 20 nm.
  • the source and the drain are formed by the same patterning process as the active layer, including:
  • the photoresist completely remaining portion corresponds at least to a region of the source and the drain to be formed, and the photoresist half-retaining portion is to form an area between the source and the drain,
  • the completely removed portion of the photoresist corresponds to other regions;
  • a photoresist that completely retains a portion of the photoresist is removed using a lift-off process.
  • the source and the drain are formed by the same patterning process as the active layer, including:
  • the active layer, the source and the drain region, the photoresist completely removed portion corresponds to other regions;
  • a photoresist that completely retains a portion of the photoresist is removed using a lift-off process.
  • the high degenerate semiconductor comprises a high degenerate semiconductor of a Group IV element, or a high degenerate semiconductor of a binary compound, or a high degenerate semiconductor of a ternary or higher compound.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, and a display device, the thin film transistor including a gate, a gate insulating layer, an active layer, a source and a drain disposed on a substrate;
  • the material of the active layer is a high degenerate semiconductor.
  • FIG. 1 is a schematic structural view 1 of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view 2 of a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view 3 of a thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of transfer characteristics of a thin film transistor according to an embodiment of the present invention.
  • 5a-5d are schematic diagrams showing states of energy levels of a thin film transistor under different gate voltages according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram 1 of an array substrate including a pixel electrode according to an embodiment of the present disclosure
  • FIG. 7 is an array substrate including a pixel electrode and a common electrode according to an embodiment of the present invention. Schematic diagram of structure one;
  • FIG. 8 is a schematic structural diagram 2 of an array substrate including a pixel electrode and a common electrode according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of an array substrate including an anode and a cathode according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a pixel electrode of an array substrate in the same layer as an active layer, a source, and a drain according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of an anode of an array substrate in the same layer as an active layer, a source, and a drain according to an embodiment of the present invention
  • 12a-12d are schematic diagrams showing processes for preparing active layers, sources, and drains in different layers by one patterning process according to an embodiment of the present invention
  • 13a-13c are schematic diagrams showing processes for preparing an active layer, a source, and a drain in the same layer by one patterning process according to an embodiment of the present invention.
  • the embodiment of the present invention provides a thin film transistor 10.
  • the thin film transistor 10 includes a gate electrode 101, a gate insulating layer 102, an active layer 103, and a source disposed on a base substrate 100. Pole 104 and drain 105.
  • the material of the active layer 103 is a high degenerate semiconductor.
  • the gate insulating layer 102 is disposed between the gate electrode 101 and the active layer 103.
  • the active layer 103 has a thickness of 5 to 20 nm.
  • the energy level state of the thin film transistor 10 when the voltage of the gate electrode 101 is not applied (Vg) is as shown in FIG. 5a, and the Fermi level of the active layer 103 is higher than that of the active layer 103, so that a conductive channel can be formed.
  • Vg voltage of the gate electrode 101
  • the Fermi level of the active layer 103 is higher than that of the active layer 103, so that a conductive channel can be formed.
  • the thin film transistor 10 can obtain a large source-drain current.
  • This state corresponds to the third and fourth portions of the transfer characteristics of FIG.
  • the active layer 103 Since the thickness of the active layer is extremely thin (for example, 10 nm), the active layer 103 is entirely subjected to energy level bending under the action of an external voltage, and when the thin film transistor 10 is sufficiently negative, for example, a gate of -40 to -20 V is applied.
  • the energy level state at the voltage of 101 is as shown in FIG. 5b, and the Fermi level of the active layer 103 is completely lower than the conduction band of the active layer 103, so that the channel is pinched off, even if the source 104 and the drain 105 are interposed. With the voltage applied, no current is passed. This state corresponds to the first part of the transfer characteristics of FIG. 4;
  • the voltage of the gate electrode 101 is further increased based on a certain negative value, for example, it is raised to -10 to 10 V (which can be raised to 0 V and a forward voltage), and the energy level diagram of the thin film transistor 10 is as shown in FIG. 5d.
  • the active layer 103 is bent at an energy level, most of the bottom of the conduction band is below the Fermi level, thereby forming a conductive channel.
  • a voltage is applied between the source 104 and the drain 105, a source can be formed. Leakage current. This state corresponds to the III region in the transfer characteristic of FIG. 4.
  • the voltage of the gate electrode 101 is further increased by, for example, greater than 10 V, the source-drain current is more greatly increased, which corresponds to the IV region in the transfer characteristic in FIG.
  • the work function of the gate electrode 101 material used is preferably close to the work function of the material of the active layer 103.
  • the Fermi level E is equal to or higher than the conduction band bottom E C (n type), equal to or lower than the valence band top E V (p type). It is called a degenerate semiconductor.
  • the Fermi level is called a weak degenerate semiconductor near the conduction band or the valence band, and the Fermi level enters the band to be called a high degenerate semiconductor.
  • the hierarchical structure of the active layer 103 is not limited, and it may be one layer or two or more layers.
  • the active layer 103 may be in an amorphous state, a single crystal state, or a combination of the two.
  • the active layer 103 may also be in a polycrystalline state.
  • the thin film transistor 10 may be an n-type, a p-type, a dual-type, or the like.
  • the thin film transistor 10 may be of a bottom gate type or a top gate type.
  • the top gate and the bottom gate are opposite to the positions of the gate electrode 101 and the gate insulating layer 102, that is, the gate insulating layer is close to the base substrate 100 and the gate insulating layer relative to the base substrate 100.
  • the gate 101 is away from the base substrate 100, it is a bottom gate type thin film transistor; when the gate electrode 101 is away from the base substrate 100 and the gate insulating layer 102 is close to the base substrate 100, it is a top gate type thin film transistor.
  • the material of the source 104 and the drain 105 can also use the above-described high degenerate semiconductor.
  • the source 104 and the drain 105 may also use a common metal material.
  • the thin film transistor 10 may be Divided into staggered, inverted staggered, and coplanar, anti-coplanar.
  • An embodiment of the present invention provides a thin film transistor 10 including a gate electrode 101, a gate insulating layer 102, an active layer 103, a source 104, and a drain 105 disposed on a base substrate 100; wherein the active layer
  • the material of 103 is a high degenerate semiconductor.
  • the active layer of the thin film transistor is currently a non-degenerate semiconductor and the thickness can only be 40 nm to 60 nm, the overall thickness of the thin film transistor can not be further reduced; in addition, it must use more materials.
  • the active layer having a thickness of 40 nm to 60 nm can be prepared, so that the material cost thereof is relatively high. Therefore, the embodiment of the present invention sets the thickness of the active layer 103 to 5-20 nm, compared to the prior art.
  • the active layer having a thickness of 40 nm to 60 nm can at least reduce the thickness of the active layer by at least half, so that the overall thickness of the entire thin film transistor 10 is reduced; since the thickness of the active layer 103 is lowered, the required material is correspondingly Reduced, so its material costs are also reduced.
  • the active layer 103, the source 104, and the drain 105 may be prepared by the same patterning process.
  • the one-time patterning process refers to an operation of performing one or more etchings to obtain various patterns after performing one exposure using a mask.
  • the mask may be a normal mask, a two-tone mask, or the like.
  • the source 104 and the drain 105 are disposed in different layers from the active layer 103, and the source 104 and the drain 105 may be selected from the active layer. 103 different materials and different thicknesses, such as metal materials.
  • the material of the source 104 and the drain 105 is made of a metal material because the metal material has a lower resistivity and can reduce the power consumption of the wiring.
  • the source 104 and the drain 105 are integrally disposed in the same layer as the active layer 103, and the material of the source 104 and the drain 105 and the active layer 103 are The materials are the same, ie the materials are high degenerate semiconductors. Of course, the thickness can also be the same, both 5 to 20 nm.
  • the active layer 103, the source 104, and the drain 105 can be simultaneously formed by one patterning process, and It can be realized by using a common mask in a patterning process, which not only saves the number of patterning processes, but also simplifies the preparation process.
  • the high degenerate semiconductor may be a high degenerate semiconductor of a Group IV element, such as heavily doped silicon (Si), or may be a binary compound of Group II-VI, III-V, or the like.
  • Highly degenerate semiconductors such as tin-doped zinc oxide (ITO), indium-doped zinc oxide (IZO), or high degenerate semiconductors of ternary and multi-component compounds, such as indium gallium zinc oxide (IGZO).
  • An embodiment of the present invention further provides an array substrate 01. As shown in FIGS. 6 to 11, the array substrate 01 includes the above-described thin film transistor 10 and an electrode structure.
  • the array substrate further includes a gate line electrically connected to the gate 101, a gate line lead (not shown), and a data line and a data line lead electrically connected to the source 104 (not shown in the figure) )Wait.
  • the electrode structure includes a first electrode electrically connected to the drain 105 of the thin film transistor 10; wherein, according to the type of the array substrate 01, the first electrode may be a pixel electrode, or anode.
  • the electrode structure includes a pixel electrode 20.
  • the electrode structure may further include a common electrode 30.
  • the pixel electrode 20 and the common electrode 30 are spaced apart from each other in the same layer, and both are strips.
  • the electrode structure includes an anode 40 and a cathode 50.
  • the array substrate 01 further includes an organic material functional layer 60 disposed between the anode 40 and the cathode 50; wherein the organic material functional layer 60 may include a hole transport layer and a light emitting layer. a layer and an electron transport layer; in order to increase the efficiency of electron and hole injection into the light-emitting layer, the organic material functional layer may further include an electron injection layer disposed between the cathode 50 and the electron transport layer, and A hole injection layer between the anode 40 and the hole transport layer.
  • the organic electroluminescent diode display further includes an encapsulation layer.
  • the materials of the anode 40 and the cathode 50 it can be divided into a single-sided light-emitting array substrate and a double-sided light-emitting array substrate; that is, when one of the anode 40 and the cathode 50 is When the material of the electrode is opaque or translucent material, the array substrate is a single-sided light-emitting type; when the materials of the anode 40 and the cathode 50 are both transparent materials and/or translucent materials, the array substrate is double Surface light type.
  • the single-sided light-emitting array substrate can be further classified into an upper light-emitting type and a lower light-emitting type depending on the materials of the anode 40 and the cathode 50. Specifically, when the anode 40 is disposed adjacent to the substrate substrate 100, the cathode 50 is disposed away from the substrate substrate 100, and the material of the anode 40 is a transparent conductive material, and the material of the cathode 50 is opaque.
  • a conductive material since light is emitted from the anode 40 and then through the substrate substrate 100 side, it may be referred to as a lower emission type; when the material of the anode 40 is an opaque conductive material, the material of the cathode 50 is transparent or In the case of a translucent conductive material, since light is emitted from the side of the cathode 50 away from the substrate substrate 100, it may be referred to as an upper emission type.
  • the relative positions of the above two anodes 40 and 50 may be replaced, and will be further described herein.
  • the anode 40 when the anode 40 is disposed adjacent to the substrate substrate 100, the cathode 50 is disposed away from the substrate substrate 100, and the materials of the anode 40 and the cathode 50 are both
  • a transparent conductive and/or translucent material light is emitted from the anode 40 and the substrate substrate 100 on the one hand, and from the cathode 50 away from the substrate substrate 100 on the other hand.
  • This can be referred to as a double-sided illumination type.
  • the anode 40 is disposed away from the substrate substrate 100, and the cathode 50 is disposed adjacent to the substrate substrate 100.
  • the array substrate of the organic electroluminescent diode display may further include a pixel defining layer 70 for isolating adjacent two sub-pixel units.
  • FIGS. 6-9 only the active layer 103, the source 104, and the drain 105 are illustrated in the same layer, but the embodiment of the invention is not limited thereto, and the active layer 103 and the source 104 are not limited thereto.
  • the drain 105 and the drain 105 can be different layers.
  • the pixel electrode 20 or the anode 40 may be integrally formed with the source 104 and the drain 105 of the thin film transistor 10 and the active layer 103 in the same layer, that is, through the same patterning process.
  • the active layer 103, the source 104 and the drain 105, and the pixel electrode 20 or the anode 40 are formed.
  • the embodiment of the invention further provides a display device comprising the above array substrate 01.
  • the above display device may specifically be a liquid crystal display, an organic electroluminescence diode display or the like.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor, the method comprising: forming a gate electrode 101, a gate insulating layer 102, an active layer 103, a source 104, and a drain 105 on a base substrate;
  • the material of the active layer 103 is a high degenerate semiconductor.
  • the active layer has a thickness of 5 to 20 nm.
  • the hierarchical structure of the active layer 103 is not limited, and may be one layer or two layers or two or more layers.
  • the active layer 103 may be in an amorphous state, a single crystal state, or a combination of the two.
  • the active layer 103 may also be in a polycrystalline state.
  • the order of forming the gate electrode 101 and the gate insulating layer 102 is not limited.
  • the gate electrode 101 may be formed first, and then the gate insulating layer 102 may be formed.
  • the gate insulating layer 102 may be formed first, and then the gate is formed. Extreme 101.
  • the order in which the active layer 103, the source 104, and the drain 105 are formed is not limited.
  • the material of the source 104 and the drain 105 can also use the above-described high degenerate semiconductor, and therefore, the active layer 103, the source 104, and The drains 105 can be formed simultaneously.
  • the source 104 and the drain 105 and the active layer 103 may also be formed in a sequential order.
  • the thin film transistor 10 can be classified into a staggered type, an inverted staggered type, and a coplanar type and an anti-coplanar type.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, including: forming a gate electrode 101, a gate insulating layer 102, an active layer 103, a source 104, and a drain 105 on a base substrate; wherein the active
  • the material of layer 103 is a high degenerate semiconductor.
  • the active layer of the thin film transistor is currently a non-degenerate semiconductor and the thickness can only be 40 nm to 60 nm, the overall thickness of the thin film transistor can not be further reduced; in addition, it must use more materials.
  • the active layer having a thickness of 40 nm to 60 nm can be prepared, so that the material cost thereof is relatively high. Therefore, the embodiment of the present invention sets the thickness of the active layer to 5-20 nm, compared to 40 nm in the prior art.
  • the embodiment of the present invention can reduce the thickness of the active layer by at least half, so that the overall thickness of the thin film transistor 10 as a whole is reduced; since the thickness of the active layer 103 is reduced, the required material is required. The corresponding reduction is also made, so the material cost is also reduced.
  • the active layer 103, the source 104, and the drain 105 may be prepared by the same patterning process. The following two situations are explained:
  • the source 104 and the drain 105 are in different layers from the active layer 103, that is, the source 104 and the drain 105 may be selected and active.
  • Layer 103 is of a different material and a different thickness, such as a metallic material.
  • the resistivity of the source 104 and the drain 105 can be lowered, thereby reducing the power consumption of the wiring.
  • forming the active layer 103, the source 104, and the drain 105 includes the following steps:
  • a high degenerate semiconductor thin film 103a and a metal thin film 104a are sequentially formed on a substrate on which the gate electrode 101 and the gate insulating layer 102 are formed, and a photoresist 80 is formed on the metal thin film.
  • the high degenerate semiconductor film 103a has a thickness of 5 to 20 nm.
  • the thickness of the metal thin film 104a may be greater than the thickness of the high degenerate semiconductor thin film 103a.
  • a silicon film may be formed first, then the silicon film is heavily doped by a doping process, activated, and then the metal film is formed. 104a.
  • CVD Chemical Vapor Deposition
  • MBE Molecular Beam Epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • Sputter a sputtering method
  • the substrate on which the photoresist 80 is formed is exposed by using a half-order mask 90 or a gray-scale mask.
  • a photoresist completely remaining portion 801 is formed, and the photoresist is completely removed.
  • the photoresist completely removed portion 802 corresponds to other regions.
  • the half-order mask 90 includes a completely opaque portion 901, a completely transparent portion 902, and a translucent portion 903; that is, the half-order mask 90 refers to a certain area on the transparent substrate material.
  • Forming an opaque light-shielding metal layer forming a semi-transmissive light-shielding metal layer in other regions, and forming no light-shielding metal layer in other regions; wherein the semi-transmissive light-shielding metal layer has a thickness smaller than the completely impervious The thickness of the light-shielding metal layer of light; in addition, the transmittance of the semi-transmissive light-shielding metal layer to ultraviolet light can be changed by adjusting the thickness of the semi-transmissive light-shielding metal layer.
  • the working principle of the half-order mask 90 is explained as follows: by controlling the thickness of the light-shielding metal layer at different regions on the half-stage mask 90, the intensity of transmitted light in different regions is different.
  • the photoresist 80 is selectively exposed and developed, the photoresist corresponding to the completely opaque portion 901, the translucent portion 903, and the completely transparent portion 902 of the half-order mask 90 is completely retained.
  • the principle of the gray scale mask is similar to that of the half mask 90.
  • the photoresists 80 referred to in all the embodiments of the present invention are positive gels.
  • the metal thin film 104a and the high degenerate semiconductor thin film 103a of the photoresist completely removed portion 802 are removed by an etching process.
  • the source 104 and the drain 105, and the active layer 103 can be formed using a half-order mask 90 or a gray-scale mask in a patterning process, thereby saving Number of composition processes.
  • the source 104 and the drain 105 are in the same layer as the active layer 103, and the material of the source 104 and the drain 105 and the active layer
  • the material of 103 is the same, that is, the materials are degenerate semiconductors.
  • the thickness can also be the same, both 5 to 20 nm.
  • forming the active layer 103, the source 104, and the drain 105 includes the following steps:
  • the high degenerate semiconductor film 103a is formed on a substrate on which the gate electrode 101 and the gate insulating layer 102 are formed, and a photoresist 80 is formed on the high degenerate semiconductor film 103a.
  • the source 104 and the drain 105, and the active layer 103 can be formed by using a common mask in a patterning process, thereby saving the number of patterning processes, and The preparation process can be simplified.
  • the high degenerate semiconductor may be a high degenerate semiconductor of a Group IV element, such as heavily doped silicon (Si), or may be a binary compound of Group II-VI, III-V, or the like.
  • High degeneracy Semiconductors such as tin-doped zinc oxide (ITO), indium-doped zinc oxide (IZO), or high degenerate semiconductors of ternary and multi-component compounds, such as indium gallium zinc oxide (IGZO).
  • the embodiment of the invention further provides a method for preparing the array substrate 01, comprising the steps of preparing the thin film transistor 10 and the steps of preparing the electrode structure.
  • the electrode structure includes a first electrode electrically connected to the drain 105 of the thin film transistor 10; wherein the first electrode may be the pixel electrode 20 or the anode 40 according to the type of the array substrate 01 .
  • the electrode structure includes a pixel electrode 20.
  • the electrode structure may further include a common electrode 30.
  • the electrode structure includes an anode 40 and a cathode 50.
  • the array substrate 01 further includes an organic material functional layer 60 disposed between the anode 40 and the cathode 50; the organic material functional layer 60 includes at least: a hole transport layer, a light emitting layer, and Electronic transport layer.
  • the hole transport layer, the light-emitting layer, the electron transport layer, and the cathode 50 may be vapor-deposited under a vacuum of 1 ⁇ 10 ⁇ 5 Pa.

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Abstract

提供了一种薄膜晶体管（10）及其制备方法、阵列基板（01）、显示装置。提出一种新的适用于薄膜晶体管（10）有源层（103）的材料，可以扩大有源层（103）在材料上的可选择性，也可基于有源层（103）的多种可选择材料来提高薄膜晶体管（10）在工艺、成本方面的改善空间。该薄膜晶体管（10）包括设置在衬底基板（100）上的栅极（101）、栅绝缘层（102）、有源层（103）、源极（104）和漏极（105）；其中，所述有源层（103）的材料为高简并半导体。

Description

薄膜晶体管及其制备方法、阵列基板、显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、阵列基板、显示装置。
背景技术
TFT背板技术是现代和未来显示的核心技术，有源层工艺是TFT(Thin Film Transistor，薄膜场效应晶体管)背板技术的最为核心工艺之一。
目前有源层的材料还沿用非晶硅、金属氧化物半导体等材料，在材料选择上可选择性较小，因此在工艺、成本方面的改善空间较小。
发明内容
本发明的实施例提供一种薄膜晶体管及其制备方法、阵列基板、显示装置，提出一种新的适用于薄膜晶体管有源层的材料，可以扩大有源层在材料上的可选择性，也可基于有源层的多种可选择材料来提高薄膜晶体管在工艺、成本方面的改善空间。
一方面，提供一种薄膜晶体管，包括栅极、栅绝缘层、有源层、源极和漏极；其中，所述有源层的材料为高简并半导体。
在一个示例中，所述有源层的厚度为5～20nm。
在一个示例中，所述源极和所述漏极与所述有源层通过同一次构图工艺制备得到，且所述源极和所述漏极与所述有源层不同层设置。
在一个示例中，所述源极和所述漏极与所述有源层同层且一体设置；其中，所述源极和所述漏极的材料为高简并半导体。
在一个示例中，所述高简并半导体包括第Ⅳ族元素的高简并半导体、或二元化合物的高简并半导体、或三元及以上化合物的高简并半导体。
另一方面，提供一种阵列基板，包括上述的薄膜晶体管和电极结构。
在一个示例中，所述电极结构包括与所述薄膜晶体管的漏极电连接的第一电极；
其中，所述第一电极为像素电极，所述阵列基板用于驱动液晶；
或所述第一电极为阳极，所述阵列基板还包括位于所述阳极上方的有机材料功能层和阴极。
在一个示例中，在所述源极和所述漏极与所述有源层同层设置，且材料均为高简并半导体的情况下，所述第一电极与所述薄膜晶体管的源极和漏极同层且一体设置；其中，所述第一电极的材料为高简并半导体。
在一个示例中，在所述第一电极为像素电极的情况下，所述阵列基板还包括公共电极。
又一方面，提供一种显示装置，包括上述的阵列基板。
再一方面，提供一种薄膜晶体管的制备方法，包括在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极；其中，所述有源层的材料为高简并半导体。
在一个示例中，所述有源层的厚度为5～20nm。
在一个示例中，所述源极和所述漏极与所述有源层通过同一次构图工艺形成，包括：
依次形成高简并半导体薄膜、以及金属薄膜，并在所述金属薄膜上形成光刻胶；
采用半阶掩模板或灰阶掩膜板对形成有所述光刻胶的基板进行曝光，显影后形成光刻胶完全保留部分、光刻胶半保留部分和光刻胶完全去除部分；其中，所述光刻胶完全保留部分至少对应待形成的所述源极和所述漏极的区域，所述光刻胶半保留部分对待形成所述源极和所述漏极之间的区域，所述光刻胶完全去除部分对应其他区域；
采用刻蚀工艺去除所述光刻胶完全去除部分的所述金属薄膜和所述高简并半导体薄膜；
采用灰化工艺去除所述光刻胶半保留部分的光刻胶，并刻蚀所述源极和所述漏极之间区域的所述金属薄膜，形成所述源极和所述漏极、以及所述有源层；
采用剥离工艺去除所述光刻胶完全保留部分的光刻胶。
在一个示例中，所述源极和所述漏极与所述有源层通过同一次构图工艺形成，包括：
形成所述高简并半导体薄膜，并在所述高简并半导体薄膜上形成光刻胶；
采用普通掩膜板对形成有所述光刻胶的基板进行曝光，显影后形成光刻胶完全保留部分和光刻胶完全去除部分；其中，所述光刻胶完全保留部分至少对应待形成的所述有源层、所述源极和所述漏极区域，所述光刻胶完全去除部分对应其他区域；
采用刻蚀工艺去除所述光刻胶完全去除部分的所述高简并半导体薄膜，形成所述源极和所述漏极、以及所述有源层；
采用剥离工艺去除所述光刻胶完全保留部分的光刻胶。
基于上述描述，可选的，所述高简并半导体包括第Ⅳ族元素的高简并半导体、或二元化合物的高简并半导体、或三元及以上化合物的高简并半导体。
本发明实施例提供了一种薄膜晶体管及其制备方法、阵列基板、显示装置，该薄膜晶体管包括设置在衬底基板上的栅极、栅绝缘层、有源层、源极和漏极；其中，所述有源层的材料为高简并半导体。通过提出一种适用于薄膜晶体管有源层的高简并半导体材料，可以扩大有源层在材料上的可选择性，也可基于有源层的多种可选择材料来提高薄膜晶体管在工艺、成本方面的改善空间。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例提供的一种薄膜晶体管的结构示意图一；
图2为本发明实施例提供的一种薄膜晶体管的结构示意图二；
图3为本发明实施例提供的一种薄膜晶体管的结构示意图三；
图4为本发明实施例提供的一种薄膜晶体管的转移特性示意图；
图5a-5d为本发明实施例提供的一种薄膜晶体管在不同栅极电压下的能级状态示意图；
图6为本发明实施例提供的一种包括像素电极的阵列基板的结构示意图一；
图7为本发明实施例提供的一种包括像素电极和公共电极的阵列基板的 结构示意图一；
图8为本发明实施例提供的一种包括像素电极和公共电极的阵列基板的结构示意图二；
图9为本发明实施例提供的一种包括阳极和阴极的阵列基板的结构示意图；
图10为本发明实施例提供的一种阵列基板的像素电极与有源层、源极和漏极同层的结构示意图；
图11为本发明实施例提供的一种阵列基板的阳极与有源层、源极和漏极同层的结构示意图；
图12a-12d为本发明实施例提供的一种通过一次构图工艺制备位于不同层的有源层、源极和漏极的过程示意图；
图13a-13c为本发明实施例提供的一种通过一次构图工艺制备位于同层的有源层、源极和漏极的过程示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种薄膜晶体管10，如图1至图3所示，该薄膜晶体管10包括：设置在衬底基板100上的栅极101、栅绝缘层102、有源层103、源极104和漏极105。所述有源层103的材料为高简并半导体。例如，栅绝缘层102设置在栅极101和有源层103之间。
在一个示例中，所述有源层103的厚度为5～20nm。
以n型薄膜晶体管10为例，具体工作原理描述如下：
该薄膜晶体管10在未加栅极101电压(Vg)时的能级状态如图5a所示，有源层103的费米能级高于有源层103的导带，因而可以形成导电沟道，在此基础上，当源极104和漏极105间加上电压后，所述薄膜晶体管10可以得到很大的源漏电流。该状态对应于图4的转移特性中的第III和第IV部分。
因有源层的厚度超薄(例如可以为10nm)，所以在外部电压作用下，有源层103整体发生能级弯曲，当该薄膜晶体管10在加足够负例如-40～-20V的栅极101电压时的能级状态如图5b所示，有源层103的费米能级完全低于有源层103的导带，使沟道夹断，此时即使源极104和漏极105间加上电压，也没有电流通过。该状态对应于图4的转移特性中的第I部分；
当薄膜晶体管10的栅极101电压加到某一负值例如-20～-10V时，其能级状态如图5c所示，有源层103的费米能级与有源层103的导带底持平，形成了类似普通薄膜晶体管结构的平带状态，在此情况下，导电沟道恰好形成，此时将栅极101电压稍微调高，其在源极104和漏极105间加上电压，即可有漏电流通过。该状态即对应图4的转移特性中的II区，也即阈值-亚阈值区。
当栅极101电压在上述某一负值的基础上进一步提升时例如提升到-10～10V(可提升到0V以及正向电压)，薄膜晶体管10的能级示意图如图5d所示，此时虽然有源层103发生能级弯曲，但是导带底大部分都处于费米能级之下，因而形成了导电沟道，当源极104和漏极105间加上电压后，即可形成源漏电流。该状态即对应图4的转移特性中的III区，当栅极101电压进一步提升例如大于10V时，源漏电流更大幅度提升，即可对应图4中的转移特性中的IV区。
这里，为使薄膜晶体管10容易得到转移特性，所用的栅极101材料的功函数最好同有源层103材料的功函数相近。
p型薄膜晶体管10与n型薄膜晶体管10的工作原理类似，在此不再赘述。
需要说明的是，第一，在重掺杂的半导体中，如果费米能级E，等于或高于导带底EC(n型)，等于或低于价带顶EV(p型)时，就称为简并半导体。费米能级在导带或价带边附近称弱简并半导体，费米能级进入能带内称高简并半导体。
第二，不对所述有源层103的层级结构进行限定，其可以是一层也可以是两层或两层以上。
此外，所述有源层103可以是非晶状态，也可以是单晶状态，或二者的结合，当然所述有源层103也可以是多晶状态。
第三，所述薄膜晶体管10可以为n型、p型、双型等。
第四，所述薄膜晶体管10可以为底栅型也可以为顶栅型。其中，顶栅、底栅是相对所述栅极101和栅绝缘层102的位置而定的，即：相对所述衬底基板100，当栅极101靠近所述衬底基板100，栅绝缘层102远离所述衬底基板100时，为底栅型薄膜晶体管；当栅极101远离所述衬底基板100，栅绝缘层102靠近所述衬底基板100时，为顶栅型薄膜晶体管。
第五，由于所述高简并半导体具有良好的导电性能，因此，所述源极104和所述漏极105的材料也可以使用上述高简并半导体。
当然，所述源极104和漏极105也可以使用常用的金属材料，在此基础上，根据所述有源层103与源极104和漏极105的形成次序不同，所述薄膜晶体管10可以分为交错型、反交错型、以及共面型、***面型。
第六，本发明所有实施例的附图均示意性的绘示出与发明点有关的图案层，对于与发明点无关的图案层不进行绘示或仅绘示出部分。
本发明实施例提供了一种薄膜晶体管10，包括设置在衬底基板100上的栅极101、栅绝缘层102、有源层103、源极104和漏极105；其中，所述有源层103的材料为高简并半导体。通过提出一种适用于薄膜晶体管有源层103的高简并半导体材料，可以扩大有源层103在材料上的可选择性，也可基于有源层103的多种可选择材料来提高薄膜晶体管10在工艺、成本方面的改善空间。
在此基础上，由于目前薄膜晶体管的有源层采用非简并半导体且厚度只能做到40nm～60nm，这就使得薄膜晶体管的整体厚度无法再进一步降低；另外，其必须使用更多的材料才能制备得到40nm～60nm厚度的有源层，这样其材料成本也相对较高，因此，本发明实施例通过将所述有源层103的厚度设置为5～20nm，相比于现有技术中40nm～60nm厚度的有源层，可以至少将有源层的厚度降低一半，从而使得薄膜晶体管10整体的整体厚度得到降低；由于有源层103的厚度降低了，其所需的材料也相应的减少，因此其材料成本也得到降低。
例如，为了减少构图工艺的次数，降低工艺成本，可以通过同一次构图工艺制备得到所述有源层103、源极104和漏极105。
一次构图工艺是指在利用掩模进行一次曝光后，进行一次或多次蚀刻以得到各种图案的操作。所述掩模可以为普通掩模、双色调掩模等等。
在此情况下，参考图1所示，所述源极104和所述漏极105与所述有源层103不同层设置，所述源极104和漏极105可以选择与所述有源层103不同的材料以及不同的厚度，例如金属材料。
这里，将源极104和漏极105的材料设为金属材料，是因为金属材料具有更低的电阻率，可以降低布线的功耗。
或者，参考图3所示，所述源极104和所述漏极105与所述有源层103同层一体设置，且所述源极104和漏极105的材料与所述有源层103的材料相同，即：材料均为高简并半导体。当然厚度也可以相同，均为5～20nm。
这里，通过将源极104和漏极105的材料设为高简并半导体且同层一体化设置，可以通过一次构图工艺同时形成有源层103、源极104和所述漏极105，且在一次构图工艺中采用普通掩膜板即可实现，既节省构图工艺次数，又简化制备工艺。
基于上述的描述，所述高简并半导体可以是第Ⅳ族元素的高简并半导体，例如重掺杂的硅(Si)，或者可以是第Ⅱ-Ⅵ、Ⅲ-Ⅴ族等二元化合物的高简并半导体，例如锡掺杂氧化锌(ITO)、铟掺杂氧化锌(IZO)，或者三元及多元化合物的高简并半导体，例如铟镓锌氧化物(IGZO)。
本发明实施例还提供了一种阵列基板01，如图6至图11所示，该阵列基板01包括上述的薄膜晶体管10和电极结构。
所述阵列基板还包括与所述栅极101电连接的栅线、栅线引线(图中未标识出)，与所述源极104电连接的数据线、数据线引线(图中未标识出)等。
进一步的，所述电极结构包括与所述薄膜晶体管10的漏极105电连接的第一电极；其中，根据所述阵列基板01的类型的不同，所述第一电极可以是像素电极，或是阳极。
具体的，当所述阵列基板01为液晶显示器(Liquid Crystal Display，简称LCD)的用于驱动液晶的阵列基板时，如图6所示，所述电极结构包括像素电极20。
当然，如图7和图8所示，所述电极结构还可以包括公共电极30。在此情况下，对于共平面切换型(In-Plane Switch，简称IPS)阵列基板而言，如图7所示，所述像素电极20和所述公共电极30同层间隔设置，且均为条状 电极；对于高级超维场转换型(Advanced-super Dimensional Switching，简称ADS)阵列基板而言，如图8所示，所述像素电极20和所述公共电极30不同层设置，其中在上的电极为条状电极，在下的电极为板状电极。
当所述阵列基板01为有机电致发光二极管显示器的阵列基板时，如图9所示，所述电极结构包括阳极40和阴极50。在此情况下，所述阵列基板01还包括设置于所述阳极40和所述阴极50之间的有机材料功能层60；其中，所述有机材料功能层60可以包括：空穴传输层、发光层和电子传输层；为了能够提高电子和空穴注入发光层的效率，所述有机材料功能层还可以包括设置在所述阴极50与所述电子传输层之间的电子注入层，以及设置在所述阳极40与所述空穴传输层之间的空穴注入层。
进一步的，由于有机材料功能层60材料的特殊性，所述有机电致发光二极管显示器还包括封装层。
基于此，根据所述阳极40和所述阴极50的材料的不同，可以分为单面发光型阵列基板和双面发光型阵列基板；即：当所述阳极40和所述阴极50中其中一个电极的材料为不透明或半透明材料时，所述阵列基板为单面发光型；当所述阳极40和所述阴极50的材料均为透明材料和/或半透明材料时，所阵列基板为双面发光型。
对于单面发光型阵列基板，根据所述阳极40和所述阴极50的材料的不同，又可以分为上发光型和下发光型。具体的，当所述阳极40靠近所述衬底基底100设置，所述阴极50远离所述衬底基底100设置，且所述阳极40的材料为透明导电材料，所述阴极50的材料为不透明导电材料时，由于光从阳极40、再经衬底基底100一侧出射，因此，可以称为下发光型；当所述阳极40的材料为不透明导电材料，所述阴极50的材料为透明或半透明导电材料时，由于光从阴极50远离衬底基底100一侧出射，因此，可以称为上发光型。当然，也可以将上述两种阳极40和阴极50的相对位置进行替换，在此再赘述。
对于双面发光型柔性显示基板，当所述阳极40靠近所述衬底基底100设置，所述阴极50远离所述衬底基底100设置，且所述阳极40和所述阴极50的材料均为透明导电和/或半透明材料时，由于光一方面从阳极40、再经衬底基底100一侧出射，另一方面从阴极50远离衬底基底100一侧出射，因 此可以称为双面发光型。这里，也可以是所述阳极40远离所述衬底基底100设置，所述阴极50靠近所述衬底基底100设置。
其中，所述有机电致发光二极管显示器的阵列基板还可以包括像素界定层70，用于隔离相邻两个子像素单元。
需要说明的是，上述附图6-图9中，仅以有源层103、源极104和漏极105同层进行示意，但发明实施例并不限于此，有源层103、源极104和漏极105可以不同层。
基于上述的描述，如图10和图11所示，在所述源极104和所述漏极105与所述有源层105同层且一体设置，且材料均为高简并半导体的情况下，为了减少构图工艺的次数，可以将所述像素电极20或阳极40与所述薄膜晶体管10的源极104和漏极105、以及有源层103同层一体设置，即可以通过同一次构图工艺形成所述有源层103、源极104和漏极105、以及所述像素电极20或阳极40。
本发明实施例还提供了一种显示装置，包括上述的阵列基板01。
上述的显示装置具体可以是液晶显示器、有机电致发光二级管显示器等。
本发明实施例还提供了一种薄膜晶体管的制备方法，该方法包括：在衬底基板上形成栅极101、栅绝缘层102、有源层103、源极104和漏极105；其中，所述有源层103的材料为高简并半导体。
例如，所述有源层的厚度为5～20nm。
需要说明的是，第一，不对所述有源层103的层级结构进行限定，其可以是一层也可以是两层或两层以上。
此外，所述有源层103可以是非晶状态，也可以是单晶状态，或二者的结合，当然所述有源层103也可以是多晶状态。
第二，不对所述栅极101和栅绝缘层102的形成顺序进行限定，可以是先形成所述栅极101，再形成栅绝缘层102，也可以是先形成栅绝缘层102，再形成栅极101。
第三，不对所述有源层103、源极104和漏极105的形成顺序进行限定。
由于所述高简并半导体具有良好的导电性能，因此，所述源极104和所述漏极105的材料也可以使用上述高简并半导体，因此，所述有源层103、源极104和漏极105可以同时形成。
当然，所述源极104和漏极105与所述有源层103也可以分先后次序形成，在此基础上，根据所述有源层103与源极104和漏极105的形成次序不同，所述薄膜晶体管10可以分为交错型、反交错型、以及共面型、***面型。
本发明实施例提供了一种薄膜晶体管的制备方法，包括：在衬底基板上形成栅极101、栅绝缘层102、有源层103、源极104和漏极105；其中，所述有源层103的材料为高简并半导体。通过提出一种适用于薄膜晶体管有源层103的高简并半导体材料，可以扩大有源层103在材料上的可选择性，也可基于有源层103的多种可选择材料来提高薄膜晶体管10在工艺、成本方面的改善空间。
在此基础上，由于目前薄膜晶体管的有源层采用非简并半导体且厚度只能做到40nm～60nm，这就使得薄膜晶体管的整体厚度无法再进一步降低；另外，其必须使用更多的材料才能制备得到40nm～60nm厚度的有源层，这样其材料成本也相对较高，因此，本发明实施例通过将所述有源层的厚度设置为5～20nm，相比于现有技术中40nm～60nm厚度的有源层，本发明实施例可以至少将有源层的厚度降低一半，从而使得薄膜晶体管10整体的整体厚度得到降低；由于有源层103的厚度降低了，其所需的材料也相应的减少，因此其材料成本也得到降低。
例如，为了减少构图工艺的次数，可以通过同一次构图工艺制备得到所述有源层103、源极104和漏极105。以下分两种情况进行说明：
第一种，参考图1所示，所述源极104和所述漏极105与所述有源层103位于不同层，即：所述源极104和漏极105可以选择与所述有源层103不同的材料以及不同的厚度，例如金属材料。
将源极104和漏极105的材料设为金属材料，可以降低源极104和漏极105的电阻率，从而降低布线的功耗。
具体的，以底栅型薄膜晶体管10为例，形成所述有源层103、源极104和漏极105包括如下步骤：
S101、如图12a所示，在形成有栅极101、栅绝缘层102的基板上依次形成高简并半导体薄膜103a、以及金属薄膜104a，并在所述金属薄膜上形成光刻胶80。
其中，所述高简并半导体薄膜103a的厚度为5～20nm。
所述金属薄膜104a的厚度可以大于所述高简并半导体薄膜103a的厚度。
当所述高简并半导体薄膜103a的材料为重掺杂的硅薄膜时，可以先形成硅薄膜，然后通过掺杂工艺对硅薄膜进行重掺杂，并进行激活，然后再形成所述金属薄膜104a。
这里可以采用化学气相淀积(Chemical Vapor Deposition，CVD)，或分子束外延(Molecular Beam Epitaxy，MBE)，或等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)，或溅射方法(Sputter)形成所述高简并半导体薄膜。
S102、如图12b所示，采用半阶掩模板90或灰阶掩膜板对形成有所述光刻胶80的基板进行曝光，显影后形成光刻胶完全保留部分801、光刻胶完全去除部分802和光刻胶半保留部分803；其中，所述光刻胶完全保留部分801至少对应待形成的所述源极104和所述漏极105的区域，所述光刻胶半保留部分803对待形成所述源极104和所述漏极105之间的区域，所述光刻胶完全去除部分802对应其他区域。
参考图12b所示，所述半阶掩膜板90包括完全不透明部分901、完全透明部分902、半透明部分903；即：半阶掩膜板90是指在透明衬底材料上在某些区域形成不透光的遮光金属层，在另外一些区域形成半透光的遮光金属层，其他区域不形成任何遮光金属层；其中，所述半透光的遮光金属层的厚度小于所述完全不透光的遮光金属层的厚度；此外，可以通过调节所述半透光的遮光金属层的厚度来改变所述半透光的遮光金属层对紫外光的透过率。
基于此，所述半阶掩膜板90工作原理说明如下：通过控制所述半阶掩膜板90上不同区域处遮光金属层的厚度，使曝光在不同区域的透过光的强度有所不同，从而使光刻胶80进行有选择性的曝光、显影后，形成与所述半阶掩膜板90的完全不透明部分901、半透明部分903以及完全透明部分902分别对应的光刻胶完全保留部分801、光刻胶半保留部分803、光刻胶完全去除部分802。
所述灰阶掩膜板的原理与所述半阶掩膜板90的原理类似。
其中，本发明所有实施例中所指的所述光刻胶80均为正性胶。
S103、如图12c所示，采用刻蚀工艺去除所述光刻胶完全去除部分802的所述金属薄膜104a和所述高简并半导体薄膜103a。
S104、如图12d所示，采用灰化工艺去除所述光刻胶半保留部分803的光刻胶，并刻蚀所述源极104和所述漏极105之间区域的所述金属薄膜104a，形成所述源极104和所述漏极105、以及所述有源层103。
S105、采用剥离工艺去除所述光刻胶完全保留部分801的光刻胶，形成参考图1所示的阵列基板01。
通过上述步骤S101-S105，即可在一次构图工艺中使用半阶掩模板90或灰阶掩膜板来形成所述源极104和所述漏极105、以及所述有源层103，从而节省构图工艺次数。
第二种，参考图3所示，所述源极104和所述漏极105与所述有源层103位于同层，且所述源极104和漏极105的材料与所述有源层103的材料相同，即：材料均为简并半导体。当然厚度也可以相同，均为5～20nm。
具体的，以底栅型薄膜晶体管10为例，形成所述有源层103、源极104和漏极105包括如下步骤：
S201、如图13a所示，在形成有栅极101、栅绝缘层102的基板上形成所述高简并半导体薄膜103a，并在所述高简并半导体薄膜103a上形成光刻胶80。
S202、如图13b所示，采用普通掩膜板对形成有所述光刻胶的基板进行曝光，显影后形成光刻胶完全保留部分801和光刻胶完全去除部分802；其中，所述光刻胶完全保留部分801至少对应待形成的所述有源层103、所述源极104和所述漏极105区域，所述光刻胶完全去除部分802对应其他区域。
S203、如图13c所示，采用刻蚀工艺去除所述光刻胶完全去除部分802的所述高简并半导体薄膜103a，形成所述源极104和所述漏极105、以及所述有源层103。
S204、采用剥离工艺去除所述光刻胶完全保留部分801的光刻胶，形成参考图3所示的阵列基板01。
通过上述步骤S201-S204，即可在一次构图工艺中使用普通掩膜板来形成所述源极104和所述漏极105、以及所述有源层103，从而既可以节省构图工艺次数，又可以简化制备工艺。
基于上述的描述，所述高简并半导体可以是第Ⅳ族元素的高简并半导体，例如重掺杂的硅(Si)，或者可以是第Ⅱ-Ⅵ、Ⅲ-Ⅴ族等二元化合物的高简并 半导体，例如锡掺杂氧化锌(ITO)、铟掺杂氧化锌(IZO)，或者三元及多元化合物的高简并半导体，例如铟镓锌氧化物(IGZO)。
本发明实施例还提供了一种阵列基板01的制备方法，包括制备上述薄膜晶体管10的步骤和制备电极结构的步骤。所述电极结构包括与所述薄膜晶体管10的漏极105电连接的第一电极；其中，根据所述阵列基板01的类型的不同，所述第一电极可以是像素电极20，或是阳极40。
具体的，当所述阵列基板01为液晶显示器(Liquid Crystal Display，简称LCD)的阵列基板时，参考图6和图10所示，所述电极结构包括像素电极20。当然，参考图7和图8所示，所述电极结构还可以包括公共电极30。
当所述阵列基板01为有机电致发光二极管显示器的阵列基板时，参考图9和图11所示，所述电极结构包括阳极40和阴极50。在此情况下，所述阵列基板01还包括设置于所述阳极40和所述阴极50之间的有机材料功能层60；所述有机材料功能层60至少包括：空穴传输层、发光层和电子传输层。
其中，所述空穴传输层、发光层、电子传输层、以及阴极50可以在1x10-5Pa的真空下进行蒸镀。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年5月14日递交的中国专利申请第201410203708.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种薄膜晶体管，包括栅极、栅绝缘层、有源层、源极和漏极；其中，所述有源层的材料为高简并半导体。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述有源层的厚度为5～20nm。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，所述源极和所述漏极与所述有源层通过同一次构图工艺制备得到，且所述源极和所述漏极与所述有源层不同层设置。
  4. 根据权利要求1或2所述的薄膜晶体管，其中，所述源极和所述漏极与所述有源层同层且一体设置；
    其中，所述源极和所述漏极的材料为高简并半导体。
  5. 根据权利要求1至4任一项所述的薄膜晶体管，其中，所述高简并半导体包括第Ⅳ族元素的高简并半导体、或二元化合物的高简并半导体、或三元及以上化合物的高简并半导体。
  6. 一种阵列基板，包括：
    权利要求1至5任一项所述的薄膜晶体管；和
    电极结构。
  7. 根据权利要求6所述的阵列基板，其中，
    所述电极结构包括与所述薄膜晶体管的漏极电连接的第一电极；
    其中，所述第一电极为像素电极，所述阵列基板用于驱动液晶；
    或所述第一电极为阳极，所述阵列基板还包括位于所述阳极上方的有机材料功能层和阴极。
  8. 根据权利要求7所述的阵列基板，其中，源极和漏极与有源层同层设置，且材料均为高简并半导体，所述第一电极与所述薄膜晶体管的源极和漏极同层且一体设置；
    其中，所述第一电极的材料为高简并半导体。
  9. 根据权利要求7所述的阵列基板，其中，所述第一电极为像素电极，所述阵列基板还包括公共电极。
  10. 一种显示装置，包括权利要求6至9任一项所述的阵列基板。
  11. 一种薄膜晶体管的制备方法，包括在衬底基板上形成栅极、栅绝缘层、有源层、源极和漏极；其中，所述有源层的材料为高简并半导体。
  12. 根据权利要求11所述的方法，其中，所述有源层的厚度为5～20nm。
  13. 根据权利要求11所述的方法，其中，所述源极和所述漏极与所述有源层通过同一次构图工艺形成，包括：
    依次形成高简并半导体薄膜、以及金属薄膜，并在所述金属薄膜上形成光刻胶；
    采用半阶掩模板或灰阶掩膜板对形成有所述光刻胶的基板进行曝光，显影后形成光刻胶完全保留部分、光刻胶半保留部分和光刻胶完全去除部分；其中，所述光刻胶完全保留部分至少对应待形成的所述源极和所述漏极的区域，所述光刻胶半保留部分对待形成所述源极和所述漏极之间的区域，所述光刻胶完全去除部分对应其他区域；
    采用刻蚀工艺去除所述光刻胶完全去除部分的所述金属薄膜和所述高简并半导体薄膜；
    采用灰化工艺去除所述光刻胶半保留部分的光刻胶，并刻蚀所述源极和所述漏极之间区域的所述金属薄膜，形成所述源极和所述漏极、以及所述有源层；
    采用剥离工艺去除所述光刻胶完全保留部分的光刻胶。
  14. 根据权利要求11所述的方法，其中，所述源极和所述漏极与所述有源层通过同一次构图工艺形成，包括：
    形成所述高简并半导体薄膜，并在所述高简并半导体薄膜上形成光刻胶；
    采用普通掩膜板对形成有所述光刻胶的基板进行曝光，显影后形成光刻胶完全保留部分和光刻胶完全去除部分；其中，所述光刻胶完全保留部分至少对应待形成的所述有源层、所述源极和所述漏极区域，所述光刻胶完全去除部分对应其他区域；
    采用刻蚀工艺去除所述光刻胶完全去除部分的所述高简并半导体薄膜，形成所述源极和所述漏极、以及所述有源层；
    采用剥离工艺去除所述光刻胶完全保留部分的光刻胶。
  15. 根据权利要求11至14任一项所述的方法，其中，所述高简并半导体包括第Ⅳ族元素的高简并半导体、或二元化合物的高简并半导体、或三元 及以上化合物的高简并半导体。
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CN103972300B (zh) * 2014-05-14 2015-09-30 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744864A (en) * 1995-08-03 1998-04-28 U.S. Philips Corporation Semiconductor device having a transparent switching element
CN101931009A (zh) * 2009-06-22 2010-12-29 富士胶片株式会社 薄膜晶体管和制备薄膜晶体管的方法
CN102893382A (zh) * 2010-05-17 2013-01-23 桑迪士克科技股份有限公司 包括无结的薄膜晶体管的存储器设备
CN103700707A (zh) * 2013-12-18 2014-04-02 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法、显示装置
CN103715096A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及其制作方法
CN103972300A (zh) * 2014-05-14 2014-08-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3230503B2 (ja) * 1998-12-01 2001-11-19 日本電気株式会社 トンネルトランジスタとその製造方法
WO2005088726A1 (ja) * 2004-03-12 2005-09-22 Japan Science And Technology Agency アモルファス酸化物及び薄膜トランジスタ
CN203850308U (zh) * 2014-05-14 2014-09-24 京东方科技集团股份有限公司 一种薄膜晶体管及阵列基板、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744864A (en) * 1995-08-03 1998-04-28 U.S. Philips Corporation Semiconductor device having a transparent switching element
CN101931009A (zh) * 2009-06-22 2010-12-29 富士胶片株式会社 薄膜晶体管和制备薄膜晶体管的方法
CN102893382A (zh) * 2010-05-17 2013-01-23 桑迪士克科技股份有限公司 包括无结的薄膜晶体管的存储器设备
CN103700707A (zh) * 2013-12-18 2014-04-02 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制备方法、显示装置
CN103715096A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及其制作方法
CN103972300A (zh) * 2014-05-14 2014-08-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置

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