WO2015111446A1 - 固体撮像装置および電子機器 - Google Patents
固体撮像装置および電子機器 Download PDFInfo
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- WO2015111446A1 WO2015111446A1 PCT/JP2015/050435 JP2015050435W WO2015111446A1 WO 2015111446 A1 WO2015111446 A1 WO 2015111446A1 JP 2015050435 W JP2015050435 W JP 2015050435W WO 2015111446 A1 WO2015111446 A1 WO 2015111446A1
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- solid
- state imaging
- imaging device
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- 238000003384 imaging method Methods 0.000 title claims abstract description 121
- 239000010410 layer Substances 0.000 claims description 40
- 238000012545 processing Methods 0.000 claims description 27
- 239000011229 interlayer Substances 0.000 claims description 18
- 230000003287 optical effect Effects 0.000 claims description 7
- 238000005286 illumination Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 16
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005401 electroluminescence Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present disclosure relates to a solid-state imaging device and an electronic device, and more particularly, to a solid-state imaging device and an electronic device that can reduce crosstalk interference without increasing the number of processes.
- Patent Document 1 In a multilayer solid-state imaging device, crosstalk interference often occurred between the upper and lower elements.
- Patent Document 1 a metal layer is formed on and bonded to the uppermost layer of each stacked element, thereby functioning as a shield layer and reducing crosstalk generated between the upper and lower sides. ing.
- a metal layer is formed on each of the upper and lower chips as a countermeasure against crosstalk interference generated between the upper and lower elements, but in this method, the number of processes has increased. .
- the present disclosure has been made in view of such a situation, and can reduce crosstalk interference without increasing the number of steps.
- a solid-state imaging device includes a pixel chip and a logic chip stacked on the pixel chip.
- a first layer other than the vertical signal line is disposed above the vertical signal line.
- the wiring is laid out.
- the vertical signal lines are laid out in two or more layers.
- the second wiring other than the vertical signal line is laid out below the lowest vertical signal line among the vertical signal lines.
- the vertical signal lines laid out in two or more layers are different in at least one of wiring width and thickness.
- the dielectric constant is adjusted according to the distance from the logic chip.
- the dielectric constant is adjusted to be larger as the distance from the logic chip is larger.
- the first wiring is a control line, a ground wiring, or a power supply wiring.
- the second wiring is a ground wiring or a power wiring.
- An electronic apparatus includes a pixel chip and a logic chip stacked on the pixel chip, and the first wiring other than the vertical signal line is disposed above the vertical signal line in the pixel chip.
- a signal processing circuit that processes an output signal output from the solid-state imaging device, and an optical system that makes incident light incident on the solid-state imaging device.
- the vertical signal lines are laid out in two or more layers.
- the second wiring other than the vertical signal line is laid out below the lowest vertical signal line among the vertical signal lines.
- the vertical signal lines laid out in two or more layers are different in at least one of wiring width and thickness.
- the dielectric constant is adjusted according to the distance from the logic chip.
- the dielectric constant is adjusted to be larger as the distance from the logic chip is larger.
- the first wiring is a control line, a ground wiring, or a power supply wiring.
- the second wiring is a ground wiring or a power wiring.
- a pixel chip and a logic chip stacked on the pixel chip are provided.
- a first wiring other than the vertical signal line is laid out above the vertical signal line.
- FIG. 1 illustrates a schematic configuration example of an example of a complementary metal oxide semiconductor (CMOS) solid-state imaging device applied to each embodiment of the present technology.
- CMOS complementary metal oxide semiconductor
- a solid-state imaging device (element chip) 1 includes a pixel region (a pixel region in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged two-dimensionally on a semiconductor substrate 11 (for example, a silicon substrate). A so-called imaging region) 3 and a peripheral circuit section.
- the pixel 2 includes a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors (so-called MOS transistors).
- the plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplifying transistor, and can further be constituted by four transistors by adding a selection transistor. Since the equivalent circuit of each pixel 2 (unit pixel) is the same as a general one, detailed description thereof is omitted here.
- the pixel 2 can have a shared pixel structure.
- the pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor that is shared.
- the peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.
- the control circuit 8 receives data for instructing an input clock, an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 1. Specifically, the control circuit 8 is based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and the clock signal or the reference signal for the operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 Generate a control signal. The control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6.
- the vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel 2 to the selected pixel drive wiring, and drives the pixels 2 in units of rows. Specifically, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 sequentially in the vertical direction in units of rows, and generates the signal according to the amount of light received by the photoelectric conversion element of each pixel 2 through the vertical signal line 9. A pixel signal based on the signal charge is supplied to the column signal processing circuit 5.
- the column signal processing circuit 5 is disposed, for example, for each column of the pixels 2 and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. Specifically, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixel 2, signal amplification, A / D (Analog / Digital) conversion, and the like. .
- a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.
- the horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
- the output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.
- the output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.
- the input / output terminal 12 is provided for exchanging signals with the outside.
- the solid-state imaging device 51 is of a stacked type and is configured by laminating a lower chip 62 that is a logic chip on an upper chip 61 that is a pixel chip.
- VSL vertical signal line
- wiring other than VSL for example, control lines, power supply wiring, ground (GND) wiring (hereinafter referred to as control lines) 72, and VSL 73 are stacked in this order from the lower layer.
- 2Cu, 3Cu, and 4Cu indicate the second wiring layer, the third wiring layer, and the fourth wiring layer from the bottom, respectively. That is, in the stacked solid-state imaging device 51, the VSL 73 is laid out on the uppermost layer of the upper chip 61.
- the imaging characteristics of the pixel chip may be deteriorated, such as the occurrence of a black vertical band. This is a mechanism that deteriorates due to the influence of crosstalk during the AD period when the VSL is in a floating state.
- the present technology is to reduce crosstalk interference by laying out wiring other than VSL such as control lines and power supply wiring in a layer above the vertical signal line (VSL) in the pixel chip.
- FIG. 3 is a cross-sectional view illustrating a configuration example of a solid-state imaging device to which the present technology is applied.
- 3 is the same as the solid-state imaging device 51 of FIG. 2 in that the solid-state imaging device 101 includes the lower chip 62. 3 is different from the solid-state imaging device 51 of FIG. 2 in that the upper chip 61 is replaced with the upper chip 111.
- VSL 71, VSL 73, and control line 72 are stacked in this order from the lower layer. That is, in the multilayer solid-state imaging device 101, the control line 72 is laid out on the uppermost layer of the upper chip 111.
- VSL is laid out in two or more layers to reduce the VSL load capacity as in the solid-state imaging device 101
- the distance to the control line 72 is VSL71 and VSL73 as shown by the dotted line. Therefore, there is a difference in VSL load capacity.
- a wiring 162 such as a ground wiring or a power supply wiring in 1Cu is laid out immediately below the VSL 71.
- the capacitance difference between VSL 71 and VSL 73 can be reduced.
- FIG. 5 a graph for comparing VSL load capacity differences in the solid-state imaging device 51 of FIG. 2, the solid-state imaging device 101 of FIG. 3, and the solid-state imaging device 151 of FIG.
- the vertical axis indicates the total capacity [F].
- VSL0, VSL2, VSL4, and VSL6 in the graph correspond to VSL73
- VSL1, VSL3, VSL5, and VSL7 in the graph correspond to VSL71.
- FIG. 6 is the same as the solid-state imaging device 101 of FIG. 3 in that the solid-state imaging device 201 of FIG.
- the solid-state imaging device 201 in FIG. 6 is different from the solid-state imaging device 101 in FIG. 3 in that the upper chip 161 is replaced with the upper chip 211.
- VSL221, VSL73, and control line 72 are laminated in this order from the lower layer. That is, the size of VSL 221 is different from the size of VSL 73 in FIG.
- VSL load capacity difference between VSL 73 laid out on 3Cu and VSL 221 laid out on 2Cu can be reduced by adjusting at least one of the width and thickness of the wiring.
- the solid-state imaging device 201 in FIG. 6 is different from the solid-state imaging device 101 in FIG. 3 in that the upper chip 161 is replaced with the upper chip 261 and interlayer insulating films 262-1 and 262-2 having different dielectric constants are added. Is different.
- an interlayer insulating film 262-1 having a dielectric constant Ea is added between the 4Cu control line 72 and the 3Cu VSL 73, and an interlayer insulating film having a dielectric constant Eb is interposed between the 2Cu VSL 71 and the 3Cu VSL 73. 262-2 has been added.
- the dielectric constant Eb of the interlayer insulating film 262-2 having the larger (far) distance from the control line 72 is the dielectric constant of the interlayer insulating film 262-1 having the smaller (closer) distance from the control line 72. It is adjusted to be larger than the rate Ea. That is, Eb> Ea is adjusted.
- VSL load capacitance difference between VSL 73 laid out on 3Cu and VSL 71 laid out on 2Cu can be reduced by adjusting the dielectric constant of the interlayer insulating film.
- VSL load capacity can be reduced as in the case of the two layers of VSL in FIGS. 4, 6, and 7 described above.
- FIG. 8 is a cross-sectional view illustrating a configuration example of a solid-state imaging device to which the present technology is applied.
- the upper chip 311 of the solid-state imaging device 301 in FIG. 8 is laminated in the order of VSL 71, VSL 73, and control line 72 from the lower layer, and further, the wiring 162 is laid out directly below that, the solid-state imaging device in FIG. 151 is the same as the upper chip 161.
- the upper chip 311 of the solid-state imaging device 301 in FIG. 8 is different from the upper chip 161 of the solid-state imaging device 151 in FIG. 4 in that a VSL 321 is further added between the VSL 71 and the wiring 162.
- wiring 162, VSL321, VSL71, VSL73, and control line 72 are laminated as 1Cu to 5Cu from the lower layer.
- FIG. 9 is a cross-sectional view illustrating a configuration example of a solid-state imaging device to which the present technology is applied.
- the upper chip 361 of the solid-state imaging device 351 in FIG. 9 is common to the upper chip 211 of the solid-state imaging device 201 in FIG. 6 in that VSL 221, VSL 73, and control line 72 are stacked in this order from the lower layer.
- the upper chip 361 of the solid-state imaging device 351 in FIG. 9 is different from the upper chip 211 of the solid-state imaging device 201 in FIG. 6 in that a VSL 371 is further added to the lower layer of the VSL 221.
- the size of the VSL 371 is also different from the size of the VSL 73 in FIG.
- VSL load capacitance difference between VSL 73 laid out on 4Cu, VSL 221 laid out on 3Cu, and VSL 371 laid out on 2Cu is reduced by adjusting at least one of the width and thickness of the wiring. It is possible.
- FIG. 10 is a cross-sectional view illustrating a configuration example of a solid-state imaging device to which the present technology is applied.
- the upper chip 411 of the solid-state imaging device 401 in FIG. 10 is stacked in the order of VSL 71, VSL 73, and control line 72 from the lower layer. Further, in the upper chip 411 of the solid-state imaging device 401 in FIG. 10, an interlayer insulating film 262-2 having a dielectric constant Eb is formed between the VSL 71 and VSL 73, and the dielectric constant Ea is interposed between the VSL 73 and the control line 72. The point where the interlayer insulating film 262-1 is formed is common to the upper chip 261 of the solid-state imaging device 251 of FIG.
- a VSL 421 is added below the VSL 71, and an interlayer insulating film 262-3 having a dielectric constant Ec is formed between the VSL 71 and the VSL 421. 7 is different from the upper chip 261 of the solid-state imaging device 251 of FIG.
- the VSL load capacitance difference between the VSL 421 laid out in 2Cu, the VSL 71 laid out in 3Cu, and the VSL 73 laid out in 4Cu can be reduced by adjusting the dielectric constant of the interlayer insulating film. .
- the back-illuminated image sensor is described as an example of the image sensor included in the chip, but a front-illuminated image sensor may be used.
- the back side irradiation side is more effective because it is more affected by crosstalk.
- the present technology is not limited to application to a solid-state imaging device such as an image sensor, for example. That is, the present technology is applied to an image capturing unit (photoelectric conversion unit) such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function, or a copying machine using a solid-state imaging device as an image reading unit.
- an image capturing unit photoelectric conversion unit
- an imaging device such as a digital still camera or a video camera
- a portable terminal device having an imaging function such as a digital still camera or a video camera
- a portable terminal device having an imaging function such as a portable terminal device having an imaging function
- a copying machine using a solid-state imaging device as an image reading unit.
- the present invention can be applied to all electronic devices using a solid-state imaging device.
- FIG. 11 is a block diagram illustrating a configuration example of a camera device as an electronic apparatus to which the present technology is applied.
- the 11 includes an optical unit 601 including a lens group, a solid-state imaging device (imaging device) 602 in which each configuration of the pixel 2 described above is employed, and a DSP circuit 603 that is a camera signal processing circuit.
- the camera device 600 also includes a frame memory 604, a display unit 605, a recording unit 606, an operation unit 607, and a power supply unit 608.
- the DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, the operation unit 607, and the power supply unit 608 are connected to each other via a bus line 609.
- the optical unit 601 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging device 602.
- the solid-state imaging device 602 converts the amount of incident light imaged on the imaging surface by the optical unit 601 into an electrical signal for each pixel and outputs it as a pixel signal.
- the solid-state imaging device 602 the solid-state imaging device according to the above-described embodiment can be used. Thereby, since crosstalk interference is reduced, an electronic device with good performance can be provided.
- the display unit 605 includes a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state imaging device 602.
- the recording unit 606 records a moving image or a still image captured by the solid-state imaging device 602 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).
- the operation unit 607 issues operation commands for various functions of the camera device 600 under the operation of the user.
- the power supply unit 608 appropriately supplies various power sources serving as operation power sources for the DSP circuit 603, the frame memory 604, the display unit 605, the recording unit 606, and the operation unit 607 to these supply targets.
- the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units).
- the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit).
- a configuration other than that described above may be added to the configuration of each device (or each processing unit).
- a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.
- this technique can also take the following structures.
- the vertical signal lines laid out in two or more layers are different in at least one of a wiring width and a thickness.
- the solid-state imaging device according to any one of (1) to (4), including wiring interlayer insulating films having different dielectric constants.
- the solid-state imaging device (6)
- the dielectric constant is adjusted according to the size of the distance from the logic chip.
- the solid-state imaging device according to any one of (1) to (7), configured by a backside illumination type.
- the solid-state imaging device according to any one of (1) to (8), wherein the first wiring is a control line, a ground wiring, or a power supply wiring.
- the solid-state imaging device according to any one of (3) to (8), wherein the second wiring is a ground wiring or a power supply wiring.
- a solid-state imaging device including a pixel chip and a logic chip stacked on the pixel chip, wherein the first wiring other than the vertical signal line is laid out above the vertical signal line in the pixel chip.
- Equipment A signal processing circuit for processing an output signal output from the solid-state imaging device; And an optical system that makes incident light incident on the solid-state imaging device.
- the second wiring other than the vertical signal line is laid out below the vertical signal line of the lowest layer among the vertical signal lines.
- the electronic device according to (12).
- the dielectric constant is adjusted according to a size of a distance from the logic chip.
- the dielectric constant is adjusted to a larger value as the distance from the logic chip is larger.
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Abstract
Description
0.固体撮像装置の概略構成例
1.第1の実施の形態(固体撮像装置の例)
2.第2の実施の形態(電子機器の例)
<固体撮像装置の概略構成例>
図1は、本技術の各実施の形態に適用されるCMOS(Complementary Metal Oxide Semiconductor)固体撮像装置の一例の概略構成例を示している。
<固体撮像装置の構成例>
図3は、本技術を適用した固体撮像装置の構成例を示す断面図である。
<電子機器の構成例>
図11は、本技術を適用した電子機器としての、カメラ装置の構成例を示すブロック図である。
(1) 画素チップと、
前記画素チップの上に積層されるロジックチップと
を備え、
前記画素チップにおいて、垂直信号線より上層に前記垂直信号線以外の第1の配線がレイアウトされている
固体撮像装置。
(2) 前記垂直信号線が2層以上にレイアウトされている
前記(1)に記載の固体撮像装置。
(3) 前記垂直信号線のうち最下層の垂直信号線の下層に、前記垂直信号線以外の第2の配線がレイアウトされている
前記(2)に記載の固体撮像装置。
(4) 2層以上にレイアウトされている前記垂直信号線は、配線幅および太さの少なくとも1つが異なっている
前記(2)に記載の固体撮像装置。
(5) 誘電率が異なる配線層間絶縁膜を有する
前記(1)乃至(4)のいずれかに記載の固体撮像装置。
(6) 前記誘電率は、前記ロジックチップとの距離の大きさに応じて調整されている
前記(5)に記載の固体撮像装置。
(7) 前記誘電率は、前記ロジックチップとの距離が大きいほど大きく調整されている
前記(6)に記載の固体撮像装置。
(8) 裏面照射型で構成されている
前記(1)乃至(7)のいずれかに記載の固体撮像装置。
(9) 前記第1の配線は、制御線、グランド配線、または電源配線である
前記(1)乃至(8)のいずれかに記載の固体撮像装置。
(10) 前記第2の配線は、グランド配線、または電源配線である
前記(3)乃至(8)のいずれかに記載の固体撮像装置。
(11) 画素チップと、前記画素チップの上に積層されるロジックチップとを備え、前記画素チップにおいて、垂直信号線より上層に前記垂直信号線以外の第1の配線がレイアウトされている固体撮像装置と、
前記固体撮像装置から出力される出力信号を処理する信号処理回路と、
入射光を前記固体撮像装置に入射する光学系と
を有する電子機器。
(12) 前記垂直信号線が2層以上にレイアウトされている
前記(11)に記載の電子機器。
(13) 前記垂直信号線のうち最下層の垂直信号線の下層に、前記垂直信号線以外の第2の配線がレイアウトされている
前記(12)に電子機器。
(14) 2層以上にレイアウトされている前記垂直信号線は、配線幅および太さの少なくとも1つが異なっている
前記(12)に記載の電子機器。
(15) 誘電率が異なる配線層間絶縁膜を有する
前記(11)乃至(14)のいずれかに記載の電子機器。
(16) 前記誘電率は、前記ロジックチップとの距離の大きさに応じて調整されている
前記(15)に記載の電子機器。
(17) 前記誘電率は、前記ロジックチップとの距離が大きいほど大きい値に調整されている
前記(16)に記載の電子機器。
(18) 前記固体撮像装置は、裏面照射型で構成されている
前記(11)乃至(17)のいずれかに記載の電子機器。
(19) 前記第1の配線は、制御線、グランド配線、または電源配線である
前記(11)乃至(18)のいずれかに記載の電子機器。
(20) 前記第2の配線は、グランド配線、または電源配線である
前記(13)乃至(18)のいずれかに記載の電子機器。
Claims (20)
- 画素チップと、
前記画素チップの上に積層されるロジックチップと
を備え、
前記画素チップにおいて、垂直信号線より上層に前記垂直信号線以外の第1の配線がレイアウトされている
固体撮像装置。 - 前記垂直信号線が2層以上にレイアウトされている
請求項1の記載の固体撮像装置。 - 前記垂直信号線のうち最下層の垂直信号線の下層に、前記垂直信号線以外の第2の配線がレイアウトされている
請求項2に記載の固体撮像装置。 - 2層以上にレイアウトされている前記垂直信号線は、配線幅および太さの少なくとも1つが異なっている
請求項2に記載の固体撮像装置。 - 誘電率が異なる配線層間絶縁膜を有する
請求項2の記載の固体撮像装置。 - 前記誘電率は、前記ロジックチップとの距離の大きさに応じて調整されている
請求項5の記載の固体撮像装置。 - 前記誘電率は、前記ロジックチップとの距離が大きいほど大きく調整されている
請求項6の記載の固体撮像装置。 - 裏面照射型で構成されている
請求項1に記載の固体撮像装置。 - 前記第1の配線は、制御線、グランド配線、または電源配線である
請求項1に記載の固体撮像装置。 - 前記第2の配線は、グランド配線、または電源配線である
請求項3に記載の固体撮像装置。 - 画素チップと、前記画素チップの上に積層されるロジックチップとを備え、前記画素チップにおいて、垂直信号線より上層に前記垂直信号線以外の第1の配線がレイアウトされている固体撮像装置と、
前記固体撮像装置から出力される出力信号を処理する信号処理回路と、
入射光を前記固体撮像装置に入射する光学系と
を有する電子機器。 - 前記垂直信号線が2層以上にレイアウトされている
請求項11の記載の電子機器。 - 前記垂直信号線のうち最下層の垂直信号線の下層に、前記垂直信号線以外の第2の配線がレイアウトされている
請求項12に記載の電子機器。 - 2層以上にレイアウトされている前記垂直信号線は、配線幅および太さの少なくとも1つが異なっている
請求項12に記載の電子機器。 - 誘電率が異なる配線層間絶縁膜を有する
請求項12の記載の電子機器。 - 前記誘電率は、前記ロジックチップとの距離の大きさに応じて調整されている
請求項15の記載の電子機器。 - 前記誘電率は、前記ロジックチップとの距離が大きいほど大きい値に調整されている
請求項16の記載の電子機器。 - 前記固体撮像装置は、裏面照射型で構成されている
請求項11に記載の電子機器。 - 前記第1の配線は、制御線、グランド配線、または電源配線である
請求項11に記載の電子機器。 - 前記第2の配線は、グランド配線、または電源配線である
請求項13に記載の電子機器。
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CN201580003307.XA CN105849906B (zh) | 2014-01-22 | 2015-01-09 | 固态成像装置和电子设备 |
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JPH05160278A (ja) * | 1991-12-09 | 1993-06-25 | Toshiba Corp | 半導体装置 |
JP2011114843A (ja) * | 2009-11-30 | 2011-06-09 | Toshiba Corp | 固体撮像装置 |
JP2012089739A (ja) * | 2010-10-21 | 2012-05-10 | Sony Corp | 固体撮像装置及び電子機器 |
JP2012164870A (ja) * | 2011-02-08 | 2012-08-30 | Sony Corp | 固体撮像装置とその製造方法、及び電子機器 |
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US20090200631A1 (en) * | 2008-02-08 | 2009-08-13 | Omnivision Technologies, Inc. | Backside illuminated imaging sensor with light attenuating layer |
TWI515885B (zh) * | 2009-12-25 | 2016-01-01 | 新力股份有限公司 | 半導體元件及其製造方法,及電子裝置 |
KR101445048B1 (ko) | 2010-09-16 | 2014-09-26 | 캐논 가부시끼가이샤 | 토너 |
JP2012094720A (ja) * | 2010-10-27 | 2012-05-17 | Sony Corp | 固体撮像装置、半導体装置、固体撮像装置の製造方法、半導体装置の製造方法、及び電子機器 |
US8890047B2 (en) * | 2011-09-21 | 2014-11-18 | Aptina Imaging Corporation | Stacked-chip imaging systems |
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JPH05160278A (ja) * | 1991-12-09 | 1993-06-25 | Toshiba Corp | 半導体装置 |
JP2011114843A (ja) * | 2009-11-30 | 2011-06-09 | Toshiba Corp | 固体撮像装置 |
JP2012089739A (ja) * | 2010-10-21 | 2012-05-10 | Sony Corp | 固体撮像装置及び電子機器 |
JP2012164870A (ja) * | 2011-02-08 | 2012-08-30 | Sony Corp | 固体撮像装置とその製造方法、及び電子機器 |
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CN105849906A (zh) | 2016-08-10 |
WO2015111446A9 (ja) | 2017-10-19 |
KR102368112B1 (ko) | 2022-02-28 |
US10249670B2 (en) | 2019-04-02 |
TW201530747A (zh) | 2015-08-01 |
TWI693705B (zh) | 2020-05-11 |
CN105849906B (zh) | 2019-12-17 |
KR20160111916A (ko) | 2016-09-27 |
US20160336371A1 (en) | 2016-11-17 |
JP2015138862A (ja) | 2015-07-30 |
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