WO2015103956A1 - 一种动态整流控制电路与无源rfid及动态整流控制方法 - Google Patents

一种动态整流控制电路与无源rfid及动态整流控制方法 Download PDF

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Publication number
WO2015103956A1
WO2015103956A1 PCT/CN2015/070136 CN2015070136W WO2015103956A1 WO 2015103956 A1 WO2015103956 A1 WO 2015103956A1 CN 2015070136 W CN2015070136 W CN 2015070136W WO 2015103956 A1 WO2015103956 A1 WO 2015103956A1
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type mos
mos transistor
circuit
drain
antenna
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PCT/CN2015/070136
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English (en)
French (fr)
Inventor
吴边
韩富强
漆射虎
罗远明
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卓捷创芯科技（深圳）有限公司
无锡智速科技有限公司
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Publication of WO2015103956A1 publication Critical patent/WO2015103956A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0701—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management
    • G06K19/0707—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation
    • G06K19/0708—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation the source being electromagnetic or magnetic
    • G06K19/0709—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation the source being electromagnetic or magnetic the source being an interrogation field

Definitions

  • the invention belongs to the technical field of radio frequency identification, in particular to a dynamic rectification control circuit and a passive RFID comprising the same. At the same time, the invention also relates to a method for dynamically rectifying and controlling a circuit by using the above passive RFID.
  • the Radio Frequency Identification (RFID) tag itself does not have a battery, and it relies on the electromagnetic energy transmitted by the card reader. Because of its simple structure and economical utility, it has been widely used in logistics management, asset tracking and mobile medical.
  • a passive RFID tag When a passive RFID tag is in operation, it absorbs the electromagnetic energy emitted by the reader from the surrounding environment. After absorbing energy, the passive RFID tag rectifies a part of the energy into a DC power supply for the internal circuit of the passive RFID tag; the passive RFID tag also inputs another part of the energy into the internal modulation and demodulation circuit, and the modulation and demodulation circuit will The amplitude modulated signal carried in the energy is demodulated and the demodulated signal is sent to the digital baseband portion of the passive RFID tag for processing.
  • the electromagnetic energy absorbed by the passive RFID tag from the surrounding environment also changes as the passive RFID tag operates.
  • the signal strength received by the passive RFID tag is also strong, so that the voltage induced on the coil exceeds the voltage used by the rectifier module in the chip.
  • the voltage withstand voltage of the transistor causes permanent damage to the transistor, causing the RFID tag to fail.
  • Passive RFID tags transmit data to the reader through load modulation, and coil probes at the reader end The impedance change of the end coil of the RFID tag is measured to acquire data.
  • the load modulation signal coupled back from the RFID tag end is likely to cause saturation of the reader receiving end, and the communication fails. This failure is more likely to occur in the RTF communication mode (Reader Talk First) where the reader first issues a command and then waits for an RFID tag to answer.
  • an amplitude limiting processing circuit is required inside the RFID tag chip circuit to ensure that the voltage across the antenna on the RFID tag is limited to a predetermined value.
  • the amplitude limit function is through a voltage comparator.
  • the voltage comparator compares the relationship between the envelope signal generated by the envelope detection circuit, that is, the data information, and the average value of the envelope signal itself, so that the inverter outputs high and low logic behind the voltage comparator. Signal, the demodulated signal.
  • the demodulation circuit can adaptively ensure the stability of the averaging circuit, thereby ensuring the demodulation circuit. Normal and stable work.
  • the technique of adaptively adjusting the gate voltage of the first PMOS transistor used in the above patent is a method of indirectly monitoring the intensity of the RF signal.
  • the dynamic adjustment object is a PMOS tube used as an equivalent resistor, so that the channel equivalent resistance of the PMOS tube is stable under different signal strengths, that is, the filter time constant of the capacitor is stable, and finally a stable detection effect is obtained.
  • the present invention monitors the intensity of the RF signal for the dynamic adjustment of the voltage amplitude of the rectifier, and adjusts the limiter circuit of the rectifier so that the leakage current path from the antenna port to the ground has different degrees of opening under different signal strength conditions. Thereby protecting the transistors of the RF front end from high voltage, The occurrence of reception saturation at the reader end is avoided.
  • Limiting circuit The limiting circuit is used for limiting the signal strength, and is directed to a circuit having a constant power input, which is different from the rectification control circuit used in the present application, and cannot be used in an RFID circuit. .
  • the application does not relate to the aspect of the dynamic adjustment rectifier input voltage amplitude circuit of the present patent application, and is not repeatable with the inventive aspects of the present patent application.
  • the limit circuit of Shanghai Huahong is controlled by a high-voltage or low-voltage detection circuit to charge and discharge a capacitor to generate a limiter signal.
  • the limiting signal has a significantly larger time constant in the change of the specific field strength, that is, a change in the voltage amplitude on the slowly reacting antenna.
  • Such a technique does not serve the purpose of the overvoltage protection proposed by the present application because within a limited time constant, the transistors inside the radio frequency tag chip are already in an unreliable state of overvoltage driving. Therefore, the limiting circuit disclosed in the present application has an extremely fast response speed to the change of the voltage on the antenna, and can play a good protection role.
  • the technical problem to be solved by the embodiments of the present invention is to provide a dynamic rectification control circuit and a passive RFID including the dynamic rectification control circuit, and a method for dynamically rectifying and controlling the circuit by using the passive RFID, by using a rectifier voltage amplitude Continuous dynamic adjustment is implemented to control the circuit voltage to prevent the receiver from receiving saturation.
  • a dynamic rectification control circuit comprising:
  • a resonant capacitor connected in parallel with the resonant inductor between the first antenna end and the second antenna end, for forming a resonant circuit with the resonant inductor, receiving an external electromagnetic field and coupling it to the rectifier circuit;
  • a rectifier circuit having an input end connected to the first antenna end and the second antenna end, configured to convert the AC power coupled by the resonant circuit into a DC power supply and output, and provide power to the limiter circuit, and simultaneously connect one output end thereof For outputting the charge to the ground when the field strength is too strong;
  • the limiting circuit has a power input end connected to the output end of the rectifier circuit power supply, and an output end connected to the control input end of the rectifier circuit.
  • Another object of embodiments of the present invention is to provide a passive RFID including the above-described dynamic rectification control circuit.
  • a further object of the embodiments of the present invention is to apply a method for continuously dynamic rectification control of a circuit by using the above passive RFID, the method comprising the following steps:
  • the resonant capacitor and the resonant inductor receive an external electromagnetic field and couple it to the rectifier circuit, the rectifier circuit rectifies the AC power source into a DC power source V 1 and outputs it to the limiter circuit;
  • V 1 is less than the sum of the gate voltage of the first P-type MOS transistor and the turn-on voltage of the threshold cell, the first P-type MOS transistor and the threshold cell are not turned on, and the drain of the second P-type MOS transistor is discharged.
  • V R When the current is zero, V R is zero, and the first N-type MOS transistor is not turned on, and the amount of charge between the first antenna end and the second antenna end is not affected; if the V 1 value is greater than the first P-type MOS tube
  • the sum of the gate-source voltage and the turn-on voltage of the threshold cell, the first P-type MOS transistor and the threshold cell branch are turned on, and the first P-type MOS transistor mirrors the current to the second P-type MOS transistor and generates a voltage through the resistor
  • the difference is input to the gate of the first N-type MOS transistor, and the first N-type MOS transistor is turned on, and the charge between the first antenna end and the second antenna end is output to the ground through the source thereof, so that the first antenna end and the first antenna The amount of charge between the two antenna ends is reduced;
  • the passive RFID of the present invention can continuously perform dynamic rectification control on the voltage between the first antenna end and the second antenna end.
  • the dynamic rectification control circuit can guide the grounding path. Passing, so that the charge at the antenna end is output to the ground, reducing the amount of charge at the antenna end, so that the rectified DC voltage is lowered; when the voltage is within the limited voltage, the ground path is in an off state, and the rectifier circuit rectifies all the charges at the antenna end into
  • the DC power supply is used by the load circuit to prevent excessive voltage from damaging the load circuit and also preventing saturation at the reader end.
  • FIG. 1 is a block diagram showing the overall structure of a circuit of the present invention.
  • Embodiment 1 is a structural diagram of Embodiment 1 of a rectifier circuit used in the present invention
  • Embodiment 3 is a structural diagram of Embodiment 2 of a rectifier circuit used in the present invention.
  • Figure 4 is a structural diagram of a limiting circuit used in the present invention.
  • Figure 5 is a structural diagram of a first embodiment of a limiter circuit used in the present invention.
  • Embodiment 2 is a structural diagram of Embodiment 2 of a limiter circuit used in the present invention.
  • Fig. 7 is a structural view showing the third embodiment of the limiter circuit used in the present invention.
  • connection described in the embodiment of the present invention represents a direct or indirect connection relationship between two connection endpoints.
  • FIG. 1 is a block diagram showing the overall structure of the circuit of the present invention.
  • a dynamic rectification control circuit 1 according to the present invention includes:
  • a resonant capacitor C1 connected in parallel with the resonant inductor L between the first antenna end in1 and the second antenna end in2 for forming a resonant circuit with the resonant inductor L, receiving an external electromagnetic field and coupling it to the rectifier circuit;
  • a rectifier circuit having an input end connected to the first antenna end in1 and the second antenna end in2 for converting the AC power coupled by the resonant circuit into a DC power supply and outputting to an external load circuit, and the other output end is limiting
  • the circuit provides power and the output of one of the outputs is grounded to output the charge to the ground when the field strength is too strong;
  • the limiting circuit has a power input terminal connected to the rectifier circuit power output terminal V 1 and an output terminal V R connected to the rectifier circuit control input terminal.
  • FIG. 2 is a structural diagram of Embodiment 1 of a rectifier circuit used in the present invention.
  • the rectifier circuit 2 includes a first rectification branch, a second rectification branch, and a third rectification branch connected in parallel between the first antenna end in1 and the second antenna end in2.
  • the first rectifying branch is a bridge rectifying circuit, one output end of which is grounded, and the other output end V dd_out is connected to an external load circuit for converting the AC power coupled by the resonant circuit into a DC power supply to supply power to the external load circuit .
  • the second rectifying branch is a fifth diode D5 and a sixth diode D6 connected between the first antenna end in1 and the second antenna end in2, the fifth diode D5 and the sixth two
  • the pole tube D6 is used to convert the AC power coupled by the resonant circuit into a DC power source V 1 and output it to the input terminal of the limiter circuit to supply power to the limiter circuit.
  • the second rectifying branch is a second N-type connected between the first antenna end in1 and the second antenna end in2.
  • a MOS transistor NM2 and a third N-type MOS transistor NM3 the gate and the drain of the second N-type MOS transistor NM2 are respectively connected to the first antenna terminal in1, and the gate and the drain of the third N-type MOS transistor NM3 are respectively connected to a second antenna terminal in2,
  • the second N-MOS transistor NM2 is connected to the source of the third N-type MOS transistor NM3 source, coupled to the resonant circuit for converting AC power to DC power supply V 1 and output to the limiter circuit input , providing power to the limiter circuit.
  • the fifth diode D5 and the second N-type MOS transistor NM2, and the sixth diode D6 and the third N-type MOS transistor NM3 are all unidirectional electronic components for using the first antenna end in1 and the first
  • the AC power supply between the two antenna terminals in2 is rectified to the DC power supply V 1 , and the voltage value of V 1 is V in1 (positive half cycle AC signal) or V in2 (negative half cycle AC signal) minus the threshold voltage of the diode or MOS transistor.
  • the third rectifying branch is a seventh diode D7 and an eighth diode D8 connected between the first antenna end in1 and the second antenna end in2, the seventh diode D7 and the eighth two
  • the cathode end of the pole tube D8 is connected to the drain of the first N-type MOS transistor NM1, the gate of the first N-type MOS transistor NM1 is connected to the output terminal V R of the limiter circuit, and the source thereof is grounded for the field strength
  • the charge coupled to the resonant circuit is strongly output to the ground, thereby reducing the amount of charge between the first antenna end in1 and the second antenna end in2.
  • the third rectifying branch is a fourth N-type connected between the first antenna end in1 and the second antenna end in2.
  • a MOS transistor NM4 and a fifth N-type MOS transistor NM5 the gate and the drain of the fourth N-type MOS transistor NM4 are respectively connected to the first antenna terminal in1, and the gate and the drain of the fifth N-type MOS transistor NM5 are respectively connected to
  • the source of the fourth N-type MOS transistor NM4 is connected to the source of the fifth N-type MOS transistor NM5 and is connected to the drain of the first N-type MOS transistor NM1, and the gate of the first N-type MOS transistor NM1 Connected to the output terminal V R of the limiter circuit, the source thereof is grounded, and is used to output the charge coupled to the resonant circuit to the ground when the field strength is too strong, thereby reducing the distance between the first antenna end in1 and the second antenna end
  • the seventh diode D7 and the fourth N-type MOS transistor NM4, and the eighth diode D8 and the fifth N-type MOS transistor NM5 are all unidirectional electronic components for using the first antenna end in1 and the first
  • the AC power source between the two antenna terminals in2 is rectified to a DC power source and input to the first N-type MOS transistor NM1.
  • the unidirectional conductive electronic components in the first rectifying branch, the second rectifying branch, and the third rectifying branch that can be rectified may adopt any combination of diodes or MOS tubes, including but not limited to The two combinations shown in the figure, and the amplification ratio of the diode or MOS tube can be set by adjusting the size of the diode (ie, the area of the PN junction) or adjusting the channel size ratio of the MOS transistor to save work. The purpose of consumption.
  • FIG. 4 is a structural diagram of a limiter circuit used in the present invention.
  • the limiting circuit includes a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a resistor R, and a threshold unit.
  • the first P-type MOS transistor PM1 and PM2 second P-type MOS transistor are respectively connected to the power source V 1 as a current source, a first P-MOS transistor PM1 is connected to the gate of the second P-type MOS transistor PM2 constituting the gate In the current mirror, the gate of the first P-type MOS transistor PM1 is connected to its drain and connected to the threshold unit, and the output of the threshold unit is grounded.
  • the drain of the second P-type MOS transistor PM2 is connected to the gate of the first N-type MOS transistor NM1 and is grounded through the resistor R.
  • the threshold unit is configured to form a single-conductor branch with the first P-type MOS transistor PM1, and the function of defining the on-voltage can be achieved by setting the number of unidirectional electronic components in the branch.
  • the threshold unit may employ at least one diode connected in series, or at least one P-type MOS transistor connected in series, or at least one N-type MOS transistor connected in series.
  • One of the at least one diode is connected to the anode end of the adjacent diode to form a series structure, and the anode end of the first diode is connected to the input end of the threshold unit of the first P-type MOS transistor PM1.
  • the last diode cathode end is grounded to the output of the threshold unit;
  • the drain terminal of any P-type MOS transistor is connected to the source terminal of the adjacent P-type MOS transistor to form a series structure, and the source of the first P-type MOS transistor is connected to the first P
  • the drain terminal of the MOS transistor PM1 is the input terminal of the threshold cell, the drain of the last P-type MOS transistor is grounded to be the output terminal of the threshold cell, and the gates of each P-type MOS transistor are connected to the drain;
  • any N-type MOS transistor source terminal and an adjacent N-type MOS transistor The drain terminals are connected to form a series structure.
  • the drain of the first N-type MOS transistor is connected to the drain terminal of the first P-type MOS transistor PM1 as the input terminal of the threshold unit, and the source of the last N-type MOS transistor is grounded.
  • the gates of the respective N-type MOS transistors are connected to the drain.
  • FIG. 5 is a structural diagram of a first embodiment of a limiter circuit according to the present invention.
  • the threshold unit is a ninth diode D9 and a tenth diode D10 connected in series, and the ninth two
  • the anode of the pole tube D9 is connected to the drain terminal of the first P-type MOS transistor PM1, the cathode thereof is connected to the anode of the tenth diode D10, and the anode of the tenth diode D10 is grounded.
  • FIG. 6 is a structural diagram of a second embodiment of the limiter circuit of the present invention.
  • the threshold unit is a third P-type MOS transistor PM3 and a fourth P-type MOS transistor PM4 connected in series, the The P-type MOS transistor PM3 source is connected to the drain terminal of the first P-type MOS transistor PM1, the gate thereof is connected to the drain thereof and is connected to the fourth P-type MOS transistor PM4 source, and the fourth P-type MOS transistor PM4 The gate is connected to its drain and grounded.
  • FIG. 7 is a structural diagram of a third embodiment of the limiter circuit of the present invention.
  • the threshold unit is a sixth N-type MOS transistor NM6 and a seventh N-type MOS transistor NM7 connected in series.
  • the drain of the six N-type MOS transistor NM6 is connected to the drain terminal of the first P-type MOS transistor PM1, the gate thereof is connected to the drain terminal thereof, and the source thereof is connected to the drain of the seventh N-type MOS transistor NM7, and the seventh N-type
  • the gate of the MOS transistor NM7 is connected to its drain, and its source is grounded.
  • the first P-type MOS transistor PM1 and the threshold unit are connected in series between the voltage source and the ground, and the starting voltage of the unidirectional conduction branch is the gate voltage and the threshold unit of the first P-type MOS transistor PM1.
  • the sum of the on-voltages can be controlled by setting the diode of the threshold unit, or the number of P-type MOS tubes or N-type MOS tubes, that is, if the voltage at the antenna end is required to be started at a lower level.
  • the limiter circuit Turning on to achieve leakage; conversely, if the voltage at the antenna end is required to start the limiting circuit at a higher level, connect more diodes or MOS transistors in the branch to increase the sum of the on-voltages, when V 1 Below the sum of the on-voltages, the limiting circuit is non-conducting, and the charges are all concentrated between the first antenna end and the second antenna end, and converted into a higher DC power supply to the load circuit.
  • Another object of the embodiments of the present invention is to provide a passive RFID including the dynamic rectification control circuit, wherein the passive radio frequency identification tag can dynamically rectify a voltage between a first antenna end and a second antenna end. Controlling, when the voltage is too high, the dynamic rectification control circuit can output the electric charge of the antenna end to the ground, thereby reducing the amount of electric charge at the antenna end, reducing the rectified DC voltage, and preventing the excessive voltage from damaging the load circuit. At the same time, it prevents the occurrence of saturation at the reader end.
  • a further object of embodiments of the present invention is to provide a method for continuously dynamic rectification control of a circuit using the above passive RFID, the method comprising the following steps:
  • the resonant capacitor and the resonant inductor receive an external electromagnetic field and couple it to the rectifier circuit, the rectifier circuit rectifies the AC power source into a DC power source V 1 and outputs it to the limiter circuit;
  • V 1 is less than the sum of the gate voltage of the first P-type MOS transistor and the turn-on voltage of the threshold cell, the first P-type MOS transistor and the threshold cell are not turned on, and the drain of the second P-type MOS transistor is discharged.
  • V R When the current is zero, V R is zero, and the first N-type MOS transistor is not turned on, and the amount of charge between the first antenna end and the second antenna end is not affected; if the V 1 value is greater than the first P-type MOS tube
  • the sum of the gate-source voltage and the turn-on voltage of the threshold cell, the first P-type MOS transistor and the threshold cell branch are turned on, and the first P-type MOS transistor mirrors the current to the second P-type MOS transistor and generates a voltage through the resistor
  • the difference is input to the gate of the first N-type MOS transistor, and the first N-type MOS transistor is turned on, and the charge between the first antenna end and the second antenna end is output to the ground through the source thereof, so that the first antenna end and the first antenna The amount of charge between the two antenna ends is reduced;
  • the amount of charge between the first antenna end and the second antenna end is reduced, and the AC voltage of the two ends of the bridge rectifier circuit (ie, the first antenna end and the second antenna end) is reduced, and the DC power source is rectified. If the charge between the first antenna end and the second antenna end is always higher than the defined voltage value, the leakage path is always turned on, so that the charge amount is continuously decreased until the leakage voltage is lower than the limit voltage value.
  • the channel is disconnected to achieve continuous, cyclic dynamic rectification control of the circuit voltage, preventing excessive voltage from damaging the load circuit and preventing the receiver from receiving saturation.

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Abstract

一种动态整流控制电路(1)，包括：谐振电容(C1)，与谐振电感(L)并联连接于第一天线端(in1)与第二天线端(in2)之间，用于与谐振电感组成谐振电路，接收外部电磁场并将其耦合至整流电路(2)；整流电路，其输入端连接至第一天线端与第二天线端，用于将谐振电路耦合的交流电源转换为直流电源(Vdd_out)并输出，以及为限幅电路提供电源，同时其一路输出端接地(GND)，用于在场强过强时将电荷输出至地；限幅电路，其电源输入端连接至整流电路电源输出端(V 1)，其输出端(V R)连接至整流电路控制输入端。当天线端电压过高时，动态整流控制电路可将接地通路导通，从而使天线端的电荷输出至地，减小天线端的电荷量，使整流出的直流电压降低。该动态整流控制电路能够防止过高的电压损坏负载电路，同时也防止读卡器端接收饱和现象的发生。此外，还提供了一种包括该动态整流控制电路的无源RFID，以及一种应用该无源RFID对电路进行动态整流控制的方法。

Description

一种动态整流控制电路与无源RFID及动态整流控制方法 技术领域
本发明属于射频识别技术领域，具体是指一种动态整流控制电路以及包括该电路的无源RFID，同时，本发明还涉及应用上述无源RFID对电路进行动态整流控制的方法。
背景技术
无源射频识别(Radio Frequency Identification，RFID)标签本身不带电池，其依靠读卡器发送的电磁能量工作。由于它结构简单、经济实用，因而其在物流管理、资产追踪以及移动医疗领域获得了广泛的应用。
无源RFID标签工作时，其会从周围环境中吸收读卡器发送的电磁能量。无源RFID标签在吸收能量之后，将一部分能量整流为直流电源，以供无源RFID标签内部电路工作；无源RFID标签还将另一部分能量输入内部的调制解调电路，调制解调电路会对该能量中携带的幅度调制信号进行解调，并将解调后的信号发送给无源RFID标签的数字基带部分处理。
由于无源RFID标签与读卡器的距离是变化的，因此，当无源RFID标签工作时，其从周围环境中吸收的电磁能量也是变化的。当无源RFID标签离读卡器太近或读卡器发送的电磁能量太强时，无源RFID标签接收到的信号强度也较强，以至线圈上感应的电压超过了芯片中整流器模块所用的晶体管的耐压极限，造成晶体管的永久性损坏，导致RFID标签失效。
无源RFID标签通过负载调制的方式传输数据到读卡器，读卡器端的线圈探 测到RFID标签端线圈的阻抗变化从而获取数据。当无源RFID标签离读卡器太近或读卡器发送的电磁能量太强时，从RFID标签端耦合回来的负载调制信号容易造成读卡器接受端的饱和，以至通讯失败。这种失败在读卡器首先发命令然后等待RFID标签应答的RTF通讯模式(Reader Talk First)下更容易发生。
为了解决上述耐压可靠性以及读卡器接受饱和的问题，RFID标签芯片电路内部需要施加幅度限制处理电路，以确保RFID标签上的天线两端电压被限制在一个预定的数值。
电子科技大学以2010年11月30日申请的名称为《一种用于超高频射频识别标签芯片的解调电路》，申请号为201010568305.4的发明专利中，幅度限制功能是通过一个电压比较器实施的，该电压比较器比较了包络检波电路产生的包络信号，即数据信息，和包络信号本身的均值之间的大小对比关系，从而由电压比较器后面的反相器输出高低逻辑信号，即解调后的信号。如此，即使在读卡器与电子标签之间的很近或很远导致的信号强度差异很大的情况下，该解调电路仍能够自适应地保证均值产生电路的稳定性，从而确保了解调电路正常稳定的工作。
上述专利中所用的自适应调整第一PMOS管栅极电压的技术是间接监控射频信号强度的一种方法。其中动态调整的对象是作为等效电阻用的PMOS管，使得在不同信号强度下该PMOS管的沟道等效电阻保持稳定，也即和电容组成的滤波时间常数稳定，最终获得稳定的检波效果，确保了解调电路正常稳定的工作。本申请针对整流器电压幅度的动态调整而监控射频信号强度的大小，调整对象为整流器的限幅电路，使得从天线端口到地的漏电流通路在不同的信号强度情况下有不同程度的开启程度，从而保护了射频前端的晶体管不受高压影响，也 避免了读卡器端的接收饱和现象的发生。
株式会社岛津制作所以2008年6月9日申请的，名称为《限幅电路》，申请号为200880129721.5的PCT专利，提出一种利用晶体管的导通、截止切掉超出上下限阈值信号电压值的限幅电路。该限幅电路是用于对信号强度的限幅，且其针对的是有恒定电源输入的电路，不同于本申请中所采用的整流控制电路，且也无法将该电路转用于RFID电路中。
天津南大强芯半导体芯片设计有限公司以2007年8月20号申请的，名称为《一种射频识别标签电路***结构及其工作方法与应用》，申请号为200710058875.7的发明专利,唯一的提出的发明点是从整流器输出的供电电源线分了几路给不同的模块,并以此提出提高了能量转换和使用效率的观点。首先，就其电源线分开几路接到不同模块的做法，是芯片设计中的常规做法，但是该申请中未能阐述清楚能量转换和使用效率是如何提高的，提高到什么程度。要达到真正的效率提高，光是该申请中所提到的接法(那本身就是一个普通接法)是不够的，用整流器输出支路直接给存储器控制模块的高压产生电路供电甚至会导致电荷泵所用的振荡器功耗很大的问题。其次，该申请没有涉及本专利申请所述动态调整整流器输入端电压幅度电路的方面，跟本专利申请的发明点没有重复性。
上海华虹集成电路有限责任公司以2006年03月17日申请的，名称为《用于非接触式IC卡和射频识别标签芯片的限幅保护电路》，申请号为200610024814.4的发明专利中，提出一种以提高射频标签芯片的稳压，时钟，解调和复位电路的性能为目的的限幅电路，该限幅电路以保护瞬间感应的强场所造成的过压驱动为目的，并且解决了读卡器一端的接受饱和问题。该专利与 本申请所存在的区别点在于：
1、因为限幅电路的目的不同，所以上海华虹的限幅电路是由高压或者低压的检测电路控制对一个电容的充放电来产生限幅信号。该限幅信号在比场强度的变化有着明显较大的时间常数，即缓慢反应天线上电压幅度的变化。这样的技术不能起到本申请所提出的过压保护的目的，因为在有限的时间常数之内，射频标签芯片内部的晶体管已经处在过压驱动的不可靠状态。所以本申请所公开的限幅电路对天线上电压的变化有着极快的反应速度，能够起到很好的保护作用。
2、上海华虹的限幅电路有两条泄放通路，其中一条慢通路，如前所述，不适合过压保护，另一条由解调信号控制的泄放通路，与本申请所公开的技术有着本质的不同。
3、上海华虹的高压检测与低压检测信号所控制的开关管有两个恒定电流源作为偏置，在无源射频标签***中将造成较大的直流功耗，不利于达到低功耗，高灵敏度的目的。
4、上海华虹的限幅电路在检测天线两端电压上存在两个判断点，即电压过低的临界点和电压过高的临界点。当天线两端的电压低于电压过低的临界点时，电容上的电荷得到泄放。当天线两端电压高于电压过高的临界点时，电容上的电荷得到充电积累。这其中的问题是当天线两端的电压处于两个临界点之间时，上下两个控制开关均处于关断状态，电容上的电压是浮动的，不受任何信号控制。在无源射频标签芯片中这是一个致命的问题，容易造成不可控的泄放电流而损失能量，影响标签的灵敏度。这个问题在本申请所公开的技术中是不存在的，本申请中定义了一个唯一的判定点来控制开关的开启和关闭，一旦开启， 该调解是连续可调的。
发明内容
本发明实施例所要解决的技术问题在于，提供一种动态整流控制电路和包括该动态整流控制电路的无源RFID，以及应用该无源RFID对电路进行动态整流控制的方法，通过对整流器电压幅度进行连续动态调整实现对电路电压的控制，防止读卡器端接收饱和现象的发生。
为实现上述目的，本发明所采取的技术方案为：
一种动态整流控制电路，所述该电路包括：
谐振电容，与谐振电感并联连接于第一天线端与第二天线端之间，用于与谐振电感组成谐振电路，接收外部电磁场并将其耦合至整流电路；
整流电路，其输入端连接至第一天线端与第二天线端，用于将所述谐振电路耦合的交流电源转换为直流电源并输出，以及为限幅电路提供电源，同时其一路输出端接地，用于在场强过强时将电荷输出至地；
限幅电路，其电源输入端连接至所述整流电路电源输出端，其输出端连接至整流电路控制输入端。
本发明实施例的另一目的在于提供一种包括上述动态整流控制电路的无源RFID。
本发明实施例的再一目的在于应用上述无源RFID对电路进行连续动态整流控制的方法，该方法包括如下步骤：
a、谐振电容与谐振电感接收外部电磁场并将其耦合至整流电路，整流电路将该交流电源整流为直流电源V1并输出至限幅电路；
b、若V1值小于第一P型MOS管栅源电压及阈值单元的导通电压之和，则第一P型MOS管和阈值单元不导通，第二P型MOS管漏极输出的电流为零，则VR为零,第一N型MOS管不导通，对第一天线端与第二天线端之间的电荷量不造成影响；若V1值大于第一P型MOS管栅源电压及阈值单元的导通电压之和，则第一P型MOS管和阈值单元支路导通，第一P型MOS管将该电流镜像至第二P型MOS管并通过电阻产生电压差输入至第一N型MOS管栅极，第一N型MOS管导通，通过其源极将第一天线端与第二天线端之间的电荷输出至地，使得第一天线端与第二天线端之间的电荷量减小；
c、第一天线端与第二天线端之间的电荷量减小，则桥式整流电路两端的交流电压减小，其整流出的直流电源减小，从而实现对电路电压进行连续的、循环的动态整流控制。
本发明所述无源RFID可连续的对第一天线端与第二天线端之间的电压进行动态的整流控制，当天线端电压过高时，所述的动态整流控制电路可将接地通路导通，从而使天线端的电荷输出至地，减小天线端的电荷量，使整流出的直流电压降低；当该电压在限定电压以内时，接地通路处于截止状态，整流电路将天线端的全部电荷整流为直流电源供负载电路使用，防止了过高的电压损坏负载电路，同时也防止了读卡器端接收饱和现象的发生。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳 动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的电路总体结构框图；
图2是本发明采用的整流电路实施例一结构图；
图3是本发明采用的整流电路实施例二结构图；
图4是本发明采用的限幅电路结构图；
图5是本发明采用的限幅电路实施例一结构图；
图6是本发明采用的限幅电路实施例二结构图；
图7是本发明采用的限幅电路实施例三结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在描述本发明实施例之前，需要对本发明实施例中所涉及的一些关键词进行解释。本发明实施例中所述的连接，代表两个连接端点之间存在直接或间接的连接关系。
如图1所示，为本发明的电路总体结构框图。本发明所述一种动态整流控制电路1包括：
谐振电容C1，其与谐振电感L并联连接于第一天线端in1与第二天线端in2之间，用于与谐振电感L组成谐振电路，接收外部电磁场并将其耦合至整流电路；
整流电路，其输入端连接至第一天线端in1与第二天线端in2，用于将所述谐振电路耦合的交流电源转换为直流电源并输出至外部负载电路，其另一路输出端为限幅电路提供电源，同时一路输出端接地，用于在场强过强时将电荷输出至地；
限幅电路，其电源输入端连接至所述整流电路电源输出端V1，其输出端VR连接至整流电路控制输入端。
图2为本发明采用的整流电路实施例一结构图。所述整流电路2包括并联连接于第一天线端in1与第二天线端in2之间的第一整流支路，第二整流支路以及第三整流支路。
所述第一整流支路为桥式整流电路，其一输出端接地，另一输出端Vdd_out连接至外部负载电路，用于将谐振电路耦合的交流电源转换为直流电源为外部负载电路提供电源。
所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第五二极管D5和第六二极管D6，所述第五二极管D5和第六二极管D6用于将谐振电路耦合的交流电源转换为直流电源V1并输出至限幅电路输入端，为限幅电路提供电源。
第二整流支路的第二种实施例结构如图3所示，该实施例中所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第二N型MOS管NM2和第三N型MOS管NM3，所述第二N型MOS管NM2栅极和漏极分别连接至第一天线端in1，第三N型MOS管NM3栅极和漏极分别连接至第二天线端in2，第二N型MOS管NM2源极连接至第三N型MOS管NM3源极,用于将谐振电路耦合的交流电源转换为直流电源V1并输出至限幅电路输入端，为限幅电路提供电源。
上述第五二极管D5和第二N型MOS管NM2，以及第六二极管D6和第三N型MOS管NM3均为单向导通的电子元件，用于将第一天线端in1与第二天线端in2之间的交流电源整流为直流电源V1，则V1的电压值为Vin1(正半周交流信号)或Vin2(负半周交流信号)减去二极管或MOS管的阈值电压。
所述第三整流支路为连接于第一天线端in1与第二天线端in2之间的第七二极管D7和第八二极管D8，所述第七二极管D7和第八二极管D8阴极端连接至第一N型MOS管NM1漏极，所述第一N型MOS管NM1栅极连接至限幅电路的输出端VR，其源极接地，用于在场强过强时将谐振电路耦合的电荷输出至地，从而减小第一天线端in1与第二天线端in2之间的电荷量。
第三整流支路的第二种实施例结构如图3所示，该实施例中所述第三整流支路为连接于第一天线端in1与第二天线端in2之间的第四N型MOS管NM4和第五N型MOS管NM5，所述第四N型MOS管NM4栅极和漏极分别连接至第一天线端in1，第五N型MOS管NM5栅极和漏极分别连接至第二天线端in2，第四N型MOS管NM4源极连接至第五N型MOS管NM5源极并连接至第一N型MOS管NM1漏极，所述第一N型MOS管NM1栅极连接至限幅电路的输出端VR，其源极接地，用于在场强过强时将谐振电路耦合的电荷输出至地，从而减小第一天线端in1与第二天线端in2之间的电荷量。
上述第七二极管D7和第四N型MOS管NM4，以及第八二极管D8和第五N型MOS管NM5均为单向导通的电子元件，用于将第一天线端in1与第二天线端in2之间的交流电源整流为直流电源并输入至第一N型MOS管NM1。
所述第一整流支路、第二整流支路以及第三整流支路中起整流作用的单向导通电子元件均可采用二极管或MOS管的任意形式的组合，包含但并不限于附 图中所示出的两种组合方式，且可以通过调整所述二极管的尺寸(即PN结的面积)或调整MOS管的沟道尺寸比例来设定二极管或MOS管的放大比例，达到节省功耗的目的。
如图4所示为本发明采用的限幅电路结构图。所述限幅电路包括第一P型MOS管PM1、第二P型MOS管PM2、电阻R以及阈值单元，
所述第一P型MOS管PM1和第二P型MOS管PM2源极分别连接至电源V1作为电流源，第一P型MOS管PM1栅极连接至第二P型MOS管PM2栅极构成电流镜，第一P型MOS管PM1栅极连接至其漏极并连接至所述阈值单元，阈值单元的输出端接地。所述第二P型MOS管PM2漏极连接至第一N型MOS管NM1栅极并通过电阻R接地。
所述阈值单元用于与第一P型MOS管PM1组成一个单向导通支路，且可通过设定该支路中单向导通电子元器件的数量来达到限定导通电压的功能。因此，所述阈值单元可采用至少一个串联连接的二极管，或者是至少一个串联连接的P型MOS管，或者是至少一个串联连接的N型MOS管。
所述至少一个二极管中，任一二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至第一P型MOS管PM1的漏极端为所述阈值单元的输入端，最后一个二极管阴极端接地为所述阈值单元的输出端；
所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至第一P型MOS管PM1的漏极端为所述阈值单元的输入端，最后一个P型MOS管的漏极接地为所述阈值单元的输出端,各P型MOS管的栅极均与漏极相连；
所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的 漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至第一P型MOS管PM1的漏极端为所述阈值单元的输入端，最后一个N型MOS管的源极接地为所述阈值单元的输出端,各N型MOS管的栅极均与漏极相连。
如图5所示为本发明限幅电路的第一实施例结构图，该实施例中所述阈值单元为串联连接的第九二极管D9和第十二极管D10，所述第九二极管D9正极连接至第一P型MOS管PM1漏极端，其负极连接至第十二极管D10正极，第十二极管D10负极接地。
如图6所示为本发明限幅电路的第二实施例结构图，该实施例中所述阈值单元为串联连接的第三P型MOS管PM3和第四P型MOS管PM4，所述第三P型MOS管PM3源极连接至第一P型MOS管PM1漏极端，其栅极连接至其漏极并连接至所述第四P型MOS管PM4源极，第四P型MOS管PM4栅极连接至其漏极并接地。
如图7所示为本发明限幅电路的第三实施例结构图，该实施例中所述阈值单元为串联连接的第六N型MOS管NM6和第七N型MOS管NM7，所述第六N型MOS管NM6漏极连接至第一P型MOS管PM1漏极端，其栅极连接至其漏极端，其源极连接至所述第七N型MOS管NM7漏极，第七N型MOS管NM7栅极连接至其漏极，其源极接地。
本实施例以在电压源与地之间串接第一P型MOS管PM1和阈值单元为例，则该单向导通支路的启动电压为第一P型MOS管PM1栅源电压及阈值单元的导通电压之和，可通过设定阈值单元的二极管，或P型MOS管或N型MOS管的数量来控制启动电压的值，即：若需要天线端的电压在较低的情况下即启动限幅电路，则在该支路串接较少的二极管或MOS管，则各电子元器件的导通电压之 和小，当V1高于该导通电压之和时，该限幅电路即导通实现漏电；反之，若需要天线端的电压在较高的情况下才启动限幅电路，则在该支路串接较多的二极管或MOS管，使导通电压之和增加，当V1低于该导通电压之和时，限幅电路不导通，电荷全部聚集于第一天线端与第二天线端之间，并转换为较高的直流电源供给负载电路。
本发明实施例的另一目的在于提供一种包括上述动态整流控制电路的无源RFID，所述该无源射频识别标签可对第一天线端与第二天线端之间的电压进行动态的整流控制，当该电压过高时，所述的动态整流控制电路可将天线端的电荷输出至地，从而减小天线端的电荷量，使整流出的直流电压降低，防止过高的电压损坏负载电路，同时也防止了读卡器端接收饱和现象的发生。
本发明实施例的再一目的在于提供应用上述无源RFID对电路进行连续动态整流控制的方法，该方法包括如下步骤：
a、谐振电容与谐振电感接收外部电磁场并将其耦合至整流电路，整流电路将该交流电源整流为直流电源V1并输出至限幅电路；
b、若V1值小于第一P型MOS管栅源电压及阈值单元的导通电压之和，则第一P型MOS管和阈值单元不导通，第二P型MOS管漏极输出的电流为零，则VR为零，第一N型MOS管不导通，对第一天线端与第二天线端之间的电荷量不造成影响；若V1值大于第一P型MOS管栅源电压及阈值单元的导通电压之和，则第一P型MOS管和阈值单元支路导通，第一P型MOS管将该电流镜像至第二P型MOS管并通过电阻产生电压差输入至第一N型MOS管栅极，第一N型MOS管导通，通过其源极将第一天线端与第二天线端之间的电荷输出至地，使得第一天线端与第二天线端之间的电荷量减小；
c、第一天线端与第二天线端之间的电荷量减小，则桥式整流电路两端(即第一天线端与第二天线端)的交流电压减小，其整流出的直流电源减小，若第一天线端与第二天线端之间的电荷始终高于所限定的电压值，则该漏电的通路始终导通，使电荷量不断减小直至低于限定电压值后该漏电通路断开，实现对电路电压进行连续的、循环的动态整流控制，防止过高的电压损坏负载电路，同时也防止了读卡器端接收饱和现象的发生。

Claims (10)

  1. 一种动态整流控制电路，其特征在于，所述电路包括：
    谐振电容，与谐振电感并联连接于第一天线端与第二天线端之间，用于与谐振电感组成谐振电路，接收外部电磁场并将其耦合至整流电路；
    整流电路，其输入端连接至第一天线端与第二天线端，用于将所述谐振电路耦合的交流电源转换为直流电源并输出，以及为限幅电路提供电源，同时其一路输出端接地，用于在场强过强时将电荷输出至地；
    限幅电路，其电源输入端连接至所述整流电路电源输出端，其输出端连接至整流电路控制输入端。
  2. 根据权利要求1所述的动态整流控制电路，其特征在于，所述整流电路包括并联连接于第一天线端与第二天线端之间的第一整流支路，第二整流支路以及第三整流支路。
  3. 根据权利要求2所述的动态整流控制电路，其特征在于，所述第二整流支路为连接于第一天线端与第二天线端之间的第五二极管和第六二极管，所述第五二极管和第六二极管阴极端连接至限幅电路输入端，用于为限幅电路提供电源。
  4. 根据权利要求2所述的动态整流控制电路，其特征在于，所述第二整流支路为连接于第一天线端与第二天线端之间的第二N型MOS管和第三N型MOS管，所述第二N型MOS管栅极和漏极分别连接至第一天线端，第三N型MOS管栅极和漏极分别连接至第二天线端，第二N型MOS管源极连接至第三N型MOS管源极并输出至限幅电路输入端，用于为限幅电路提供电源。
  5. 根据权利要求2所述的动态整流控制电路，其特征在于，所述第三整流支路为连接于第一天线端与第二天线端之间的第七二极管和第八二极管，所述 第七二极管和第八二极管阴极端连接至第一N型MOS管漏极，所述第一N型MOS管栅极连接至限幅电路的输出端，其源极接地，用于在场强过强时将电荷输出至地。
  6. 根据权利要求2所述的动态整流控制电路，其特征在于，所述第三整流支路为连接于第一天线端与第二天线端之间的第四N型MOS管和第五N型MOS管，所述第四N型MOS管栅极和漏极分别连接至第一天线端，第五N型MOS管栅极和漏极分别连接至第二天线端，第四N型MOS管源极连接至第五N型MOS管源极并连接至第一N型MOS管漏极，所述第一N型MOS管栅极连接至限幅电路的输出端，其源极接地，用于在场强过强时将电荷输出至地。
  7. 根据权利要求1所述的动态整流控制电路，其特征在于，所述限幅电路包括第一P型MOS管、第二P型MOS管、电阻以及阈值单元，
    所述第一P型MOS管和第二P型MOS管源极分别连接至电源作为电流源，第一P型MOS管栅极连接至第二P型MOS管栅极构成电流镜，第一P型MOS管栅极连接至其漏极并连接至所述阈值单元，阈值单元的输出端接地；
    所述第二P型MOS管漏极连接至第一N型MOS管栅极并通过电阻接地。
  8. 根据权利要求7所述的动态整流控制电路，其特征在于，所述阈值单元为至少一个串联连接的二极管，或者是至少一个串联连接的P型MOS管，或者是至少一个串联连接的N型MOS管，
    所述至少一个二极管中，任一二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至第一P型MOS管的漏极端为所述阈值单元的输入端，最后一个二极管阴极端接地为所述阈值单元的输出端；
    所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的 源极端连接形成串联结构，第一个所述P型MOS管的源极连接至第一P型MOS管的漏极端为所述阈值单元的输入端，最后一个P型MOS管的漏极接地为所述阈值单元的输出端,各P型MOS管的栅极均与漏极相连；
    所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至第一P型MOS管的漏极端为所述阈值单元的输入端，最后一个N型MOS管的源极接地为所述阈值单元的输出端,各N型MOS管的栅极均与漏极相连。
  9. 一种无源RFID，其特征在于，所述无源RFID包括如权利要求1-8中任一所述的动态整流控制电路。
  10. 一种应用如权利要求9所述的无源RFID对电路进行连续动态整流控制的方法，其特征在于，该方法包括如下步骤：
    a、谐振电容与谐振电感接收外部电磁场并将其耦合至整流电路，整流电路将该交流电源整流为直流电源V1并输出至限幅电路；
    b、若V1值小于第一P型MOS管栅源电压及阈值单元的导通电压之和，则第一P型MOS管和阈值单元不导通，第二P型MOS管漏极输出的电流为零，则VR为零,第一N型MOS管不导通，对第一天线端与第二天线端之间的电荷量不造成影响；若V1值大于第一P型MOS管栅源电压及阈值单元的导通电压之和，则第一P型MOS管和阈值单元支路导通，第一P型MOS管将该电流镜像至第二P型MOS管并通过电阻产生电压差输入至第一N型MOS管栅极，第一N型MOS管导通，通过其源极将第一天线端与第二天线端之间的电荷输出至地，使得第一天线端与第二天线端之间的电荷量减小；
    c、第一天线端与第二天线端之间的电荷量减小，则桥式整流电路两端的交 流电压减小，其整流出的直流电源减小，从而实现对电路电压进行连续的、循环的动态整流控制。
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