WO2015025867A1 - Semiconductor adhesive - Google Patents

Semiconductor adhesive Download PDF

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Publication number
WO2015025867A1
WO2015025867A1 PCT/JP2014/071723 JP2014071723W WO2015025867A1 WO 2015025867 A1 WO2015025867 A1 WO 2015025867A1 JP 2014071723 W JP2014071723 W JP 2014071723W WO 2015025867 A1 WO2015025867 A1 WO 2015025867A1
Authority
WO
WIPO (PCT)
Prior art keywords
adhesive
semiconductor
semiconductor chip
resin
substrate
Prior art date
Application number
PCT/JP2014/071723
Other languages
French (fr)
Japanese (ja)
Inventor
麻衣 永田
幸平 竹田
久敏 岡山
畠井　宗宏
Original Assignee
積水化学工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 積水化学工業株式会社 filed Critical 積水化学工業株式会社
Priority to JP2014541453A priority Critical patent/JP5788107B2/en
Priority to CN201480034106.1A priority patent/CN105308730A/en
Priority to KR1020157032819A priority patent/KR20160045628A/en
Publication of WO2015025867A1 publication Critical patent/WO2015025867A1/en

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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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Definitions

  • the present invention relates to a semiconductor adhesive capable of suppressing voids.
  • flip chip mounting using a semiconductor chip having a large number of protruding electrodes formed on the surface has attracted attention and is rapidly spreading as a method for mounting a semiconductor chip on a substrate.
  • a liquid sealing adhesive in the gap between the semiconductor chip and the substrate
  • flip-chip mounting using underfill has a problem that it takes time to fill the underfill, and there is a problem that there is a limit in reducing the distance between the electrodes and the distance between the semiconductor chip and the substrate.
  • a void may be generated due to a volatile component from the adhesive. Such voids may cause a short circuit between the electrodes or cause cracks in the adhesive.
  • an object of the present invention is to provide an adhesive for a semiconductor that can suppress voids generated not only in the peripheral portion but also in the semiconductor chip surface inside the peripheral portion.
  • the present invention provides a step 1 for aligning a semiconductor chip having a protruding electrode having a tip portion made of solder formed on a peripheral portion and a semiconductor chip surface inside the peripheral portion on a substrate via a semiconductor adhesive. And heating the semiconductor chip to a temperature equal to or higher than the solder melting point to melt-bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and temporarily bond the adhesive for the semiconductor, and
  • a semiconductor adhesive used in a method for manufacturing a semiconductor device comprising: removing a void by heating a semiconductor adhesive in a pressurized atmosphere, wherein the semiconductor adhesive is at 80 to 200 ° C.
  • a semiconductor adhesive having a minimum melt viscosity of 1000 Pa ⁇ s or less and a required time to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method is 8 seconds or more. The present invention is described in detail below.
  • the inventor heats the semiconductor chip to a temperature equal to or higher than the solder melting point to bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and then heats the adhesive for the semiconductor in a pressurized atmosphere to form a void.
  • the adhesive for semiconductors used in the method for removing the surface was examined. As a result, even when heated by a pressurized atmosphere, the present inventor can sufficiently remove voids when the adhesive for semiconductors has progressed too much when bonding protruding electrodes.
  • an adhesive for semiconductors an adhesive whose curing is suppressed as much as possible even after a thermal history at the time of joining protruding electrodes, that is, an adhesive having a relatively slow curing rate (reaction rate) and a low minimum melt viscosity. It was found that it was necessary to use. Although it may be possible to suppress the curing of the adhesive for the semiconductor by adjusting the conditions for bonding the protruding electrodes, the temperature above the solder melting point (about 240 to 300 ° C.) is required for bonding the protruding electrodes. Therefore, there is a limit in suppressing the curing of the semiconductor adhesive only by adjusting the conditions.
  • the time required to reach a predetermined reaction rate at a constant temperature is determined from data obtained by differential scanning calorimetry (DSC measurement, Differential scanning calorimetry) of a sample.
  • An analysis method called “sawa) method” is known.
  • the present inventor studied by applying the Ozawa method to a semiconductor adhesive used in a method for manufacturing a semiconductor device. As a result, the present inventor found that a semiconductor chip having a protruding electrode in a peripheral portion is used for a semiconductor adhesive that satisfies a predetermined range of a minimum melt viscosity and a required time to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method. Voids were sufficiently removed not only when used but also when using a peripheral chip and a semiconductor chip having a protruding electrode in the surface inside the peripheral section.
  • the semiconductor adhesive of the present invention is a semiconductor chip in which a protruding electrode having a tip made of solder is formed in a peripheral part and a semiconductor chip surface inside the peripheral part on the substrate via the semiconductor adhesive.
  • the method is used in a method for manufacturing a semiconductor device, which includes Step 2 and Step 3 of removing the voids by heating the adhesive for semiconductor in a pressurized atmosphere.
  • a semiconductor chip in which a protruding electrode having a tip portion made of solder is formed in a semiconductor chip surface inside the peripheral portion and the peripheral portion Step 1 of aligning on the substrate through a semiconductor adhesive is performed.
  • the alignment step 1 generally, using a mounting device such as a flip chip bonder, the position of the protruding electrode of the semiconductor chip, the electrode portion of the substrate, and the alignment mark provided on the semiconductor chip and the substrate Is automatically recognized in the X and Y directions and the rotation direction ( ⁇ direction).
  • the semiconductor chip examples include a semiconductor chip made of a semiconductor such as silicon and gallium arsenide, and a protruding electrode having a tip portion made of solder, in addition to the peripheral portion, also exists on the inner surface of the peripheral portion.
  • the protruding electrode having the tip portion made of solder may be formed of a part of the protruding electrode, or the entire protruding electrode may be made of solder, as long as the tip portion is made of solder.
  • the method of supplying the semiconductor adhesive is not particularly limited. For example, a method of sticking a film-like adhesive on a substrate or a semiconductor chip, a paste-like adhesive filled in a syringe, and a precision nozzle at the tip of the syringe And a method of discharging onto a substrate using a dispenser device.
  • a film adhesive to the wafer by atmospheric pressure lamination, vacuum lamination, etc., or applying or printing a paste adhesive by spin coating or the like to form a coating film, blade dicing
  • a method of dividing into semiconductor chips by laser dicing or the like can be used.
  • step 3 In normal pressure lamination, air may be entrained, but the adhesive is removed in a pressurized atmosphere using a pressure oven (for example, PCO-083TA (manufactured by NTT Advanced Technology)) similar to step 3 for removing voids.
  • a pressure oven for example, PCO-083TA (manufactured by NTT Advanced Technology)
  • the voids may be removed by heating with
  • the semiconductor chip is then heated to a temperature equal to or higher than the solder melting point, and the protruding electrode of the semiconductor chip and the electrode portion of the substrate are melt bonded. And performing step 2 of temporarily adhering the semiconductor adhesive.
  • the step 2 for temporarily bonding the semiconductor adhesive is also generally performed using a mounting apparatus such as a flip chip bonder.
  • the solder melting point is usually about 215 to 235 ° C.
  • the preferable lower limit of the temperature above the solder melting point is 240 ° C., and the preferable upper limit is 300 ° C. If the temperature is lower than 240 ° C., the protruding electrode may not be sufficiently melted and electrode bonding may not be formed. When temperature exceeds 300 degreeC, a volatile component may generate
  • a preferable lower limit is 0.1 seconds, and a preferable upper limit is 3 seconds. If the holding time is less than 0.1 seconds, the protruding electrode may not be sufficiently melted and electrode bonding may not be formed. When holding time exceeds 3 second, a volatile component may generate
  • step 2 of temporarily bonding the semiconductor adhesive it is preferable to apply pressure to the semiconductor chip.
  • the pressure is not particularly limited as long as the electrode bond is formed, but is preferably 0.3 to 3 MPa.
  • the step 3 of removing the voids by heating the semiconductor adhesive in a pressurized atmosphere is then performed.
  • Under a pressurized atmosphere means a pressure atmosphere higher than normal pressure (atmospheric pressure).
  • normal pressure atmospheric pressure
  • Examples of the method for heating the semiconductor adhesive in a pressurized atmosphere include a method using a pressure oven (for example, PCO-083TA (manufactured by NTT Advanced Technology)).
  • the preferable lower limit of the pressure of the pressure oven is 0.1 MPa, and the preferable upper limit is 10 MPa. If the pressure is less than 0.1 MPa, the void may not be sufficiently removed. When the pressure exceeds 10 MPa, the semiconductor adhesive itself is deformed, which may adversely affect the reliability of the semiconductor device.
  • the more preferable lower limit of the pressure is 0.3 MPa, and the more preferable upper limit is 1 MPa.
  • the minimum with a preferable heating temperature at the time of heating the said adhesive agent for semiconductors in a pressurized atmosphere is 60 degreeC, and a preferable upper limit is 150 degreeC.
  • a preferable heating temperature at the time of heating the said adhesive agent for semiconductors in a pressurized atmosphere is 60 degreeC, and a preferable upper limit is 150 degreeC.
  • the heating time at the time of heating the said adhesive agent for semiconductors in a pressurized atmosphere is 10 minutes or more.
  • step 4 for completely curing the adhesive for semiconductor may be performed.
  • a method for completely curing the adhesive for semiconductors for example, after performing step 3 for removing voids, a method for completely curing the adhesive for semiconductors by raising the temperature in a pressurized atmosphere as it is under normal pressure. The method etc. which heat the semiconductor adhesive agent and harden it completely are mentioned.
  • the heating temperature for completely curing the adhesive for semiconductor is not particularly limited, but is preferably about 150 to 200 ° C.
  • the adhesive for semiconductors of the present invention has a minimum melt viscosity at 80 to 200 ° C. of 1000 Pa ⁇ s or less, and a required time to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method is 8 seconds or more.
  • the minimum melt viscosity is determined by rheometer measurement, and the rheometer measurement can be performed using a rotary rheometer device (for example, VAR-100 (manufactured by Rheological Corporation)). Means a value measured at a heating rate of 5 ° C./min, a frequency of 1 Hz, and a strain of 1%.
  • the Ozawa method can be performed using reaction rate analysis software (for example, manufactured by SII Nanotechnology), and means the analysis method shown below. First, differential scanning calorimetry with different heating rates is performed three or more times for the sample, and the reciprocal of temperature T and the logarithm (log B) of heating rate B are plotted.
  • the activation energy ⁇ E is calculated based on the following formula (1).
  • the reaction rate when held at 260 ° C. for 4 seconds and 260 ° C. for 6 seconds is calculated.
  • the required time to reach a reaction rate of 40% at 260 ° C. is calculated.
  • Differential scanning calorimetry can be performed using a DSC apparatus (for example, DSC 6220 (manufactured by SII Nano Technology)). (See Takeo Ozawa, Thermal Measurements 1, 2 (1974) and T. Ozawa, Bull. Chem. Soc. Japan 38, 1881 (1965).)
  • ⁇ represents a constant temperature deterioration time.
  • the adhesive for semiconductors of the present invention has a minimum melt viscosity at 80 to 200 ° C. of 1000 Pa ⁇ s or less.
  • the minimum melt viscosity exceeds 1000 Pa ⁇ s, the fluidity of the semiconductor adhesive is lowered in the step 3 of removing the voids, and even if the curing rate is within the above range, the voids cannot be sufficiently removed.
  • a more preferable upper limit is 400 Pa ⁇ s or less.
  • the lower limit of the minimum melt viscosity at 80 to 200 ° C. of the adhesive for semiconductor of the present invention is not particularly limited, but the preferable lower limit is 10 Pa ⁇ s. If the minimum melt viscosity is less than 10 Pa ⁇ s, the fillet protrudes too much and may contaminate other devices.
  • the time required for the semiconductor adhesive of the present invention to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method is 8 seconds or more.
  • the time to reach a reaction rate of 40% is less than 8 seconds, even if the minimum melt viscosity is within the above range, the curing of the semiconductor adhesive cannot be suppressed, and the void is sufficiently removed in the step 3 of removing the void. Can not be removed.
  • the time to reach a reaction rate of 40% is less than 8 seconds, the protruding electrode in the surface inside the peripheral part adversely affects the resin flow, and a characteristic void may remain in the step 3 of removing the void. There is sex.
  • the adhesive for semiconductors of the present invention may be in the form of a film or a paste, and preferably contains at least a thermosetting resin and a thermosetting agent.
  • the semiconductor adhesive of the present invention preferably further contains a curing accelerator. Since the reaction rate also depends on the concentration of the reaction system, for example, by adjusting the content of each component, particularly the addition amount of the curing accelerator, the time for reaching the reaction rate of 40% for the adhesive for semiconductors is in the above range. Can be adjusted. Specifically, the reaction rate tends to increase as the amount of the curing accelerator added increases, and the reaction rate tends to decrease as the amount increases.
  • the minimum melt viscosity of the adhesive agent for semiconductors can be adjusted to the said range by adjusting content, such as a thermosetting resin, a thermosetting agent, an inorganic filler, for example.
  • the semiconductor adhesive of the present invention preferably contains an epoxy resin, an acrylic resin having an epoxy group in the side chain, a thermosetting agent, and an inorganic filler because the minimum melt viscosity is easily adjusted to the above range.
  • thermosetting resin is not specifically limited, For example, the compound hardened
  • the thermosetting resin include urea resin, melamine resin, phenol resin, resorcinol resin, epoxy resin, acrylic resin, polyester resin, polyamide resin, polybenzimidazole resin, diallyl phthalate resin, xylene resin, alkyl -Benzene resin, epoxy acrylate resin, silicon resin, urethane resin and the like.
  • an epoxy resin is preferable from the viewpoint of easily adjusting the time required for the reaction rate of the semiconductor adhesive to reach 40% within the above range and the physical properties of the cured product.
  • the epoxy resin preferably has a low functional group concentration, that is, a high epoxy equivalent.
  • Epoxy resins with a high epoxy equivalent have a low reaction probability with a thermosetting agent and a low reactivity. By using such an epoxy resin, the time to reach a reaction rate of 40% of the adhesive for semiconductor is adjusted to the above range. It becomes easy to do.
  • the epoxy resin preferably has an epoxy equivalent of 200 or more, and more preferably 250 or more.
  • the epoxy resin is not particularly limited.
  • bisphenol type epoxy resins such as bisphenol A type, bisphenol F type, bisphenol AD type and bisphenol S type
  • novolac type epoxy resins such as phenol novolak type and cresol novolak type
  • resorcinol type epoxy Resin aromatic epoxy resin such as trisphenolmethane triglycidyl ether, naphthalene type epoxy resin, fluorene type epoxy resin, cyclopentadiene type or dicyclopentadiene type epoxy resin
  • polyether modified epoxy resin NBR modified epoxy resin, CTBN modified epoxy
  • examples thereof include resins and hydrogenated products thereof.
  • a cyclopentadiene type or dicyclopentadiene type epoxy resin having a bulky structure is preferable.
  • Cyclopentadiene-type or dicyclopentadiene-type epoxy resins have large steric hindrance and low reactivity. By using such an epoxy resin, the time to reach a reaction rate of 40% for a semiconductor adhesive is adjusted to the above range. It becomes easy.
  • These epoxy resins may be used independently and may use 2 or more types together.
  • the epoxy resin may be an epoxy resin that is liquid at room temperature, or may be an epoxy resin that is solid at room temperature, or may be used in appropriate combination.
  • commercially available products include, for example, bisphenol A type epoxy resins such as EPICLON 840, 840-S, 850, 850-S, EXA-850CRP (above, manufactured by DIC), EPICLON 830, Bisphenol F type epoxy resins such as 830-S and EXA-830CRP (made by DIC), naphthalene type epoxy resins such as EPICLON HP-4032 and HP-4032D (made by DIC), EPICLON EXA-7015 (DIC) And hydrogenated bisphenol A type epoxy resin such as EX-252 (manufactured by Nagase ChemteX), and resorcinol type epoxy resin such as EX-201 (manufactured by Nagase ChemteX).
  • epoxy resins that are solid at room temperature
  • commercially available products include, for example, bisphenol A type epoxy resins such as EPICLON 860, 10550, 1055 (manufactured by DIC), and bisphenol S such as EPICLON EXA-1514 (manufactured by DIC).
  • Type epoxy resin naphthalene type epoxy resin such as EPICLON HP-4700, HP-4710, HP-4770 (manufactured by DIC), dicyclopentadiene type epoxy resin such as EPICLON HP-7200 series (made by DIC), EPICLON Examples thereof include cresol novolac type epoxy resins such as HP-5000 and EXA-9900 (manufactured by DIC).
  • thermosetting agent is not specifically limited, A conventionally well-known thermosetting agent can be suitably selected according to the said thermosetting resin.
  • the thermosetting agent may be, for example, an acid anhydride curing agent, a phenol curing agent, an amine curing agent, a latent curing agent such as dicyandiamide, or a cationic catalytic curing. Agents and the like. These thermosetting agents may be used independently and may use 2 or more types together. Among these, an acid anhydride curing agent is preferable because of excellent physical properties of the cured product.
  • acid anhydride curing agents commercially available products include, for example, YH-306, YH-307 (manufactured by Mitsubishi Chemical Corporation, liquid at room temperature (25 ° C.)), YH-309 (manufactured by Mitsubishi Chemical Corporation, acid Anhydride type curing agent, solid at normal temperature (25 ° C.)) and the like.
  • the content of the thermosetting agent is not particularly limited.
  • the content of the thermosetting agent is an adhesive for a semiconductor.
  • a preferred lower limit to the total amount of epoxy groups contained in the agent is 60 equivalents, and a preferred upper limit is 110 equivalents. If the content is less than 60 equivalents, the semiconductor adhesive may not be sufficiently cured. Even if the content exceeds 110 equivalents, it does not particularly contribute to the curability of the adhesive for semiconductors and may cause voids due to volatilization of the excessive thermosetting agent.
  • the more preferable lower limit of the content is 70 equivalents, and the more preferable upper limit is 100 equivalents.
  • the said hardening accelerator is not specifically limited, For example, an imidazole series hardening accelerator, a tertiary amine type hardening accelerator, etc. are mentioned. Among them, imidazole-based curing is easy because it can easily adjust the time to reach a reaction rate of 40% for semiconductor adhesives within the above range, and it is easy to control the reaction system for adjusting the physical properties of the cured product. Accelerators are preferred.
  • the imidazole curing accelerator is not particularly limited, and examples thereof include Fujicure 7000 (manufactured by T & K TOKA, liquid at room temperature (25 ° C.)), 1-cyanoethyl-2-phenylimidazole in which the 1-position of imidazole is protected with a cyanoethyl group, Imidazole-based curing accelerator with basicity protected with isocyanuric acid (trade name “2MA-OK”, manufactured by Shikoku Kasei Kogyo Co., Ltd., solid at room temperature (25 ° C.)), 2MZ, 2MZ-P, 2PZ, 2PZ-PW, 2P4MZ , C11Z-CNS, 2PZ-CNS, 2PZCNS-PW, 2MZ-A, 2MZA-PW, C11Z-A, 2E4MZ-A, 2MAOK-PW, 2PZ-OK, 2MZ-OK, 2PHZ, 2PHZ-PW
  • thermosetting agents content of the said hardening accelerator is not specifically limited
  • the preferable minimum with respect to 100 weight part of thermosetting agents is 1 weight part
  • a preferable upper limit is 50 weight part
  • a more preferable minimum is 2 weight part
  • a more preferable upper limit is 30 weight. Part.
  • the content is less than 2 parts by weight, heating at a high temperature for a long time may be required for thermosetting the adhesive for semiconductor. If the content exceeds 50 parts by weight, the storage stability of the adhesive for semiconductors may be insufficient, or voids may be caused by excessive volatilization of the curing accelerator.
  • the adhesive for semiconductors of the present invention is a film adhesive
  • it preferably further contains a high molecular weight compound.
  • a high molecular weight compound By using the above-mentioned high molecular weight compound, it is possible to provide film-forming properties, flexibility, etc. to the semiconductor adhesive, and toughen the cured product of the semiconductor adhesive to ensure high bonding reliability. it can.
  • the high molecular weight compound is not particularly limited.
  • Known high molecular weight compounds such as benzene resin, epoxy acrylate resin, silicon resin, and urethane resin can be used.
  • a high molecular weight compound having an epoxy group is preferable.
  • the cured product of the semiconductor adhesive exhibits excellent flexibility. That is, the cured product of the adhesive for semiconductors has excellent mechanical strength, heat resistance and moisture resistance derived from the epoxy resin as the thermosetting resin, and excellent good resistance derived from the high molecular weight compound having the epoxy group. Since it also has flexibility, it will be excellent in cold-heat cycle resistance, solder reflow resistance, dimensional stability, etc., and will exhibit high joint reliability and high conduction reliability.
  • the high molecular weight compound having an epoxy group is not particularly limited as long as it is a high molecular weight compound having an epoxy group at the terminal and / or side chain (pendant position).
  • an epoxy group-containing acrylic rubber, an epoxy group-containing butadiene rubber examples thereof include bisphenol type high molecular weight epoxy resin, epoxy group-containing phenoxy resin, epoxy group-containing acrylic resin, epoxy group-containing urethane resin, and epoxy group-containing polyester resin.
  • an epoxy group-containing acrylic resin is preferable because a polymer compound containing a large amount of epoxy groups can be obtained and the cured product has better mechanical strength and heat resistance.
  • These high molecular weight compounds having an epoxy group may be used alone or in combination of two or more.
  • the preferred lower limit of the weight average molecular weight of the high molecular weight compound having the epoxy group is 10,000, and the preferred upper limit is 1,000,000. It is.
  • the weight average molecular weight is less than 10,000, the film forming property of the semiconductor adhesive may be insufficient, or the flexibility of the cured product of the semiconductor adhesive may not be sufficiently improved. If the weight average molecular weight exceeds 1,000,000, it becomes difficult to supply the semiconductor adhesive to a certain thickness in the alignment step 1, or the melt viscosity of the semiconductor adhesive is high in the void removal step 3. In some cases, the fluidity decreases and the voids cannot be sufficiently removed.
  • the high molecular weight compound having the epoxy group When the high molecular weight compound having the epoxy group is used as the high molecular weight compound, particularly when the epoxy group-containing acrylic resin is used, the high molecular weight compound having the epoxy group has a low functional group concentration, that is, a high epoxy equivalent. preferable. Since a high molecular weight compound having a high epoxy equivalent has low reactivity, it is easy to adjust the time required for the reaction rate of the semiconductor adhesive to reach 40% within the above range by using such a high molecular weight compound.
  • the high molecular weight compound having an epoxy group preferably has an epoxy equivalent of 200 or more, and more preferably 250 or more.
  • content of the said high molecular weight compound in the adhesive agent for semiconductors of this invention is not specifically limited, A preferable minimum is 3 weight% and a preferable upper limit is 30 weight%. If the content is less than 3% by weight, sufficient reliability against thermal strain may not be obtained. When content exceeds 30 weight%, the heat resistance of the adhesive agent for semiconductors may fall.
  • the semiconductor adhesive of the present invention preferably further contains an inorganic filler.
  • the inorganic filler is not particularly limited, and examples thereof include silica, alumina, aluminum nitride, boron nitride, silicon nitride, silicon carbide, magnesium oxide, and zinc oxide.
  • spherical silica is preferable because of excellent fluidity, and spherical silica surface-treated with a methylsilane coupling agent, a phenylsilane coupling agent, or the like is more preferable.
  • the average particle size of the inorganic filler is not particularly limited, but is preferably about 0.01 to 1 ⁇ m from the viewpoints of transparency, fluidity, bonding reliability, etc. of the adhesive for semiconductors.
  • the adhesive for semiconductors of the present invention is further provided with an adhesive imparting agent such as a diluent, a thixotropy imparting agent, a solvent, an inorganic ion exchanger, a bleed inhibitor, an imidazole silane coupling agent, and an adhesion imparting agent as necessary.
  • an adhesive imparting agent such as a diluent, a thixotropy imparting agent, a solvent, an inorganic ion exchanger, a bleed inhibitor, an imidazole silane coupling agent, and an adhesion imparting agent as necessary.
  • Other additives such as stress relieving agents such as rubber particles may be contained.
  • the method for producing the semiconductor adhesive of the present invention is not particularly limited, and when it is a paste-like adhesive, for example, a thermosetting resin and a thermosetting agent, if necessary, a curing accelerator, a high molecular weight compound, A method in which a predetermined amount of an inorganic filler and other additives are mixed and mixed may be mentioned.
  • the mixing method is not particularly limited, and examples thereof include a method using a homodisper, a universal mixer, a Banbury mixer, a kneader, a bead mill, a homogenizer, and the like.
  • the thickness of the semiconductor adhesive of the present invention is not particularly limited, but is preferably 10 to 50 ⁇ m, and more preferably 10 to 40 ⁇ m.
  • a semiconductor chip having a protruding electrode in the peripheral portion not only a semiconductor chip having a protruding electrode in the peripheral portion, but also a void can be sufficiently suppressed even if a semiconductor chip having a protruding electrode on the inner side of the peripheral portion and the peripheral portion is used.
  • the adhesive for semiconductors which can be provided can be provided.
  • Examples 1 to 4 and Comparative Examples 1 to 7 (1) Manufacture of adhesives The materials shown below were added to a solvent (methyl ethyl ketone) in accordance with the composition described in Table 1, and the mixture was stirred and mixed using a homodisper to prepare an adhesive solution. The obtained adhesive solution was applied on a release PET film using an applicator so that the thickness after drying was 40 ⁇ m, and the adhesive solution was dried to produce a film-like adhesive. Until use, another release PET film (protective film) was adhered to the surface of the adhesive layer formed on the release PET film for protection.
  • a solvent methyl ethyl ketone
  • Step 1 for aligning a semiconductor chip on a substrate via an adhesive, and Step 2 for temporarily bonding an adhesive to the substrate and the semiconductor chip A semiconductor chip in which a protruding electrode having a tip portion made of solder was formed in a peripheral portion, a semiconductor chip surface inside the peripheral portion, and a substrate having a Cu / Solder electrode were prepared.
  • the protective film on one side of the adhesive was peeled off and stuck on the semiconductor chip using a vacuum laminator (ATM-812M, manufactured by Takatori) at a stage temperature of 60 ° C. and a vacuum of 100 Pa.
  • step 1 the semiconductor chip is aligned on the substrate via an adhesive (step 1).
  • the temperature was raised to 290 ° C. by contact at 0 ° C., and a load was applied at 0.96 MPa for 2.4 seconds to melt-bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and to temporarily bond the adhesive (step 2) .
  • Step 3 for removing voids
  • the obtained temporary adhesive body is put into a pressure oven (VFS, manufactured by APT), and the adhesive is heated under a pressure atmosphere under the following pressure and heating conditions to remove voids (step 3).
  • the adhesive was completely cured to obtain a semiconductor device.
  • ⁇ Pressurization and heating conditions> STEP 1: Constant temperature increase from 30 ° C to 100 ° C in 20 minutes, 0.8 MPa STEP 2: Hold at 100 ° C. for 60 minutes, 0.8 Pa STEP3: Constant temperature increase from 100 ° C to 180 ° C, 0.8 MPa STEP 4: Hold at 180 ° C. for 10 minutes, 0.8 MPa STEP5: Temperature drop from 180 ° C to 30 ° C in 20 minutes, 0.8 MPa
  • Presence / absence of voids Using an ultrasonic exploration imaging apparatus (C-SAM D9500, manufactured by Nihon Burns), the semiconductor device was observed before and after step 3 for removing voids, and the presence / absence of voids was evaluated.
  • Whether the product is a non-defective product or a defective product was determined for a semiconductor device in which the number of n was 5, and the area of the void generation portion with respect to the bonding area of the semiconductor chip was the smallest. Further, the non-defective product rate (x / 5) was determined with the number of n being 5.
  • a semiconductor adhesive capable of sufficiently suppressing voids even when a semiconductor chip having a protruding electrode is used not only in the peripheral portion but also in the peripheral portion and the surface inside the peripheral portion. can do.

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Abstract

The objective of the present invention is to provide a semiconductor adhesive capable of minimizing voids. The present invention is a semiconductor adhesive used in a method for manufacturing a semiconductor device having: a step (1) for aligning on a substrate a semiconductor chip in which a protruding electrode having a tip section comprising solder is formed in a peripheral portion and farther inward of the peripheral portion in the plane of the semiconductor chip, with the semiconductor adhesive being interposed therebetween; a step (2) for heating the semiconductor chip to a temperature at or above the melting point of the solder to fusion-bond the protruding electrode of the semiconductor chip and an electrode section of the substrate, and to temporarily bond the semiconductor adhesive; and a step (3) for heating the semiconductor adhesive in a pressurized environment to eliminate voids, wherein the semiconductor adhesive has a minimum melt viscosity of 1000 Pa・s or less at 80-200°C, and the time required to reach a reaction rate of 40% at 260°C is 8 seconds or more as determined using the Ozawa method.

Description

半導体用接着剤Adhesive for semiconductor
本発明は、ボイドを抑制することのできる半導体用接着剤に関する。 The present invention relates to a semiconductor adhesive capable of suppressing voids.
半導体装置の小型化及び高密度化に伴い、半導体チップを基板に実装する方法として、表面に多数の突起電極が形成された半導体チップを用いたフリップチップ実装が注目され、急速に広まってきている。
フリップチップ実装においては、接合部分の接続信頼性を確保するための方法として、半導体チップの突起電極と基板の電極部とを接合した後に、半導体チップと基板との隙間に液状封止接着剤（アンダーフィル）を注入し、硬化させることが一般的な方法として採られている。しかしながら、アンダーフィルを用いたフリップチップ実装は、アンダーフィル充填に時間がかかるといった問題や、電極間の距離及び半導体チップと基板との距離を狭めるのに限界があるといった問題を抱えている。 As semiconductor devices are miniaturized and densified, flip chip mounting using a semiconductor chip having a large number of protruding electrodes formed on the surface has attracted attention and is rapidly spreading as a method for mounting a semiconductor chip on a substrate. .
In flip chip mounting, as a method for ensuring the connection reliability of the joint portion, after bonding the protruding electrode of the semiconductor chip and the electrode portion of the substrate, a liquid sealing adhesive (in the gap between the semiconductor chip and the substrate) It is a common method to inject and cure the underfill. However, flip-chip mounting using underfill has a problem that it takes time to fill the underfill, and there is a problem that there is a limit in reducing the distance between the electrodes and the distance between the semiconductor chip and the substrate.
そこで、近年、基板上にペースト状接着剤を塗布した後、半導体チップを搭載する方法、半導体ウエハ又は半導体チップ上にフィルム状又はペースト状接着剤を供給した後、接着剤付き半導体チップを基板上に搭載する方法等のいわゆる先塗布型のフリップチップ実装が提案されている。特に接着剤付き半導体チップを基板上に搭載する場合には、半導体ウエハ上に接着剤を一括供給し、ダイシングによって接着剤付き半導体チップを一括で多量に生産できることから、大幅なプロセス短縮が期待される。 Therefore, in recent years, after applying a paste adhesive on a substrate, a method of mounting a semiconductor chip, after supplying a film or paste adhesive on a semiconductor wafer or semiconductor chip, the semiconductor chip with adhesive on the substrate A so-called pre-coating type flip chip mounting method such as a method for mounting on a substrate has been proposed. In particular, when mounting semiconductor chips with adhesives on a substrate, the adhesive can be supplied all over the semiconductor wafer, and a large number of semiconductor chips with adhesives can be produced in large quantities by dicing. The
しかしながら、先塗布型のフリップチップ実装では、半導体チップの突起電極と基板の電極部とを接触させる際に、半導体チップ又は基板と接着剤との間に空気を巻き込んでボイドを生じたり、半導体チップを基板上に搭載する際の熱圧着工程において、接着剤からの揮発成分によってボイドが生じたりすることがある。このようなボイドは、電極間の短絡を招いたり、接着剤中にクラックを発生させる要因となったりする。 However, in the pre-applied flip chip mounting, when the protruding electrode of the semiconductor chip and the electrode portion of the substrate are brought into contact with each other, air is involved between the semiconductor chip or the substrate and the adhesive to generate a void, or the semiconductor chip In the thermocompression bonding process when mounting the substrate on the substrate, a void may be generated due to a volatile component from the adhesive. Such voids may cause a short circuit between the electrodes or cause cracks in the adhesive.
そこで、ボイドを抑制するために、接着剤の熱硬化反応を加圧雰囲気下で行うことによりボイドを収縮させる方法、半導体チップと基板とを接着剤を用いて仮接合した後、仮接合体を加圧雰囲気下で加熱することによりボイドを小さくする方法等が提案されている（例えば、特許文献１～２）。しかしながら、これらの方法であっても、特に接着剤付き半導体チップを基板上に搭載する場合には基板の凹凸により空気を巻き込みやすいことから、従来の接着剤ではボイドを充分に抑制するには至っていない。 Therefore, in order to suppress voids, a method of shrinking the voids by performing a thermosetting reaction of the adhesive in a pressurized atmosphere, after temporarily bonding the semiconductor chip and the substrate using the adhesive, There has been proposed a method of reducing voids by heating in a pressurized atmosphere (for example, Patent Documents 1 and 2). However, even with these methods, especially when mounting a semiconductor chip with an adhesive on a substrate, air can easily be engulfed by the unevenness of the substrate, so that conventional adhesives can sufficiently suppress voids. Not in.
特開２００４－３１１７０９号公報JP 2004-311709 A 特開２００９－００４４６２号公報JP 2009-004462 A
ところで、市場で使用されている半導体チップのなかにはペリフェラル部のみならずペリフェラル部より内側の半導体チップ面内にも突起電極を持っている半導体チップがある。しかし、このようなペリフェラル部とペリフェラル部より内側の半導体チップ面内との両方に突起電極を有する半導体チップを用いた場合、ペリフェラル部より内側の半導体チップ面内の突起電極が樹脂流動及び加圧効果に悪影響を及ぼすため、仮接合体を加圧雰囲気下で加熱したとしても従来の接着剤ではボイドを充分に抑制するに至っていない。
そこで、本発明は、ペリフェラル部だけでなく、ペリフェラル部より内側の半導体チップ面内に発生するボイドを抑制できる半導体用接着剤を提供することを目的とする。 By the way, among the semiconductor chips used in the market, there are semiconductor chips having protruding electrodes not only in the peripheral part but also in the semiconductor chip surface inside the peripheral part. However, when a semiconductor chip having a protruding electrode on both the peripheral portion and the semiconductor chip surface inside the peripheral portion is used, the protruding electrode in the semiconductor chip surface inside the peripheral portion is caused to flow and pressurize the resin. In order to adversely affect the effect, even if the temporary joined body is heated in a pressurized atmosphere, the conventional adhesive has not sufficiently suppressed the void.
Therefore, an object of the present invention is to provide an adhesive for a semiconductor that can suppress voids generated not only in the peripheral portion but also in the semiconductor chip surface inside the peripheral portion.
本発明は、半田からなる先端部を有する突起電極がペリフェラル部及び該ペリフェラル部より内側の半導体チップ面内に形成された半導体チップを、半導体用接着剤を介して基板上に位置合わせする工程１と、前記半導体チップを半田溶融点以上の温度に加熱して、前記半導体チップの突起電極と前記基板の電極部とを溶融接合させるとともに、前記半導体用接着剤を仮接着させる工程２と、前記半導体用接着剤を加圧雰囲気下で加熱してボイドを除去する工程３とを有する半導体装置の製造方法に用いられる半導体用接着剤であって、前記半導体用接着剤は、８０～２００℃における最低溶融粘度が１０００Ｐａ・ｓ以下であり、小澤法によって求めた２６０℃で反応率４０％に達する所要時間が８秒以上である半導体用接着剤である。
以下、本発明を詳述する。 The present invention provides a step 1 for aligning a semiconductor chip having a protruding electrode having a tip portion made of solder formed on a peripheral portion and a semiconductor chip surface inside the peripheral portion on a substrate via a semiconductor adhesive. And heating the semiconductor chip to a temperature equal to or higher than the solder melting point to melt-bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and temporarily bond the adhesive for the semiconductor, and A semiconductor adhesive used in a method for manufacturing a semiconductor device, comprising: removing a void by heating a semiconductor adhesive in a pressurized atmosphere, wherein the semiconductor adhesive is at 80 to 200 ° C. A semiconductor adhesive having a minimum melt viscosity of 1000 Pa · s or less and a required time to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method is 8 seconds or more.
The present invention is described in detail below.
本発明者は、半導体チップを半田溶融点以上の温度に加熱して、半導体チップの突起電極と基板の電極部とを接合させ、その後、半導体用接着剤を加圧雰囲気下で加熱してボイドを除去する方法に用いられる半導体用接着剤を検討した。その結果、本発明者は、加圧雰囲気下で加熱したとしても、突起電極を接合する際に半導体用接着剤の硬化が進行しすぎている場合には、ボイドを充分に除去することはできず、半導体用接着剤として、突起電極を接合させる際の熱履歴を経ても硬化が極力抑えられる接着剤、即ち、硬化速度（反応速度）の比較的遅い、かつ、最低溶融粘度の低い接着剤を用いる必要があることを見出した。
なお、突起電極を接合する際の条件を調整することで半導体用接着剤の硬化を抑えることも考えられるが、突起電極を接合するためには半田溶融点以上の温度（２４０～３００℃程度）で保持する必要があるため、条件の調整のみで半導体用接着剤の硬化を抑えるのには限界がある。 The inventor heats the semiconductor chip to a temperature equal to or higher than the solder melting point to bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and then heats the adhesive for the semiconductor in a pressurized atmosphere to form a void. The adhesive for semiconductors used in the method for removing the surface was examined. As a result, even when heated by a pressurized atmosphere, the present inventor can sufficiently remove voids when the adhesive for semiconductors has progressed too much when bonding protruding electrodes. In addition, as an adhesive for semiconductors, an adhesive whose curing is suppressed as much as possible even after a thermal history at the time of joining protruding electrodes, that is, an adhesive having a relatively slow curing rate (reaction rate) and a low minimum melt viscosity. It was found that it was necessary to use.
Although it may be possible to suppress the curing of the adhesive for the semiconductor by adjusting the conditions for bonding the protruding electrodes, the temperature above the solder melting point (about 240 to 300 ° C.) is required for bonding the protruding electrodes. Therefore, there is a limit in suppressing the curing of the semiconductor adhesive only by adjusting the conditions.
ここで、熱分析、反応速度解析等の分野では、試料の示差走査熱量測定（ＤＳＣ測定、Ｄｉｆｆｅｒｅｎｔｉａｌ　ｓｃａｎｎｉｎｇ　ｃａｌｏｒｉｍｅｔｒｙ）により得られたデータから一定温度における所定の反応率に到達する時間を求める「小澤（沢）法」とよばれる解析方法が知られている。
本発明者は、半導体装置の製造方法に用いられる半導体用接着剤に対して、小澤法を適用することで検討を行った。その結果、本発明者は、最低溶融粘度と小澤法によって求めた２６０℃で反応率４０％に達する所要時間とが所定範囲を満たす半導体用接着剤は、ペリフェラル部に突起電極を有する半導体チップを用いた場合のみならず、ペリフェラル部とペリフェラル部より内側の面内にも突起電極を有する半導体チップを用いた場合でもボイドを充分に除去するに至った。 Here, in the fields of thermal analysis, reaction rate analysis, and the like, the time required to reach a predetermined reaction rate at a constant temperature is determined from data obtained by differential scanning calorimetry (DSC measurement, Differential scanning calorimetry) of a sample. An analysis method called “sawa) method” is known.
The present inventor studied by applying the Ozawa method to a semiconductor adhesive used in a method for manufacturing a semiconductor device. As a result, the present inventor found that a semiconductor chip having a protruding electrode in a peripheral portion is used for a semiconductor adhesive that satisfies a predetermined range of a minimum melt viscosity and a required time to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method. Voids were sufficiently removed not only when used but also when using a peripheral chip and a semiconductor chip having a protruding electrode in the surface inside the peripheral section.
本発明の半導体用接着剤は、半田からなる先端部を有する突起電極がペリフェラル部及び該ペリフェラル部より内側の半導体チップ面内に形成された半導体チップを、半導体用接着剤を介して基板上に位置合わせする工程１と、前記半導体チップを半田溶融点以上の温度に加熱して、前記半導体チップの突起電極と前記基板の電極部とを溶融接合させるとともに、前記半導体用接着剤を仮接着させる工程２と、前記半導体用接着剤を加圧雰囲気下で加熱してボイドを除去する工程３とを有する半導体装置の製造方法に用いられるものである。 The semiconductor adhesive of the present invention is a semiconductor chip in which a protruding electrode having a tip made of solder is formed in a peripheral part and a semiconductor chip surface inside the peripheral part on the substrate via the semiconductor adhesive. Step 1 for aligning and heating the semiconductor chip to a temperature equal to or higher than the solder melting point to melt-bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and temporarily bond the adhesive for semiconductor The method is used in a method for manufacturing a semiconductor device, which includes Step 2 and Step 3 of removing the voids by heating the adhesive for semiconductor in a pressurized atmosphere.
本発明の半導体用接着剤が用いられる半導体装置の製造方法では、まず、半田からなる先端部を有する突起電極がペリフェラル部及び該ペリフェラル部より内側の半導体チップ面内に形成された半導体チップを、半導体用接着剤を介して基板上に位置合わせする工程１を行う。
上記位置合わせする工程１では、一般的に、フリップチップボンダ等の実装用装置を用いて、半導体チップの突起電極、基板の電極部、並びに、半導体チップ及び基板上に設けられたアライメントマークの位置をカメラに認識させることで、Ｘ、Ｙ方向及び回転方向（θ方向）に自動的に位置あわせを行う。 In the method for manufacturing a semiconductor device using the adhesive for semiconductor of the present invention, first, a semiconductor chip in which a protruding electrode having a tip portion made of solder is formed in a semiconductor chip surface inside the peripheral portion and the peripheral portion, Step 1 of aligning on the substrate through a semiconductor adhesive is performed.
In the alignment step 1, generally, using a mounting device such as a flip chip bonder, the position of the protruding electrode of the semiconductor chip, the electrode portion of the substrate, and the alignment mark provided on the semiconductor chip and the substrate Is automatically recognized in the X and Y directions and the rotation direction (θ direction).
上記半導体チップとして、例えば、シリコン、ガリウム砒素等の半導体からなり、半田からなる先端部を有する突起電極がペリフェラル部に加えて、ペリフェラル部より内側の面内にも存在する半導体チップが挙げられる。なお、半田からなる先端部を有する突起電極は、先端部が半田からなっていれば、突起電極の一部が半田からなっていても、突起電極全体が半田からなってもよい。 Examples of the semiconductor chip include a semiconductor chip made of a semiconductor such as silicon and gallium arsenide, and a protruding electrode having a tip portion made of solder, in addition to the peripheral portion, also exists on the inner surface of the peripheral portion. It should be noted that the protruding electrode having the tip portion made of solder may be formed of a part of the protruding electrode, or the entire protruding electrode may be made of solder, as long as the tip portion is made of solder.
上記半導体用接着剤を供給する方法は特に限定されず、例えば、フィルム状の接着剤を基板上又は半導体チップ上に貼付する方法、ペースト状の接着剤をシリンジに充填し、シリンジ先端に精密ノズルを取り付けて、ディスペンサ装置を用いて基板上に吐出する方法等が挙げられる。
また、予めウエハにフィルム状の接着剤を常圧ラミネート、真空ラミネート等により貼付したり、ペースト状の接着剤をスピンコート法等により塗布又は印刷して塗膜を形成したりした後、ブレードダイシング、レーザーダイシング等により半導体チップに個片化する方法を用いることもできる。常圧ラミネートでは空気が巻き込まれる場合があるが、ボイドを除去する工程３と同様の加圧オーブン（例えば、ＰＣＯ－０８３ＴＡ（ＮＴＴアドバンステクノロジ社製））等を用いて接着剤を加圧雰囲気下で加熱して、ボイドを除去してもよい。 The method of supplying the semiconductor adhesive is not particularly limited. For example, a method of sticking a film-like adhesive on a substrate or a semiconductor chip, a paste-like adhesive filled in a syringe, and a precision nozzle at the tip of the syringe And a method of discharging onto a substrate using a dispenser device.
In addition, after applying a film adhesive to the wafer by atmospheric pressure lamination, vacuum lamination, etc., or applying or printing a paste adhesive by spin coating or the like to form a coating film, blade dicing Alternatively, a method of dividing into semiconductor chips by laser dicing or the like can be used. In normal pressure lamination, air may be entrained, but the adhesive is removed in a pressurized atmosphere using a pressure oven (for example, PCO-083TA (manufactured by NTT Advanced Technology)) similar to step 3 for removing voids. The voids may be removed by heating with
本発明の半導体用接着剤が用いられる半導体装置の製造方法では、次いで、上記半導体チップを半田溶融点以上の温度に加熱して、上記半導体チップの突起電極と上記基板の電極部とを溶融接合させるとともに、上記半導体用接着剤を仮接着させる工程２を行う。
上記半導体用接着剤を仮接着させる工程２もまた、一般的に、フリップチップボンダ等の実装用装置を用いて行われる。 In the method for manufacturing a semiconductor device using the semiconductor adhesive of the present invention, the semiconductor chip is then heated to a temperature equal to or higher than the solder melting point, and the protruding electrode of the semiconductor chip and the electrode portion of the substrate are melt bonded. And performing step 2 of temporarily adhering the semiconductor adhesive.
The step 2 for temporarily bonding the semiconductor adhesive is also generally performed using a mounting apparatus such as a flip chip bonder.
半田溶融点は、通常、２１５～２３５℃程度である。上記半田溶融点以上の温度の好ましい下限は２４０℃、好ましい上限は３００℃である。温度が２４０℃未満であると、突起電極が充分に溶融せず、電極接合が形成されないことがある。温度が３００℃を超えると、半導体用接着剤から揮発成分が発生してボイドを増加させることがある。また、半導体用接着剤の硬化が進行してしまい、ボイドを除去する工程３において半導体用接着剤の流動性が低下し、ボイドを充分に除去できないことがある。 The solder melting point is usually about 215 to 235 ° C. The preferable lower limit of the temperature above the solder melting point is 240 ° C., and the preferable upper limit is 300 ° C. If the temperature is lower than 240 ° C., the protruding electrode may not be sufficiently melted and electrode bonding may not be formed. When temperature exceeds 300 degreeC, a volatile component may generate | occur | produce from the adhesive agent for semiconductors, and a void may be increased. In addition, the curing of the semiconductor adhesive progresses, and the fluidity of the semiconductor adhesive decreases in the step 3 of removing the void, and the void may not be sufficiently removed.
上記半導体チップを半田溶融点以上の温度に加熱する時間（保持時間）は、好ましい下限が０．１秒、好ましい上限が３秒である。保持時間が０．１秒未満であると、突起電極が充分に溶融せず、電極接合が形成されないことがある。保持時間が３秒を超えると、半導体用接着剤から揮発成分が発生してボイドを増加させることがある。また、半導体用接着剤の硬化が進行してしまい、ボイドを除去する工程３において半導体用接着剤の流動性が低下し、ボイドを充分に除去できないことがある。 As for the time (holding time) for heating the semiconductor chip to a temperature equal to or higher than the solder melting point, a preferable lower limit is 0.1 seconds, and a preferable upper limit is 3 seconds. If the holding time is less than 0.1 seconds, the protruding electrode may not be sufficiently melted and electrode bonding may not be formed. When holding time exceeds 3 second, a volatile component may generate | occur | produce from the adhesive agent for semiconductors and a void may be increased. In addition, the curing of the semiconductor adhesive progresses, and the fluidity of the semiconductor adhesive decreases in the step 3 of removing the void, and the void may not be sufficiently removed.
上記半導体用接着剤を仮接着させる工程２では、上記半導体チップに対して圧力をかけることが好ましい。圧力は、電極接合が形成される圧力であれば特に限定されないが、０．３～３ＭＰａが好ましい。 In step 2 of temporarily bonding the semiconductor adhesive, it is preferable to apply pressure to the semiconductor chip. The pressure is not particularly limited as long as the electrode bond is formed, but is preferably 0.3 to 3 MPa.
本発明の半導体用接着剤が用いられる半導体装置の製造方法では、次いで、上記半導体用接着剤を加圧雰囲気下で加熱してボイドを除去する工程３を行う。
加圧雰囲気下とは、常圧（大気圧）より高い圧力雰囲気下を意味する。上記ボイドを除去する工程３では、ボイドを単に成長させないだけではなく、積極的に除去できるものと考えられることから、本発明の半導体用接着剤が用いられる半導体装置の製造方法では、仮に半導体用接着剤に空気が巻き込まれた場合であってもボイドを除去することができる。 In the method for manufacturing a semiconductor device using the semiconductor adhesive of the present invention, the step 3 of removing the voids by heating the semiconductor adhesive in a pressurized atmosphere is then performed.
Under a pressurized atmosphere means a pressure atmosphere higher than normal pressure (atmospheric pressure). In the step 3 of removing the voids, it is considered that the voids are not simply grown but can be removed positively. Therefore, in the method of manufacturing a semiconductor device using the semiconductor adhesive of the present invention, the semiconductor Even when air is entrained in the adhesive, the voids can be removed.
上記半導体用接着剤を加圧雰囲気下で加熱する方法として、例えば、加圧オーブン（例えば、ＰＣＯ－０８３ＴＡ（ＮＴＴアドバンステクノロジ社製））を用いる方法等が挙げられる。
上記加圧オーブンの圧力の好ましい下限は０．１ＭＰａ、好ましい上限は１０ＭＰａである。圧力が０．１ＭＰａ未満であると、ボイドを充分に除去できないことがある。圧力が１０ＭＰａを超えると、半導体用接着剤自体の変形が生じ、半導体装置の信頼性に悪影響を及ぼすことがある。圧力のより好ましい下限は０．３ＭＰａ、より好ましい上限は１ＭＰａである。 Examples of the method for heating the semiconductor adhesive in a pressurized atmosphere include a method using a pressure oven (for example, PCO-083TA (manufactured by NTT Advanced Technology)).
The preferable lower limit of the pressure of the pressure oven is 0.1 MPa, and the preferable upper limit is 10 MPa. If the pressure is less than 0.1 MPa, the void may not be sufficiently removed. When the pressure exceeds 10 MPa, the semiconductor adhesive itself is deformed, which may adversely affect the reliability of the semiconductor device. The more preferable lower limit of the pressure is 0.3 MPa, and the more preferable upper limit is 1 MPa.
上記半導体用接着剤を加圧雰囲気下で加熱する際の加熱温度の好ましい下限は６０℃、好ましい上限は１５０℃である。ただし、上記半導体用接着剤を加圧雰囲気下で加熱する際には、一定温度及び一定圧力で保持してもよいし、昇温及び／又は昇圧しながら段階的に温度及び／又は圧力を変化させてもよい。
また、ボイドをより確実に除去するためには、上記半導体用接着剤を加圧雰囲気下で加熱する際の加熱時間は、１０分以上であることが好ましい。 The minimum with a preferable heating temperature at the time of heating the said adhesive agent for semiconductors in a pressurized atmosphere is 60 degreeC, and a preferable upper limit is 150 degreeC. However, when heating the semiconductor adhesive in a pressurized atmosphere, it may be held at a constant temperature and a constant pressure, or the temperature and / or pressure may be changed stepwise while raising and / or raising the pressure. You may let them.
Moreover, in order to remove a void more reliably, it is preferable that the heating time at the time of heating the said adhesive agent for semiconductors in a pressurized atmosphere is 10 minutes or more.
本発明の半導体用接着剤が用いられる半導体装置の製造方法では、ボイドを除去する工程３を行った後、半導体用接着剤を完全に硬化させる工程４を行ってもよい。
上記半導体用接着剤を完全に硬化させる方法として、例えば、ボイドを除去する工程３を行った後、加圧雰囲気下でそのまま温度を上げて半導体用接着剤を完全に硬化させる方法、常圧下で半導体用接着剤を加熱して完全に硬化させる方法等が挙げられる。上記半導体用接着剤を完全に硬化させる際の加熱温度は特に限定されないが、１５０～２００℃程度が好ましい。 In the method for manufacturing a semiconductor device using the adhesive for semiconductor of the present invention, after performing step 3 for removing voids, step 4 for completely curing the adhesive for semiconductor may be performed.
As a method for completely curing the adhesive for semiconductors, for example, after performing step 3 for removing voids, a method for completely curing the adhesive for semiconductors by raising the temperature in a pressurized atmosphere as it is under normal pressure. The method etc. which heat the semiconductor adhesive agent and harden it completely are mentioned. The heating temperature for completely curing the adhesive for semiconductor is not particularly limited, but is preferably about 150 to 200 ° C.
本発明の半導体用接着剤は、８０～２００℃における最低溶融粘度が１０００Ｐａ・ｓ以下、小澤法によって求めた２６０℃で反応率４０％に達する所要時間が８秒以上である。
最低溶融粘度と小澤法によって求めた２６０℃で反応率４０％に達する所要時間とが、上記範囲を満たす半導体用接着剤は、硬化速度（反応速度）が比較的遅く反応速度の温度依存性が小さいため、半導体用接着剤を仮接着させる工程２において突起電極を接合させる際の熱履歴を経ても硬化が極力抑えられ、かつ、硬化のバラつきが少ない半導体用接着剤であるといえる。このような半導体用接着剤は、ペリフェラル部に突起電極を有する半導体チップを用いた場合のみならず、ペリフェラル部とペリフェラル部より内側の面内にも突起電極を有する半導体チップを用いた場合でもボイドを充分に除去することができる。 The adhesive for semiconductors of the present invention has a minimum melt viscosity at 80 to 200 ° C. of 1000 Pa · s or less, and a required time to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method is 8 seconds or more.
The adhesive for semiconductors satisfying the above range with the minimum melt viscosity and the time required to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method has a relatively slow curing rate (reaction rate), and the temperature dependence of the reaction rate is Since it is small, it can be said that it is the adhesive for semiconductors which can suppress hardening as much as possible even if it passes through the thermal history at the time of joining a protruding electrode in the process 2 which temporarily bonds the adhesive for semiconductors, and there are few variations in hardening. Such a semiconductor adhesive is not only used when a semiconductor chip having a protruding electrode in the peripheral portion, but also when using a semiconductor chip having a protruding electrode in the surface inside the peripheral portion and the peripheral portion. Can be sufficiently removed.
なお、最低溶融粘度は、レオメーター測定によって求められるものであり、レオメーター測定は、回転式レオメーター装置（例えば、ＶＡＲ－１００（レオロジカ社製））を用いて行うことができ、溶融粘度とは、昇温速度５℃／分、周波数１Ｈｚ、歪み１％で測定した値を意味する。
また、小澤法は、反応速度解析ソフト（例えば、エスアイアイ・ナノテクノロジー社製）を用いて行うことができ、下記に示す解析方法を意味する。
まず、試料について昇温速度の異なる示差走査熱量測定を３回以上行い、温度Ｔの逆数と、昇温速度Ｂの対数（ｌｏｇＢ）とをプロットする。得られた直線の傾きから、下記式（１）にもとづいて、活性化エネルギーΔＥを算出する。次いで、活性化エネルギーΔＥから、下記式（２）の定温劣化式にもとづいて、２６０℃４秒及び２６０℃６秒保持した場合の反応率を算出する。算出した４秒保持した場合の反応率と６秒保持した場合の反応率とに基づき、２６０℃で反応率４０％に達する所要時間を算出する。示差走査熱量測定は、ＤＳＣ装置（例えば、ＤＳＣ６２２０（エスアイアイ・ナノテクノロジー社製））を用いて行うことができる。（小澤丈夫，熱測定１，２（１９７４）、及び、Ｔ．Ｏｚａｗａ，Ｂｕｌｌ．Ｃｈｅｍ．Ｓｏｃ．Ｊａｐａｎ　３８，１８８１（１９６５）参照。） The minimum melt viscosity is determined by rheometer measurement, and the rheometer measurement can be performed using a rotary rheometer device (for example, VAR-100 (manufactured by Rheological Corporation)). Means a value measured at a heating rate of 5 ° C./min, a frequency of 1 Hz, and a strain of 1%.
The Ozawa method can be performed using reaction rate analysis software (for example, manufactured by SII Nanotechnology), and means the analysis method shown below.
First, differential scanning calorimetry with different heating rates is performed three or more times for the sample, and the reciprocal of temperature T and the logarithm (log B) of heating rate B are plotted. From the slope of the obtained straight line, the activation energy ΔE is calculated based on the following formula (1). Next, from the activation energy ΔE, based on the constant temperature deterioration formula of the following formula (2), the reaction rate when held at 260 ° C. for 4 seconds and 260 ° C. for 6 seconds is calculated. Based on the calculated reaction rate when held for 4 seconds and reaction rate when held for 6 seconds, the required time to reach a reaction rate of 40% at 260 ° C. is calculated. Differential scanning calorimetry can be performed using a DSC apparatus (for example, DSC 6220 (manufactured by SII Nano Technology)). (See Takeo Ozawa, Thermal Measurements 1, 2 (1974) and T. Ozawa, Bull. Chem. Soc. Japan 38, 1881 (1965).)
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
式（２）中、τは定温劣化時間を表す。 In formula (2), τ represents a constant temperature deterioration time.
本発明の半導体用接着剤は、８０～２００℃における最低溶融粘度が１０００Ｐａ・ｓ以下である。最低溶融粘度が１０００Ｐａ・ｓを超えると、ボイドを除去する工程３において半導体用接着剤の流動性が低下し、硬化速度が上記範囲内であってもボイドを充分に除去することができない。より好ましい上限は４００Ｐａ・ｓ以下である。
本発明の半導体用接着剤の８０～２００℃における最低溶融粘度の下限は特に限定されないが、好ましい下限は１０Ｐａ・ｓである。最低溶融粘度が１０Ｐａ・ｓ未満であると、フィレットのはみ出しが多すぎて、他デバイスを汚染してしまうことがある。 The adhesive for semiconductors of the present invention has a minimum melt viscosity at 80 to 200 ° C. of 1000 Pa · s or less. When the minimum melt viscosity exceeds 1000 Pa · s, the fluidity of the semiconductor adhesive is lowered in the step 3 of removing the voids, and even if the curing rate is within the above range, the voids cannot be sufficiently removed. A more preferable upper limit is 400 Pa · s or less.
The lower limit of the minimum melt viscosity at 80 to 200 ° C. of the adhesive for semiconductor of the present invention is not particularly limited, but the preferable lower limit is 10 Pa · s. If the minimum melt viscosity is less than 10 Pa · s, the fillet protrudes too much and may contaminate other devices.
本発明の半導体用接着剤は、小澤法によって求めた２６０℃で反応率４０％に達する所要時間が８秒以上である。反応率４０％に達する時間が８秒未満となると、最低溶融粘度が上記範囲内であっても、半導体用接着剤の硬化を抑制することができず、ボイドを除去する工程３においてボイドを充分に除去することができない。また、反応率４０％に達する時間が８秒未満となると、ペリフェラル部より内側の面内の突起電極が樹脂流動に悪影響を及ぼし、ボイドを除去する工程３において特徴的なボイドが残ってしまう可能性がある。 The time required for the semiconductor adhesive of the present invention to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method is 8 seconds or more. When the time to reach a reaction rate of 40% is less than 8 seconds, even if the minimum melt viscosity is within the above range, the curing of the semiconductor adhesive cannot be suppressed, and the void is sufficiently removed in the step 3 of removing the void. Can not be removed. Also, if the time to reach a reaction rate of 40% is less than 8 seconds, the protruding electrode in the surface inside the peripheral part adversely affects the resin flow, and a characteristic void may remain in the step 3 of removing the void. There is sex.
本発明の半導体用接着剤は、フィルム状であってもペースト状であってもよく、少なくとも熱硬化性樹脂と熱硬化剤とを含有することが好ましい。本発明の半導体用接着剤は、更に、硬化促進剤を含有することが好ましい。
反応速度は反応系の濃度にも依存することから、例えば、各成分の含有量、特に硬化促進剤の添加量を調整することによって、半導体用接着剤の反応率４０％に達する時間を上記範囲に調整することができる。具体的には、硬化促進剤の添加量が多いほど反応速度が上がり、少ないほど反応速度が落ちる傾向がある。ただし、適切な硬化促進剤の添加量は個々の反応系によって異なることから、半導体用接着剤の反応率４０％に達する時間を上記範囲に調整するために、各成分の含有量を適宜調整する必要がある。
また、半導体用接着剤の最低溶融粘度は、例えば、熱硬化性樹脂、熱硬化剤、無機フィラー等の含有量を調整することによって、上記範囲に調整することができる。本発明の半導体用接着剤は、最低溶融粘度を上記範囲に調整しやすいことから、エポキシ樹脂、側鎖にエポキシ基を有するアクリル樹脂、熱硬化剤及び無機フィラーを含有することが好ましい。 The adhesive for semiconductors of the present invention may be in the form of a film or a paste, and preferably contains at least a thermosetting resin and a thermosetting agent. The semiconductor adhesive of the present invention preferably further contains a curing accelerator.
Since the reaction rate also depends on the concentration of the reaction system, for example, by adjusting the content of each component, particularly the addition amount of the curing accelerator, the time for reaching the reaction rate of 40% for the adhesive for semiconductors is in the above range. Can be adjusted. Specifically, the reaction rate tends to increase as the amount of the curing accelerator added increases, and the reaction rate tends to decrease as the amount increases. However, since the amount of the appropriate curing accelerator added varies depending on the individual reaction system, the content of each component is adjusted as appropriate in order to adjust the time required for the semiconductor adhesive to reach a reaction rate of 40% within the above range. There is a need.
Moreover, the minimum melt viscosity of the adhesive agent for semiconductors can be adjusted to the said range by adjusting content, such as a thermosetting resin, a thermosetting agent, an inorganic filler, for example. The semiconductor adhesive of the present invention preferably contains an epoxy resin, an acrylic resin having an epoxy group in the side chain, a thermosetting agent, and an inorganic filler because the minimum melt viscosity is easily adjusted to the above range.
上記熱硬化性樹脂は特に限定されず、例えば、付加重合、重縮合、重付加、付加縮合、開環重合等の反応により硬化する化合物が挙げられる。上記熱硬化性樹脂として、具体的には例えば、ユリア樹脂、メラミン樹脂、フェノール樹脂、レゾルシノール樹脂、エポキシ樹脂、アクリル樹脂、ポリエステル樹脂、ポリアミド樹脂、ポリベンズイミダゾール樹脂、ジアリルフタレート樹脂、キシレン樹脂、アルキル－ベンゼン樹脂、エポキシアクリレート樹脂、珪素樹脂、ウレタン樹脂等が挙げられる。なかでも、半導体用接着剤の反応率４０％に達する時間を上記範囲に調整しやすい点、また、硬化物の物性等の点から、エポキシ樹脂が好ましい。 The said thermosetting resin is not specifically limited, For example, the compound hardened | cured by reaction, such as addition polymerization, polycondensation, polyaddition, addition condensation, ring-opening polymerization, is mentioned. Specific examples of the thermosetting resin include urea resin, melamine resin, phenol resin, resorcinol resin, epoxy resin, acrylic resin, polyester resin, polyamide resin, polybenzimidazole resin, diallyl phthalate resin, xylene resin, alkyl -Benzene resin, epoxy acrylate resin, silicon resin, urethane resin and the like. Among these, an epoxy resin is preferable from the viewpoint of easily adjusting the time required for the reaction rate of the semiconductor adhesive to reach 40% within the above range and the physical properties of the cured product.
上記エポキシ樹脂は、官能基濃度が低い、即ち、エポキシ当量が高いことが好ましい。エポキシ当量が高いエポキシ樹脂は、熱硬化剤との反応確率が低く反応性が低いため、このようなエポキシ樹脂を用いることで、半導体用接着剤の反応率４０％に達する時間を上記範囲に調整しやすくなる。上記エポキシ樹脂は、エポキシ当量が２００以上であることがより好ましく、２５０以上であることが更に好ましい。 The epoxy resin preferably has a low functional group concentration, that is, a high epoxy equivalent. Epoxy resins with a high epoxy equivalent have a low reaction probability with a thermosetting agent and a low reactivity. By using such an epoxy resin, the time to reach a reaction rate of 40% of the adhesive for semiconductor is adjusted to the above range. It becomes easy to do. The epoxy resin preferably has an epoxy equivalent of 200 or more, and more preferably 250 or more.
上記エポキシ樹脂は特に限定されず、例えば、ビスフェノールＡ型、ビスフェノールＦ型、ビスフェノールＡＤ型、ビスフェノールＳ型等のビスフェノール型エポキシ樹脂、フェノールノボラック型、クレゾールノボラック型等のノボラック型エポキシ樹脂、レゾルシノール型エポキシ樹脂、トリスフェノールメタントリグリシジルエーテル等の芳香族エポキシ樹脂、ナフタレン型エポキシ樹脂、フルオレン型エポキシ樹脂、シクロペンタジエン型又はジシクロペンタジエン型エポキシ樹脂、ポリエーテル変性エポキシ樹脂、ＮＢＲ変性エポキシ樹脂、ＣＴＢＮ変性エポキシ樹脂、及び、これらの水添化物等が挙げられる。なかでも、嵩高い構造を有するシクロペンタジエン型又はジシクロペンタジエン型エポキシ樹脂が好ましい。シクロペンタジエン型又はジシクロペンタジエン型エポキシ樹脂は、立体障害が大きく反応性が低いため、このようなエポキシ樹脂を用いることで、半導体用接着剤の反応率４０％に達する時間を上記範囲に調整しやすくなる。これらのエポキシ樹脂は、単独で用いてもよく、２種以上を併用してもよい。 The epoxy resin is not particularly limited. For example, bisphenol type epoxy resins such as bisphenol A type, bisphenol F type, bisphenol AD type and bisphenol S type, novolac type epoxy resins such as phenol novolak type and cresol novolak type, resorcinol type epoxy Resin, aromatic epoxy resin such as trisphenolmethane triglycidyl ether, naphthalene type epoxy resin, fluorene type epoxy resin, cyclopentadiene type or dicyclopentadiene type epoxy resin, polyether modified epoxy resin, NBR modified epoxy resin, CTBN modified epoxy Examples thereof include resins and hydrogenated products thereof. Among these, a cyclopentadiene type or dicyclopentadiene type epoxy resin having a bulky structure is preferable. Cyclopentadiene-type or dicyclopentadiene-type epoxy resins have large steric hindrance and low reactivity. By using such an epoxy resin, the time to reach a reaction rate of 40% for a semiconductor adhesive is adjusted to the above range. It becomes easy. These epoxy resins may be used independently and may use 2 or more types together.
上記エポキシ樹脂は、常温で液状のエポキシ樹脂であっても、常温で固体のエポキシ樹脂であってもよく、これらを適宜組み合わせて用いてもよい。
上記常温で液状のエポキシ樹脂のうち、市販品として、例えば、ＥＰＩＣＬＯＮ　８４０、８４０－Ｓ、８５０、８５０－Ｓ、ＥＸＡ－８５０ＣＲＰ（以上、ＤＩＣ社製）等のビスフェノールＡ型エポキシ樹脂、ＥＰＩＣＬＯＮ　８３０、８３０－Ｓ、ＥＸＡ－８３０ＣＲＰ（以上、ＤＩＣ社製）等のビスフェノールＦ型エポキシ樹脂、ＥＰＩＣＬＯＮ　ＨＰ－４０３２、ＨＰ－４０３２Ｄ（以上、ＤＩＣ社製）等のナフタレン型エポキシ樹脂、ＥＰＩＣＬＯＮ　ＥＸＡ－７０１５（ＤＩＣ社製）、ＥＸ－２５２（ナガセケムテックス社製）等の水添ビスフェノールＡ型エポキシ樹脂、ＥＸ－２０１（ナガセケムテックス社製）等のレゾルシノール型エポキシ樹脂等が挙げられる。 The epoxy resin may be an epoxy resin that is liquid at room temperature, or may be an epoxy resin that is solid at room temperature, or may be used in appropriate combination.
Among the epoxy resins that are liquid at room temperature, commercially available products include, for example, bisphenol A type epoxy resins such as EPICLON 840, 840-S, 850, 850-S, EXA-850CRP (above, manufactured by DIC), EPICLON 830, Bisphenol F type epoxy resins such as 830-S and EXA-830CRP (made by DIC), naphthalene type epoxy resins such as EPICLON HP-4032 and HP-4032D (made by DIC), EPICLON EXA-7015 (DIC) And hydrogenated bisphenol A type epoxy resin such as EX-252 (manufactured by Nagase ChemteX), and resorcinol type epoxy resin such as EX-201 (manufactured by Nagase ChemteX).
上記常温で固体のエポキシ樹脂のうち、市販品として、例えば、ＥＰＩＣＬＯＮ　８６０、１０５５０、１０５５（以上、ＤＩＣ社製）等のビスフェノールＡ型エポキシ樹脂、ＥＰＩＣＬＯＮ　ＥＸＡ－１５１４（ＤＩＣ社製）等のビスフェノールＳ型エポキシ樹脂、ＥＰＩＣＬＯＮ　ＨＰ－４７００、ＨＰ－４７１０、ＨＰ－４７７０（以上、ＤＩＣ社製）等のナフタレン型エポキシ樹脂、ＥＰＩＣＬＯＮ　ＨＰ－７２００シリーズ（ＤＩＣ社製）等のジシクロペンタジエン型エポキシ樹脂、ＥＰＩＣＬＯＮ　ＨＰ－５０００、ＥＸＡ－９９００（以上、ＤＩＣ社製）等のクレゾールノボラック型エポキシ樹脂等が挙げられる。 Among the epoxy resins that are solid at room temperature, commercially available products include, for example, bisphenol A type epoxy resins such as EPICLON 860, 10550, 1055 (manufactured by DIC), and bisphenol S such as EPICLON EXA-1514 (manufactured by DIC). Type epoxy resin, naphthalene type epoxy resin such as EPICLON HP-4700, HP-4710, HP-4770 (manufactured by DIC), dicyclopentadiene type epoxy resin such as EPICLON HP-7200 series (made by DIC), EPICLON Examples thereof include cresol novolac type epoxy resins such as HP-5000 and EXA-9900 (manufactured by DIC).
上記熱硬化剤は特に限定されず、従来公知の熱硬化剤を上記熱硬化性樹脂に合わせて適宜選択することができる。上記熱硬化性樹脂としてエポキシ樹脂を用いる場合、上記熱硬化剤として、例えば、酸無水物系硬化剤、フェノール系硬化剤、アミン系硬化剤、ジシアンジアミド等の潜在性硬化剤、カチオン系触媒型硬化剤等が挙げられる。これらの熱硬化剤は、単独で用いてもよく、２種以上を併用してもよい。なかでも、硬化物の物性等に優れることから、酸無水物系硬化剤が好ましい。 The said thermosetting agent is not specifically limited, A conventionally well-known thermosetting agent can be suitably selected according to the said thermosetting resin. When an epoxy resin is used as the thermosetting resin, the thermosetting agent may be, for example, an acid anhydride curing agent, a phenol curing agent, an amine curing agent, a latent curing agent such as dicyandiamide, or a cationic catalytic curing. Agents and the like. These thermosetting agents may be used independently and may use 2 or more types together. Among these, an acid anhydride curing agent is preferable because of excellent physical properties of the cured product.
上記酸無水物系硬化剤のうち、市販品として、例えば、ＹＨ－３０６、ＹＨ－３０７（以上、三菱化学社製、常温（２５℃）で液状）、ＹＨ－３０９（三菱化学社製、酸無水物系硬化剤、常温（２５℃）で固体）等が挙げられる。 Among the above acid anhydride curing agents, commercially available products include, for example, YH-306, YH-307 (manufactured by Mitsubishi Chemical Corporation, liquid at room temperature (25 ° C.)), YH-309 (manufactured by Mitsubishi Chemical Corporation, acid Anhydride type curing agent, solid at normal temperature (25 ° C.)) and the like.
上記熱硬化剤の含有量は特に限定されず、上記熱硬化性樹脂としてエポキシ樹脂を用い、エポキシ基と等量反応する熱硬化剤を用いる場合、上記熱硬化剤の含有量は、半導体用接着剤中に含まれるエポキシ基の総量に対する好ましい下限が６０当量、好ましい上限が１１０当量である。含有量が６０当量未満であると、半導体用接着剤を充分に硬化させることができないことがある。含有量が１１０当量を超えても、特に半導体用接着剤の硬化性には寄与せず、過剰な熱硬化剤が揮発することによってボイドの原因となることがある。含有量のより好ましい下限は７０当量、より好ましい上限は１００当量である。 The content of the thermosetting agent is not particularly limited. When an epoxy resin is used as the thermosetting resin and a thermosetting agent that reacts with an epoxy group in an equal amount is used, the content of the thermosetting agent is an adhesive for a semiconductor. A preferred lower limit to the total amount of epoxy groups contained in the agent is 60 equivalents, and a preferred upper limit is 110 equivalents. If the content is less than 60 equivalents, the semiconductor adhesive may not be sufficiently cured. Even if the content exceeds 110 equivalents, it does not particularly contribute to the curability of the adhesive for semiconductors and may cause voids due to volatilization of the excessive thermosetting agent. The more preferable lower limit of the content is 70 equivalents, and the more preferable upper limit is 100 equivalents.
上記硬化促進剤は特に限定されず、例えば、イミダゾール系硬化促進剤、３級アミン系硬化促進剤等が挙げられる。なかでも、半導体用接着剤の反応率４０％に達する時間を上記範囲に調整しやすい点、また、硬化物の物性等の調整をするための反応系の制御をしやすい点から、イミダゾール系硬化促進剤が好ましい。 The said hardening accelerator is not specifically limited, For example, an imidazole series hardening accelerator, a tertiary amine type hardening accelerator, etc. are mentioned. Among them, imidazole-based curing is easy because it can easily adjust the time to reach a reaction rate of 40% for semiconductor adhesives within the above range, and it is easy to control the reaction system for adjusting the physical properties of the cured product. Accelerators are preferred.
上記イミダゾール系硬化促進剤は特に限定されず、例えば、フジキュアー７０００（Ｔ＆Ｋ　ＴＯＫＡ社製、常温（２５℃）で液状）、イミダゾールの１位をシアノエチル基で保護した１－シアノエチル－２－フェニルイミダゾール、イソシアヌル酸で塩基性を保護したイミダゾール系硬化促進剤（商品名「２ＭＡ－ＯＫ」、四国化成工業社製、常温（２５℃）で固体）、２ＭＺ、２ＭＺ－Ｐ、２ＰＺ、２ＰＺ－ＰＷ、２Ｐ４ＭＺ、Ｃ１１Ｚ－ＣＮＳ、２ＰＺ－ＣＮＳ、２ＰＺＣＮＳ－ＰＷ、２ＭＺ－Ａ、２ＭＺＡ－ＰＷ、Ｃ１１Ｚ－Ａ、２Ｅ４ＭＺ－Ａ、２ＭＡＯＫ－ＰＷ、２ＰＺ－ＯＫ、２ＭＺ－ＯＫ、２ＰＨＺ、２ＰＨＺ－ＰＷ、２Ｐ４ＭＨＺ、２Ｐ４ＭＨＺ－ＰＷ、２Ｅ４ＭＺ・ＢＩＳ、ＶＴ、ＶＴ－ＯＫ、ＭＡＶＴ、ＭＡＶＴ－ＯＫ（以上、四国化成工業社製）等が挙げられる。これらのイミダゾール系硬化促進剤は、単独で用いてもよく、２種以上を併用してもよい。 The imidazole curing accelerator is not particularly limited, and examples thereof include Fujicure 7000 (manufactured by T & K TOKA, liquid at room temperature (25 ° C.)), 1-cyanoethyl-2-phenylimidazole in which the 1-position of imidazole is protected with a cyanoethyl group, Imidazole-based curing accelerator with basicity protected with isocyanuric acid (trade name “2MA-OK”, manufactured by Shikoku Kasei Kogyo Co., Ltd., solid at room temperature (25 ° C.)), 2MZ, 2MZ-P, 2PZ, 2PZ-PW, 2P4MZ , C11Z-CNS, 2PZ-CNS, 2PZCNS-PW, 2MZ-A, 2MZA-PW, C11Z-A, 2E4MZ-A, 2MAOK-PW, 2PZ-OK, 2MZ-OK, 2PHZ, 2PHZ-PW, 2P4MHZ, 2P4MHZ -PW, 2E4MZ ・ BIS, VT, VT-OK, MAVT, MAVT-O (Or more, Shikoku Chemicals Co., Ltd.), and the like. These imidazole type hardening accelerators may be used independently and may use 2 or more types together.
上記硬化促進剤の含有量は特に限定されないが、熱硬化剤１００重量部に対する好ましい下限が１重量部、好ましい上限が５０重量部であり、より好ましい下限は２重量部、より好ましい上限は３０重量部である。含有量が２重量部未満であると、半導体用接着剤の熱硬化のために高温で長時間の加熱を必要とすることがある。含有量が５０重量部を超えると、半導体用接着剤の貯蔵安定性が不充分となったり、過剰な硬化促進剤が揮発することによってボイドの原因となったりすることがある。 Although content of the said hardening accelerator is not specifically limited, The preferable minimum with respect to 100 weight part of thermosetting agents is 1 weight part, A preferable upper limit is 50 weight part, A more preferable minimum is 2 weight part, A more preferable upper limit is 30 weight. Part. When the content is less than 2 parts by weight, heating at a high temperature for a long time may be required for thermosetting the adhesive for semiconductor. If the content exceeds 50 parts by weight, the storage stability of the adhesive for semiconductors may be insufficient, or voids may be caused by excessive volatilization of the curing accelerator.
本発明の半導体用接着剤は、フィルム状の接着剤である場合には、更に、高分子量化合物を含有することが好ましい。上記高分子量化合物を用いることで、半導体用接着剤に製膜性、可撓性等を付与するとともに、半導体用接着剤の硬化物に強靭性を持たせ、高い接合信頼性を確保することができる。
上記高分子量化合物は特に限定されず、例えば、ユリア樹脂、メラミン樹脂、フェノール樹脂、レゾルシノール樹脂、エポキシ樹脂、アクリル樹脂、ポリエステル樹脂、ポリアミド樹脂、ポリベンズイミダゾール樹脂、ジアリルフタレート樹脂、キシレン樹脂、アルキル－ベンゼン樹脂、エポキシアクリレート樹脂、珪素樹脂、ウレタン樹脂等の公知の高分子量化合物が挙げられる。なかでも、エポキシ基を有する高分子量化合物が好ましい。 When the adhesive for semiconductors of the present invention is a film adhesive, it preferably further contains a high molecular weight compound. By using the above-mentioned high molecular weight compound, it is possible to provide film-forming properties, flexibility, etc. to the semiconductor adhesive, and toughen the cured product of the semiconductor adhesive to ensure high bonding reliability. it can.
The high molecular weight compound is not particularly limited. For example, urea resin, melamine resin, phenol resin, resorcinol resin, epoxy resin, acrylic resin, polyester resin, polyamide resin, polybenzimidazole resin, diallyl phthalate resin, xylene resin, alkyl- Known high molecular weight compounds such as benzene resin, epoxy acrylate resin, silicon resin, and urethane resin can be used. Among these, a high molecular weight compound having an epoxy group is preferable.
上記エポキシ基を有する高分子量化合物を添加することで、半導体用接着剤の硬化物は、優れた可撓性を発現する。即ち、半導体用接着剤の硬化物は、上記熱硬化性樹脂としてのエポキシ樹脂に由来する優れた機械的強度、耐熱性及び耐湿性と、上記エポキシ基を有する高分子量化合物に由来する優れた可撓性とを兼備することとなるので、耐冷熱サイクル性、耐ハンダリフロー性、寸法安定性等に優れるものとなり、高い接合信頼性及び高い導通信頼性を発現することとなる。 By adding the high molecular weight compound having the epoxy group, the cured product of the semiconductor adhesive exhibits excellent flexibility. That is, the cured product of the adhesive for semiconductors has excellent mechanical strength, heat resistance and moisture resistance derived from the epoxy resin as the thermosetting resin, and excellent good resistance derived from the high molecular weight compound having the epoxy group. Since it also has flexibility, it will be excellent in cold-heat cycle resistance, solder reflow resistance, dimensional stability, etc., and will exhibit high joint reliability and high conduction reliability.
上記エポキシ基を有する高分子量化合物は、末端及び／又は側鎖（ペンダント位）にエポキシ基を有する高分子量化合物であれば特に限定されず、例えば、エポキシ基含有アクリルゴム、エポキシ基含有ブタジエンゴム、ビスフェノール型高分子量エポキシ樹脂、エポキシ基含有フェノキシ樹脂、エポキシ基含有アクリル樹脂、エポキシ基含有ウレタン樹脂、エポキシ基含有ポリエステル樹脂等が挙げられる。なかでも、エポキシ基を多く含む高分子化合物を得ることができ、硬化物の機械的強度及び耐熱性がより優れたものとなることから、エポキシ基含有アクリル樹脂が好ましい。これらのエポキシ基を有する高分子量化合物は、単独で用いてもよく、２種以上を併用してもよい。 The high molecular weight compound having an epoxy group is not particularly limited as long as it is a high molecular weight compound having an epoxy group at the terminal and / or side chain (pendant position). For example, an epoxy group-containing acrylic rubber, an epoxy group-containing butadiene rubber, Examples thereof include bisphenol type high molecular weight epoxy resin, epoxy group-containing phenoxy resin, epoxy group-containing acrylic resin, epoxy group-containing urethane resin, and epoxy group-containing polyester resin. Among them, an epoxy group-containing acrylic resin is preferable because a polymer compound containing a large amount of epoxy groups can be obtained and the cured product has better mechanical strength and heat resistance. These high molecular weight compounds having an epoxy group may be used alone or in combination of two or more.
上記高分子量化合物として、上記エポキシ基を有する高分子量化合物、特に、エポキシ基含有アクリル樹脂を用いる場合、上記エポキシ基を有する高分子量化合物の重量平均分子量の好ましい下限は１万、好ましい上限は１００万である。重量平均分子量が１万未満であると、半導体用接着剤の製膜性が不充分となったり、半導体用接着剤の硬化物の可撓性が充分に向上しなかったりすることがある。重量平均分子量が１００万を超えると、位置合わせする工程１において半導体用接着剤を一定の厚みに供給することが困難となったり、ボイドを除去する工程３において半導体用接着剤の溶融粘度が高くなりすぎて流動性が低下し、ボイドを充分に除去できなかったりすることがある。 When the high molecular weight compound having an epoxy group, particularly an epoxy group-containing acrylic resin is used as the high molecular weight compound, the preferred lower limit of the weight average molecular weight of the high molecular weight compound having the epoxy group is 10,000, and the preferred upper limit is 1,000,000. It is. When the weight average molecular weight is less than 10,000, the film forming property of the semiconductor adhesive may be insufficient, or the flexibility of the cured product of the semiconductor adhesive may not be sufficiently improved. If the weight average molecular weight exceeds 1,000,000, it becomes difficult to supply the semiconductor adhesive to a certain thickness in the alignment step 1, or the melt viscosity of the semiconductor adhesive is high in the void removal step 3. In some cases, the fluidity decreases and the voids cannot be sufficiently removed.
上記高分子量化合物として、上記エポキシ基を有する高分子量化合物、特に、エポキシ基含有アクリル樹脂を用いる場合、上記エポキシ基を有する高分子量化合物は、官能基濃度が低い、即ち、エポキシ当量が高いことが好ましい。エポキシ当量が高い高分子量化合物は、反応性が低いため、このような高分子量化合物を用いることで、半導体用接着剤の反応率４０％に達する時間を上記範囲に調整しやすくなる。上記エポキシ基を有する高分子量化合物は、エポキシ当量が２００以上であることがより好ましく、２５０以上であることが更に好ましい。 When the high molecular weight compound having the epoxy group is used as the high molecular weight compound, particularly when the epoxy group-containing acrylic resin is used, the high molecular weight compound having the epoxy group has a low functional group concentration, that is, a high epoxy equivalent. preferable. Since a high molecular weight compound having a high epoxy equivalent has low reactivity, it is easy to adjust the time required for the reaction rate of the semiconductor adhesive to reach 40% within the above range by using such a high molecular weight compound. The high molecular weight compound having an epoxy group preferably has an epoxy equivalent of 200 or more, and more preferably 250 or more.
本発明の半導体用接着剤における上記高分子量化合物の含有量は特に限定されないが、好ましい下限は３重量％、好ましい上限は３０重量％である。含有量が３重量％未満であると、熱ひずみに対する充分な信頼性が得られないことがある。含有量が３０重量％を超えると、半導体用接着剤の耐熱性が低下することがある。 Although content of the said high molecular weight compound in the adhesive agent for semiconductors of this invention is not specifically limited, A preferable minimum is 3 weight% and a preferable upper limit is 30 weight%. If the content is less than 3% by weight, sufficient reliability against thermal strain may not be obtained. When content exceeds 30 weight%, the heat resistance of the adhesive agent for semiconductors may fall.
本発明の半導体用接着剤は、更に、無機フィラーを含有することが好ましい。
上記無機フィラーは特に限定されず、例えば、シリカ、アルミナ、窒化アルミニウム、窒化ホウ素、窒化珪素、炭化珪素、酸化マグネシウム、酸化亜鉛等が挙げられる。なかでも、流動性に優れることから球状シリカが好ましく、メチルシランカップリング剤、フェニルシランカップリング剤等で表面処理された球状シリカがより好ましい。表面処理された球状シリカを用いることで、半導体用接着剤の増粘を抑えることができ、ボイドを除去する工程３において極めて効率的にボイドを除去することができる。 The semiconductor adhesive of the present invention preferably further contains an inorganic filler.
The inorganic filler is not particularly limited, and examples thereof include silica, alumina, aluminum nitride, boron nitride, silicon nitride, silicon carbide, magnesium oxide, and zinc oxide. Of these, spherical silica is preferable because of excellent fluidity, and spherical silica surface-treated with a methylsilane coupling agent, a phenylsilane coupling agent, or the like is more preferable. By using the surface-treated spherical silica, it is possible to suppress the thickening of the adhesive for semiconductors, and it is possible to remove voids very efficiently in the step 3 of removing voids.
上記無機フィラーの平均粒子径は特に限定されないが、半導体用接着剤の透明性、流動性、接合信頼性等の観点から、０．０１～１μｍ程度が好ましい。 The average particle size of the inorganic filler is not particularly limited, but is preferably about 0.01 to 1 μm from the viewpoints of transparency, fluidity, bonding reliability, etc. of the adhesive for semiconductors.
本発明の半導体用接着剤は、必要に応じて、更に、希釈剤、チキソトロピー付与剤、溶媒、無機イオン交換体、ブリード防止剤、イミダゾールシランカップリング剤等の接着性付与剤、密着性付与剤、ゴム粒子等の応力緩和剤等のその他の添加剤を含有してもよい。 The adhesive for semiconductors of the present invention is further provided with an adhesive imparting agent such as a diluent, a thixotropy imparting agent, a solvent, an inorganic ion exchanger, a bleed inhibitor, an imidazole silane coupling agent, and an adhesion imparting agent as necessary. Other additives such as stress relieving agents such as rubber particles may be contained.
本発明の半導体用接着剤を製造する方法は特に限定されず、ペースト状の接着剤である場合、例えば、熱硬化性樹脂及び熱硬化剤に、必要に応じて硬化促進剤、高分子量化合物、無機フィラー及びその他の添加剤を所定量配合して混合する方法が挙げられる。上記混合の方法は特に限定されず、例えば、ホモディスパー、万能ミキサー、バンバリーミキサー、ニーダー、ビーズミル、ホモジナイザー等を使用する方法が挙げられる。また、フィルム状の接着剤である場合、例えば、同様の材料を溶媒に所定量添加して接着剤溶液を調製し、接着剤溶液を離型ＰＥＴフィルム上に塗工し、接着剤溶液を乾燥させる方法が挙げられる。フィルム状の接着剤である場合、本発明の半導体用接着剤の厚みは特に限定されないが、１０～５０μｍが好ましく、１０～４０μｍがより好ましい。 The method for producing the semiconductor adhesive of the present invention is not particularly limited, and when it is a paste-like adhesive, for example, a thermosetting resin and a thermosetting agent, if necessary, a curing accelerator, a high molecular weight compound, A method in which a predetermined amount of an inorganic filler and other additives are mixed and mixed may be mentioned. The mixing method is not particularly limited, and examples thereof include a method using a homodisper, a universal mixer, a Banbury mixer, a kneader, a bead mill, a homogenizer, and the like. In the case of a film-like adhesive, for example, a predetermined amount of the same material is added to a solvent to prepare an adhesive solution, the adhesive solution is applied onto a release PET film, and the adhesive solution is dried. The method of letting it be mentioned. In the case of a film adhesive, the thickness of the semiconductor adhesive of the present invention is not particularly limited, but is preferably 10 to 50 μm, and more preferably 10 to 40 μm.
本発明によれば、ペリフェラル部に突起電極を有する半導体チップのみならず、ペリフェラル部とペリフェラル部より内側の面内とに突起電極を有する半導体チップを用いても、ボイドを充分に抑制することができる半導体用接着剤を提供することができる。 According to the present invention, not only a semiconductor chip having a protruding electrode in the peripheral portion, but also a void can be sufficiently suppressed even if a semiconductor chip having a protruding electrode on the inner side of the peripheral portion and the peripheral portion is used. The adhesive for semiconductors which can be provided can be provided.
以下に実施例を掲げて本発明の態様を更に詳しく説明するが、本発明はこれら実施例のみに限定されない。 The embodiments of the present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.
（実施例１～４及び比較例１～７）
（１）接着剤の製造
表１に記載した配合組成に従って下記に示す材料を溶媒（メチルエチルケトン）に加え、ホモディスパーを用いて攪拌混合して接着剤溶液を製造した。得られた接着剤溶液を、アプリケーターを用いて離型ＰＥＴフィルム上に乾燥後の厚みが４０μｍとなるように塗工し、接着剤溶液を乾燥させて、フィルム状の接着剤を製造した。使用時まで、離型ＰＥＴフィルム上に形成された接着剤層の表面に、別の離型ＰＥＴフィルム（保護フィルム）を貼り付けて保護した。
・ＨＰ－７２００ＨＨ（ジシクロペンタジエン型エポキシ樹脂、エポキシ当量２８０、ＤＩＣ社製）
・ＥＰ－４０８８Ｓ（ジシクロペンタジエン型エポキシ樹脂、エポキシ当量１７０、アデカ社製）
・ＹＨ－３０９（酸無水物系硬化剤、三菱化学社製）
・フジキュアー７０００（イミダゾール系硬化促進剤、Ｔ＆Ｋ　ＴＯＫＡ社製）
・２ＭＺＡ－ＰＷ（イミダゾール系硬化促進剤、四国化成工業社製）
・Ｇ－２０５０Ｍ（グリシジル基含有アクリル樹脂、エポキシ当量３４０、日油社製）
・Ｇ－０２５０ＳＰ（グリシジル基含有アクリル樹脂、エポキシ当量３１０、日油社製）
・ＹＡ０５０Ｃ－ＳＰ５（シリカフィラー、アドマテックス社製）
・ＫＢＥ－４０２（３－グリシドキシプロピルメチルジエトキシシラン、信越化学工業社製） (Examples 1 to 4 and Comparative Examples 1 to 7)
(1) Manufacture of adhesives The materials shown below were added to a solvent (methyl ethyl ketone) in accordance with the composition described in Table 1, and the mixture was stirred and mixed using a homodisper to prepare an adhesive solution. The obtained adhesive solution was applied on a release PET film using an applicator so that the thickness after drying was 40 μm, and the adhesive solution was dried to produce a film-like adhesive. Until use, another release PET film (protective film) was adhered to the surface of the adhesive layer formed on the release PET film for protection.
・ HP-7200HH (dicyclopentadiene type epoxy resin, epoxy equivalent 280, manufactured by DIC)
EP-4088S (dicyclopentadiene type epoxy resin, epoxy equivalent 170, manufactured by Adeka)
・ YH-309 (acid anhydride curing agent, manufactured by Mitsubishi Chemical Corporation)
・ Fujicure 7000 (Imidazole-based curing accelerator, manufactured by T & K TOKA)
・ 2MZA-PW (Imidazole-based curing accelerator, manufactured by Shikoku Kasei Kogyo Co., Ltd.)
・ G-2050M (Glycidyl group-containing acrylic resin, epoxy equivalent 340, manufactured by NOF Corporation)
・ G-0250SP (Glycidyl group-containing acrylic resin, epoxy equivalent 310, manufactured by NOF Corporation)
・ YA050C-SP5 (silica filler, manufactured by Admatechs)
・ KBE-402 (3-glycidoxypropylmethyldiethoxysilane, manufactured by Shin-Etsu Chemical Co., Ltd.)
（２）最低溶融粘度の測定
得られた接着剤について、回転式レオメーター装置（ＶＡＲ－１００、レオロジカ社製）を用い、昇温速度５℃／分、周波数１Ｈｚ、歪み１％で「８０℃～２００℃における最低溶融粘度」を測定した。 (2) Measurement of Minimum Melt Viscosity For the obtained adhesive, using a rotary rheometer device (VAR-100, manufactured by Rheologicala), a temperature rising rate of 5 ° C./min, a frequency of 1 Hz, a strain of 1% is “80 ° C. The “minimum melt viscosity at ˜200 ° C.” was measured.
（３）示差走査熱量の測定
得られた接着剤について、昇温速度１、２、５、１０℃／ｍｉｎの４条件で示差走査熱量測定を行い、温度Ｔの逆数と、昇温速度Ｂの対数（ｌｏｇＢ）とをプロットした。得られた直線の傾きから、上記式（１）にもとづいて、活性化エネルギーΔＥを算出した。次いで、活性化エネルギーΔＥから、上記式（２）の定温劣化式にもとづいて、２６０℃４秒及び２６０℃６秒保持した場合の反応率を算出した。
なお、示差走査熱量計（ＤＳＣ６２２０、日立ハイテクノロジー社製）及び反応速度解析ソフト（エスアイアイ・ナノテクノロジー社製）を使用した。
算出した４秒保持した場合の反応率と６秒保持した場合の反応率とに基づき、「２６０℃で反応率４０％に達する所要時間」を算出した。 (3) Measurement of differential scanning calorific value The obtained adhesive was subjected to differential scanning calorimetric measurement under four conditions of heating rate 1, 2, 5, 10 ° C./min. Logarithm (log B) was plotted. The activation energy ΔE was calculated from the slope of the obtained straight line based on the above formula (1). Next, from the activation energy ΔE, the reaction rate when held at 260 ° C. for 4 seconds and 260 ° C. for 6 seconds was calculated based on the constant temperature deterioration formula of the above formula (2).
A differential scanning calorimeter (DSC 6220, manufactured by Hitachi High-Technologies Corporation) and a reaction rate analysis software (manufactured by SII Nanotechnology Inc.) were used.
Based on the calculated reaction rate when held for 4 seconds and reaction rate when held for 6 seconds, the “required time to reach a reaction rate of 40% at 260 ° C.” was calculated.
（４）半導体装置の製造
（４－１）半導体チップを接着剤を介して基板上に位置合わせする工程１、及び、基板及び半導体チップに接着剤を仮接着させる工程２
半田からなる先端部を有する突起電極がペリフェラル部とペリフェラル部より内側の半導体チップ面内とに形成された半導体チップと、Ｃｕ／Ｓｏｌｄｅｒ電極を有する基板とを用意した。接着剤の片面の保護フィルムを剥がし、真空ラミネーター（ＡＴＭ－８１２Ｍ、タカトリ社製）を用いて、ステージ温度６０℃、真空度１００Ｐａで半導体チップ上に貼付した。
次いで、フリップチップボンダ（ＦＣ－３０００Ｓ、東レエンジニアリング社製）を用いて、半導体チップを、接着剤を介して基板上に位置合わせし（工程１）、ボンディングステージ温度１００℃の条件下で、１６０℃接触で２９０℃まで昇温し、０．９６ＭＰａで２．４秒間荷重をかけ、半導体チップの突起電極と基板の電極部とを溶融接合させるとともに、接着剤を仮接着させた（工程２）。 (4) Manufacturing of semiconductor device (4-1) Step 1 for aligning a semiconductor chip on a substrate via an adhesive, and Step 2 for temporarily bonding an adhesive to the substrate and the semiconductor chip
A semiconductor chip in which a protruding electrode having a tip portion made of solder was formed in a peripheral portion, a semiconductor chip surface inside the peripheral portion, and a substrate having a Cu / Solder electrode were prepared. The protective film on one side of the adhesive was peeled off and stuck on the semiconductor chip using a vacuum laminator (ATM-812M, manufactured by Takatori) at a stage temperature of 60 ° C. and a vacuum of 100 Pa.
Next, using a flip chip bonder (FC-3000S, manufactured by Toray Engineering Co., Ltd.), the semiconductor chip is aligned on the substrate via an adhesive (step 1). The temperature was raised to 290 ° C. by contact at 0 ° C., and a load was applied at 0.96 MPa for 2.4 seconds to melt-bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and to temporarily bond the adhesive (step 2) .
（４－２）ボイドを除去する工程３
得られた仮接着体を、加圧オーブン（ＶＦＳ、ＡＰＴ社製）に投入し、以下の加圧、加熱条件により接着剤を加圧雰囲気下で加熱してボイドを除去するとともに（工程３）、接着剤を完全に硬化させて、半導体装置を得た。
＜加圧、加熱条件＞
ＳＴＥＰ１：３０℃から１００℃まで２０分で一定昇温、０．８ＭＰａ
ＳＴＥＰ２：１００℃で６０分保持、０．８Ｐａ
ＳＴＥＰ３：１００℃から１８０℃まで一定昇温、０．８ＭＰａ
ＳＴＥＰ４：１８０℃で１０分保持、０．８ＭＰａ
ＳＴＥＰ５：１８０℃から３０℃まで２０分で降温、０．８ＭＰａ (4-2) Step 3 for removing voids
The obtained temporary adhesive body is put into a pressure oven (VFS, manufactured by APT), and the adhesive is heated under a pressure atmosphere under the following pressure and heating conditions to remove voids (step 3). The adhesive was completely cured to obtain a semiconductor device.
<Pressurization and heating conditions>
STEP 1: Constant temperature increase from 30 ° C to 100 ° C in 20 minutes, 0.8 MPa
STEP 2: Hold at 100 ° C. for 60 minutes, 0.8 Pa
STEP3: Constant temperature increase from 100 ° C to 180 ° C, 0.8 MPa
STEP 4: Hold at 180 ° C. for 10 minutes, 0.8 MPa
STEP5: Temperature drop from 180 ° C to 30 ° C in 20 minutes, 0.8 MPa
＜評価＞
実施例及び比較例で得られた半導体装置について、以下の評価を行った。結果を表１に示した。 <Evaluation>
The following evaluation was performed about the semiconductor device obtained by the Example and the comparative example. The results are shown in Table 1.
ボイドの有無
超音波探査映像装置（Ｃ－ＳＡＭ　Ｄ９５００、日本バーンズ社製）を用いて、ボイドを除去する工程３の前後における半導体装置を観察し、ボイドの有無を評価した。半導体チップの接着面積に対するボイド発生部分の面積が１％未満であった場合を良品（〇）、１％以上であった場合を不良品（×）とした。なお、良品か不良品かの判断は、ｎ数を５個として、半導体チップの接着面積に対するボイド発生部分の面積が最も小さかった半導体装置について行った。また、ｎ数を５個として良品率（ｘ／５）を求めた。 Presence / absence of voids Using an ultrasonic exploration imaging apparatus (C-SAM D9500, manufactured by Nihon Burns), the semiconductor device was observed before and after step 3 for removing voids, and the presence / absence of voids was evaluated. A case where the area of the void generation portion with respect to the bonding area of the semiconductor chip was less than 1% was judged as a non-defective product (◯) and a case where it was 1% or more as a defective product (x). Whether the product is a non-defective product or a defective product was determined for a semiconductor device in which the number of n was 5, and the area of the void generation portion with respect to the bonding area of the semiconductor chip was the smallest. Further, the non-defective product rate (x / 5) was determined with the number of n being 5.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
本発明によれば、ペリフェラル部のみならず、ペリフェラル部とペリフェラル部より内側の面内とに突起電極を有する半導体チップを用いても、ボイドを充分に抑制することができる半導体用接着剤を提供することができる。 According to the present invention, there is provided a semiconductor adhesive capable of sufficiently suppressing voids even when a semiconductor chip having a protruding electrode is used not only in the peripheral portion but also in the peripheral portion and the surface inside the peripheral portion. can do.

Claims (3)

  1. 半田からなる先端部を有する突起電極がペリフェラル部及び該ペリフェラル部より内側の半導体チップ面内に形成された半導体チップを、半導体用接着剤を介して基板上に位置合わせする工程１と、
    前記半導体チップを半田溶融点以上の温度に加熱して、前記半導体チップの突起電極と前記基板の電極部とを溶融接合させるとともに、前記半導体用接着剤を仮接着させる工程２と、
    前記半導体用接着剤を加圧雰囲気下で加熱してボイドを除去する工程３とを有する半導体装置の製造方法に用いられる半導体用接着剤であって、
    前記半導体用接着剤は、８０～２００℃における最低溶融粘度が１０００Ｐａ・ｓ以下であり、小澤法によって求めた２６０℃で反応率４０％に達する所要時間が８秒以上である
    ことを特徴とする半導体用接着剤。     A step 1 of aligning a semiconductor chip in which a protruding electrode having a tip portion made of solder is formed in a peripheral portion and a semiconductor chip surface inside the peripheral portion on a substrate via a semiconductor adhesive;
    Heating the semiconductor chip to a temperature equal to or higher than a solder melting point to melt-bond the protruding electrode of the semiconductor chip and the electrode portion of the substrate, and temporarily bond the adhesive for the semiconductor; and
    A semiconductor adhesive used in a method for manufacturing a semiconductor device, comprising: removing the voids by heating the adhesive for semiconductor in a pressurized atmosphere;
    The semiconductor adhesive has a minimum melt viscosity at 80 to 200 ° C. of 1000 Pa · s or less, and a required time to reach a reaction rate of 40% at 260 ° C. determined by the Ozawa method is 8 seconds or more. Adhesive for semiconductors.
  2. 少なくとも熱硬化性樹脂と熱硬化剤とを含有し、前記熱硬化性樹脂は、エポキシ樹脂であることを特徴とする請求項１記載の半導体用接着剤。 The adhesive for semiconductor according to claim 1, comprising at least a thermosetting resin and a thermosetting agent, wherein the thermosetting resin is an epoxy resin.
  3. 更に、硬化促進剤を含有することを特徴とする請求項１又は２記載の半導体用接着剤。 Furthermore, a hardening accelerator is contained, The adhesive agent for semiconductors of Claim 1 or 2 characterized by the above-mentioned.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016148121A1 (en) * 2015-03-19 2016-09-22 ナミックス株式会社 Method for manufacturing flip chip package, flip chip package, and resin composition for pre-application type underfills
JP2017186483A (en) * 2016-04-08 2017-10-12 積水化学工業株式会社 Laminated sheet, method of manufacturing semiconductor chip with adhesive layer and metal material, and method of manufacturing semiconductor device
JP2022100210A (en) * 2020-12-23 2022-07-05 ドゥーサン コーポレイション Underfill film for semiconductor package and manufacturing method of semiconductor package using the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7176536B2 (en) * 2018-01-30 2022-11-22 昭和電工マテリアルズ株式会社 Adhesive composition, film adhesive, adhesive sheet, and method for manufacturing semiconductor device
KR102555721B1 (en) * 2018-08-20 2023-07-17 삼성전자주식회사 method for bonding flip chip
JP6691998B1 (en) * 2019-12-24 2020-05-13 株式会社鈴木 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011211156A (en) * 2009-10-19 2011-10-20 Sumitomo Bakelite Co Ltd Process for production electronic device, and electronic device
JP2012089571A (en) * 2010-10-15 2012-05-10 Sumitomo Bakelite Co Ltd Resin composition and manufacturing method of electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004311709A (en) 2003-04-07 2004-11-04 Renesas Technology Corp Manufacturing method of semiconductor device and semiconductor manufacturing device
JP4640380B2 (en) 2007-06-20 2011-03-02 パナソニック株式会社 Mounting method of semiconductor device
WO2011048774A1 (en) * 2009-10-19 2011-04-28 住友ベークライト株式会社 Process for production of electronic device, electronic device, and device for production of electronic device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011211156A (en) * 2009-10-19 2011-10-20 Sumitomo Bakelite Co Ltd Process for production electronic device, and electronic device
JP2012089571A (en) * 2010-10-15 2012-05-10 Sumitomo Bakelite Co Ltd Resin composition and manufacturing method of electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016148121A1 (en) * 2015-03-19 2016-09-22 ナミックス株式会社 Method for manufacturing flip chip package, flip chip package, and resin composition for pre-application type underfills
KR20170128224A (en) * 2015-03-19 2017-11-22 나믹스 가부시끼가이샤 Method for manufacturing flip chip package, flip chip package, and resin composition for pre-application type underfills
JPWO2016148121A1 (en) * 2015-03-19 2017-12-28 ナミックス株式会社 Flip chip mounted body manufacturing method, flip chip mounted body, and pre-supplied underfill resin composition
KR102455429B1 (en) * 2015-03-19 2022-10-14 나믹스 가부시끼가이샤 Method for manufacturing flip chip package, flip chip package, and resin composition for pre-application type underfills
JP2017186483A (en) * 2016-04-08 2017-10-12 積水化学工業株式会社 Laminated sheet, method of manufacturing semiconductor chip with adhesive layer and metal material, and method of manufacturing semiconductor device
JP2022100210A (en) * 2020-12-23 2022-07-05 ドゥーサン コーポレイション Underfill film for semiconductor package and manufacturing method of semiconductor package using the same
JP7220260B2 (en) 2020-12-23 2023-02-09 ドゥーサン コーポレイション Semiconductor package underfill film and semiconductor package manufacturing method using the same

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