WO2014205924A1 - Method for generating layout of addressable test chip - Google Patents
Method for generating layout of addressable test chip Download PDFInfo
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- WO2014205924A1 WO2014205924A1 PCT/CN2013/083597 CN2013083597W WO2014205924A1 WO 2014205924 A1 WO2014205924 A1 WO 2014205924A1 CN 2013083597 W CN2013083597 W CN 2013083597W WO 2014205924 A1 WO2014205924 A1 WO 2014205924A1
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- the invention comprises a decoder in a peripheral circuit of the addressable test chip, and a library containing design rules and technical files is designed in the software to facilitate adjustment and design of the decoder, and the circuit verification can be run according to customer input requirements;
- the invention comprises
- the test structure is a parameterization unit, the parameterization unit of the size required by the DUT can be succinctly generated in the design, so that the device under test can be flexibly placed in the addressable test chip;
- the invention is based on the addressable test
- the advantages and test procedures are automatically generated according to the design information, so the test speed is fast and the test result is accurate; the software generated by the invention can be applied to the standard parameter test machine in the industry; the test accuracy of the invention can reach pA level.
- FIG. 2 is a flow chart of test chip generation and testing of the present invention.
- constructing a basic structure can be a template structure.
- the template structure describes the shape of the test structure, and its shape is implemented by a large number of parameter constraints.
- each sub-unit must select one element as the reference element, and then all other elements are used as a reference to constrain the relative distance before the reference element to determine its shape.
- the template structure is instantiated on a large scale. In the process of instantiation, the process is to assign different values to the parameters. This can generate a large number of actual structures that meet the requirements. The whole process is implemented in software. In the end, it is possible to quickly implement large-scale test layouts.
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Abstract
The present invention relates to the field of integrated circuit test chips. Disclosed is a method for generating the layout of an addressable test chip, comprising the following steps: (1) selecting an IP; (2) according to a design rule, placing test structures into an array; and (3) automatically connecting the IP and the test structure array to a winding to generate the layout of a test chip. The present invention is automatically generated, according to the advantage of an addressable test and a test program, in accordance with design information, so that the test speed is fast and the test result is accurate. Software generated in the present invention can be applied to a parameter tester of intra-industry standards. The test accuracy of the present invention can reach the pA level. The automation generation of the present invention not only greatly shortens the development time of a test chip, reduces human resource costs, and avoids design errors caused by hand drawing, but also improves the extensibility and reusability of the addressable test chip, and provides a powerful guarantee for quickly coping with procedure changes and process node transitions.
Description
本发明涉及集成电路设计领域，尤其涉及一种可寻址测试芯片版图的生成方法。 The present invention relates to the field of integrated circuit design, and in particular, to a method for generating an addressable test chip layout.
传统半导体制造中，短程测试芯片依靠其生产周期长、测试灵活性大，成为获取半导体生产工艺缺陷率和成品率的重要方法。但是短程测试芯片需要将测试单元单独的连接到终端PAD（焊盘）上，通常每个测试单元需要连接两个或多个PAD。当芯片在进行测量时，连接测量仪器的探针打在PAD上，测量信号通过探针进入到PAD，进而进入到与PAD相连接的测试单元中，从而对测试单元进行测量来检测是否存在缺陷。但是PAD面积较大，这造成了短程测试芯片的面积利用率很低。基于这个考虑，普通可寻址测试芯片通过引入类似于静态记忆体芯片的地址译码电路，大大减少了PAD的数量，相对提高了测试芯片的面积利用率。
In traditional semiconductor manufacturing, short-range test chips rely on their long production cycle and high test flexibility, making them an important method for obtaining defect rate and yield of semiconductor manufacturing processes. However, the short-range test chip needs to connect the test unit separately to the terminal PAD (pad). Usually, each test unit needs to connect two or more PADs. When the chip is measuring, the probe connected to the measuring instrument is hit on the PAD, and the measurement signal enters the PAD through the probe, and then enters the test unit connected to the PAD, thereby measuring the test unit to detect whether there is a defect. . However, the PAD area is large, which results in a low area utilization of the short-range test chip. Based on this consideration, the ordinary addressable test chip greatly reduces the number of PADs by introducing an address decoding circuit similar to a static memory chip, and relatively improves the area utilization of the test chip.
普通可寻址测试芯片包括行列地址译码电路，信号选择电路以及测试单元。行译码电路的任务是从测试单元阵列诸多行中选择所需的行，列译码电路的任务是产生列选信号，从选中行所对应的某个测试单元中选取所需要的某个测试结构；信号选择电路由与信号线相连的列导通管串联而成，并分别由行列地址译码电路产生的行列选信号来控制，当行列选信号均为高电平时，对应的行列导通管均导通，信号线上的测试信号就可以单独地进入到选中的测试结构，进行相应的测试。例如，当有m和PAD作为行地址位，n个PAD作为列地址位，4个PAD作为信号线，那么通过（m+n+4）个PAD，可以控制（2m×2n）个测试单元。The general addressable test chip includes a row and column address decoding circuit, a signal selection circuit, and a test unit. The task of the row decoding circuit is to select a desired row from a plurality of rows of the test cell array. The task of the column decoding circuit is to generate a column selection signal, and select a required test from a test unit corresponding to the selected row. The signal selection circuit is formed by connecting the column conduction pipes connected to the signal lines in series, and is controlled by the row and column selection signals generated by the row and column address decoding circuits respectively. When the row and column selection signals are all high level, the corresponding row and column are turned on. The tubes are all turned on, and the test signals on the signal lines can be individually entered into the selected test structure for corresponding testing. For example, when there are m and PAD as row address bits, n PADs as column address bits, and 4 PADs as signal lines, then (2 m × 2 n ) tests can be controlled by (m + n + 4) PADs. unit.
但是由于普通可寻址测试芯片的测试单元的测试结构采用了平铺式的摆放方法，并且PAD所占据的区域是不允许有测试单元的，使得测试芯片的面积相对较大且利用率很低。对不同DUT(待测器件)放入设计复杂，一个固定的pad
framer如 2x20
pads适用于几乎任何形状和尺寸的DUT，此时，在可寻址阵列中，根据具体情况需要调整解码器并重新设计以适用于不同形状和尺寸的DUT。
However, since the test structure of the test unit of the ordinary addressable test chip adopts a tiled placement method, and the area occupied by the PAD is not allowed to have a test unit, the test chip has a relatively large area and a high utilization rate. low. Putting a complex design on a different DUT (device under test), a fixed pad
Framer like 2x20
Pads are suitable for DUTs of almost any shape and size. In this case, in an addressable array, the decoder needs to be tuned and redesigned to suit DUTs of different shapes and sizes as needed.
普通可寻址测试芯片在测量过程中，设计***电路中包含解码器，相对于储存器只需要测量出0或1的数字信号，解码器的模拟信号测量要复杂的多，如电流等模拟信息测试等；传统测试芯片很简单，如测试机只需要施加一个直流电压，电路会直接通过探针测量出来，而可寻址测试芯片的测试程序则需要创建，通过解码器寻址，通过***电路施加电压，通过***电路测量电流；普通可寻址测试芯片在数据分析验证中需要特殊处理，如解码错误会对整个DUT电路产生影响，因此解码器必须在数据分析前验证。
In the measurement process, the general addressable test chip includes a decoder in the peripheral circuit, and only needs to measure 0 or 1 digital signal with respect to the memory. The analog signal measurement of the decoder is much more complicated, such as analog information such as current. Test, etc.; the traditional test chip is very simple, such as the test machine only needs to apply a DC voltage, the circuit will be measured directly through the probe, and the test program of the addressable test chip needs to be created, addressed by the decoder, through the peripheral circuit Voltage is applied and current is measured through peripheral circuits; common addressable test chips require special processing in data analysis and verification. For example, decoding errors will affect the entire DUT circuit, so the decoder must be verified before data analysis.
由此可见，普通可寻址测试芯片在设计上包含上述译码电路、信号选择电路、测试单元及***电路等，相比较传统测试芯片的设计和数据验证等方面要复杂的多。
It can be seen that the general addressable test chip includes the above-mentioned decoding circuit, signal selection circuit, test unit and peripheral circuit in design, which is much more complicated than the traditional test chip design and data verification.
针对现有技术存在的不足，本发明提供了一种可寻址测试芯片版图的生成方法，根据测试芯片的不同需求，建立关键参数的尺寸变量，从单一的参数化结构批量实例化大量测试结构的版图，然后模块布局、整合成完整的测试芯片，最后输出GDSII版图。
In view of the deficiencies of the prior art, the present invention provides a method for generating an addressable test chip layout. According to the different requirements of the test chip, a size variable of a key parameter is established, and a large number of test structures are instantiated from a single parameterized structure. The layout, then the module layout, integrated into a complete test chip, and finally output GDSII layout.
一种可寻址测试芯片版图的生成方法 ，包括以下步骤： A method for generating an addressable test chip layout includes the following steps:
（1）选择IP； (1) Select IP;
（2）根据设计规则将测试结构摆放成阵列； (2) placing the test structures in an array according to design rules;
（3）IP和测试结构阵列自动连接绕线产生测试芯片版图。 (3) The IP and test structure arrays are automatically connected to the winding to generate a test chip layout.
作为优选，可寻址测试芯片***电路被定义为IP，且IP是分别根据测试对象和测试芯片在晶圆上的位置不同而分类的。设计者需要根据设计情况在解码器中选择特定的IP。
Preferably, the addressable test chip peripheral circuit is defined as IP, and the IP is classified according to the position of the test object and the test chip on the wafer, respectively. The designer needs to select a specific IP in the decoder depending on the design.
作为优选，测试结构是参数化单元或者是非参数化单元。 Preferably, the test structure is a parameterized unit or a non-parametric unit.
作为优选，若测试结构是参数化单元，参数化单元中的基本元素是通过已定义测试结构的模板，搭配不同的参数，自动生成特定测试结构的版图。
Preferably, if the test structure is a parameterization unit, the basic element in the parameterization unit is to automatically generate a layout of the specific test structure by using a template of the defined test structure with different parameters.
作为优选，自动产生测试芯片版图后，可以对版图进行验证并生成验证文件。 Preferably, after the test chip layout is automatically generated, the layout can be verified and a verification file generated.
作为优选，测试对象包含晶体管或无源器件。 Preferably, the test object comprises a transistor or a passive device.
作为优选，步骤（3）之后还包括以下几个步骤： Preferably, after step (3), the following steps are further included:
A. 验证***电路，对之前所有的设计、版图绘制进行检查； A. Verify the peripheral circuits and check all previous design and layout drawings;
B. 生成验证文件； B. Generate a verification file;
C. 生成测试文件。 C. Generate a test file.
作为优选，验证***电路即就是使用多个已知属性的DUT按一定的位置规则摆放在阵列中,与***可寻址电路连接测试，根据测试结果的位置规则的对错验证***可寻址电路是否正常工作。
Preferably, the verification peripheral circuit means that the DUT using a plurality of known attributes is placed in the array according to a certain position rule, and the peripheral addressable circuit is connected to the test, and the peripheral addressable according to the positional rule of the test result is verified. The circuit is working properly.
作为优选，DUT的类型为高阻器件或低阻器件或晶体管器件。 Preferably, the type of DUT is a high resistance device or a low resistance device or a transistor device.
作为优选，根据版图中DUT的位置自动获得DUT的地址并根据用户的定义生成测试文件。 Preferably, the address of the DUT is automatically obtained according to the location of the DUT in the layout and a test file is generated according to the definition of the user.
本发明由于采用了以上技术方案，具有显著的技术效果： The invention has the remarkable technical effects by adopting the above technical solutions:
本发明根据可寻址测试芯片的***电路中包含解码器，设计包含设计规则和技术文件的库在软件中，方便解码器的调整及设计，并可以根据客户输入要求运行电路验证；本发明包含的测试结构是参数化单元时，设计中可以简洁地产生DUT所需尺寸的参数化单元，故可以灵活地把待测器件放到可寻址测试芯片中去；本发明根据可寻址测试的优点及测试程序根据设计信息自动生成，故测试速度迅速且测试结果精确；本发明生成的软件可以应用到行业内标准的参数测试机中；本发明测试精度可达到pA级。本发明自动化生成不仅大大缩短了测试芯片的开发时间，降低了人力成本、避免了人工绘图带来的设计错误，还提高了可寻址测试芯片的可延展性和重复使用力，为快速应对制程变更、工艺节点转移提供了有力保障。
The invention comprises a decoder in a peripheral circuit of the addressable test chip, and a library containing design rules and technical files is designed in the software to facilitate adjustment and design of the decoder, and the circuit verification can be run according to customer input requirements; the invention comprises When the test structure is a parameterization unit, the parameterization unit of the size required by the DUT can be succinctly generated in the design, so that the device under test can be flexibly placed in the addressable test chip; the invention is based on the addressable test The advantages and test procedures are automatically generated according to the design information, so the test speed is fast and the test result is accurate; the software generated by the invention can be applied to the standard parameter test machine in the industry; the test accuracy of the invention can reach pA level. The automatic generation of the invention not only greatly shortens the development time of the test chip, reduces the labor cost, avoids the design error caused by the manual drawing, but also improves the malleability and reusability of the addressable test chip, and responds quickly to the process. Change, process node transfer provides a strong guarantee.
图1是本发明的生成流程图。 Figure 1 is a flow chart of the generation of the present invention.
图2是本发明的测试芯片生成及测试流程图。 2 is a flow chart of test chip generation and testing of the present invention.
下面结合附图与实施例对本发明作进一步详细描述。 The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
实施例1 Example 1
一种可寻址测试芯片版图的生成方法， 如图1所示，包括以下步骤： A method for generating an addressable test chip layout, as shown in FIG. 1, includes the following steps:
（1）选择IP； (1) Select IP;
（2）根据设计规则将测试结构摆放成阵列； (2) placing the test structures in an array according to design rules;
（3）IP和测试结构阵列自动连接绕线产生测试芯片版图； (3) The IP and test structure arrays are automatically connected to the winding to generate a test chip layout;
可寻址测试芯片***电路被定义为IP，且IP是分别根据测试对象和测试芯片在晶圆上的位置不同而分类的。IP包括了测试芯片***的译码电路，信号选择电路以及它们的走线。IP的类型是由需要设计的测试芯片的类型所决定。设计者需要考虑测试芯片在晶圆上放置位置的不同，测试对象的不同，来选择特定的IP。
The addressable test chip peripheral circuit is defined as IP, and the IP is classified according to the position of the test object and the test chip on the wafer, respectively. The IP includes decoding circuits on the periphery of the test chip, signal selection circuits, and their traces. The type of IP is determined by the type of test chip that needs to be designed. The designer needs to consider the difference in the placement of the test chip on the wafer, the difference in the test object, to select a specific IP.
测试结构是参数化单元或者是非参数化单元，若测试结构是参数化单元，参数化单元中的基本元素是通过已定义测试结构的模板，搭配不同的参数，自动生成特定测试结构的版图。
The test structure is a parameterized unit or a non-parameterized unit. If the test structure is a parameterized unit, the basic element in the parameterized unit is to automatically generate a layout of the specific test structure by using a template of the defined test structure with different parameters.
具体实施过程如下： The specific implementation process is as follows:
首先，设计者需要考虑测试芯片在晶圆上放置位置的不同，测试对象的不同，来选择特定的IP。IP是为了方便客户使用并设计测试芯片而设计出来的，将IP根据测试对象分为专门用来测试晶体管的和专门测试无源器件的两种类型，根据芯片放置位置不同分为放置在划片槽上的和放置在普通芯片位置的两种类型。客户可以根据不同的需求选择不同的IP，同时，IP是参数化的，用户可以给予IP不同的输入值而自动生成不同大小、不同测试容量的IP。
First, the designer needs to consider the difference in the placement of the test chip on the wafer, the difference in the test object, to select a specific IP. IP is designed for the convenience of customers to use and design test chips. The IP is divided into two types according to the test object, which are specially used for testing transistors and testing passive devices. They are divided into dicing according to different placement positions of the chips. There are two types of slots on the slot and placed in the normal chip position. Customers can choose different IPs according to different needs. At the same time, IP is parameterized. Users can give IP different input values and automatically generate IPs of different sizes and different test capacities.
其次，构建一个基本结构，可以成为模板结构，此模板结构描述出了测试结构的形状，其形状由大量的参数约束实现。在构建结构的构成中，每一个子单元必须选中一个元素作为参考元素，接下来其他所有的元素以此作为参考，约束其参考元素之前的相对距离达到确定其形状的目的。完成模板结构后对此模板结构大规模的实例化，在实例化的过程中其实就是对其中的参数赋予不同值的过程，这样就可以产生大量满足需求的实际结构，整个过程以软件的方式实现，最终能够快速实现大规模的测试版图。
Secondly, constructing a basic structure can be a template structure. The template structure describes the shape of the test structure, and its shape is implemented by a large number of parameter constraints. In the construction of the construction structure, each sub-unit must select one element as the reference element, and then all other elements are used as a reference to constrain the relative distance before the reference element to determine its shape. After the template structure is completed, the template structure is instantiated on a large scale. In the process of instantiation, the process is to assign different values to the parameters. This can generate a large number of actual structures that meet the requirements. The whole process is implemented in software. In the end, it is possible to quickly implement large-scale test layouts.
再次，在完成测试结构单元的版图生成之后，测试结构布局模块负责将测试结构布局到PAD阵列中，根据测试结构尺寸将其放置在PAD之间或者PAD外侧。测试结构布线模块根据测试结构与PAD的连接关系。由迷宫算法自动寻找走线路径，完成从测试结构引脚到PAD的金属连线，即绕线。
Again, after the layout of the test building unit is completed, the test structure layout module is responsible for arranging the test structure into the PAD array, placing it between the PADs or outside the PAD depending on the size of the test structure. The test structure wiring module is based on the connection relationship between the test structure and the PAD. The maze algorithm automatically finds the trace path and completes the metal connection from the test structure pin to the PAD, that is, the winding.
完成连线之后的测试宏进行Floorplan排布，就是对所有位置定义好的module按照一定的规则排布在decoder电路里，完成最终的测试芯片版图。
After the completion of the connection, the test macro is arranged in the Floorplan, that is, the modules defined for all positions are arranged in the decoder circuit according to certain rules to complete the final test chip layout.
实施例2 Example 2
一种可寻址测试芯片版图的生成方法， 如图1所示，包括如下步骤： A method for generating an addressable test chip layout, as shown in FIG. 1, includes the following steps:
（1）根据测试芯片在晶圆上放置的位置以及测试对象的不同，来选择特定的IP； (1) selecting a specific IP according to the position of the test chip placed on the wafer and the test object;
（2）根据设计规则将测试结构摆放成阵列； (2) placing the test structures in an array according to design rules;
（3）IP和测试结构阵列自动连接绕线产生测试芯片版图； (3) The IP and test structure arrays are automatically connected to the winding to generate a test chip layout;
在步骤（3）之后，可以继续以下几个步骤： After step (3), you can continue with the following steps:
A. 验证***电路，对之前所有的设计、版图绘制进行检查； A. Verify the peripheral circuits and check all previous design and layout drawings;
B. 生成验证文件； B. Generate a verification file;
C. 生成测试文件。 C. Generate a test file.
可寻址测试芯片***电路被定义为IP，且IP是分别根据测试对象和测试芯片在晶圆上的位置不同而分类的。IP包括了测试芯片***的译码电路，信号选择电路以及它们的走线。IP的类型是由需要设计的测试芯片的类型所决定。设计者需要考虑测试芯片在晶圆上放置位置的不同，测试对象的不同，来选择特定的IP。
The addressable test chip peripheral circuit is defined as IP, and the IP is classified according to the position of the test object and the test chip on the wafer, respectively. The IP includes decoding circuits on the periphery of the test chip, signal selection circuits, and their traces. The type of IP is determined by the type of test chip that needs to be designed. The designer needs to consider the difference in the placement of the test chip on the wafer, the difference in the test object, to select a specific IP.
测试结构是参数化单元或者是非参数化单元，若测试结构是参数化单元，参数化单元中的基本元素是通过已定义测试结构的模板，搭配不同的参数，自动生成特定测试结构的版图。
The test structure is a parameterized unit or a non-parameterized unit. If the test structure is a parameterized unit, the basic element in the parameterized unit is to automatically generate a layout of the specific test structure by using a template of the defined test structure with different parameters.
具体实施过程如下： The specific implementation process is as follows:
首先，设计者需要考虑测试芯片在晶圆上放置位置的不同，测试对象的不同，来选择特定的IP。IP是为了方便客户使用并设计测试芯片而设计出来的，将IP根据测试对象分为专门用来测试晶体管的和专门测试无源器件的两种类型，根据芯片放置位置不同分为放置在划片槽上的和放置在普通芯片位置的两种类型。客户可以根据不同的需求选择不同的IP，同时，IP是参数化的，用户可以给予IP不同的输入值而自动生成不同大小、不同测试容量的IP。
First, the designer needs to consider the difference in the placement of the test chip on the wafer, the difference in the test object, to select a specific IP. IP is designed for the convenience of customers to use and design test chips. The IP is divided into two types according to the test object, which are specially used for testing transistors and testing passive devices. They are divided into dicing according to different placement positions of the chips. There are two types of slots on the slot and placed in the normal chip position. Customers can choose different IPs according to different needs. At the same time, IP is parameterized. Users can give IP different input values and automatically generate IPs of different sizes and different test capacities.
其次，构建一个基本结构，可以成为模板结构，此模板结构描述出了测试结构的形状，其形状由大量的参数约束实现。在构建结构的构成中，每一个子单元必须选中一个元素作为参考元素，接下来其他所有的元素以此作为参考，约束其参考元素之前的相对距离达到确定其形状的目的。完成模板结构后对此模板结构大规模的实例化，在实例化的过程中其实就是对其中的参数赋予不同值的过程，这样就可以产生大量满足需求的实际结构，整个过程以软件的方式实现，最终能够快速实现大规模的测试版图。
Secondly, constructing a basic structure can be a template structure. The template structure describes the shape of the test structure, and its shape is implemented by a large number of parameter constraints. In the construction of the construction structure, each sub-unit must select one element as the reference element, and then all other elements are used as a reference to constrain the relative distance before the reference element to determine its shape. After the template structure is completed, the template structure is instantiated on a large scale. In the process of instantiation, the process is to assign different values to the parameters. This can generate a large number of actual structures that meet the requirements. The whole process is implemented in software. In the end, it is possible to quickly implement large-scale test layouts.
再次，在完成测试结构单元的版图生成之后，测试结构布局模块负责将测试结构布局到PAD阵列中，根据测试结构尺寸将其放置在PAD之间或者PAD外侧。测试结构布线模块根据测试结构与PAD的连接关系。由迷宫算法自动寻找走线路径，完成从测试结构引脚到PAD的金属连线，即绕线。
Again, after the layout of the test building unit is completed, the test structure layout module is responsible for arranging the test structure into the PAD array, placing it between the PADs or outside the PAD depending on the size of the test structure. The test structure wiring module is based on the connection relationship between the test structure and the PAD. The maze algorithm automatically finds the trace path and completes the metal connection from the test structure pin to the PAD, that is, the winding.
完成连线之后的测试宏进行Floorplan排布，就是对所有位置定义好的module按照一定的规则排布在decoder电路里，完成最终的测试芯片版图。
After the completion of the connection, the test macro is arranged in the Floorplan, that is, the modules defined for all positions are arranged in the decoder circuit according to certain rules to complete the final test chip layout.
最后使用解码器进行验证，会生成对应的测试程序和数据分析程序,测试芯片可以测试出短路、短路、阻抗以及晶体管特性参数等。使用多个已知属性的DUT按一定的位置规则摆放在阵列中,与***可寻址电路连接测试，根据测试结果的位置规则的对错验证***可寻址电路是否正常工作DUT的类型为高阻器件或低阻器件或晶体管器件根据版图中DUT的位置自动获得DUT的地址并根据用户的定义生成测试文件。
Finally, the decoder is used for verification, and the corresponding test program and data analysis program are generated. The test chip can test short circuit, short circuit, impedance and transistor characteristic parameters. The DUT using multiple known attributes is placed in the array according to a certain position rule, and is connected to the peripheral addressable circuit for testing. According to the positional error of the test result, it is verified whether the peripheral addressable circuit works normally. The type of the DUT is A high-impedance device or a low-resistance device or transistor device automatically obtains the address of the DUT according to the location of the DUT in the layout and generates a test file according to the user's definition.
总之，以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所作的均等变化与修饰，皆应属本发明专利的涵盖范围。
In summary, the above description is only the preferred embodiment of the present invention, and all changes and modifications made by the scope of the present invention should be covered by the present invention.
Claims (10)
1． 一种可寻址测试芯片版图的生成方法 ，其特征在于包括以下步骤： 1. A method for generating an addressable test chip layout, comprising the steps of:
（1）选择IP；(1) Select IP;
（2）根据设计规则将测试结构摆放成阵列；(2) placing the test structures in an array according to design rules;
（3）IP和测试结构阵列自动连接绕线产生测试芯片版图。(3) The IP and test structure arrays are automatically connected to the winding to generate a test chip layout.
根据权利要求1所述的一种可寻址测试芯片版图的生成方法，其特征在于：可寻址测试芯片***电路被定义为IP，且IP是分别根据测试对象和测试芯片在晶圆上的位置不同而分类的，根据设计情况在解码器中选择特定的IP。The method for generating an addressable test chip layout according to claim 1, wherein the addressable test chip peripheral circuit is defined as IP, and the IP is respectively based on the test object and the test chip on the wafer. For different locations, select a specific IP in the decoder depending on the design.
根据权利要求1所述的一种可寻址测试芯片版图的生成方法，其特征在于：测试结构是参数化单元或者是非参数化单元。
The method for generating an addressable test chip layout according to claim 1, wherein the test structure is a parameterization unit or a non-parameterization unit.
根据权利要求3所述的一种可寻址测试芯片版图的生成方法，其特征在于：若测试结构是参数化单元，参数化单元中的基本元素是通过已定义测试结构的模板，搭配不同的参数，自动生成特定测试结构的版图。The method for generating an addressable test chip layout according to claim 3, wherein if the test structure is a parameterization unit, the basic element in the parameterization unit is a template through a defined test structure, and is matched with different Parameters that automatically generate a layout of a particular test structure.
根据权利要求4所述的一种可寻址测试芯片版图的生成方法，其特征在于：自动产生测试芯片版图后，可以对版图进行验证并生成验证文件。The method for generating an addressable test chip layout according to claim 4, wherein after the test chip layout is automatically generated, the layout can be verified and a verification file is generated.
根据权利要求2所述的一种可寻址测试芯片版图的生成方法，其特征在于：测试对象包括晶体管或无源器件。
A method of generating an addressable test chip layout according to claim 2, wherein the test object comprises a transistor or a passive device.
根据权利要求1
所述的一种可寻址测试芯片版图的生成方法，其特征在于：步骤（3）之后还包括以下几个步骤：According to claim 1
The method for generating an addressable test chip layout is characterized in that: after step (3), the following steps are further included:
A. 验证***电路，对之前所有的设计、版图绘制进行检查；A. Verify the peripheral circuits and check all previous design and layout drawings;
B. 生成验证文件；B. Generate a verification file;
C. 生成测试文件。C. Generate a test file.
根据权利要求7所述的一种可寻址测试芯片版图的生成方法，其特征在于：验证***电路即就是使用已知属性的DUT按一定的位置规则摆放在阵列中,与***可寻址电路连接测试，根据测试结果的位置规则的对错验证***可寻址电路是否正常工作。The method for generating an addressable test chip layout according to claim 7, wherein the verifying the peripheral circuit is that the DUT using the known attribute is placed in the array according to a certain position rule, and is addressable with the periphery. The circuit connection test verifies that the peripheral addressable circuit works normally according to the correctness of the position of the test result.
根据权利要求8所述的一种可寻址测试芯片版图的生成方法，其特征在于：DUT的类型为高阻器件或低阻器件或晶体管器件。
The method for generating an addressable test chip layout according to claim 8, wherein the type of the DUT is a high resistance device or a low resistance device or a transistor device.
根据权利要求8所述的一种可寻址测试芯片版图的生成方法，其特征在于：根据版图中DUT的位置自动获得DUT的地址并根据用户的定义生成测试文件。
The method for generating an addressable test chip layout according to claim 8, wherein the address of the DUT is automatically obtained according to the position of the DUT in the layout and the test file is generated according to the definition of the user.
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