CN103366055A - Method for generating addressable test chip layout - Google Patents
Method for generating addressable test chip layout Download PDFInfo
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- CN103366055A CN103366055A CN2013102721857A CN201310272185A CN103366055A CN 103366055 A CN103366055 A CN 103366055A CN 2013102721857 A CN2013102721857 A CN 2013102721857A CN 201310272185 A CN201310272185 A CN 201310272185A CN 103366055 A CN103366055 A CN 103366055A
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The invention relates to the field of integrated circuit test chips and discloses a method for generating an addressable test chip layout. The method comprises the following steps: (1) selecting an IP (a peripheral circuit of an addressable test chip is defined as the IP); (2) arranging test structures in an array according to a design rule; (3) performing automatic connecting and winding on the IP and the test structure array to generate the test chip layout. According to the method, the advantages of an addressable test are combined and a test program is automatically generated according to design information, so that the test speed is high and a test result is accurate; generated software can be applied to a standard parameter test machine in the industry; the test precision can reach the level of pA. Due to automatic generation, the development time of the test chip is greatly shortened, the labor cost is reduced, a design error caused by manual drawing is avoided, the extensibility and the reusability of the addressable test chip are improved and a strong guarantee is provided for quick response to process change and process node transfer.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, relate in particular to a kind of generation method of addressable test chip domain.
Background technology
In the traditional semiconductor fabrication, the short distance test chip rely on its production cycle long, the test dirigibility is large, becomes the important method of obtaining defects of production process of semiconductor rate and yield rate.But the short distance test chip need to test cell independent be connected to terminal PAD(pad) on, each test cell need to connect two or more PAD usually.When chip when measuring, the probe that connects surveying instrument is beaten on PAD, measuring-signal enters into PAD by probe, and then enters into the test cell that is connected with PAD, thereby measurement detects whether there is defective to test cell.But the PAD area is larger, and this has caused the area utilization of short distance test chip very low.Consider that based on this common addressable test chip is similar to the address decoding circuitry of static memory body chip by introducing, greatly reduced the quantity of PAD, relatively improved the area utilization of test chip.
Common addressable test chip comprises the rank addresses decoding scheme, signal selecting circuit and test cell.The task of column decode circuitry is the required row of selection from all multirows of test cell array, and the task of array decoding circuit is to produce the column selection signal, chooses needed certain test structure from corresponding certain test cell of selected line; Signal selecting circuit is in series by the row conduction pipe that links to each other with signal wire, and the ranks that produced by the rank addresses decoding scheme respectively select signal to control, when ranks select signal to be high level, the corresponding equal conducting of ranks conduction pipe, test signal on the signal wire just can enter into the test structure of choosing individually, tests accordingly.For example, when m and PAD being arranged as row address bit, n PAD is as column address bit, and 4 PAD by (m+n+4) individual PAD, can control (2 so as signal wire
m* 2
n) individual test cell.
But because the test structure of the test cell of common addressable test chip has adopted the arrangement method of flush system, and the occupied zone of PAD is not allow test cell, so that the area of test chip is relatively large and utilization factor is very low.Different DUT (device under test) are put into the design complexity, fixing pad framer such as 2x20pads are applicable to the almost DUT of any shape and size, at this moment, in addressable array, need as the case may be to adjust demoder and redesign to be applicable to the DUT of difformity and size.
Common addressable test chip is in measuring process, and design comprises demoder in the peripheral circuit, only need to measure 0 or 1 digital signal with respect to reservoir, and the simulating signal of demoder is measured and wanted complicated many, such as analog information tests such as electric currents etc.; The traditional test chip is very simple, only need to apply a DC voltage such as test machine, and circuit can be directly by probe measurement out, the test procedure of addressable test chip then needs to create, by decoder adresses, apply voltage by peripheral circuit, measure electric current by peripheral circuit; Common addressable test chip needs special processing in the data analysis checking, can exert an influence to whole DUT circuit such as decoding error, so demoder must be verified before data analysis.
This shows that common addressable test chip comprises above-mentioned decoding scheme, signal selecting circuit, test cell and peripheral circuit etc. in design, the many of complexity are wanted in the aspects such as the design of the traditional test chip of comparing and data verification.
Summary of the invention
Deficiency for the prior art existence, the invention provides a kind of generation method of addressable test chip domain, different demands according to test chip, set up the size variable of key parameter, domain from the single a large amount of test structures of parametrization structure batch instantiation, then module placement, be integrated into complete test chip, export at last the GDSII domain.
A kind of generation method of addressable test chip domain may further comprise the steps:
(1) selects IP;
(2) according to design rule test structure is put into array;
(3) IP and test structure array produce the test chip domain from the coiling that is dynamically connected.
As preferably, addressable test chip peripheral circuit is defined as IP, and IP is respectively according to tested object and different classification of the position of test chip on wafer.The deviser need to select specific IP according to design conditions in demoder.
As preferably, test structure is parameterized units or imparametrization unit.
As preferably, if test structure is parameterized units, the fundamental element in the parameterized units is the template by defined test structure, and the different parameter of arranging in pairs or groups generates the domain of fc-specific test FC structure automatically.
As preferably, automatically produce the test chip domain after, can verify and generate authenticating documents to domain.
As preferably, tested object comprises transistor or passive device.
As preferably, step (3) also comprises following step afterwards:
A. verify peripheral circuit, all before designs, layout drawing are checked;
B. generate authenticating documents;
C. generate test file.
As preferably, the checking peripheral circuit namely is exactly to use the DUT of a plurality of known attributes to be placed in the array by certain location rule, with peripheral addressable circuits connecting test, according to the location rule of test result mistake is verified whether peripheral addressable circuits works.
As preferably, the type of DUT is high-resistance device or low-resistance device or transistor device.
As preferably, automatically obtain the address of DUT and generate test file according to user's definition according to the position of DUT in the domain.
The present invention has significant technique effect owing to adopted above technical scheme:
Comprise demoder in the peripheral circuit of the present invention according to the addressable test chip, the storehouse that design comprises design rule and technological document makes things convenient for adjustment and the design of demoder in software, and can be according to client's input requirements operation Circuit verification; When the test structure that the present invention comprises is parameterized units, can produce compactly the parameterized units of DUT required size in the design, go so can be put into device under test in the addressable test chip neatly; The present invention generates according to design information automatically according to advantage and the test procedure of addressable test, so test speed is rapid and test result is accurate; The software that the present invention generates can be applied in the parameter testing machine of industry internal standard; Measuring accuracy of the present invention can reach the pA level.Robotization of the present invention generates the development time that has not only greatly shortened test chip, the design mistake that has reduced human cost, avoided Man Graphics to bring, also improved the ductility of addressable test chip and reused power, for fast reply processing procedure change, process node transfer provide powerful guarantee.
Description of drawings
Fig. 1 is product process figure of the present invention.
Fig. 2 is that test chip of the present invention generates and test flow chart.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail.
Embodiment 1
A kind of generation method of addressable test chip domain as shown in Figure 1, may further comprise the steps:
(1) selects IP;
(2) according to design rule test structure is put into array;
(3) IP and test structure array produce the test chip domain from the coiling that is dynamically connected;
Addressable test chip peripheral circuit is defined as IP, and IP is respectively according to tested object and different classification of the position of test chip on wafer.IP has comprised the decoding scheme of test chip periphery, signal selecting circuit and their cabling.The type of IP is that the type by the test chip of needs designs is determined.The deviser need to consider the difference of test chip placement location on wafer, and the difference of tested object is selected specific IP.
Test structure is parameterized units or imparametrization unit, if test structure is parameterized units, the fundamental element in the parameterized units is the template by defined test structure, and the different parameter of arranging in pairs or groups generates the domain of fc-specific test FC structure automatically.
Specific implementation process is as follows:
At first, the deviser need to consider the difference of test chip placement location on wafer, and the difference of tested object is selected specific IP.IP is in order to make things convenient for the client to use and design test chip and designing, with IP according to tested object be divided into be used for specially test transistor and two types of special testing passive device, according to chip placement location difference be divided into be placed on the scribe line and two types of being placed on the common chip position.The client can select different IP according to different demand, and simultaneously, IP is parameterized, and the user can give the different input value of IP and automatically generate the IP of different sizes, different test capacity.
Secondly, make up a basic structure, can become formwork structure, this formwork structure has been described out the shape of test structure, and its shape is realized by a large amount of restrictions on the parameters.In the formation that makes up structure, each subelement must choose an element as the reference element, and next other all elements retrain its reference element relative distance before and reach the purpose of determining its shape with this as a reference.Finish behind the formwork structure the large-scale instantiation of this formwork structure, be exactly the process of giving different value to parameter wherein in fact in the process of instantiation, so just can produce the practical structures that satisfies the demands in a large number, whole process realizes in the mode of software, finally can realize fast testing on a large scale domain.
Again, after the domain of finishing the test structure unit generated, the test structure layout modules was responsible for the test structure layout in the PAD array, placed it between the PAD or the PAD outside according to the test structure size.The test structure interconnect module is according to the annexation of test structure and PAD.By labyrinth algorithm Automatic-searching wiring path, finish the metal connecting line from the test structure pin to PAD, i.e. coiling.
Finish the line grand Floorplan of carrying out of test afterwards and arrange, the module that exactly all positions is defined is arranged in the decoder circuit according to certain rule, finishes final test chip domain.
Embodiment 2
A kind of generation method of addressable test chip domain as shown in Figure 1, comprises the steps:
(1) according to test chip in position that wafer is placed and the difference of tested object, select specific IP;
(2) according to design rule test structure is put into array;
(3) IP and test structure array produce the test chip domain from the coiling that is dynamically connected;
In step (3) afterwards, can continue following step:
A. verify peripheral circuit, all before designs, layout drawing are checked;
B. generate authenticating documents;
C. generate test file.
Addressable test chip peripheral circuit is defined as IP, and IP is respectively according to tested object and different classification of the position of test chip on wafer.IP has comprised the decoding scheme of test chip periphery, signal selecting circuit and their cabling.The type of IP is that the type by the test chip of needs designs is determined.The deviser need to consider the difference of test chip placement location on wafer, and the difference of tested object is selected specific IP.
Test structure is parameterized units or imparametrization unit, if test structure is parameterized units, the fundamental element in the parameterized units is the template by defined test structure, and the different parameter of arranging in pairs or groups generates the domain of fc-specific test FC structure automatically.
Specific implementation process is as follows:
At first, the deviser need to consider the difference of test chip placement location on wafer, and the difference of tested object is selected specific IP.IP is in order to make things convenient for the client to use and design test chip and designing, with IP according to tested object be divided into be used for specially test transistor and two types of special testing passive device, according to chip placement location difference be divided into be placed on the scribe line and two types of being placed on the common chip position.The client can select different IP according to different demand, and simultaneously, IP is parameterized, and the user can give the different input value of IP and automatically generate the IP of different sizes, different test capacity.
Secondly, make up a basic structure, can become formwork structure, this formwork structure has been described out the shape of test structure, and its shape is realized by a large amount of restrictions on the parameters.In the formation that makes up structure, each subelement must choose an element as the reference element, and next other all elements retrain its reference element relative distance before and reach the purpose of determining its shape with this as a reference.Finish behind the formwork structure the large-scale instantiation of this formwork structure, be exactly the process of giving different value to parameter wherein in fact in the process of instantiation, so just can produce the practical structures that satisfies the demands in a large number, whole process realizes in the mode of software, finally can realize fast testing on a large scale domain.
Again, after the domain of finishing the test structure unit generated, the test structure layout modules was responsible for the test structure layout in the PAD array, placed it between the PAD or the PAD outside according to the test structure size.The test structure interconnect module is according to the annexation of test structure and PAD.By labyrinth algorithm Automatic-searching wiring path, finish the metal connecting line from the test structure pin to PAD, i.e. coiling.
Finish the line grand Floorplan of carrying out of test afterwards and arrange, the module that exactly all positions is defined is arranged in the decoder circuit according to certain rule, finishes final test chip domain.
Use at last demoder to verify, can generate corresponding test procedure and DAP, test chip can test out short circuit, short circuit, impedance and the Characteristic Parameters of Transistor etc.Use the DUT of a plurality of known attributes to be placed in the array by certain location rule, with peripheral addressable circuits connecting test, according to the location rule of test result mistake is verified whether work peripheral addressable circuits to be high-resistance device or low-resistance device or transistor device automatically obtain the address of DUT and generate test file according to user's definition according to the position of DUT in the domain for the type of DUT.
In a word, the above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (10)
1. the generation method of an addressable test chip domain is characterized in that may further comprise the steps:
(1) selects IP;
(2) according to design rule test structure is put into array;
(3) IP and test structure array produce the test chip domain from the coiling that is dynamically connected.
2. the generation method of a kind of addressable test chip domain according to claim 1, it is characterized in that: addressable test chip peripheral circuit is defined as IP, and IP is respectively according to tested object and different classification of the position of test chip on wafer, selects specific IP according to design conditions in demoder.
3. the generation method of a kind of addressable test chip domain according to claim 1, it is characterized in that: test structure is parameterized units or imparametrization unit.
4. the generation method of a kind of addressable test chip domain according to claim 3, it is characterized in that: if test structure is parameterized units, fundamental element in the parameterized units is the template by defined test structure, the different parameter of arranging in pairs or groups generates the domain of fc-specific test FC structure automatically.
5. the generation method of a kind of addressable test chip domain according to claim 4 is characterized in that: after automatically producing the test chip domain, can verify and generate authenticating documents to domain.
6. the generation method of a kind of addressable test chip domain according to claim 2, it is characterized in that: tested object comprises transistor or passive device.
7. the generation method of a kind of addressable test chip domain according to claim 1, it is characterized in that: step (3) also comprises following step afterwards:
A. verify peripheral circuit, all before designs, layout drawing are checked;
B. generate authenticating documents;
C. generate test file.
8. the generation method of a kind of addressable test chip domain according to claim 7, it is characterized in that: the checking peripheral circuit namely is exactly to use the DUT of known attribute to be placed in the array by certain location rule, with peripheral addressable circuits connecting test, according to the location rule of test result mistake is verified whether peripheral addressable circuits works.
9. the generation method of a kind of addressable test chip domain according to claim 8, it is characterized in that: the type of DUT is high-resistance device or low-resistance device or transistor device.
10. the generation method of a kind of addressable test chip domain according to claim 8 is characterized in that: automatically obtain the address of DUT and generate test file according to user's definition according to the position of DUT in the domain.
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| CN2013102721857A CN103366055A (en) | 2013-06-28 | 2013-06-28 | Method for generating addressable test chip layout |
| PCT/CN2013/083597 WO2014205924A1 (en) | 2013-06-28 | 2013-09-17 | Method for generating layout of addressable test chip |
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| CN106649894A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | Method for quickly generating device array in integrated circuit layout |
| CN108241765A (en) * | 2016-12-26 | 2018-07-03 | 杭州广立微电子有限公司 | A kind of chip transistor testing chip design method |
| CN108267682A (en) * | 2016-12-30 | 2018-07-10 | 杭州广立微电子有限公司 | A kind of high-density test chip and its test system and its test method |
| CN113514475A (en) * | 2021-06-25 | 2021-10-19 | 深圳格芯集成电路装备有限公司 | Method for generating reference template for chip detection and related equipment |
| CN116542209A (en) * | 2023-07-05 | 2023-08-04 | 上海韬润半导体有限公司 | Layout optimization method and device for SOC (system on chip) |
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| CN111346845B (en) * | 2020-03-18 | 2022-06-24 | 广东利扬芯片测试股份有限公司 | Chip testing method and chip testing system |
| CN111680470B (en) * | 2020-05-26 | 2023-03-24 | 西北核技术研究院 | Digital signal processor layout distribution positioning method |
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| CN116542209A (en) * | 2023-07-05 | 2023-08-04 | 上海韬润半导体有限公司 | Layout optimization method and device for SOC (system on chip) |
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