WO2014153886A1 - 阵列基板及其扇出线结构 - Google Patents

阵列基板及其扇出线结构 Download PDF

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Publication number
WO2014153886A1
WO2014153886A1 PCT/CN2013/078248 CN2013078248W WO2014153886A1 WO 2014153886 A1 WO2014153886 A1 WO 2014153886A1 CN 2013078248 W CN2013078248 W CN 2013078248W WO 2014153886 A1 WO2014153886 A1 WO 2014153886A1
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Prior art keywords
segment
fan
out line
conductive film
length
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PCT/CN2013/078248
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English (en)
French (fr)
Inventor
柴立
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深圳市华星光电技术有限公司
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Priority to US14/113,815 priority Critical patent/US20140291846A1/en
Publication of WO2014153886A1 publication Critical patent/WO2014153886A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to an array substrate and a fan-out line structure thereof. ⁇ Background technique ⁇
  • the liquid crystal panel is an important component of the liquid crystal display device, and the liquid crystal panel can display an image under the cooperation of the backlight module and the driving circuit.
  • the liquid crystal panel includes an array substrate and a color filter substrate. As shown in FIG. 1, the TFT array region 2 is disposed on the liquid crystal panel 1, the signal array and the TFT are filled in the TFT array region, and the driving circuit board 3 passes through the fan-out line 4 ( Fanout line) The signal line of the array substrate is connected to the soldering leg of the driving circuit board, and the setting area of the fan-out line 4 is called a fanout area.
  • the current uniformity of the fan-out area line impedance of the conventional array substrate is completed by a winding design.
  • the structure of the fan-out line is as shown in FIG. 3, and includes: a first metal layer 410, an insulating layer 420, and a second The metal layer 430 and the passivation layer, the main work layer is metal AL.
  • the fan-out area design tends to increase the winding length of the fan-out line in the middle area and reduce the impedance difference between the line in the middle area of the fan-out area and the fan-out line on both sides, thus increasing the height of the fan-out area (winding length) Increase the need to increase the area used for winding).
  • the intermediate fan-out line 200 in the middle of the fan-out area increases the impedance by increasing the length of the winding, so that it and both sides
  • the height of the fan-out area increases, which is a limitation on the layout of the array substrate, and also affects the product technology. Development, for example: narrow frame design, the increase in the height of the fan-out area is undoubtedly reducing the display area of the liquid crystal display panel, which in turn increases the frame width of the liquid crystal display device.
  • the technical problem to be solved by the present invention is to provide an array substrate and a display panel that reduce the difference in fan-out line impedance and the height of the fan-out area is small.
  • the array substrate and the display panel provided by the present invention can further reduce the liquid crystal display device at the same time.
  • the frame makes the frame of the liquid crystal display device narrower.
  • a fan-out line structure of an array substrate the fan-out line is used for connecting a signal line and a solder fillet, and includes: a plurality of fan-out lines disposed in a fan-out area of the array substrate, The fan-out line has a plurality of different lengths; at least one fan-out line includes a first segment and a second segment, and a material resistivity of the second segment is greater than a resistivity of the first segment, The length of the second segment of the shorter length fan-out line is greater than the length of the second segment of the longer length fan-out line.
  • the lengths of the first segment and the second segment of the fan-out lines of different lengths are different, and the resistance values of the fan-out lines are equal.
  • the length of the second segment of the shorter fan-out line is greater than the second segment of the longer fan-out line, such that the difference in impedance between the two fan-out lines of different lengths is reduced or even the same.
  • the first segment is a metal conductive film disposed on the array substrate
  • the second segment is an indium tin oxide conductive film.
  • the two segments use different conductive materials, respectively, and the resistivity of the two segmented conductive materials is different, so that the length of the two segments can be adjusted such that the impedance difference between the fan-out line and the other fan-out lines is reduced.
  • the first segment is a double conductive layer structure, which is a first metal conductive film, an insulating layer and a second metal conductive film which are sequentially arranged on the array substrate; the second segment is indium tin oxide. Conductive film.
  • the double-layer metal conductive film can effectively ensure the stable operation of the fan-out line.
  • the first metal conductive film and the second metal conductive film are provided with a dew portion, and the indium tin oxide conductive film covers the junction between the first segment and the second segment. Describe the dew. By providing a dew portion and covering it on the dew portion in the indium tin oxide fabrication process, the contact area between the two segments is increased, thereby improving the electrical connection stability between the two segments.
  • the fan-out line further includes a third segment, the third segment is also a double conductive layer structure, and the third segment includes a first metal conductive film and insulation disposed on the array substrate in sequence. a layer and a second metal conductive film, wherein an impedance of the fan-out line is adjusted according to a length of the second segment, and a length of the second segment of the shorter fan-out line is greater than a second length of the longer fan-out line The length of the segment.
  • the second section can be set at the partition, and the process can be single, and the impedance of the fan-out line can be adjusted only by adjusting the length of the partition.
  • An array substrate comprising: a glass substrate, wherein the glass substrate is provided with a plurality of signal lines, a plurality of fan-out lines, and solder fillets, wherein the fan-out lines are disposed in a fan-out line arrangement area of the glass substrate, the fan-out line Connecting the signal line to the solder fillet; the plurality of fan-out lines have a plurality of different lengths; at least one fan-out line includes a first segment and a second segment, and the material of the second segment The resistivity is greater than the resistivity of the first segment, and the length of the second segment of the shorter fan-out line is greater than the length of the second segment of the longer fan-out line.
  • the lengths of the first segment and the second segment of the fan-out lines of different lengths are different, and the resistance values of the fan-out lines are equal.
  • the length of the second segment of the shorter fan-out line is greater than the second segment of the longer fan-out line, such that the difference in impedance between the two fan-out lines of different lengths is reduced or even the same.
  • the first segment is a metal conductive film disposed on the array substrate, and the first segment is a double conductive layer structure, which is a first metal conductive film sequentially disposed on the array substrate. And an insulating layer and a second metal conductive film; the second segment is an indium tin oxide conductive film; a junction of the first segment and the second segment, the first metal conductive film, and the The second metal conductive film is provided with a dew portion, and the indium tin oxide conductive film covers the dew portion.
  • the two segments use different conductive materials, respectively, and the resistivity of the two segmented conductive materials is different, so that the length of the two segments can be adjusted.
  • the difference between the impedance of the fan-out line and the impedance of the other fan-out lines is reduced; the double-layer metal conductive film can effectively ensure the stable operation of the fan-out line; by setting the dew portion and covering it in the indium tin oxide manufacturing process On the exposed portion of the tree, the contact area between the two segments is increased, thereby improving the electrical connection stability between the two segments.
  • the fan-out line further includes a third segment, the third segment is also a double conductive layer structure, and the third segment includes a first metal conductive film and an insulating layer sequentially disposed on the array substrate. And a second metal conductive film, the impedance of the fan-out line is adjusted according to the length of the second segment, and the length of the second segment of the shorter fan-out line is greater than the second segment of the longer fan-out line The length of the segment.
  • the existing process it is only necessary to divide in the fan-out line, and the second section can be set at the partition, and the process can be single, and the impedance of the fan-out line can be adjusted only by adjusting the length of the partition.
  • At least one fan-out line of the fan-out area of the array substrate includes a first segment and a second segment, and a material resistivity of the second segment is greater than a resistivity of the first segment, the fan
  • the length of the first segment and the second segment of the outgoing line are set according to the impedance of the fan-out line and the other fan-out lines, and the length of the first segment and the second segment is adjusted to make the shorter fan-out line
  • the length of the two segments is greater than the length of the second segment of the longer fan-out line, such that the impedance difference between the shorter fan-out line and the longer fan-out line is reduced.
  • the effect of reducing the impedance between the fan-out lines can be achieved without winding, and at the same time, since the winding is not required, the laying area of the fan-out line in the middle area is fixed.
  • the reduction of the fan-out area is correspondingly reduced, which is advantageous for increasing the display area of the liquid crystal panel and reducing the width of the non-display area, and further reducing the liquid crystal display device without increasing the number of ICs.
  • the frame makes the frame of the liquid crystal display device narrower, and at the same time reduces the production cost of the liquid crystal display device (the number of ICs does not increase).
  • 1 is a structural tube diagram of a conventional liquid crystal panel
  • FIG. 2 is a schematic view showing a fan-out line arrangement of a fan-out area of a conventional liquid crystal panel
  • Figure 3 is a cross-sectional view taken along line DD of Figure 2
  • 4 is a schematic view showing the arrangement of a fan-out line of a liquid crystal panel according to Embodiment 1 of the present invention
  • Figure 5 is a cross-sectional view taken along line A-A of Figure 4,
  • Figure 6 is a cross-sectional view taken along line B-B of Figure 4,
  • Figure 7 is a cross-sectional view taken along line C-C of Figure 4,
  • FIG. 8 is a schematic structural view of an array substrate (partial) according to Embodiment 1 of the present invention.
  • FIG. 9 is a schematic view showing the arrangement of a fan-out line of a liquid crystal panel according to Embodiment 2 of the present invention.
  • FIG. 4 is a specific embodiment of a fan-out line structure of an array substrate according to the present invention.
  • the fan-out line is used for connecting a signal line and a solder fillet, and includes: a plurality of fan-out lines disposed in a fan-out area of the array substrate, The plurality of fan-out lines have a plurality of different length levels; the at least one fan-out line includes a first segment and a second segment, and the second segment has a material resistivity greater than a resistivity of the first segment
  • the length of the second segment of the shorter fan-out line is greater than the length of the second segment of the longer fan-out line, and the length of the first segment and the second segment of the fan-out line is based on the fan-out line
  • An impedance difference setting of the other fan-out lines, the length of the second segment of the shorter fan-out line being greater than the length of the second segment of the longer fan-out line by adjusting the lengths of the first segment and the second segment The length, so
  • the middlemost intermediate fan-out line 200 includes: 210, the second segment 220 and the third segment 230, the first segment 210 and the third segment 230 are respectively connected to the driving circuit board and the signal lines on the array substrate, and the first segment 210 and the third segment 230 Electrical connection is achieved by the second segment 220.
  • the impedance of the longest left fan outlet line 100 and the right fan outlet line 300 is the largest, this embodiment
  • the middle left fan outlet 100 and the right fan outlet 300 do not need to be provided with the second segment, but for the fanout line between the intermediate fan outlet 200 and the left fan outlet 100 and the right fan outlet 300, it is still necessary to set the first Two segments.
  • the fan-out lines are sequentially arranged to the two sides from the position of the intermediate fan-out line 100, and the length thereof is sequentially increased, and the impedance thereof is also increased. Therefore, the lengths of the second segments of the fan-out lines need to be set to be sequentially decreased.
  • the sum of the lengths of the first segment and the third segment of each fan-out line is also kept increasing in order to balance the impedance between the fan-out lines, so that the impedance difference of each fan-out line is reduced or even equal.
  • the first segment 210 and the third segment 230 of the intermediate fan-out line 200 are the same double-conducting layer structure, and the intermediate fan-out line 200 includes: a first metal conductive film 410, an insulating layer 420, a second metal conductive film 430 and a passivation film 440.
  • the main working layer of the intermediate fan-out line 200 is a metal conductive film, that is, the first metal conductive film 410 and the second metal conductive film 430;
  • the film can be made of other conductive materials such as molybdenum, aluminum, and copper.
  • the second segment 220 is made of an indium tin oxide conductive film.
  • the resistivity of the indium tin oxide material is greater than the resistivity of the metal conductive film.
  • the length of the second segment of the shorter fan-out line is greater than the length of the second segment of the longer fan-out line.
  • the second segment is not set for the longest fan-out line on the left and right sides.
  • the intermediate fanout line needs to be adjusted according to the actual impedance of the left fanout line 100 and the right fanout line 300.
  • the length of the second segment 220 of 200 is such that the difference in impedance between the left fan-out line 100 and the right fan-out line 300 on both sides is minimized or even equal.
  • the first segment 210 and the second segment 220 are connected, the first metal conductive film 410 and the second metal conductive film 430.
  • the exposed portions 411 and 431 are respectively disposed, and the indium tin oxide conductive film 450 covers the exposed portions 411 and 431.
  • the indium tin oxide conductive film 450 is formed at the break of the first segment 210 and the third segment 230. Second segment 220.
  • the structure of the third segment 230 is the same as that of the first segment 210, and includes a first metal conductive film 410 and insulation disposed on the array substrate.
  • its electrical connection with the second segment 220 is also the same as for the first segment 210. According to the existing process, it is only necessary to divide the fan-out line, and the second section can be set at the partition, and the process can be single, and the impedance of the fan-out line can be adjusted only by adjusting the length of the partition.
  • the embodiment further provides an array substrate, which includes: a glass substrate 10, wherein the glass substrate 10 is provided with a plurality of signal lines 13 and a plurality of fans.
  • the outlet 11 and the solder fillet 12 are disposed on the fan-out line arrangement area 14 of the glass substrate 10, and the arrangement of the fan-out line 11 is arranged in the above-described configuration.
  • FIG. 9 Another embodiment provided by the technical solution according to the present invention is shown in FIG. 9.
  • the difference between this embodiment and the first embodiment is that only two segments are set in the intermediate fanout line 200 of the embodiment: 210 and a second segment 220, the first segment 210 adopts a metal conductive film structure, and the second segment 220 adopts an indium tin oxide conductive film structure.
  • the lengths of the first segment 210 and the second segment 220 are set according to the impedances of the left fanout line 100 and the right fanout line 300, by adjusting the length ratio between the first segment 210 and the second segment 220.
  • the impedance difference between the left fan outlet line 100 and the right fan outlet line 300 can be reduced or even equal.
  • the segmentation of the fan-out line in the present invention is not limited to two ends or three segments, and those skilled in the art can easily associate with the method of using more segments under the concept of the present invention;
  • the material usage between the segments is not limited to the metal conductive film and the indium tin oxide conductive film, and it is easy for those skilled in the art to associate other alternative materials. Therefore, it will be apparent to those skilled in the art that the present invention can be deduced or replaced without departing from the inventive concept. The scope of protection.

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Abstract

一种阵列基板及其扇出线结构，所述扇出线用于连接信号线以及焊脚，包括：多条布置在阵列基板扇出区的扇出线，所述扇出线具有多个不同的长度；至少一条扇出线包括有第一分段以及第二分段，所述第二分段的材料电阻率大于所述第一分段的电阻率，所述长度较短的扇出线的第二分段的长度大于长度较长的扇出线的第二分段的长度。

Description

阵列基板及其扇出线结构
【技术领域】
本发明涉及液晶显示领域， 更具体的说， 涉及一种阵列基板及其扇出线结 构。 【背景技术】
液晶面板是液晶显示装置的重要组件， 在背光模组的配合以及驱动电路的 驱动下下， 液晶面板能够显示出图像。
液晶面板包括阵列基板以及彩膜基板， 如图 1所示， 在液晶面板 1上设置 有 TFT阵列区域 2, TFT阵列区域内布满了信号线以及 TFT以及， 驱动电路板 3通过扇出线 4 ( fanout line )将阵列基板的信号线与驱动电路板的焊脚连接， 而 扇出线 4的设置区域则称为扇出区 （ fanout area )。
由于焊脚紧密排列而信号线分散排列， 也就是说焊脚到信号线的距离各不 相同， 这样就造成了阻抗不均的情况， 从而会影响业绩显示装置的显示质量。 如图 2所示， 目前常规的阵列基板扇出区线阻抗均一化都是通过绕线设计完成， 扇出线的架构如图 3所示， 包括： 第一金属层 410、绝缘层 420、第二金属层 430 以及钝化层， 主要 work layer (工作层） 为 metal AL (金属层）， 由于中间的焊 脚到信号线的距离最短， 为了达到与两侧扇出线的阻抗差异最小而保证良好的 显示品质， 扇出区设计往往会尽量增加中间区域扇出线的绕线长度而降低扇出 区中间区域的线与两侧的扇出线的阻抗差异， 这样就导致扇出区高度增加 （绕 线长度增加需要增加用于绕线的区域）。
如图 2所示， 以中间的最短距离以及两侧最长距离的需要布置的扇出线线 为例， 扇出区中间的中间扇出线 200通过绕线增加长度进行增加阻抗， 使其与 两侧的左侧扇出线 100、右侧扇出线 300阻抗差异变小， 扇出线 100由于处于最 中间， 其绕线的长度也最长， 这样就增加了最中间的高度。 在玻璃基板大小一 定的情况， 扇出区高度增加， 对阵列基板设计排版是一种限制， 也影响产品技 术开发， 例如： 窄边框设计， 扇出区高度的增加无疑是减小了液晶显示面板的 显示区域， 反过来则增大了液晶显示装置的边框宽度。
虽然目前也可以通过增加驱动 IC的数量来减小扇出线的绕线长度进而减小 扇出区的高度， 实现窄边框设计， 但这样却增加了液晶显示装置的生产成本， 不利于成本控制。
【发明内容】
本发明所要解决的技术问题是提供一种减小扇出线阻抗差异、 且扇出区高 度小的阵列基板及显示面板； 本发明所提供的阵列基板以及显示面板同时可以 更进一步减小液晶显示装置的边框， 使得液晶显示装置的边框变得更窄。
本发明的目的是通过以下技术方案来实现的： 一种阵列基板的扇出线结构， 所述扇出线用于连接信号线以及焊脚， 包括： 多条布置在阵列基板扇出区的扇 出线， 所述扇出线具有多个不同的长度； 至少一条扇出线包括有第一分段以及 第二分段， 所述第二分段的材料电阻率大于所述第一分段的电阻率， 所述长度 较短的扇出线的第二分段的长度大于长度较长的扇出线的第二分段的长度。
优选的， 所述各长度不同扇出线的第一分段与第二分段的长度各不相同， 所述各扇出线的阻值相等。 长度较短的扇出线的第二分段的长度大于长度较长 的扇出线的第二分段， 从而使得长度不同的两条扇出线之间阻抗差异减小甚至 相同。
优选的， 所述第一分段为布置在所述阵列基板上的金属导电薄膜， 所述第 二分段为氧化铟锡导电薄膜。 两个分段分别使用不同的导电材料， 并且两个分 段的导电材料的电阻率不同， 从而可以调节两个分段的长度以使得该扇出线的 阻抗与其它扇出线的阻抗差异减小。
优选的， 所述第一分段是双导电层结构， 为依次布置在所述阵列基板上的 第一金属导电膜、 绝缘层以及第二金属导电膜； 所述第二分段为氧化铟锡导电 薄膜。 双层金属导电膜可以有效的保证扇出线的稳定工作。 优选的， 所述第一分段与所述第二分段的连接处， 所述第一金属导电膜以 及所述第二金属导电膜设置有棵露部， 所述氧化铟锡导电膜覆盖所述棵露部。 通过设置棵露部， 并在氧化铟锡制作工艺中使其覆盖于棵露部上， 使得两个分 段之间的接触面积增大， 从而提高两个分段之间的电连接稳定性。
优选的，， 所述扇出线还包括第三分段， 所述第三分段也是双导电层结构， 所述第三分段包括依次布置在所述阵列基板上的第一金属导电膜、 绝缘层以及 第二金属导电膜， 所述扇出线的阻抗大小根据所述第二分段的长短进行调整， 所述较短的扇出线的第二分段的长度大于较长的扇出线的第二分段的长度。 按 照现有工艺， 只需在扇出线中间隔断， 在隔断处设置第二分段即可， 工艺筒单， 而调整扇出线的阻抗只需调整隔断处的长度即可。
一种阵列基板， 包括： 玻璃基板， 所述玻璃基板上设置有多条信号线、 多 条扇出线以及焊脚， 所述扇出线设置在所述玻璃基板的扇出线布置区域， 所述 扇出线将所述信号线与所述焊脚进行连接； 所述多条扇出线具有多个不同的长 度； 至少一条扇出线包括有第一分段以及第二分段， 所述第二分段的材料电阻 率大于所述第一分段的电阻率， 所述长度较短的扇出线的第二分段的长度大于 长度较长的扇出线的第二分段的长度。
优选的， 所述各长度不同扇出线的第一分段与第二分段的长度各不相同， 所述各扇出线的阻值相等。 长度较短的扇出线的第二分段的长度大于长度较长 的扇出线的第二分段， 从而使得长度不同的两条扇出线之间阻抗差异减小甚至 相同。
优选的，， 所述第一分段为布置在所述阵列基板上的金属导电薄膜， 所述第 一分段是双导电层结构， 为依次布置在所述阵列基板上的第一金属导电膜、 绝 缘层以及第二金属导电膜； 所述第二分段为氧化铟锡导电薄膜； 所述第一分段 与所述第二分段的连接处， 所述第一金属导电膜以及所述第二金属导电膜设置 有棵露部， 所述氧化铟锡导电膜覆盖所述棵露部。 两个分段分别使用不同的导 电材料， 并且两个分段的导电材料的电阻率不同， 从而可以调节两个分段的长 度以使得该扇出线的阻抗与其它扇出线的阻抗差异减小； 双层金属导电膜可以 有效的保证扇出线的稳定工作； 通过设置棵露部， 并在氧化铟锡制作工艺中使 其覆盖于棵露部上， 使得两个分段之间的接触面积增大， 从而提高两个分段之 间的电连接稳定性。
优选的， 所述扇出线还包括第三分段， 所述第三分段也是双导电层结构， 所述第三分段包括依次布置在所述阵列基板上的第一金属导电膜、 绝缘层以及 第二金属导电膜， 所述扇出线的阻抗大小根据所述第二分段的长短进行调整， 所述较短的扇出线的第二分段的长度大于较长的扇出线的第二分段的长度。 按 照现有工艺， 只需在扇出线中间隔断， 在隔断处设置第二分段即可， 工艺筒单， 而调整扇出线的阻抗只需调整隔断处的长度即可。
本发明由于阵列基板扇出区的至少一条扇出线包括有第一分段以及第二分 段， 而所述第二分段的材料电阻率大于所述第一分段的电阻率， 所述扇出线的 第一分段以及第二分段的长度根据该扇出线与其它扇出线的阻抗设置， 通过调 整所述第一分段以及所述第二分段的长度使较短的扇出线的第二分段的长度大 于较长的扇出线的第二分段的长度， 这样就使得长度较短的扇出线与长度较长 的扇出线的阻抗差异减小。 这样， 在不需要绕线的情况下， 即可达到了各扇出 线之间阻抗减小的效果， 同时， 由于不需要绕线， 中间区域的扇出线铺设宽度 一定的情况下其铺设面积就相应的减小， 扇出区的高度也相应的降了下来， 有 利于增大液晶面板的显示区域而减小非显示区域的宽度， 在不需要增加 IC数量 即可以更进一步减小液晶显示装置的边框， 使得液晶显示装置的边框变得更窄， 同时还降低了液晶显示装置的生产成本（ IC数量不增加 )。
【附图说明】
图 1是现有液晶面板的结构筒图，
图 2是现有液晶面板的扇出区的扇出线布置示意图，
图 3是图 2中 D-D剖面图， 图 4是本发明实施例一的液晶面板扇出线布置示意图，
图 5是图 4中 A-A剖面图，
图 6是图 4中 B-B剖面图，
图 7是图 4中 C-C剖面图，
图 8是本发明实施例一的阵列基板（局部） 的结构示意图，
图 9是本发明实施例二的液晶面板扇出线布置示意图。
【具体实施方式】
下面结合附图和较佳的实施例对本发明作进一步说明。
实施例一
如图 4所示为本发明一种阵列基板的扇出线结构的具体实施例， 所述扇出线 用于连接信号线以及焊脚， 包括： 多条布置在阵列基板扇出区的扇出线， 所述 多条扇出线的具有多个不同的长度等级； 至少一条扇出线包括有第一分段以及 第二分段， 所述第二分段的材料电阻率大于所述第一分段的电阻率， 所述长度 较短的扇出线的第二分段的长度大于长度较长的扇出线的第二分段的长度， 扇 出线的第一分段以及第二分段的长度根据该扇出线与其它扇出线的阻抗差异设 置， 通过调整所述第一分段以及所述第二分段的长度使较短的扇出线的第二分 段的长度大于较长的扇出线的第二分段的长度， 这样就使得长度较短的扇出线 与长度较长的扇出线的阻抗差异减小， 甚至使两条不同长度的扇出线的阻抗相 等。
为了方便说明， 本实施例以最中间的中间扇出线 200, 以及两侧最长的左侧 扇出线 100、 右侧扇出线 300作为说明， 最中间的中间扇出线 200包括有： 第一 分段 210、 第二分段 220以及第三分段 230, 第一分段 210以及第三分段 230分 别与驱动电路板以及阵列基板上的信号线连接，第一分段 210以及第三分段 230 通过第二分段 220实现电连接。
由于最长的左侧扇出线 100以及右侧扇出线 300的阻抗最大， 因此本实施例 中左侧扇出线 100 以及右侧扇出线 300不需要再设置第二分段， 而对于中间扇 出线 200与左侧扇出线 100以及右侧扇出线 300之间的扇出线， 则还是需要设 置第二分段。 这些扇出线由中间扇出线 100 的位置开始依次向两侧排布， 其长 度依次增大， 其阻抗也增大， 因此， 这些扇出线的第二分段的长度需要设置成 依次减小， 而各扇出线的第一分段与第三分段的长度之和也是保持依次增大， 这样才能平衡各扇出线之间的阻抗， 使各扇出线的阻抗差异减小甚至相等。
如图 5-图 7所示， 中间扇出线 200的第一分段 210以及第三分段 230为相同 的双导电层结构， 中间扇出线 200包括： 第一金属导电膜 410、 绝缘层 420、 第 二金属导电膜 430以及钝化膜 440, 中间扇出线 200的主要工作层（work layer ) 为金属导电薄膜， 即所述第一金属导电膜 410以及第二金属导电膜 430; 所述金 属导电薄膜可选用钼、 铝、 铜等其它导电性能优越的金属材料制作。 所述第二 分段 220采用氧化铟锡导电膜， 氧化铟锡材料的电阻率大于金属导电膜的电阻 率， 这样， 通过调整第二分段 220 的长度， 进而改变整条扇出线的阻抗， 所述 较短的扇出线的第二分段的长度大于较长的扇出线的第二分段的长度， 在本实 施例的说明中， 由于左右两侧的最长扇出线不设置第二分段， 因此， 我们可以 认为左侧扇出线 100、右侧扇出线 300的第二分段的长度为零， 而只要中间扇出 线 200的第二分段 220的长度不为零， 则其与左侧扇出线 100、 右侧扇出线 300 的阻抗差异就会减小， 但本实施例为了达到更优的效果， 需要根据左侧扇出线 100、右侧扇出线 300的实际阻抗来调整中间扇出线 200的第二分段 220的长度， 使其与两侧的左侧扇出线 100、右侧扇出线 300的阻抗差异做到最小，甚至相等。
本实施例中， 如图 5-8中所示， 所述第一分段 210与所述第二分段 220的连 接处， 所述第一金属导电膜 410 以及所述第二金属导电膜 430分别设置有棵露 部 411、 431 , 所述氧化铟锡导电膜 450覆盖所述棵露部 411、 431 ; 氧化铟锡导 电膜 450在第一分段 210以及第三分段 230的断裂处形成第二分段 220。通过设 置棵露部 411、 431 , 同时在氧化铟锡导电膜 450制作工艺中使其覆盖于棵露部 上， 使得两个分段之间的接触面积增大， 从而提高两个分段之间的电连接稳定 性。
本实施例中， 如图 5所示， 所述第三分段 230的结构与所述第一分段 210的 结构相同， 包括依次布置在所述阵列基板上的第一金属导电膜 410、 绝缘层 420 以及第二金属导电膜 430以及设置在第二金属导电膜 430之上的钝化膜 440。同 样的， 其与所述第二分段 220的电连接方式也与所述第一分段 210的相同。 根 据现有工艺， 只需在扇出线中间隔断， 在隔断处设置第二分段即可， 工艺筒单， 而调整扇出线的阻抗只需调整隔断处的长度即可。
根据本实施例提供的扇出线结构， 如图 8所示， 本实施例同时提供一种阵列 基板， 其包括： 玻璃基板 10, 所述玻璃基板 10上设置有多条信号线 13、 多条 扇出线 11以及焊脚 12,所述扇出线 11设置在所述玻璃基板 10的扇出线布置区 域 14, 所述扇出线 11的设置方式按上述的结构进行布置。
实施例二
如图 9所示为根据本发明的技术方案所提供的另一种实施例， 本实施例与 实施例一不同在于， 本实施例的中间扇出线 200仅设置两个分段： 第一分段 210 以及第二分段 220, 所述第一分段 210采用金属导电膜结构， 所述第二分段 220 采用氧化铟锡导电膜结构。 所述第一分段 210以及第二分段 220的长度根据左 侧扇出线 100、右侧扇出线 300的阻抗进行设置， 通过调整第一分段 210以及第 二分段 220之间的长度比例， 可使其与所述左侧扇出线 100、右侧扇出线 300的 阻抗差异缩小甚至相等。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 不能 认定本发明的具体实施只局限于这些说明。 比如， 本发明中的扇出线的分段并 不限于两端或者是三段， 在本发明的构思下， 本领域普通技术人员很容易能够 联想到使用更多分段的方式； 另外， 不同分段之间的材料使用也不仅限于金属 导电膜以及氧化铟锡导电膜， 对于本普通技术人员来说也很容易联想到其它的 替代材料。 因此， 对于本发明所属技术领域的普通技术人员来说， 在不脱离本 发明构思的前提下， 还可以做出若干筒单推演或替换， 都应当视为属于本发明 的保护范围。

Claims

权利要求
1、 一种阵列基板的扇出线结构， 所述扇出线用于连接信号线以及焊脚， 包 括：
多条布置在阵列基板扇出区的扇出线， 所述扇出线具有多个不同的长度； 至少一条扇出线包括有第一分段以及第二分段， 所述第二分段的材料电阻 率大于所述第一分段的电阻率， 所述长度较短的扇出线的第二分段的长度大于 长度较长的扇出线的第二分段的长度。
2、 如权利要求 1所述的扇出线结构， 其中， 所述各长度不同的扇出线的第 一分段与第二分段的长度各不相同， 所述各扇出线的阻值相等。
3、 如权利要求 1所述的扇出线结构， 其中， 所述第一分段为布置在所述阵 列基板上的金属导电薄膜， 所述第二分段为氧化铟锡导电薄膜。
4、如权利要求 1所述的扇出线结构，其中，所述第一分段是双导电层结构， 为依次布置在所述阵列基板上的第一金属导电膜、 绝缘层以及第二金属导电膜； 所述第二分段为氧化铟锡导电薄膜。
5、 如权利要求 4所述的扇出线结构， 其中， 在所述第一分段与所述第二分 段的连接处， 所述第一金属导电膜以及所述第二金属导电膜设置有棵露部， 所 述氧化铟锡导电膜覆盖所述棵露部。
6、 如权利要求 4所述的扇出线结构， 其中， 所述扇出线还包括第三分段， 所述第三分段也是双导电层结构， 所述第三分段包括依次布置在所述阵列基板 上的第一金属导电膜、 绝缘层以及第二金属导电膜， 所述扇出线的阻抗大小根 据所述第二分段的长短进行调整， 所述较短的扇出线的第二分段的长度大于较 长的扇出线的第二分段的长度。
7、 一种阵列基板， 包括：
玻璃基板， 所述玻璃基板上设置有多条信号线、 多条扇出线以及焊脚， 所 述扇出线设置在所述玻璃基板的扇出线布置区域， 所述扇出线将所述信号线与 所述焊脚进行连接；
所述多条扇出线具有多个不同的长度； 至少一条扇出线包括有第一分段以 及第二分段， 所述第二分段的材料电阻率大于所述第一分段的电阻率， 所述长 度较短的扇出线的第二分段的长度大于长度较长的扇出线的第二分段的长度。
8、 如权利要求 7所述的阵列基板， 其中， 所述各长度不同扇出线的第一分 段与第二分段的长度各不相同， 所述各扇出线的阻值相等。
9、 如权利要求 7所述的阵列基板， 其中， 所述第一分段为布置在所述阵列 基板上的金属导电薄膜， 所述第一分段是双导电层结构， 为依次布置在所述阵 列基板上的第一金属导电膜、 绝缘层以及第二金属导电膜； 所述第二分段为氧 化铟锡导电薄膜； 所述第一分段与所述第二分段的连接处， 所述第一金属导电 膜以及所述第二金属导电膜设置有棵露部， 所述氧化铟锡导电膜覆盖所述棵露 部。
10、 如权利要求 9所述的阵列基板， 其中， 所述扇出线还包括第三分段， 所述第三分段也是双导电层结构， 所述第三分段包括依次布置在所述阵列基板 上的第一金属导电膜、 绝缘层以及第二金属导电膜， 所述扇出线的阻抗大小根 据所述第二分段的长短进行调整， 所述较短的扇出线的第二分段的长度大于较 长的扇出线的第二分段的长度。
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