WO2014137283A1

WO2014137283A1 - Method of fabricating a solar cell

Info

Publication number: WO2014137283A1
Application number: PCT/SG2013/000088
Authority: WO
Inventors: Thomas Mueller; Ankit Khanna; Johnson WONG; Anahita KARPOUR; Fei Zheng; Armin Gerhard Aberle
Original assignee: Trina Solar Energy Development Pte Ltd
Priority date: 2013-03-05
Filing date: 2013-03-05
Publication date: 2014-09-12

Abstract

According to one aspect, there is provided a method of fabricating a solar cell comprising: performing metallisation over a patterned passivation layer that provides access to predetermined material in trenches in a surface of a wafer, wherein metal contacts are formed within the trenches in the surface of the wafer in response to the predetermined material.

Description

Method of fabricating a solar cell

FIELD OF INVENTION The invention relates to a method of fabricating a solar cell.

BACKGROUND

All-back-contact (ABC) silicon wafer solar cells have the potential of achieving high energy conversion efficiency with a cost-effective and industrially feasible fabrication process. The cells are sometimes referred to as interdigitated-back- contact (IBC) cells, because of the interpenetrating contacts (metal fingers) of opposite polarity on the rear of the cell. ABC cells have several advantages over conventional silicon wafer solar cells, which have contacts on both surfaces (whereby the front contact is a metal grid consisting of parallel fingers and several busbars connecting the metal fingers). The advantages of ABC cells include improved photo- generation of carriers due to the elimination of the optical front-metal grid shading and improved blue response since heav front-surface doping to reduce the front contact resistance is not required due to the shifting of the front contacts to the rear of the cell. In addition, ABC cells have a uniform and thus more favourable appearance in modules, due to the absence of the front metal grid on the front surface.

Wafers with high carrier lifetime and good front surface passivation are typically required for ABC solar cells, because photo-generated carriers must all travel to the rear surface where the charge-separating p-n junction is located. As a result, n-type wafers are typically used for ABC solar cells due to their higher carrier lifetime compared to p-type wafers. ABC silicon wafer solar cell architectures have the potential for conversion efficiencies of well over 24% due to the high-lifetime wafers, eliminated optical shading at the front, improved blue response and lower surface recombination rates by good surface passivation possibilities. However, current fabrication methods and cost considerations have prevented the ABC cell from being cost-effective for application in conventional low-cost industrial solar cell manufacturing lines. The main issues during the manufacture are the patterning of the rear side to establish the interdigitated p-doped and n-doped regions including the use of photoresist or printed resist, resist processing, mask alignments, and the use of metal deposition providing a low contact resistance, such as evaporation (thermal or electron-beam) or sputtering. As these processes mainly originate from the semiconductor industry, the processing must typically be carried out in a cleanroom environment.

Industrial silicon wafer solar cells (area > 100 cm²) typically favour the use of screen-printed metallisation processes for contact formation, since this is a low-cost and high-throughput process. However, high-efficiency ABC cells with screen-printed metal contacts for both polarities require good alignment between the interdigitated diffused silicon regions and the printed metal contacts. In addition to alignment requirements, the moderate conductivity of screen-printed metal contacts to n+ regions can be efficiency limiting when a low area ratio of the rear n+/p+ region needs to be implemented.

A need therefore exists to have a solar cell fabrication method that addresses problems associated with mask alignment, reduces production costs of industrial all- back-contact solar cells and provides high conductivity metal contacts. SUMMARY

BRIEF DESCRIPTION OF THE DRAWINGS Example embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention, in which:

Figure 1 shows a flowchart that illustrates a method to fabricate a solar cell according to one embodiment.

Figures 2A to 2B illustrate a first process to fabricate a solar cell in accordance with a method that follows the flowchart of Figure 1.

Figures 3A to 3G illustrate a second process to fabricate a solar cell in accordance with a method that follows the flowchart of Figure 1.

DEFINITIONS The following provides sample, but not exhaustive, definitions for expressions used throughout various embodiments disclosed herein.

The term "patterned passivation layer" may refer to an initial passivation layer that has portions removed so that there are openings that allow access to a surface with which the initial passivation layer is in contact or covers.

The term "passivation layer" may mean a layer made from materials such as silicon nitride, silicon dioxide, titanium dioxide, aluminium oxide, amorphous silicon or amorphous silicon alloys that can reduce surface recombination, which leads to losses in solar cells.

The term "access" may mean that portions of a wafer are exposed through openings in the patterned passivation layer that covers the remainder of the surface of the wafer on which the patterned passivation layer is formed.

The term "predetermined material" may mean material used to form walls of the trenches and in several embodiments, may be the material used to fabricate a wafer.

The term "trenches" may mean openings in the wafer having a depth that is confined within the thickness of the wafer.

The term "metal contacts" may mean the by-product after metallisation is performed and may mean a volume of metal formed after metallisation. In various embodiments, this volume of metal may provide a seed to further growth the metal contacts, where the metal contacts provide a means for electrical communication with the wafer.

The term "in response" may mean that the predetermined material has a composition that allows the metal contacts to form thereon.

DETAILED DESCRIPTION

Metallisation of ABC (all-back-contact) cells is a challenging fabrication step because good alignment is necessary between interdigitated doped regions and deposited metal. Herein disclosed are fabrication methods that simplify the metallisation step for ABC cells by making self-aligned plated contacts to a rear n+ region. A high area ratio for the rear p+/n+ regions additionally ensures that the alignment requirement for the metal contacts to the p+ region is relaxed and can be easily met by screen printing. Plated contacts are used as they are capable of providing a higher conductivity n+ electrode than can be achieved by screen printing. Metal recombination at the n+ region is also minimised since the metal only contacts the n+ region in narrow laser openings and are thickened outside the neck of the laser opening to provide excellent conductivity.

In the following description, various embodiments are described with reference to the drawings, where like reference characters generally refer to the same parts throughout the different views.

Various embodiments provide for fabricating a solar cell having a set of electrodes that are self-aligned and formed without any mask, eliminating alignment errors that may arise from using a mask.

Figure 1 shows a flowchart 100 that illustrates a method to fabricate a solar cell (not shown) according to one embodiment.

In step 102, metallisation is performed over a patterned passivation layer that provides access to predetermined material in trenches in a surface of a wafer. Reference numeral 104 is used to denote that metal contacts are formed within the trenches in the surface of the wafer in response to the predetermined material. Although not shown, the metal contacts may be formed only within the trenches during this metallisation.

As the patterned passivation layer is fabricated from dielectric material, such as silicon nitride, silicon dioxide or titanium dioxide, the regions of the patterned passivation layer, other than the trenches, are unresponsive to metallisation that is performed over it, i.e. metal contacts do not form on regions of the patterned passivation layer other than trenches. Regions of the patterned passivation layer other than the trenches are unresponsive to any metalisation technique which does not first open the patterned passivation layer. Examples of metallisation techniques which will not form metal contacts on the patterned passivation layer include: screen printing using metal pastes without glass-frit additives, sputtering, thermal evaporation, electron-beam evaporation, electrolytic plating and light-induced plating. During metallisation, metal contacts only form on the responsive portions, i.e. the exposed predetermined material of the trenches which has a composition that allows the metal contacts to form thereon.

Figures 2A to 2B illustrate a first process to fabricate a solar cell in accordance with a method that follows the flowchart 100 of Figure 1.

In Figure 2A, a wafer 200 is provided, having a surface 202 (interchangeably referred to as the rear surface) and an opposite surface 204 (interchangeably referred to as the front surface). In the embodiment shown in Figure 2A, a patterned passivation layer 206 is in contact with the surface 202 of the wafer 200. However, it will also be appreciated that one or more layers (not shown) may be between the surface 202 and the patterned passivation layer 206. The patterned passivation layer 206 provides access to predetermined material in trenches 208 in the surface 202 of the wafer 200.

In Figure 2B, metallisation is performed over the patterned passivation layer 206 to form metal contacts 210 within the trenches 208 in the surface 202 of the wafer 200 in response to the predetermined material.

The formation of the metal contacts 210 is performed without any mask. The omission of a mask eliminates alignment issues associated with using a mask in semiconductor fabrication. As the predetermined material is responsive to metallisation, the metal contacts 210 are self aligned by the exposed surfaces provided by the trench 208 walls.

The predetermined material may be material used for the wafer 200, such as monocrystalline silicon, polycrystalline silicon, cadmium telluride or copper indium gallium selenide. The metal contacts 210 may be formed by electroless nickel plating, where the wafer 200 is dipped into a suitable solution to form the metal contacts 210 in the trenches 208.

Figures 3A to 3G illustrate a second process to fabricate a solar cell in accordance with a method that follows the flowchart 100 of Figure 1.

The second process is a method to manufacture an all-back-contact (ABC) silicon wafer solar cell with self-aligned plated metal contacts to the rear n+ region, which may be summarised as follows. The structure of the ABC cell has a rear p+ doped silicon region, with a single dielectric film or a stack of dielectric films for surface passivation. A laser ablation step and a subsequent wet-chemical etching process defines openings on less than 10% of the total area of the p+ region. In a later process step, an n+ doped region (back-surface-field, BSF) is formed in the laser-formed openings. The n+ doped region facilitates a self-aligned contacting method using plating. Further detail on the second process is provided below.

Figure 3A shows a cross-sectional view of a wafer 300 fabricated from predetermined material. In one embodiment, silicon may be used for the wafer 300, although other materials such as germanium or a compound like gallium arsenide may be used. Other materials that may be used include monocrystalline silicon, polycrystalline silicon, cadmium telluride or copper indium gallium selenide.

The wafer 300 has a surface 302 (interchangeably referred to as the rear surface) and an opposite surface 304 (interchangeably referred to as the front surface). The wafer 300 is textured on the front surface 304. A caustic etch (KOH, NaOH, TMAH or similar) may be used to texture the front surface 304 of the wafer 300 by using the rear surface 302 as a texturing-stop-layer. In a preferred embodiment, the front surface 304 of the wafer 300 is modified for anti-reflectivity, by texturing the front surface 304 to be uneven. The front surface 304 may be made uneven by having the wafer 300 comprise a monocrystalline structure having an orientation aligned to form protrusions on the opposite surface 304, such as using monocrystalline wafers of orientation <100>, leading to the formation of upright pyramids with <111> oriented sidewalls. The typical height of the pyramids is in the range of 1-10 pm. The texture reduces reflection losses at the front surface 304, thereby potentially improving the efficiency of the solar cell 350 (see Figure 3G) by raising the short-circuit current density.

The rear surface 302 is doped with dopant of a first polarity, which in one embodiment may be a full-area p+ surface layer at the rear. The p+ layer can be formed by known methods such as thermal diffusion, ion implantation or chemical vapour deposition (CVD). In the preferred embodiment, thermal diffusion is utilized. Example surface concentrations of majority carriers for these regions are ~10¹⁹- 10²⁰ cm^'3 (p+ region), and 0¹⁵ cm^"3 (wafer).

Figure 3B shows the same wafer 300 as in Figure 3A after surface passivation of the front surface 304 and rear surface 302 by a single layer dielectric film or a stack of dielectric films. During surface passivation, a passivation layer 305 is formed on the surface 302 of the wafer 300, while another passivation layer 312 is formed on the opposite surface 304 of the wafer 300. These passivation layers 305 and 312 can be plasma grown silicon oxide, thermal oxide, aluminium oxide, silicon nitride, amorphous silicon or amorphous silicon alloys. Other methods where these materials are used to form the passivation layers 305 and 312 include LPCVD (low-pressure chemical vapour deposition) or sputtering. In one embodiment, the passivation layers 305 and 312 are separately formed or simultaneously formed, wherein the latter has the advantage of fabricating both layers in a single step, as opposed to two fabrication steps.

Figure 3C shows the same wafer 300 as in Figure 3B after laser ablation of the passivation layer 305 to form a patterned passivation layer 306 for later n+ layer formation. Thus, the patterned passivation layer 306 is derived using laser ablation.

The laser ablation forms trenches 307 in the surface 302 of the wafer 300, where the patterned passivation layer 306 provides access to the predetermined material in the trenches 307.

The laser ablation is followed by a subsequent wet-chemical etch using a caustic etch (KOH, NaOH, or similar) to remove the p+/n+ junction and laser damage. This further etches the trenches 307 to form deeper trenches 308 (refer to Figure 3D). The trenches 308 are then doped with dopant of second polarity that is opposite to the dopant of the first polarity used on the surface 302. With the surface 302 being p-type doped, the trenches are n-type doped. The n+ profile overcompensates the p+ profile at the corners of the trenches 308 ('butting junction') opened by the laser ablation, so that when the trenches 308 are plated (see Figure 3E), no shunting of the n+ and p+ regions occurs. Figure 3D shows the wafer 300 after the n+ formation step. The n+ doped trenches 308 can be formed by known methods such as thermal diffusion, ion implantation or chemical vapour deposition (CVD). In the preferred embodiment, thermal diffusion is utilised. The dielectric stacks provided by the passivation layer 312 and the patterned passivation layer 306 at the front surface 304 and the rear surface 302 respectively act as local barriers for the dopant atoms. Figure 3E shows the same wafer 300 as in Figure 3D after metallisation is performed over the patterned passivation layer 306 that provides access to the predetermined material in the trenches 308 in the surface 302 of the wafer 300. Metal contacts 310 are formed within the trenches 302 in the surface 302 of the wafer in response to the predetermined material. As shown in Figure 3E, the preferred embodiment has the metal contacts 310 formed only within the trenches 302. In one embodiment where metallisation is performed using electroless plating, such as electroless nickel plating, a nickel layer is deposited directly onto the n+ doped regions of the trenches 308 opened by the laser ablation described above. The nickel plates only on the exposed n+ regions, making the metallisation process inherently self-aligned. Due to the self-aligned nature of the plating step, alignment requirements for metallisation of the n+ region are eliminated. The patterned passivation layer 306 is unresponsive to metallisation that is performed over it, i.e. metal contacts do not form on the patterned passivation layer 306. The metal layer contacts 310 formed by this step serves as a seed layer contact which is thickened in a subsequent step (see Figure 3G). Other materials that can be used for the seed layer contact include any one or more of the following: palladium or silver. Figure 3F shows the same wafer as in Figure 3E, wherein electrodes 314 (although only one is shown) is provided in contact with the surface 302 of the wafer 300. The electrodes 314 are obtained after screen-printing of a metal paste onto the patterned passivation layer 306 and subsequently fired to penetrate the patterned passivation layer 306 and make contact with the surface 302 of the wafer 300 to contact the p+ region provided at the surface 302. The metal pastes used may be fritted glass-metal pastes and typical firing temperatures are around 550-800 °C. During the firing, the glass frit additives open the patterned passivation layer 306, allowing a metal contact to be formed. The screen-printing requires an alignment accuracy of less than 500 μιη due to the high area ratio of the rear p+/n+ doped regions (i.e. the ratio of the area provided by the p+ doped surface 302 to that of the n+ doped trenches 302). The drying step of the paste after printing or the firing step can serve as a silicidation anneal for the nickel deposition in the previous step described in Figure 3E. Nickel silicides are expected to be stable during the firing process and are known to provide a low resistance contact to silicon.

Figure 3G shows the same wafer as in Figure 3F. The metal contacts 310 to the n+ region of the trenches 308 are developed to protrude from the patterned passivation layer 306 and spread over a region 318 of the patterned passivation layer 306 surface that is adjacent to the access to the trenches 308. In one embodiment, the metal contacts 310 are thickened by plating on top of the nickel seed layer contact deposited in Figure 3E. The plating process used in this step may be light-induced plating (LIP) for developing the metal contacts 310 to protrude from the patterned passivation layer 306. LIP uses the solar cell photovoltaic effect to provide a negative potential at the n+ doped rear region of the trenches 308. Consequently only the metal seed contact to the n+ region is plated in this step. The material used for developing the metal contacts 310 to form developed metal contacts 316 may be different from the material used for the metal contacts 310. The metal plated in this step may be silver or copper. If copper is used the earlier nickel plated layer also provides a diffusion barrier to prevent copper diffusion into the silicon wafer 300. The plated metal contacts 302 to the n+ region is grown thicker (i.e., wider) outside the narrower neck structure of the trenches 308 opened by laser ablation, leading to a mushroom-shaped contact which provides high conductivity while minimising metal recombination losses. Thus, the developed metal contacts 316 may be fabricated entirely of self-aligned low-cost metals like nickel and copper, compared to screen printing the n+ doped region using expensive silver pastes.

Typically, when using screen-printed metal contacts to realise a low metal contact area ratio on a rear n+/p+ region, this leads to moderate conductivity of n+ regions, which can be efficiency limiting, along with screen-printing alignment requirements. Comparing the electrodes 3 4 to the developed metal contacts 316, a surface area of the electrodes 314 is larger than a surface area of the developed metal contacts 316. However, the developed metal contacts 316 are formed by plating, which produces metal contacts of higher conductivity than those created by screen printing. Thus, the developed metal contacts 316 enable implementation of a low area ratio of the rear n+/p+ regions (e.g. 5/95). The alignment requirements for the screen printed p+ metal contact (i.e the electrodes 314) are also relaxed because of the high area ratio of the rear p+/n+ regions (e.g. 95/5). Thus from Figures 3A to 3G, a method of fabricating a solar cell 350 includes providing a wafer 300 having a rear surface 302 being doped with dopant of a first polarity and a front surface 304 that is opposite to the rear surface 302. A first passivation layer 312 is formed that is in contact with the front surface 304 of the wafer 300. A second passivation layer 305 is formed that is in contact with the back surface 302 of the wafer 300, wherein the second passivation layer 305 is patterned to form a patterned passivation layer 306. Trenches 307 in the rear surface 302 of the wafer that result after forming the patterned passivation layer 306 are further etched and then doped with dopant of second polarity that is opposite to the dopant of the first polarity. Metallisation is performed over the patterned passivation layer 306 wherein metal contact 310 is formed within the trenches 308 in the rear surface 302 of the wafer 300, in response to the predetermined material in the trenches 308. The metal contacts 310 can be further developed to protrude from the patterned passivation layer 306 and spread over a region of the patterned passivation layer 306 surface that is adjacent to the access to the trenches 308. In one embodiment, metallisation is such that the metal contacts 310 are formed only within the trenches 308.

From the above, the preferred embodiment uses p-type dopant as dopant of the first polarity to form a first doped region on the surface 302 of the wafer 300 and n-type dopant as dopant of the second polarity to form a second doped region in the trenches 308. However, in another embodiment, the dopant of the first polarity to form the first doped region is n-type; while the dopant of the second polarity to form the second doped region is p-type.

The following describes other modifications to the preferred embodiment to realise the solar cell.

Modified embodiment 1

The n+ or p+ doped silicon regions may be formed by either thermal diffusion, ion implantation, or chemical vapour deposition (CVD), or any combination of those.

Modified embodiment 2

The cell may additionally have an n⁺ doped silicon region at the front ('front surface field', FSF). Such a cell may follow the fabrication steps shown in Figures 3A to 3D with the modification that a passivation layer 312 is not formed during the step shown in Figure 3B, but at a later step. In Figure 3D of fabricating this embodiment, there will be a wafer with a surface (compare rear surface 302) having trenches (compare trenches 308) that are accessible by a patterned passivation layer (compare patterned passivation layer 306) on the surface, where the surface of the wafer is doped with dopant of a first polarity (as per the rear surface 302 of the wafer 300 shown in Figure 3A). However, the wafer of this embodiment will not have the passivation layer 312 shown in Figure 3D. An opposite surface of the wafer (i.e. the front surface 304 of the wafer 300, when referring to Figure 3D) may be doped with dopant of second polarity that is opposite to dopant of the first polarity. In this embodiment, the trenches can be doped simultaneously with the opposite surface of the wafer, so that the trenches are also doped with dopant of the second polarity. This has the advantage of forming the BSF (back surface field) and the FSF in one process, instead of two separate processes. With the dopant of the second polarity being of n-type, the rear surface is provided with a n+ layer that forms the back- surface-field (BSF), which reduces the recombination losses in the solar cell and the contact resistance losses at the base contact; at the front side, the front-surface-field (FSF) is created to repel minority charge carriers and reduce lateral resistivity. Another passivation layer can then be formed on the opposite surface of the wafer.

Modified embodiment 3

The dielectric surface passivation layers (or stacks) may include dielectrics other than the materials stated earlier (silicon oxide, aluminium oxide, silicon nitride, amorphous silicon or amorphous silicon alloys) or other growth techniques (thermal oxide, sputtering, CVD, etc.).

Modified embodiment 4

The openings in the rear surface dielectric may be achieved by chemical etching or other alternative techniques to laser ablation.

Modified embodiment 5

The area ratio of the rear n7p⁺ regions may be varied.

Modified embodiment 6

The nickel plating step may be followed by an additional annealing step for silicidation (e.g. rapid thermal annealing, laser annealing etc), instead of using the drying and firing step after screen printing as the silicidation anneal.

Modified embodiment 7

The silver or copper may be deposited on top of the nickel layer by using alternative techniques to light-induced plating (e.g. electroplating or light-induced electroless plating).

Modified embodiment 8

Cu plated layers may be capped with a thin metal layer (e.g. silver, tin etc) to provide a corrosion resistant layer or to improve solderability.

The above describes various methods for fabricating an all-back-contact

(ABC) silicon wafer solar cells with self-aligned metal contacts to rear n+ silicon regions. Dielectric passivation layers are applied to the front and rear surfaces of a silicon wafer with a rear p+ surface layer. Laser ablation is used to locally open the rear dielectric, followed by a process step to form the rear n+ regions. In the preferred embodiment, the n+ and p+ doped silicon regions are formed by thermal diffusion. Metal contacts to the rear p+ regions are formed by screen printing of a metal paste and firing of the paste through the rear dielectric. Metal contacts to the rear n+ regions are formed by a plating step which self-aligns to the exposed n+ doped surfaces in the laser-formed openings. No shunting of the n+ and p+ regions occurs during the plating step since the n+ profile overcompensates the p+ profile at the corners of the laser openings ('butting junction'). The plated contact to the n+ region is grown thicker (i.e., wider) outside the narrower neck structure of the laser opening, leading to a mushroom-like contact which provides high conductivity while minimising metal recombination losses. The conductivity of the metal electrode plated on the n+ region is higher than the electrode conductivity that can be achieved by screen printing. Due to the self-aligned nature of the plating step, alignment requirements for metallisation of the n+ region are eliminated, which enables the implementation of a low area ratio of the rear n+/p+ regions (e.g. 5/95). The alignment requirements for the screen printed p+ metal contact are also relaxed because of the high area ratio of the rear p+/n+ regions (e.g. 95/5).

It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the embodiments without departing from a spirit or scope of the invention as broadly described. The embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive.

Claims

1. A method of fabricating a solar cell comprising:

performing metallisation over a patterned passivation layer that provides access to predetermined material in trenches in a surface of a wafer, wherein metal contacts are formed within the trenches in the surface of the wafer in response to the predetermined material.

2. The method of claim 1 , wherein the metal contacts are formed only within the trenches.

3. The method of claim 1 or 2, wherein the predetermined material comprises monocrystalline silicon, polycrystalline silicon, cadmium telluride or copper indium gallium selenide.

4. The method of any one of the preceding claims, wherein the surface is doped with dopant of a first polarity and wherein the trenches are doped with dopant of second polarity that is opposite to the first polarity.

5. The method of any one of the preceding claims, wherein a passivation layer is formed on an opposite surface of the wafer.

6. The method of claim 5, wherein the passivation layer on the opposite surface of the wafer is formed simultaneously with a passivation layer from which the patterned passivation layer on the surface of the wafer is derived.

7. The method of claim 6, wherein the patterned passivation layer is derived using laser ablation.

8. The method of claims 5 to 7, wherein the opposite surface of the wafer is doped with dopant of second polarity.

9. The method of any one of the preceding claims, wherein the metal contacts are formed by electroless plating.

10. The method of any one of the preceding claims, further comprising developing the metal contacts to protrude from the patterned passivation layer and spread over a region of the patterned passivation layer surface that is adjacent to the access to the trenches.

11. The method of claim 10, wherein light-induced plating is used for developing the metal contacts to protrude from the patterned passivation layer.

12. The method of claim 10 or 11 , wherein a different material is used for developing the metal contacts.

13. The method of claims 10 to 12, wherein the material used for developing the metal contacts is silver or copper.

14. The method of any one of the preceding claims, wherein any one or more of the following is used for the metal contacts: nickel, palladium or silver.

15. The method of claims 10 to 14, further comprising providing electrodes in contact with the surface of the wafer.

16. The method of claim 15, wherein the electrodes are screen printed onto the patterned passivation layer and subsequently fired to penetrate the patterned passivation layer and make contact with the surface of the wafer.

17. The method of claim 15 or 16, wherein a surface area of the electrodes is larger than a surface area of the developed metal contacts that protrude from the patterned passivation layer.

18. The method of claims 4 to 17, wherein the dopant of the first polarity is p- type and the dopant of the second polarity is n-type.

19. The method of claims 4 to 17, wherein the dopant of the first polarity is n- type and the dopant of the second polarity is p-type.