WO2016068711A2 - Back side contacted wafer-based solar cells with in-situ doped crystallized silicon oxide regions - Google Patents

Back side contacted wafer-based solar cells with in-situ doped crystallized silicon oxide regions Download PDF

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WO2016068711A2
WO2016068711A2 PCT/NL2015/050759 NL2015050759W WO2016068711A2 WO 2016068711 A2 WO2016068711 A2 WO 2016068711A2 NL 2015050759 W NL2015050759 W NL 2015050759W WO 2016068711 A2 WO2016068711 A2 WO 2016068711A2
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doped
layer
solar cell
silicon
regions
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WO2016068711A3 (en
WO2016068711A4 (en
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Guangtao YANG
Andrea INGENITO
Olindo ISABELLA
Miroslav Zeman
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Technische Universiteit Delft
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    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H01L31/03682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic System
    • H01L31/03685—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors including only elements of Group IV of the Periodic System including microcrystalline silicon, uc-Si
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
    • H01L31/1824—Special manufacturing methods for microcrystalline Si, uc-Si
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/545—Microcrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention is in the field of a process for making back side contacted wafer-based solar cells with in-situ doped crystallized thin-film silicon oxide regions and optionally in-situ doped silicon regions, and back side contacted solar cells.
  • a solar cell, or photovoltaic (PV) cell is an electrical device that converts energy of light, typically sun light (hence “solar”), directly into electricity by the so- called photovoltaic effect.
  • the solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.
  • Solar cells are described as being photovoltaic irrespective of whether the source is sunlight or an artificial light. They may also be used as photo detector.
  • a solar cell When a solar cell absorbs light it may generate either electron-hole pairs or excitons. In order to obtain an electrical current charge carriers of opposite types are separated. The separated charge carriers are "extracted" to an ex- ternal circuit, typically providing a DC-current. For practical use a DC-current may be transformed into an AC-current, e.g. by using a transformer.
  • solar cells are grouped into an array of elements.
  • Various elements may form a panel, and various pan- els may form a system.
  • a disadvantage of solar cells is that the conversion per se is not very efficient, typically, for Si-solar cells, limited to some 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of
  • the highest ratio achieved for a solar cell per se at present is about 44%.
  • the record is about 25.6%.
  • the front contacts were moved to a rear or back side, eliminating shaded areas.
  • thin silicon films were applied to the wafer.
  • Solar cells also suffer from various imperfections, such as recombination losses, reflectance losses, heating during use, thermodynamic losses, shadow, internal resistance, such as shunt and series resistance, leakage, etc.
  • a qualifi- cation of performance of a solar cell is the fill factor (FF) .
  • the fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current.
  • a typical advanced commercial solar cell has a fill factor > 0.75, whereas less advanced cells have a fill factor between 0.4 and 0.7.
  • Cells with a high fill factor typically have a low equivalent series resistance and a high equivalent shunt resistance; in other words less internal losses occur. Efficiency is nevertheless improving gradually, so every relatively small improvement is welcomed and of significant importance.
  • a disadvantage with various prior art processes for manufacturing solar cells is that a relatively high thermal budget for manufacturing is required, which is detrimental for the solar cells and not cost effective.
  • Such high temperature process steps are for instance used for annealing, such as annealing of silicon, and also for annealing of the dopants in order to diffuse the dopants.
  • annealing such as annealing of silicon
  • dopants in order to diffuse the dopants.
  • an additional high quality passivation layer is required in order to minimize electrical losses.
  • thermal Si0 2 thermal Si0 2
  • ALD A1 2 0 3 or PECVD SiN low thermal budget
  • the principle of oxygen-doped polycrystalline silicon is known from transistor process technology. It is also known to have doped Poly-Si (n-type or p-type) . In both case, the Poly-Si layers need a thermal annealing at high tem- perature (T > 900 °C) . Also the (re-) crystallization of a-Si requires a (similar) high temperature thermal annealing step. I For various processes, typically additional thermally grown silicon dioxide and silicon nitride is still needed to passiv- ate the crystalline silicon surface. The passivation layer may be an intrinsic a-Si layer, and amorphous layer, such as SiO x , and the like. Often an additional contact layer (transparent conductive oxide, TCO) is needed as well. In a way one may conclude that various process steps are not fully integrated, c.q. optimized with respect to one and another.
  • TCO transparent conductive oxide
  • the first two relate to single junction type passivating contact based back-contact solar cells, whereas the next three relate to hetero-junction based back contact solar cells.
  • These two types of cells and processes for manufacturing can not be com- bined easily.
  • the hetero junction cells have a limited temperature budget; especially higher temperatures of e.g. above 200 °C destroy the devices and hence these higher temperatures should not be used in the manufacturing process; on the contrary the single junction type cells may have higher process temperatures, e.g. of above 850 °C.
  • the hetero- junction devices typically need a couple of silicon layers (extra) and transparent conductive layers, such as ITO.
  • EP 2 797 124 Al recites a solar cell that includes a semiconductor substrate, a tunneling layer on one surface of the semiconductor substrate, a first conductive type area on the tunneling layer, a second conductive type area on the tunneling layer such that the second conductive type area is separated from the first conductive type area, and a barrier area interposed between the first conductive type area and the sec- ond conductive type area such that the barrier area separates the first conductive type area from the second conductive type area .
  • US2014 / 166095 Al recites an all back contact solar cell has a hybrid emitter design.
  • the solar cell has a thin dielectric layer formed on a backside surface of a single crystalline silicon substrate.
  • One emitter of the solar cell is made of doped polycrystalline silicon that is formed on the thin dielectric layer.
  • the other emitter of the solar cell is formed in the single crystalline silicon substrate and is made of doped single crystalline silicon.
  • the solar cell includes contact holes that allow metal contacts to connect to corresponding emitters.
  • Doping is diffusion based and hence typically requires an extra high temperature step of more than 30 minutes, typically more than 60 minutes. Is disadvantage of thermally assisted diffusion of dopants is that dopants enter a silicon bulk material.
  • WO2013/172056 Al recites an n-type semiconductor layer and a p-type semiconductor layer, a collector electrode that is formed on the n-type semiconductor layer, and a col- lector electrode that is formed on the p-type semiconductor layer on a light receiving surface of an n-type crystalline silicon substrate and a rear surface on the opposite side, and an n-type semiconductor area on a surface on the light receiving surface side of the n-type crystalline silicon substrate.
  • the average impurity concentration is different between an n-type semiconductor area that opposes the n-type semiconductor layer via the n-type crystalline silicon substrate and an n-type semiconductor area that opposes the p-type semiconductor layer via the n-type crystalline silicon substrate.
  • US2014 / 096819 Al recites a rear contact heterojunc- tion solar cell and a fabricating method.
  • the solar cell comprises a silicon substrate having a passivating layer and an intrinsic amorphous silicon layer.
  • an emitter layer and a base layer are provided at a back side of the in- trinsic amorphous silicon layer.
  • a separation layer comprising an electrically insulating material. This separation layer as well as the base layer and emitter layer may be generated by vapour deposition.
  • adjacent regions of the emitter layer and the separating layer and adjacent regions of the base layer and the separating layer partially laterally overlap in overlapping areas in such a way that at least a part of the separating layer is located closer to the substrate than an overlapping portion of the respective one of the emitter layer and the base layer.
  • US2015/007867 Al recites a photoelectric conversion device includes an n-type semiconductor layer and a p-type semiconductor layer, a col- lecting electrode formed on the n-type semiconductor layer, and a collecting electrode formed on the p-type semiconductor layer, on a back surface opposite to a light receiving surface of an n-type crystalline silicon substrate, and an n-type semiconductor region on a surface on a light receiving surface side of the n-type crystalline silicon substrate, wherein in the n-type semiconductor region, an n-type semiconductor region that is opposed to the n-type semiconductor layer with the n-type crystalline silicon substrate there between and an n-type semiconductor region that is opposed to the p-type sem- iconductor layer with the n-type crystalline silicon substrate there between have different average impurity concentrations.
  • the present invention relates to an increased efficiency back contacted silicon based solar cell and various aspects thereof and a simplified process for manufacturing the solar cell which overcomes one or more of the above disadvantages, without jeopardizing functionality and advantages.
  • the present invention relates in a first aspect to a silicon based solar cell with back side contacts according to claim 1, and in a second aspect to a process for making a silicon based solar cell with back side contacts according to claim 10.
  • the present invention makes use of various techniques in order to solve one or more of the prior art problems and provides further advantages; these advantages relate to measurable characteristics (effects) of the obtained devices and hence constitute noticeable physical differences over e.g. the prior art.
  • these advantages relate to measurable characteristics (effects) of the obtained devices and hence constitute noticeable physical differences over e.g. the prior art.
  • use is made of in-situ doped micro- crystalline silicon oxide or in-situ doped microcrystalline silicon layers deposited by PECVD at low temperature, with the proviso that at least one micro-crystalline thin film silicon oxide region is present. It has been found that such results in a minimized surface recombination velocity and enhances lateral transport (e.g. at the front side) .
  • the obtained doping profiles are better compared to diffusion stimulated doping profiles, e.g.
  • dopants/cm 3 an almost spatially constant concentration in the PECVD layer.
  • dopants/cm 3 an almost spatially constant concentration in the PECVD layer.
  • these dopants do not diffuse to e.g. a silicon substrate.
  • Such layers may be used both as passivation layer and as doped regions; it is found that these in-situ doped microcrystalline silicon oxide or silicon layers are already highly crystallized.
  • a lower thermal annealing temperature T ⁇ 900 °C, typically ⁇ 800 °C, and often ⁇ 700 °C
  • relatively short process times 1-30 min, such as 2-20 min, and typically 5-10 min, or in an alternative even no annealing step is required.
  • the thermal budget for the annealing step is therefore limited.
  • microcrystalline silicon oxide material has an even higher band gap (> 1.8 eV after forming thereof, and somewhat lower (0.1-0.2 eV) after annealing, compared to 1.12 eV of crystalline silicon) compared to Poly-Si; it has been found that this will make the passivated contacts more efficient in the case of carrier-selectivity. It has also been found that oxygen atoms in the above material can also effectively passivate the c-Si surface. Therefore no additional passivation layer is required.
  • the present process makes use of a unique combination of in-situ doped layers fabricated via PECVD, micro- crystallinity and low temperature annealing. These techniques are preferably applied to a single-side, allowing to separately optimizing each doped region according to required specifications.
  • the present process requires a low temperature ( T ⁇ 500 °C) to activate dopants and in addition a or reduced thermal budget (T ⁇ 900 °C and t ⁇ 30 min.) to crystallize thin film material; it provides dopant regions which are virtually gap-less, and dopant regions that are separated by a thin dielectric layer. It has been found that the present gap-less structure reduces recombination, espe- cially recombination occurring in case of low quality passivation layer. In addition, by reducing such gap, the overall series resistance of the device is minimized.
  • doping techniques are sin- gle-sided. It has been found that optimizing doping profiles at a front side and back side separately minimizes overall electrical losses of a photovoltaic device. Moreover, the present gap less structure with the two doped layers separated by a trench minimizes a leakage current between two adjacent oppositely doped regions. It is noted that in an alternative approach of so-called fully implanted devices, both doped regions are fabricated via ion implantation. In such a case, a gap-less and self-aligned structure could be fabricated. However, the annealing of ion implanted boron is complicated.
  • the activation of the boron atoms is not easy and when this is successfully achieved it requires a high thermal budget (T > 1000 °C) .
  • the present solution allows for in-situ doping of e.g. boron, phosphorous or arsenic, combined with phosphorous im- plantation in order to activate the dopants at low temperature.
  • in-situ doping activation takes place at relatively reduced temperatures of ⁇ 500 °C, often ⁇ 350 °C, such as ⁇ 200 °C; typically a PECVD technique is used in such cases.
  • Such is a major difference com- pared to most prior art techniques.
  • Such annealing advantageously may occur during the growth of the epitaxial layer; hence no extra annealing step is then required.
  • the present invention involves the use of doping techniques which can either accurately provide a required doping profile or overcome technical limitations of a diffusion process.
  • the doping profile is found to be limited by the solid solubility of the dopants in silicon, hence can not be optimized fully.
  • the combination of e.g. ion implanted phosphorous and epitaxial grown of Si doped in situ with e.g. boron enables the use of a low temperature annealing step (see e.g. fig. 2) .
  • the doping profile of each doped layer can be separately optimized.
  • a disadvantage the present in- vention is that an additional doping is required with respect to a prior art process.
  • the solar cells are so-called Interdigitat- ed Back Contact (IBC) solar cell structures.
  • IBC Interdigitat- ed Back Contact
  • the present invention relates in a first aspect to interdigitated back contacted solar cells according to claim 1 which may be obtained by the present reduced temperature pro- cess.
  • the interdigitated regions of n-type and p-type regions are (in a cross sectional view, such as in the figures) at a same height. It is noted that in principle n-doped regions and p-doped regions may be interchanged. If an in-situ doped PECVD microcrystalline silicon oxide or silicon layer is n-doped a back surface field is formed, if it is p-doped an emitter is formed.
  • Dopant concentrations are in the order of l*10 17 /cm 3 -l*10 19 /cm 3 , such as 2*10 17 /cm 3 - 5*10 18 /cm 3 .
  • the present cells may be regarded as het- ero-junction cells.
  • the present solar cell is double sided polished (fig. la) .
  • the solar cell is one side polished and one side textured, and in a further example it is double sided textured (fig lb) .
  • a textured surface increases surface recombination.
  • a textured surface preferably has an aspect ratio ( height : depth of a textured structure) of 2-10, preferably 5- 8.
  • the doped regions are formed by PECVD and thermal annealing of the re- gions .
  • the contacts independently consist of in-situ doped semi-insulating material, such as micro-crystalline thin-film silicon and micro-crystalline thin film silicon oxide. It has been found that such contacts minimize contact recombination of both silicon and silicon/metal surfaces; hence increase efficiency.
  • the contacts are passivated. Such is found to reduce contact recom- bination and reduces the number of process steps. It has been found that a dark saturation current, being representative for recombination, is in the order of 5*1CT 15 A/cm 2 versus 50*1CT 15 A/cm 2 of a comparable contact of some of the above prior art; this current is about 10 times better.
  • the un- doped silicon-oxide tunneling layer between the n-doped or p-doped regions is present only between doped regions and the silicon substrate.
  • the tunneling layer is preferably an un-doped Si0 2 layer, having a thickness of less than 3 nm, preferably less than 2 nm, such as less than 1.5 nm.
  • the present solar cell further comprises an un-doped silicon oxide on a front side of the silicon substrate, a doped layer on said front side silicon oxide layer, and a passivation layer on said doped front side layer.
  • a front side field is further optimized.
  • the oppositely doped regions are separated by trenches, wherein trenches are filled with a (semi) insulating material, preferably with an insulating material, such as a dielectric, e.g. air, SiN, SiO, etc.
  • a dielectric e.g. air, SiN, SiO, etc.
  • the micro- crystalline thin-film silicon and micro-crystalline thin film silicon oxide each independently comprise hydrogen in a concentration of 0.2-20 atom%, preferably 0.5-10 atom%, such as 1-5 atom%. It has been found that hydrogen improves passivation characteristics of the thin-film as well as reduces recombination .
  • the present solar cell or light de- tector has an efficiency of > 21%, a series resistance of ⁇ 1 Ohm*cm, a shunt resistance of > 1000 Ohm*cm, a fill factor of > 75%, a pitch of 0.1-5 mm, wherein the epitaxial-doped region and ion-implant-doped region are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region, a leakage current of ⁇ 1000 fA/cm 2 . It preferably has a front side aspect ratio of >50.
  • the present device has a different FSF and BSF.
  • the present invention relates to a process for manufacturing a solar cell according to the invention, comprising the steps of providing a silicon substrate, providing at least one n-doped region and at least one p-doped region, wherein the doped regions are independently selected from thin-film silicon and thin film sil- icon oxide, activating (typically during growth thereof) said doped regions at a temperature of less than 500 °C during a sufficient period of time, such as less than 350 °C, annealing said doped regions (41,42) at a temperature of less than 900 °C during a sufficient period of time of typically less than 30 minutes, providing an un-doped silicon-oxide tunneling layer between the n-doped or p-doped regions, respectively, and the silicon substrate, and providing contacts each being in electrical contact with a doped region.
  • at least one micro-crystalline thin film silicon oxide region is present. It is noted that the present process has a disadvantage, namely a somewhat more complicated process flow for the fabrication
  • a first doped layer is etched, thereby forming first doped regions, and thereafter second doped regions are formed, preferably wherein first and second doped regions are alternating.
  • both doped layers are covered with an insulating layer, the insulating layer extending in between oppositely doped regions.
  • doped regions are deposited by low temperature PECVD.
  • contacts are provided by metal deposition and lift off (of non-contact areas), screen printing, and electrical plating.
  • the photovoltaic energy can be harvested.
  • Metal may be deposited using sputtering techniques. It is preferred to use copper, aluminum, or tungsten as metal.
  • the non-contact areas can be etched in order to remove the metal.
  • an area of a p-doped region is two- to eight- times an area of an n-doped region .
  • the n-doped region and p-doped region are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region. As is detailed above such provides for improved characteristics of the present solar cell.
  • the present process further comprises forming a doped region at the front side of the wafer, thereby forming a front doped region, wherein the front doped region is independently selected from the back side doped region (see fig. 6) .
  • the front doped region may form a front side field (FSF) .
  • the present process further comprises the step of an anti-reflective coating the solar cell.
  • an anti-reflective coating improves light absorbance, and reduces recombination.
  • p-doped regions and n-doped regions have a pitch of 0.1 mm-5 mm, such as of 1-2 mm.
  • the pitch is used to describe a distance be- tween repeated elements in a structure possessing transla- tional symmetry: in the present case, a sequence of alternating p-doped regions and n-doped regions. It has been found that by optimizing the pitch also characteristics of the solar cell can be optimized.
  • At least one side of the wafer is provided with a texture, such as a mi- croscale texture, a nanoscale texture, and combinations thereof, wherein the texture preferably has a high aspect ratio.
  • the aspect ratio is preferably 2-10, preferably 5-8. It has been found that a high aspect ratio improves energy conversion .
  • the back side doped region and the front side doped region are different.
  • the front side doped region has a dopant con- centration of 1 * 10 11 / cm 3 - 1 * 10 19 / cm 3
  • the back side doped region a relative dopant concentration of >105% of the front side doped region.
  • Figures 1-10 show a schematic representation of an example of the present process.
  • dielectric layer typically SiN
  • a silicon wafer 21 is provided.
  • the wafer is cleaned at room temperature using 99% wt . % HN0 3 , and at 110 °C using 68% wt . % HN0 3 .
  • If the wafer is textured tetramethyl ammonium hydroxide (TMAH) is used. During 10 min. of cleaning the temperature is increased to 110 °C. If the wafer is textured 6-8 wt . % HN0 3 is used.
  • a textured wafer is than obtained (fig 10), which textured wafer may be processed in a similar fashion as a non-textured wafer.
  • a 1 nm intrinsic SiOx tunneling layer 31a is formed by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HNO 3 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the concentration of HN0 3 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min. Thereafter a first in-situ doped microcrystal- line silicon or silicon oxide layer 41 of 20 nm is made by PECVD. A B-dopant concentration reached is 10 19 /cm 3 . As an alternative (to B) P may be used, than changing the dopant type from p to n.
  • NOS nitric acid oxidation
  • the thickness of the layer may be from 10-100 nm.
  • a temperature used during PECVD is from 100-300 °C.
  • gases used are SiH 4 (or SiF 4 ) , C0 2 , B 2 H 6 (for p-type material, or PH 3 for n-type material), and optionally H 2 .
  • a first protective layer 32a is deposited, such as a SiOx or
  • SiNx protective layer A layer thickness used is 80 nm, which may vary from 10-100 nm.
  • a PECVD system is used for deposition, using a temperature between 100 and 300 °C, such as 150 °C.
  • Typical gases used are SiH 4 (or SiF 4 ) , H 2 , and C0 2 for SiOx, or SiH (or SiF ) , H 2 , and NH 3 for SiNx material.
  • a photoresist is applied.
  • a pattern is formed, defining first doped regions.
  • Thereto a 248 nm light source is used.
  • the protective layer, first doped layer, and tunneling layer are isotropically etched using dry etching.
  • (second) intrinsic SiOx tunneling layer 31b is formed by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HN0 3 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the con- centration of HN0 3 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min. Thereafter a second in-situ doped layer 42 of 20 nm is made by PECVD; typically this second doped layer 42 is of opposite dopant nature compared to the first dopant layer 41. A P-dopant concentration reached is 10 19 /cm 3 . As an alternative (to P) B may be used, than changing the dopant type from n to p.
  • NAOS nitric acid oxidation
  • the thickness of the layer may be from 10-100 nm.
  • a temperature used during PECVD is from 100-300 °C.
  • gases used are SiH (or SiF ) , C0 2 , PH 3 (for p-type material, or B 2 H 6 for n-type material), and optionally H 2 .
  • a second protective layer 32b is deposited, such as a SiOx or SiNx protective layer.
  • a layer thickness used is 80 nm, which may vary from 10-100 nm.
  • a PECVD system is used for deposi- tion, using a temperature between 100 and 300 °C, such as 150 °C.
  • gases used are SiH 4 (or SiF 4 ) , H 2 , and C0 2 for Si- Ox, or SiH 4 (or SiF 4 ) , H 2 , and NH 3 for SiNx material.
  • a photoresist 61 is applied.
  • a pattern is formed, defining second doped regions.
  • Thereto a 248 nm light source is used.
  • the non-protected second protective layer 32b, second doped layer 42, and second tunneling layer 31b are etched using wet etching, such as using 10% HF; this leaves behind in the etched regions (left, middle and right) a se- quence of layers from top to bottom of silicon 21, first intrinsic tunneling layer 31a, first in situ n-doped layer 41 and intrinsic protective layer 32a; in the etched regions (mid left and mid right) a sequence of layers from top to bottom of silicon 21, second intrinsic tunneling layer 31b, second in situ n-doped layer 42 and second intrinsic protective layer
  • the first and second doped regions are in the example alternating.
  • the regions are separated by a (later added) dielectric material.
  • a 1 nm intrinsic SiOx tunneling layer 31c is formed on the front side of the wafer 21 by a nitric acid oxidation (NAOS) method.
  • Wafers are dipped in 61% HN0 3 solutions at temperature of 50 °C for a process time of 10 min.
  • the concentration of HN0 3 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min.
  • a front side field (FSF) layer 45 of 20 nm is formed.
  • the P-dopant concentration is 5 10 18 /cm 3 .
  • a typical equipment used is a PECVD system using a temperature between 100 and 300 °C, such as 150 °C; such temperatures are extremely low compared to prior art process steps, where implanted dopants are annealed at e.g. 900 °C or more; in addition prior art processes typically also incorporate a removal of a doped layer (e.g. BSG, PSG) , from which dopants are driven away during annealing.
  • Typical gases used are SiH , C0 2 , PH 3 , and H 2 .
  • the processed wafer is annealed, at temperature less than 1000 °C, typically less than 900°C, in N2, for a proper duration.
  • Part of the annealing may relate to crystallizing microcrys- talline material.
  • a process time can be relatively short, preferably from 1-30 min, more preferably from 2-20 min, even more preferably from 3-15 min, such as 4-6 minutes.
  • ARC anti-reflective coating
  • a PECVD system is used for deposition, using a temperature between 100 and 400 °C, such as 150-300 °C.
  • Typical gases used are SiH 4 (or SiF 4 ) , option- ally H 2 , and NH 3 for SiNx material.
  • Typical gases used are SiH 4 (or SiF 4 ) , option- ally H 2 , and NH 3 for SiNx material.
  • a similar dielectric layer 51 is deposited as well, the layer extending in between the doped regions, thereby electrically separating these doped regions from one and another.
  • a trench of dielectric or semiconducting material 81 may be present.
  • a photoresist 61 is applied.
  • a pattern is formed, defining contact areas on the doped layers.
  • a 248 nm light source is used and the photoresist is partially etched .
  • the layers 51 and 31 are etched up to the first and second doped layer 41,42, respectively
  • a 2 pm metal layer 71 is deposited using PVD, such as an Al-layer.
  • the metal layer may be from 0.2-5 pm, e.g. 0.5-3 pm.
  • the metal is lift- off.
  • a metallization process can be replaced by a screen-printing process.
  • a textured wafer is shown, in this case textured at both sides thereof.

Abstract

The present invention is in the field of a process for making back side contacted wafer-based solar cells with in-situ doped crystallized thin-film silicon oxide regions and optionally in-situ doped silicon regions, and back side contacted solar cells. A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence "solar"), directly into electricity by the so-called photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.

Description

Title: Back side contacted wafer-based solar cells with in- situ doped crystallized silicon oxide regions
FIELD OF THE INVENTION
The present invention is in the field of a process for making back side contacted wafer-based solar cells with in-situ doped crystallized thin-film silicon oxide regions and optionally in-situ doped silicon regions, and back side contacted solar cells.
BACKGROUND OF THE INVENTION
A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence "solar"), directly into electricity by the so- called photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.
Solar cells are described as being photovoltaic irrespective of whether the source is sunlight or an artificial light. They may also be used as photo detector.
When a solar cell absorbs light it may generate either electron-hole pairs or excitons. In order to obtain an electrical current charge carriers of opposite types are separated. The separated charge carriers are "extracted" to an ex- ternal circuit, typically providing a DC-current. For practical use a DC-current may be transformed into an AC-current, e.g. by using a transformer.
Typically solar cells are grouped into an array of elements. Various elements may form a panel, and various pan- els may form a system.
A disadvantage of solar cells is that the conversion per se is not very efficient, typically, for Si-solar cells, limited to some 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of
33.7%. An infinite number of layers may reach a maximum power efficiency of 86%. The highest ratio achieved for a solar cell per se at present is about 44%. For commercial silicon solar cells the record is about 25.6%. In view of efficiency the front contacts were moved to a rear or back side, eliminating shaded areas. In addition thin silicon films were applied to the wafer. Solar cells also suffer from various imperfections, such as recombination losses, reflectance losses, heating during use, thermodynamic losses, shadow, internal resistance, such as shunt and series resistance, leakage, etc. A qualifi- cation of performance of a solar cell is the fill factor (FF) . The fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current. It is considered to be a key parameter in evaluating performance. A typical advanced commercial solar cell has a fill factor > 0.75, whereas less advanced cells have a fill factor between 0.4 and 0.7. Cells with a high fill factor typically have a low equivalent series resistance and a high equivalent shunt resistance; in other words less internal losses occur. Efficiency is nevertheless improving gradually, so every relatively small improvement is welcomed and of significant importance.
A disadvantage with various prior art processes for manufacturing solar cells is that a relatively high thermal budget for manufacturing is required, which is detrimental for the solar cells and not cost effective. Such high temperature process steps are for instance used for annealing, such as annealing of silicon, and also for annealing of the dopants in order to diffuse the dopants. For achieving high conversion efficiency solar cells, typically an additional high quality passivation layer is required in order to minimize electrical losses. Several techniques including high thermal budget
(thermal Si02) or low thermal budget (ALD A1203 or PECVD SiN) are used. Further, as indicated above especially the efficiency of solar cells is not optimal, yet.
Some recent developments are discussed below.
The principle of oxygen-doped polycrystalline silicon (Poly-Si) is known from transistor process technology. It is also known to have doped Poly-Si (n-type or p-type) . In both case, the Poly-Si layers need a thermal annealing at high tem- perature (T > 900 °C) . Also the (re-) crystallization of a-Si requires a (similar) high temperature thermal annealing step. I For various processes, typically additional thermally grown silicon dioxide and silicon nitride is still needed to passiv- ate the crystalline silicon surface. The passivation layer may be an intrinsic a-Si layer, and amorphous layer, such as SiOx, and the like. Often an additional contact layer (transparent conductive oxide, TCO) is needed as well. In a way one may conclude that various process steps are not fully integrated, c.q. optimized with respect to one and another.
Some prior art documents are mentioned below. The first two relate to single junction type passivating contact based back-contact solar cells, whereas the next three relate to hetero-junction based back contact solar cells. These two types of cells and processes for manufacturing can not be com- bined easily. For instance, the hetero junction cells have a limited temperature budget; especially higher temperatures of e.g. above 200 °C destroy the devices and hence these higher temperatures should not be used in the manufacturing process; on the contrary the single junction type cells may have higher process temperatures, e.g. of above 850 °C. Also the hetero- junction devices typically need a couple of silicon layers (extra) and transparent conductive layers, such as ITO.
EP 2 797 124 Al recites a solar cell that includes a semiconductor substrate, a tunneling layer on one surface of the semiconductor substrate, a first conductive type area on the tunneling layer, a second conductive type area on the tunneling layer such that the second conductive type area is separated from the first conductive type area, and a barrier area interposed between the first conductive type area and the sec- ond conductive type area such that the barrier area separates the first conductive type area from the second conductive type area .
US2014 / 166095 Al recites an all back contact solar cell has a hybrid emitter design. The solar cell has a thin dielectric layer formed on a backside surface of a single crystalline silicon substrate. One emitter of the solar cell is made of doped polycrystalline silicon that is formed on the thin dielectric layer. The other emitter of the solar cell is formed in the single crystalline silicon substrate and is made of doped single crystalline silicon. The solar cell includes contact holes that allow metal contacts to connect to corresponding emitters. Doping is diffusion based and hence typically requires an extra high temperature step of more than 30 minutes, typically more than 60 minutes. Is disadvantage of thermally assisted diffusion of dopants is that dopants enter a silicon bulk material.
WO2013/172056 Al recites an n-type semiconductor layer and a p-type semiconductor layer, a collector electrode that is formed on the n-type semiconductor layer, and a col- lector electrode that is formed on the p-type semiconductor layer on a light receiving surface of an n-type crystalline silicon substrate and a rear surface on the opposite side, and an n-type semiconductor area on a surface on the light receiving surface side of the n-type crystalline silicon substrate. In the n-type semiconductor area (8), the average impurity concentration is different between an n-type semiconductor area that opposes the n-type semiconductor layer via the n-type crystalline silicon substrate and an n-type semiconductor area that opposes the p-type semiconductor layer via the n-type crystalline silicon substrate.
US2014 / 096819 Al recites a rear contact heterojunc- tion solar cell and a fabricating method. The solar cell comprises a silicon substrate having a passivating layer and an intrinsic amorphous silicon layer. At a back side of the in- trinsic amorphous silicon layer, an emitter layer and a base layer are provided. Interposed between these emitter and base layers is a separation layer comprising an electrically insulating material. This separation layer as well as the base layer and emitter layer may be generated by vapour deposition. Due to such processing, adjacent regions of the emitter layer and the separating layer and adjacent regions of the base layer and the separating layer partially laterally overlap in overlapping areas in such a way that at least a part of the separating layer is located closer to the substrate than an overlapping portion of the respective one of the emitter layer and the base layer.
US2015/007867 Al (equivalent to WO 2013/172056 Al) recites a photoelectric conversion device includes an n-type semiconductor layer and a p-type semiconductor layer, a col- lecting electrode formed on the n-type semiconductor layer, and a collecting electrode formed on the p-type semiconductor layer, on a back surface opposite to a light receiving surface of an n-type crystalline silicon substrate, and an n-type semiconductor region on a surface on a light receiving surface side of the n-type crystalline silicon substrate, wherein in the n-type semiconductor region, an n-type semiconductor region that is opposed to the n-type semiconductor layer with the n-type crystalline silicon substrate there between and an n-type semiconductor region that is opposed to the p-type sem- iconductor layer with the n-type crystalline silicon substrate there between have different average impurity concentrations.
In all the above cases a Si semiconductor is used for doping .
The present invention relates to an increased efficiency back contacted silicon based solar cell and various aspects thereof and a simplified process for manufacturing the solar cell which overcomes one or more of the above disadvantages, without jeopardizing functionality and advantages.
SUMMARY OF THE INVENTION
The present invention relates in a first aspect to a silicon based solar cell with back side contacts according to claim 1, and in a second aspect to a process for making a silicon based solar cell with back side contacts according to claim 10.
The present invention makes use of various techniques in order to solve one or more of the prior art problems and provides further advantages; these advantages relate to measurable characteristics (effects) of the obtained devices and hence constitute noticeable physical differences over e.g. the prior art. For instance use is made of in-situ doped micro- crystalline silicon oxide or in-situ doped microcrystalline silicon layers deposited by PECVD at low temperature, with the proviso that at least one micro-crystalline thin film silicon oxide region is present. It has been found that such results in a minimized surface recombination velocity and enhances lateral transport (e.g. at the front side) . The obtained doping profiles are better compared to diffusion stimulated doping profiles, e.g. in terms of an almost spatially constant concentration (dopants/cm3) in the PECVD layer. In addition, as no annealing step is required to diffuse dopants, these dopants do not diffuse to e.g. a silicon substrate. Such layers may be used both as passivation layer and as doped regions; it is found that these in-situ doped microcrystalline silicon oxide or silicon layers are already highly crystallized. There- fore in case of further solar cell processing especially in view of recrystallization of microcrystalline material a lower thermal annealing temperature (T < 900 °C, typically < 800 °C, and often < 700 °C) ) and relatively short process times of 1-30 min, such as 2-20 min, and typically 5-10 min, or in an alternative even no annealing step is required. The thermal budget for the annealing step is therefore limited. It has also been found that the microcrystalline silicon oxide material has an even higher band gap (> 1.8 eV after forming thereof, and somewhat lower (0.1-0.2 eV) after annealing, compared to 1.12 eV of crystalline silicon) compared to Poly-Si; it has been found that this will make the passivated contacts more efficient in the case of carrier-selectivity. It has also been found that oxygen atoms in the above material can also effectively passivate the c-Si surface. Therefore no additional passivation layer is required.
As a result an improved silicon based solar cell is provided with an increased efficiency (10-20% relative increase) . The present process makes use of a unique combination of in-situ doped layers fabricated via PECVD, micro- crystallinity and low temperature annealing. These techniques are preferably applied to a single-side, allowing to separately optimizing each doped region according to required specifications. The present process requires a low temperature ( T < 500 °C) to activate dopants and in addition a or reduced thermal budget (T < 900 °C and t<30 min.) to crystallize thin film material; it provides dopant regions which are virtually gap-less, and dopant regions that are separated by a thin dielectric layer. It has been found that the present gap-less structure reduces recombination, espe- cially recombination occurring in case of low quality passivation layer. In addition, by reducing such gap, the overall series resistance of the device is minimized.
The above and other improvements quenches the series resistance of doped regions and the leakage current be- tween them making the shunt resistance very high leading to a high pseudo fill factor of >0.75. In a first exemplary embodiment solar cells with a conversion efficiency of 20.2 % have been fabricated; improving various aspects of the process and specifically various steps thereof a conversion ef- ficiency of 22-23 % or more is found to be achievable. Such relates to an improvement of 1-3% over prior art devices, which is a relative improvement of 5-15%. For return of investment such a difference is considered huge.
In the present process doping techniques are sin- gle-sided. It has been found that optimizing doping profiles at a front side and back side separately minimizes overall electrical losses of a photovoltaic device. Moreover, the present gap less structure with the two doped layers separated by a trench minimizes a leakage current between two adjacent oppositely doped regions. It is noted that in an alternative approach of so-called fully implanted devices, both doped regions are fabricated via ion implantation. In such a case, a gap-less and self-aligned structure could be fabricated. However, the annealing of ion implanted boron is complicated. In particular, the activation of the boron atoms is not easy and when this is successfully achieved it requires a high thermal budget (T > 1000 °C) . On the contrary, the present solution allows for in-situ doping of e.g. boron, phosphorous or arsenic, combined with phosphorous im- plantation in order to activate the dopants at low temperature. In examples of the present in-situ doping activation takes place at relatively reduced temperatures of < 500 °C, often < 350 °C, such as < 200 °C; typically a PECVD technique is used in such cases. Such is a major difference com- pared to most prior art techniques. Such annealing advantageously may occur during the growth of the epitaxial layer; hence no extra annealing step is then required.
With respect to prior art solar cells fabricated via diffusion, the present invention involves the use of doping techniques which can either accurately provide a required doping profile or overcome technical limitations of a diffusion process. In fact, in case of standard doping diffusion, the doping profile is found to be limited by the solid solubility of the dopants in silicon, hence can not be optimized fully. The combination of e.g. ion implanted phosphorous and epitaxial grown of Si doped in situ with e.g. boron enables the use of a low temperature annealing step (see e.g. fig. 2) . In addition, by using single-side doping techniques, the doping profile of each doped layer can be separately optimized. A disadvantage the present in- vention is that an additional doping is required with respect to a prior art process.
In an example the solar cells are so-called Interdigitat- ed Back Contact (IBC) solar cell structures.
Thereby the present invention provides a solution to one or more of the above mentioned problems.
Advantages of the present description are detailed throughout the description. References to the figures are not limiting, and are only intended to guide the person skilled in the art through details of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates in a first aspect to interdigitated back contacted solar cells according to claim 1 which may be obtained by the present reduced temperature pro- cess. In an example the interdigitated regions of n-type and p-type regions are (in a cross sectional view, such as in the figures) at a same height. It is noted that in principle n-doped regions and p-doped regions may be interchanged. If an in-situ doped PECVD microcrystalline silicon oxide or silicon layer is n-doped a back surface field is formed, if it is p-doped an emitter is formed. Dopant concentrations are in the order of l*1017/cm3-l*1019/cm3, such as 2*1017/cm3- 5*1018/cm3. As such the present cells may be regarded as het- ero-junction cells.
In an example the present solar cell is double sided polished (fig. la) . In a further example the solar cell is one side polished and one side textured, and in a further example it is double sided textured (fig lb) . A textured surface increases surface recombination. In this respect it has been found that a textured surface preferably has an aspect ratio ( height : depth of a textured structure) of 2-10, preferably 5- 8.
In an example of the present solar cell the doped regions are formed by PECVD and thermal annealing of the re- gions .
In an example of the present solar cell the contacts independently consist of in-situ doped semi-insulating material, such as micro-crystalline thin-film silicon and micro-crystalline thin film silicon oxide. It has been found that such contacts minimize contact recombination of both silicon and silicon/metal surfaces; hence increase efficiency.
In an example of the present solar cell the contacts are passivated. Such is found to reduce contact recom- bination and reduces the number of process steps. It has been found that a dark saturation current, being representative for recombination, is in the order of 5*1CT15 A/cm2 versus 50*1CT15 A/cm2 of a comparable contact of some of the above prior art; this current is about 10 times better.
In an example of the present solar cell the un- doped silicon-oxide tunneling layer between the n-doped or p-doped regions is present only between doped regions and the silicon substrate. The tunneling layer is preferably an un-doped Si02 layer, having a thickness of less than 3 nm, preferably less than 2 nm, such as less than 1.5 nm.
In an example of the present solar cell further comprises an un-doped silicon oxide on a front side of the silicon substrate, a doped layer on said front side silicon oxide layer, and a passivation layer on said doped front side layer. Thereby a front side field is further optimized.
In an example of the present solar cell the oppositely doped regions are separated by trenches, wherein trenches are filled with a (semi) insulating material, preferably with an insulating material, such as a dielectric, e.g. air, SiN, SiO, etc. Therewith the above mentioned advantages are achieved.
In an example of the present solar cell the micro- crystalline thin-film silicon and micro-crystalline thin film silicon oxide each independently comprise hydrogen in a concentration of 0.2-20 atom%, preferably 0.5-10 atom%, such as 1-5 atom%. It has been found that hydrogen improves passivation characteristics of the thin-film as well as reduces recombination .
In an example the present solar cell or light de- tector has an efficiency of > 21%, a series resistance of < 1 Ohm*cm, a shunt resistance of > 1000 Ohm*cm, a fill factor of > 75%, a pitch of 0.1-5 mm, wherein the epitaxial-doped region and ion-implant-doped region are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region, a leakage current of < 1000 fA/cm2. It preferably has a front side aspect ratio of >50.
In an example the present device has a different FSF and BSF.
In a second aspect the present invention relates to a process for manufacturing a solar cell according to the invention, comprising the steps of providing a silicon substrate, providing at least one n-doped region and at least one p-doped region, wherein the doped regions are independently selected from thin-film silicon and thin film sil- icon oxide, activating (typically during growth thereof) said doped regions at a temperature of less than 500 °C during a sufficient period of time, such as less than 350 °C, annealing said doped regions (41,42) at a temperature of less than 900 °C during a sufficient period of time of typically less than 30 minutes, providing an un-doped silicon-oxide tunneling layer between the n-doped or p-doped regions, respectively, and the silicon substrate, and providing contacts each being in electrical contact with a doped region. Typically at least one micro-crystalline thin film silicon oxide region is present. It is noted that the present process has a disadvantage, namely a somewhat more complicated process flow for the fabrication of the
photovoltaic device.
In an example of the present process a first doped layer is etched, thereby forming first doped regions, and thereafter second doped regions are formed, preferably wherein first and second doped regions are alternating.
In an example of the present process after forming a second doped layer, both doped layers are covered with an insulating layer, the insulating layer extending in between oppositely doped regions.
In an example of the present process doped regions are deposited by low temperature PECVD.
In an example of the present process contacts are provided by metal deposition and lift off (of non-contact areas), screen printing, and electrical plating. As such the photovoltaic energy can be harvested. Metal may be deposited using sputtering techniques. It is preferred to use copper, aluminum, or tungsten as metal. In an alternative, after deposition, the non-contact areas can be etched in order to remove the metal.
In an example of the present process an area of a p-doped region is two- to eight- times an area of an n-doped region .
In an example of the present process the n-doped region and p-doped region are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region. As is detailed above such provides for improved characteristics of the present solar cell.
In an example the present process further comprises forming a doped region at the front side of the wafer, thereby forming a front doped region, wherein the front doped region is independently selected from the back side doped region (see fig. 6) . The front doped region may form a front side field (FSF) . By independently doping a front and a back side especially the fill factor of the solar cell can be improved, e.g. to above 20% efficiency.
In an example the present process further comprises the step of an anti-reflective coating the solar cell. Such an anti-reflective coating improves light absorbance, and reduces recombination.
In an example of the present process p-doped regions and n-doped regions have a pitch of 0.1 mm-5 mm, such as of 1-2 mm. The pitch is used to describe a distance be- tween repeated elements in a structure possessing transla- tional symmetry: in the present case, a sequence of alternating p-doped regions and n-doped regions. It has been found that by optimizing the pitch also characteristics of the solar cell can be optimized.
In an example of the present process at least one side of the wafer is provided with a texture, such as a mi- croscale texture, a nanoscale texture, and combinations thereof, wherein the texture preferably has a high aspect ratio. The aspect ratio is preferably 2-10, preferably 5-8. It has been found that a high aspect ratio improves energy conversion .
In an example of the present process the back side doped region and the front side doped region are different. In an example the front side doped region has a dopant con- centration of 1 * 1011 / cm3- 1 * 1019 / cm3 , whereas the back side doped region a relative dopant concentration of >105% of the front side doped region.
The invention is further detailed by the accompanying figures and examples, which are exemplary and explanatory of nature and are not limiting the scope of the invention. To the person skilled in the art it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, defined by the present claims .
SUMMARY OF FIGURES
Figures 1-10 show a schematic representation of an example of the present process.
DETAILED DESCRIPTION OF FIGURES
21: Si wafer
31a, b: intrinsic SiOx tunneling layer
32a, b: intrinsic SiOx protective layer
41 first in-situ n-doped layer
42 second in-situ p-doped layer
45 front side field
51a, b: dielectric layer, typically SiN
61: Photo-resist
71: metal (contacts)
81: trench of dielect3ic or semiconducting material
The figures are further detailed in the description of the experiments below.
In figure 1 a silicon wafer 21 is provided. The wafer is cleaned at room temperature using 99% wt . % HN03, and at 110 °C using 68% wt . % HN03. If the wafer is textured tetramethyl ammonium hydroxide (TMAH) is used. During 10 min. of cleaning the temperature is increased to 110 °C. If the wafer is textured 6-8 wt . % HN03 is used. A textured wafer is than obtained (fig 10), which textured wafer may be processed in a similar fashion as a non-textured wafer. On the bottom side of the wafer a 1 nm intrinsic SiOx tunneling layer 31a is formed by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HNO3 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the concentration of HN03 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min. Thereafter a first in-situ doped microcrystal- line silicon or silicon oxide layer 41 of 20 nm is made by PECVD. A B-dopant concentration reached is 1019/cm3. As an alternative (to B) P may be used, than changing the dopant type from p to n.
The thickness of the layer may be from 10-100 nm. A temperature used during PECVD is from 100-300 °C. Typically gases used are SiH4 (or SiF4) , C02, B2H6 (for p-type material, or PH3 for n-type material), and optionally H2.
After deposition of the n- or p-type doped layer a first protective layer 32a is deposited, such as a SiOx or
SiNx protective layer. A layer thickness used is 80 nm, which may vary from 10-100 nm. Typically a PECVD system is used for deposition, using a temperature between 100 and 300 °C, such as 150 °C. Typical gases used are SiH4 (or SiF4) , H2, and C02 for SiOx, or SiH (or SiF ) , H2, and NH3 for SiNx material.
In Fig. 2 a photoresist is applied. A pattern is formed, defining first doped regions. Thereto a 248 nm light source is used. The protective layer, first doped layer, and tunneling layer are isotropically etched using dry etching.
In fig. 3 conformal layers are deposited. First a
(second) intrinsic SiOx tunneling layer 31b is formed by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HN03 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the con- centration of HN03 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min. Thereafter a second in-situ doped layer 42 of 20 nm is made by PECVD; typically this second doped layer 42 is of opposite dopant nature compared to the first dopant layer 41. A P-dopant concentration reached is 1019/cm3. As an alternative (to P) B may be used, than changing the dopant type from n to p.
The thickness of the layer may be from 10-100 nm. A temperature used during PECVD is from 100-300 °C. Typically gases used are SiH (or SiF ) , C02, PH3 (for p-type material, or B2H6 for n-type material), and optionally H2. Thereafter a second protective layer 32b is deposited, such as a SiOx or SiNx protective layer. A layer thickness used is 80 nm, which may vary from 10-100 nm. Typically a PECVD system is used for deposi- tion, using a temperature between 100 and 300 °C, such as 150 °C. Typical gases used are SiH4 (or SiF4) , H2, and C02 for Si- Ox, or SiH4 (or SiF4) , H2, and NH3 for SiNx material.
In fig. 4 a photoresist 61 is applied. A pattern is formed, defining second doped regions. Thereto a 248 nm light source is used.
In fig. 5 the non-protected second protective layer 32b, second doped layer 42, and second tunneling layer 31b are etched using wet etching, such as using 10% HF; this leaves behind in the etched regions (left, middle and right) a se- quence of layers from top to bottom of silicon 21, first intrinsic tunneling layer 31a, first in situ n-doped layer 41 and intrinsic protective layer 32a; in the etched regions (mid left and mid right) a sequence of layers from top to bottom of silicon 21, second intrinsic tunneling layer 31b, second in situ n-doped layer 42 and second intrinsic protective layer
32b. The first and second doped regions are in the example alternating. The regions are separated by a (later added) dielectric material.
In fig. 6 a 1 nm intrinsic SiOx tunneling layer 31c is formed on the front side of the wafer 21 by a nitric acid oxidation (NAOS) method. Wafers are dipped in 61% HN03 solutions at temperature of 50 °C for a process time of 10 min. Depending on a required thickness (0.5-5nm) the concentration of HN03 may be increased to 69.5%, the temperature by be in a range of 25-121 C, and the process time may be from 2-30 min.
Next a front side field (FSF) layer 45 of 20 nm is formed. The P-dopant concentration is 5 1018/cm3. A typical equipment used is a PECVD system using a temperature between 100 and 300 °C, such as 150 °C; such temperatures are extremely low compared to prior art process steps, where implanted dopants are annealed at e.g. 900 °C or more; in addition prior art processes typically also incorporate a removal of a doped layer (e.g. BSG, PSG) , from which dopants are driven away during annealing. Typical gases used are SiH , C02, PH3, and H2. Thereafter the processed wafer is annealed, at temperature less than 1000 °C, typically less than 900°C, in N2, for a proper duration. Part of the annealing may relate to crystallizing microcrys- talline material. A process time can be relatively short, preferably from 1-30 min, more preferably from 2-20 min, even more preferably from 3-15 min, such as 4-6 minutes. After an- nealing an anti-reflective coating (ARC) 51 of 10-100 nm, such as 80 nm, is provided. Typically a PECVD system is used for deposition, using a temperature between 100 and 400 °C, such as 150-300 °C. Typical gases used are SiH4 (or SiF4) , option- ally H2, and NH3 for SiNx material. At the bottom side a similar dielectric layer 51 is deposited as well, the layer extending in between the doped regions, thereby electrically separating these doped regions from one and another.
In between dopant regions a trench of dielectric or semiconducting material 81 may be present.
In fig. 7 a photoresist 61 is applied. A pattern is formed, defining contact areas on the doped layers. Thereto a 248 nm light source is used and the photoresist is partially etched .
In fig. 8 the layers 51 and 31 are etched up to the first and second doped layer 41,42, respectively
In fig. 9 a 2 pm metal layer 71 is deposited using PVD, such as an Al-layer. The metal layer may be from 0.2-5 pm, e.g. 0.5-3 pm. For non-contact regions the metal is lift- off. As an alternative a metallization process can be replaced by a screen-printing process.
In fig. 10 a textured wafer is shown, in this case textured at both sides thereof.
EXAMPLES/EXPERIMENTS
The invention although described in detailed explanatory context may be best understood in conjunction with the accompanying figures.
It should be appreciated that for commercial application it may be preferable to use one or more variations of the present system, which would similar be to the ones disclosed in the present application and are within the spirit of the invention .

Claims

1. Increased efficiency silicon based solar cell (100) with back side contacts (71), comprising
a silicon substrate (21),
at least one n-doped region (41) and at least one p-doped region (42), wherein materials of the doped regions are independently selected from micro-crystalline thin-film silicon and micro-crystalline thin film silicon oxide, with the proviso that at least one micro-crystalline thin film silicon oxide region is present,
an un-doped silicon-oxide tunnelling layer (31a, b) between the n-doped or p-doped regions, respectively, and the silicon substrate,
and wherein each contact (71) is in electrical contact with a doped region (41,42) .
2. Solar cell according to claim 1, wherein the solar cell is double sided polished, one side polished and one side textured, or double sided textured.
3. Solar cell according to any of the preceding claims, wherein the doped regions (41,42) are PECVD and thermal an- nealed regions.
4. Solar cell according to any of the preceding claims, wherein the contacts (71) independently consist of in-situ doped semi-insulating material, such as micro-crystalline thin-film silicon and micro-crystalline thin film silicon ox- ide .
5. Solar cell according to any of the preceding claims, wherein at least one of the contacts (71) are passivated, an area of a p-doped region is two- to eight- times an area of an n-doped region, the n-doped region and p-doped region are sep- arated by a distance of 0.1-5% relative to a length of the epitaxial-doped region, and p-doped regions and n-doped regions have a pitch of 0.1 mm-5 mm.
6. Solar cell according to any of the preceding claims, wherein the un-doped silicon-oxide tunnelling layer (31a, b) between the n-doped or p-doped regions is present only between doped regions and the silicon substrate.
7. Solar cell according to any of the preceding claims, further comprising at least one of an un-doped silicon oxide (31c) on a front side of the silicon substrate,
a doped layer (45) on said front side silicon oxide layer, and
a passivation layer (51a) on said doped front side layer.
8. Solar cell according to any of the preceding claims, wherein the oppositely doped regions (41, 42) are separated by trenches (81), wherein trenches are filled with a (semi) insulating material.
9. Solar cell according to any of the preceding claims, wherein the micro-crystalline thin-film silicon and micro- crystalline thin film silicon oxide each independently comprise hydrogen in a concentration of 0.2-20 atom%.
10. Process for manufacturing a solar cell according to any of claims 1-9, comprising the steps of
providing a silicon substrate (21),
providing at least one n-doped region (41) and at least one p-doped region (42), wherein the doped regions are independently selected from thin-film silicon and thin film silicon oxide,
annealing said doped regions (41,42) at a temperature of less than 900 °C during a sufficient period of time,
providing an un-doped silicon-oxide tunnelling layer
(31a, b) between the n-doped or p-doped regions, respectively, and the silicon substrate, and
providing contacts (71) each being in electrical contact with a doped region (41,42) .
11. Process according to claims 10, wherein a first doped layer (41) is etched, thereby forming first doped regions, and thereafter
second doped regions (42) are formed, preferably wherein first and second doped regions are alternating.
12. Process according to any of claims 10-11, wherein after forming a second doped layer (42), both doped layers
(41,42) are covered with an insulating layer (51b), the insu- lating layer extending in between oppositely doped regions.
13. Process according to any of claims 10-12, wherein at least one doped region is deposited by low temperature PECVD.
14. Process according to any of the preceding claims, wherein contacts (71) are provided by metal deposition and lift off (of non-contact areas), screen printing, and electrical plating.
PCT/NL2015/050759 2014-10-31 2015-10-30 Back side contacted wafer-based solar cells with in-situ doped crystallized silicon oxide regions WO2016068711A2 (en)

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