WO2014092137A1 - Multilayer printed circuit board and manufacturing method thereof - Google Patents

Multilayer printed circuit board and manufacturing method thereof Download PDF

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Publication number
WO2014092137A1
WO2014092137A1 PCT/JP2013/083266 JP2013083266W WO2014092137A1 WO 2014092137 A1 WO2014092137 A1 WO 2014092137A1 JP 2013083266 W JP2013083266 W JP 2013083266W WO 2014092137 A1 WO2014092137 A1 WO 2014092137A1
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WO
WIPO (PCT)
Prior art keywords
layer
built
resin layer
multilayer printed
printed wiring
Prior art date
Application number
PCT/JP2013/083266
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French (fr)
Japanese (ja)
Inventor
和弘 大澤
敏文 松島
桑子　富士夫
Original Assignee
三井金属鉱業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 三井金属鉱業株式会社 filed Critical 三井金属鉱業株式会社
Priority to CN201380063322.4A priority Critical patent/CN104823530B/en
Priority to KR1020157015166A priority patent/KR102097847B1/en
Priority to JP2014552075A priority patent/JP6295206B2/en
Publication of WO2014092137A1 publication Critical patent/WO2014092137A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present invention relates to a multilayer printed wiring board and a manufacturing method thereof.
  • the present invention relates to a multilayer printed wiring board manufactured by a built-up method.
  • multilayer printed wiring boards have been widely used to achieve the purpose of increasing the signal transmission speed and reducing the mounting area as a printed wiring board.
  • This multilayer printed wiring board is used by mounting various electronic components.
  • Various methods such as a solder reflow method and a wire bonding method are used for mounting electronic components on the multilayer printed wiring board.
  • the multilayer printed wiring board has “warp”, “twist”, and “dimensional change”, it is not preferable because good electronic components cannot be mounted.
  • “warping”, “twisting”, and “dimensional change” are likely to occur even during processing.
  • Technology has been advocated. Such prior art will be exemplified below.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 11-2612278 describes “a core substrate with an interlayer” for the purpose of providing a multilayer printed wiring board with small dimensional changes in the XY direction and Z direction and less surface waviness and warpage.
  • a prepreg having a thickness of 0.15 mm or less in which a core substrate is impregnated with a bismaleimide triazine resin in a low thermal expansion fiber cloth such as a glass cloth.
  • the core substrate in which the prepreg is laminated that is, the multilayer printed wiring board in the XY direction is formed.
  • the technique of preventing dimensional change and warping is disclosed.
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2003-086941 provides a printed wiring board that can reduce the occurrence of warping due to thermal history and can easily form the outermost conductor layer with a fine pattern.
  • the outermost insulating resin layer is based on glass cloth.
  • Patent Document 3 Japanese Patent Application Laid-Open No. 2004-342827 discloses that a resin is filled in IVH and has less warping / twisting and a higher elastic modulus than a multilayer printed wiring board that is built up and laminated only by a resin layer.
  • the front and back of the inner layer board having IVH A printed wiring having a structure in which an organic film base resin composition or a resin composition layer without base material reinforcement is formed and filled with IVH, and at least the outermost layer is a fiber nonwoven base material reinforcing resin composition layer.
  • a manufacturing method is adopted.
  • Patent Document 4 Japanese Patent Application Laid-Open No. 2008-307886 discloses that “a metal foil is disposed on a prepreg and formed for the purpose of providing a method for producing a metal-clad laminate and a multilayer laminate with reduced warpage.
  • the temperature of the laminate is maintained at a temperature that is 5 ° C. lower than the temperature at which the prepreg has the lowest melt viscosity. It includes two steps and a third step of cooling and forming the laminated body after 30 minutes or more have passed since the predetermined time point. It is disclosed.
  • the outermost insulating resin layer is formed as a resin-based layer not containing glass cloth as a base material.
  • the second insulating resin layer from the outermost layer is formed as a layer containing glass cloth as a base material” must be satisfied.
  • the pressure ratio is 0.4 or less of the first molding pressure for a period of at least 5 minutes from the predetermined time point after the heating and pressurizing in the first step.
  • a second step in which the temperature of the laminate is maintained at a temperature 5 ° C. lower than the temperature at which the prepreg has the lowest melt viscosity while pressing the laminate at a certain second molding pressure.
  • the inventors of the present invention simply changed the manufacturing method, or changed the layer configuration of the multilayer printed wiring board, so that the multilayer printed wiring board obtained by using the built-up method was warped and twisted. ⁇ Recognized that it is difficult to suppress “dimensional changes” without variation. As a result, by adopting the following technical concept, it is possible to reduce variations among printed wiring board products even if the multilayer printed wiring board has slight “warping”, “twist”, and “dimensional change”. I thought. The outline of the invention related to the present application will be described below.
  • the multilayer printed wiring board according to the present application is a multilayer printed wiring board in which two or more built-up wiring layers are provided on both sides of the core board, and the core board constituting the multilayer printed wiring board is insulated.
  • the layer thickness is 150 ⁇ m or less
  • the inner layer circuit is provided on both surfaces of the skeleton material-containing insulating layer
  • the XY direction linear expansion coefficient of the skeleton material-containing insulating layer is 0 ppm / ° C. to 20 ppm / ° C.
  • the insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer of the multilayer printed wiring board according to the present application preferably has a tensile elastic modulus at 25 ° C. of 5 GPa to 10 GPa.
  • the insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer of the multilayer printed wiring board according to the present application preferably has a thickness of 20 ⁇ m to 80 ⁇ m.
  • the dielectric constant of the insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer of the multilayer printed wiring board according to the present application is 3.5 or less.
  • a built-up wiring layer including an insulating resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa on the outermost layer of the multilayer printed wiring board according to the present application.
  • the manufacturing method of the multilayer printed wiring board concerning this application includes the concept of the following two manufacturing methods. Therefore, they are referred to as a first manufacturing method and a second manufacturing method.
  • This first manufacturing method is the above-described method for manufacturing a multilayer printed wiring board, comprising the following steps 1 to 3.
  • Step 1 Using a copper clad laminate having a copper foil layer on the surface of a skeleton-containing insulating layer having an insulating layer thickness of 150 ⁇ m or less and an XY direction linear expansion coefficient of 0 ppm / ° C. to 20 ppm / ° C. Then, an inner layer circuit is formed to obtain a core substrate.
  • Step 2 Using a copper foil with a semi-cured resin layer in which a semi-cured resin layer having an XY linear expansion coefficient of 1 ppm / ° C. to 50 ppm / ° C. is formed on the surface of the copper foil.
  • Step 3 The semi-cured resin layer of the copper foil with the semi-cured resin layer is brought into contact with the surface of the laminate with the first build-up wiring layer to further form a built-up layer composed of an insulating resin layer and a copper foil layer. Then, an operation for forming a circuit is set as a first unit process, and this first unit process is repeated n 1 times (an integer of n 1 ⁇ 1) on both surfaces of the laminated board with the first buildup wiring layer. Then, a multilayer printed wiring board having (4 + 2n 1 ) layer built-up layers on both surfaces of the core substrate is obtained.
  • This second manufacturing method is a method for manufacturing a multilayer printed wiring board as described above, comprising the following steps 1 to 4.
  • Step 1 Using a copper clad laminate having a copper foil layer on the surface of a skeleton-containing insulating layer having an insulating layer thickness of 150 ⁇ m or less and an XY direction linear expansion coefficient of 0 ppm / ° C. to 20 ppm / ° C. Then, an inner layer circuit is formed to obtain a core substrate.
  • Step 2 Using a copper foil with a semi-cured resin layer in which a semi-cured resin layer having an XY linear expansion coefficient of 1 ppm / ° C. to 50 ppm / ° C. is formed on the surface of the copper foil.
  • Step 3 The semi-cured resin layer of the copper foil with the semi-cured resin layer is brought into contact with the surface of the laminate with the first build-up wiring layer to further form a built-up layer composed of an insulating resin layer and a copper foil layer. Then, an operation for forming a circuit is set as a first unit process, and this first unit process is repeated n 1 times (an integer of n 1 ⁇ 1) on both surfaces of the laminated board with the first buildup wiring layer.
  • Step 4 A multilayer printed wiring board having (4 + 2n 1 ) built-up wiring layers on both surfaces of the core substrate is obtained.
  • Step 4 A semi-cured resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing is formed on the surface of the (4 + 2n 1 ) layer of the built-up wiring layer formed using the first unit step.
  • the second unit process is defined as an operation in which the semi-cured resin layer side of the copper foil with the semi-cured resin layer is brought into contact with each other to perform circuit formation.
  • a multilayer printed wiring board having a built-up wiring layer provided with an insulating resin layer of less than 5.0 GPa is obtained.
  • the linear expansion coefficient in the XY direction of the insulating layer of the core substrate and the linear expansion coefficient in the XY direction of the insulating resin layer constituting the built-up wiring layer provided on both surfaces thereof are obtained.
  • a multilayer printed wiring board 1 according to the present application includes two or more first built-up wiring layers Bu1 and second built-up wiring layers Bu2 on both surfaces of a core substrate 2, and a cross-sectional schematic view in FIG. It has the layer structure shown in the figure. If the “first built-up wiring layer Bu1” and the “second built-up wiring layer Bu2” constituting the multilayer printed wiring board 1 according to the present application satisfy the conditions described below, the third and subsequent layers are used. This built-up wiring layer can reduce “warping”, “twisting”, and “dimensional change” even if the preferred conditions described in the present invention are not satisfied.
  • FIG. 1 shows a configuration in which a skipped via 21 serving as an interlayer conduction means is provided as a layer configuration including two first built-up wiring layers Bu1 and second built-up wiring layers Bu2.
  • a skipped via 21 serving as an interlayer conduction means is provided as a layer configuration including two first built-up wiring layers Bu1 and second built-up wiring layers Bu2.
  • the core substrate 2 constituting the multilayer printed wiring board 1 according to the present application has an insulating layer thickness of 150 ⁇ m or less, and has inner layer circuits on both sides of the skeleton-containing insulating layer, and
  • the linear expansion coefficient in the XY direction of the insulating layer containing a skeleton material is preferably 0 ppm / ° C. to 20 ppm / ° C.
  • the lower limit of the linear expansion coefficient in the XY direction of the insulating layer containing the skeleton material is set to 0 ppm / ° C. even in consideration of the combination of the types of the insulating layer constituting resin 11 and the skeleton material 12 constituting the core substrate 2.
  • the “XY expansion coefficient in the XY direction” indicates that the expansion coefficient in the direction along one side when a square plate-like core substrate is assumed in plan view is expressed as “X direction line The expansion coefficient in the direction perpendicular to the one side is referred to as “Y-direction linear expansion coefficient”.
  • the measurement of the linear expansion coefficient in the XY direction of the skeleton material-containing insulating layer described above is performed by laminating copper foil on both surfaces of the skeleton material-containing insulating layer, and then etching and removing the copper foil to cure the sheet-like skeleton.
  • An insulating layer containing a material is obtained, and this is used as a sample, using a TMA test apparatus, and measured twice by the tensile load method at a temperature rising rate of 5 ° C./min. From the second measurement of room temperature to the glass transition temperature It is the value which calculated the average value of the linear expansion coefficient.
  • the core substrate 2 of the multilayer printed wiring board 1 usually includes inner layer circuits 22 on both sides thereof.
  • the inner layer circuit 22 and the copper circuit 23 of the first built-up wiring layer Bu1 located on the outer layer side of the core substrate 2 are used by being connected by any interlayer conduction means (not shown) such as a via hole or a through hole. It is done.
  • the core substrate 2 of the multilayer printed wiring board 1 has an insulating layer thickness of 150 ⁇ m or less. If the thickness of the insulating layer of the core substrate 2 exceeds 150 ⁇ m, the requirement for a thin printed wiring board cannot be satisfied, which is not preferable. Although the lower limit is not set here, 15 ⁇ m is considered as the lower limit at the present stage when considering the thinnest skeleton material 12. In consideration of the demand for thinner printed wiring boards in the market, the thickness of the core substrate 2 is 100 ⁇ m or less, more preferably 80 ⁇ m or less.
  • the skeleton material 12 can be made of glass cloth or glass nonwoven fabric used as a constituent material of the insulating layer of the printed wiring board, and there is no particular limitation on the material of the glass.
  • the insulating layer constituting resin 11 of the core substrate 2 an epoxy resin, a cyanate resin, a maleimide resin, a polyphenylene ether resin, a polybutadiene resin, an acrylate resin used as a constituent material of an insulating layer of a printed wiring board. Resin or the like can be used, and there is no particular limitation.
  • the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 are provided on the surface of the core substrate on which the inner layer circuit 22 is formed.
  • the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 constituting the multilayer printed wiring board according to the present application at this time have copper circuit layers 23 and 24 and an XY direction linear expansion coefficient.
  • Insulating resin layers 30 and 31 of 1 ppm / ° C. to 50 ppm / ° C.
  • the reason why the lower limit of the linear expansion coefficient in the XY direction of the insulating resin layers 30 and 31 is set to 1 ppm / ° C. is that it is difficult to make the lower limit of this value practically.
  • epoxy resin As the resin constituting the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 mentioned here, epoxy resin, cyanate resin, maleimide resin, polyphenylene ether resin, polyamide Resins, polyimide resins, polyamideimide resins, polybutadiene resins, acrylate resins, and the like can be used.
  • the measurement of the linear expansion coefficient in the XY direction of the built-up wiring layer described above is based on the above-described resin component used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2. Is used to manufacture two semi-cured resin layer-attached copper foils which will be described later, these resin surfaces are brought into contact with each other and laminated, and then the copper foil is etched away and cured sheet-like insulating resin layer And measured with the above-described TMA test apparatus and test conditions.
  • silica particles, hollow It is also preferable to contain silica particles, alumina particles, talc and the like. In this case, it is preferable to use a filler having an average particle diameter of 20 nm to 1 ⁇ m. At this time, although there is no special limitation in the lower limit of the average particle diameter of a filler, it is 20 nm in consideration of the actual state as an industrial product.
  • the filler is 30% by weight to the insulating resin layers 30 and 31. It is preferable to make it contain in 70 weight%.
  • the linear expansion coefficient in the XY direction of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 is adjusted. Is not preferable because it becomes difficult.
  • the filler content exceeds 70% by weight, it is difficult to embed an insulating resin layer containing the filler between the inner layer circuits provided in the core substrate.
  • the insulating resin layers 30 and 31 preferably have a tensile elastic modulus at 25 ° C. of 5 GPa to 10 GPa.
  • a tensile elastic modulus at 25 ° C. of the insulating resin layers 30 and 31 is less than 5 GPa, “warp”, “twist”, and “dimensional change” when the multilayer printed wiring board 1 is formed tend to increase. It is not preferable.
  • the tensile elastic modulus at 25 ° C. of the insulating resin layers 30 and 31 exceeds 10 GPa, the insulating resin layers 30 and 31 become brittle. Due to the “twist”, the tendency of the built-up wiring layer to crack during component mounting is increased, which is not preferable.
  • the “tensile elastic modulus at 25 ° C.” here refers to the measurement of the resin component used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2. Using the two semi-cured resin layer-attached copper foils, which will be described later, and laminating these resin surfaces in contact with each other, the copper foil was removed by etching, and a cured sheet-like insulating resin layer was obtained. This is a value measured using a viscoelasticity measuring device (DMA) as a sample.
  • DMA viscoelasticity measuring device
  • the relative dielectric constant of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application is 3.5 or less. Is preferred.
  • the reason why the relative permittivity is specified will be described. Considering the impedance control of a high-density printed wiring board in the case of using a high-frequency signal such as a mobile phone, good control of the crosstalk characteristics between layers is required. Factors affecting the crosstalk characteristics include the circuit width, the insulation distance between layers, the relative dielectric constant of the resin component used in the insulation layer, and the like.
  • the dielectric constant of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application is 3.5 or less.
  • the relative dielectric constants of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 are used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2.
  • the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application are specially adapted to the glass transition temperature (Tg) after curing.
  • the temperature is preferably less than 160 ° C.
  • the glass transition temperature (Tg) By setting the glass transition temperature (Tg) to less than 160 ° C., it tends to be low elasticity in the high temperature region of the insulating resin layers 30 and 31 and warpage is less likely to occur.
  • the “glass transition temperature” here is two sheets to be described later using the above-described resin components used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2.
  • the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application preferably have a thickness of 20 ⁇ m to 80 ⁇ m.
  • the thickness of the insulating resin layers 30 and 31 is less than 20 ⁇ m, it is difficult to ensure insulation, and “warp”, “twist”, and “dimensional change” tend to increase, which is preferable. Absent.
  • the thickness of the insulating resin layers 30 and 31 exceeds 80 ⁇ m, it becomes difficult to satisfy the requirement for a thin printed wiring board, and the thickness variation of the insulating resin layers 30 and 31 becomes large.
  • the thickness of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 is more preferably 50 ⁇ m or less in consideration of the demand for thinner printed wiring boards in the market. Preferably, it is 40 ⁇ m or less.
  • Multi-layer printed wiring board having 8 or more layers The multilayer printed wiring board according to the present application has 6 layers as the smallest layer structure, and a new built-up wiring layer is provided on the outer layer of the 6-layer multilayer printed wiring board.
  • the built-up wiring layer described below is preferably provided on the outermost layer of the multilayer printed wiring board having eight or more layers.
  • the built-up wiring layer disposed in the outermost layer preferably has an insulating resin layer constituting the built-up wiring layer having a low elasticity with a tensile elastic modulus at 25 ° C. of less than 5.0 GPa.
  • the reason why such an insulating resin layer having a low elastic modulus is employed is as follows. After mounting a component on a multilayer printed wiring board using a solder ball or the like, if the mounting board is accidentally dropped and collides with the floor surface, the mounting board receives a very strong drop impact.
  • the tensile elastic modulus is less than 5.0 GPa, even if it falls after it becomes a mounting board, it effectively prevents cracks, peeling of mounting parts, circuit disconnection, etc., and good drop resistance to the mounting board Can give performance.
  • the tensile elastic modulus is less than 3.5 GPa, the drop resistance performance of the mounting substrate is remarkably increased, and when the tensile elastic modulus is less than 3.0 GPa, the drop resistance performance is further improved. Almost no damage will occur even if dropped during handling.
  • the lower limit of the tensile elastic modulus is not described, it is about 0.1 GPa from experience. When the tensile elastic modulus is less than 0.1 GPa, the circuit at the mounting position is pushed in due to the pressure of the bonder used at the time of component mounting and is not preferable.
  • the insulating resin layer constituting the built-up wiring layer disposed in the outermost layer preferably has a breaking elongation of 5% or more.
  • the insulating resin layer constituting the built-up wiring layer becomes brittle, and even if the tensile elastic modulus is less than 5.0 GPa, the drop resistance performance of the mounting board described above varies. May occur.
  • the insulating resin layer constituting the built-up wiring layer has sufficient flexibility with respect to impact, and a good drop resistance performance tends to be obtained. Because there is.
  • epoxy resin that constitutes the insulating resin layer of the built-up wiring layer arranged in the outermost layer here, epoxy resin, cyanate resin, maleimide resin, polyphenylene ether resin, polyamide resin, polyimide resin, polyamideimide Resins, polybutadiene resins, acrylate resins, polyester resins, phenoxy resins, polyvinyl acetal resins, styrene-butadiene resins, and the like can be used.
  • the first method for producing a multilayer printed wiring board includes the following steps 1 to 3. Hereinafter, each process will be described with reference to FIGS.
  • Step 2 In this step, as shown in FIG. 3C, the semi-cured resin layer side 15 of the copper foil 50 with a semi-cured resin layer is brought into contact with the surface of the core substrate 2 shown in FIG. As shown in FIG. 3D, the first built-up layer 3 a composed of the insulating resin layer 30 and the copper foil layer 14 is formed on both surfaces of the core substrate 2.
  • the insulating resin layer 30 at this time has an XY direction linear expansion coefficient of 1 ppm / ° C. to 50 ppm / ° C., and the X direction linear expansion coefficient (Bx) value of the insulating resin layer and the Y direction.
  • the semi-cured resin layer-attached copper foil 50 is manufactured by applying a resin varnish for forming an insulating resin layer on the surface of the copper foil 14 and drying it.
  • the method for producing the semi-cured resin layer-attached copper foil 50 can be easily understood by those skilled in the art of producing printed wiring boards, and therefore description thereof using drawings is omitted.
  • Step 2 from the state shown in FIG. 3D, via hole processing, interlayer conductive plating processing, etching processing is performed on the copper foil layer 14 on the surface of the first built-up layer 3a as necessary. Etc., the circuit 23 is formed, and the first built-up wiring layer Bu1 is provided to obtain the first buildup wiring layer-equipped laminate 51 shown in FIG.
  • Step 3 In this step, the first unit step is repeated n 1 times (an integer of n 1 ⁇ 1) on the circuit forming surfaces on both surfaces of the first build-up wiring layer-equipped laminate 51, and the core A multilayer printed wiring board having (4 + 2n 1 ) built-up wiring layers on both sides of the substrate is obtained.
  • the 1st unit process here is "it makes the semi-hardened resin layer of the copper foil with the said semi-hardened resin layer contact
  • the first unit process corresponds to the process shown in FIGS. 4 (f) to 5 (h). That is, as shown in FIG. 4 (f), the semi-cured resin layer-attached copper foil 50 half of the circuit-forming surface of the first built-up wiring layer Bu 1 of the first build-up wiring layer-attached laminate 51.
  • the cured resin layer 15 is brought into contact with each other to form the second built-up layer 3b composed of the insulating resin layer 31 and the copper foil layer 14, and two layers are formed on both surfaces of the core substrate 2 as shown in FIG.
  • a multilayer copper clad laminate 52 having the first built-up wiring layer Bu1 and the second built-up layer 3b is obtained.
  • via hole processing, interlayer conductive plating processing, etching processing, or the like is performed on the copper foil layer 14 of the second built-up layer 3b on both surfaces of the multilayer copper clad laminate 52 shown in FIG.
  • the circuit 24 is formed to obtain the multilayer printed wiring board 1 provided with the second built-up wiring layer Bu2.
  • the interlayer via plating 20 is applied to form the skipped via 21
  • the first built-up wiring layer Bu1 on the inner layer side can be omitted, so that the first built-up This is preferable because the steps for forming the wiring layer Bu1 can be reduced.
  • n 1 times an integer of n 1 ⁇ 1
  • a multilayer printed wiring board 1 having (4 + 2n 1 ) built-up wiring layers on both surfaces of the core substrate is obtained. be able to.
  • the second method for manufacturing a multilayer printed wiring board is the above-described method for manufacturing a multilayer printed wiring board, and includes the following steps 1 to 4.
  • Steps 1 to 3 are the same as those in the first manufacturing method described above. Therefore, only the process 4 which is a different process will be described here, and a duplicate description will be omitted.
  • Step 4 In this step, the built-up on the outermost layer on both sides of the “multilayer printed wiring board having (4 + 2n 1 ) built-up wiring layers on both sides of the core substrate” obtained in Step 3 of the first manufacturing method.
  • a multilayer printed wiring board provided with a built-up wiring layer provided with an insulating resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa on the outermost layer with respect to the circuit forming surface of the wiring layer is obtained.
  • n 2 times an integer of n 2 ⁇ 1
  • a built-up wiring layer having a ⁇ 4 + 2 (n 1 + n 2 ) ⁇ layer structure is provided on both surfaces of the core substrate. Can do.
  • the manufacturing process of the second unit process is the same as the manufacturing process of the first unit process.
  • the copper foil with a semi-cured resin layer used for forming the built-up layer is different. That is, for the semi-cured resin layer of the copper foil with a semi-cured resin layer used in the second unit process, a material having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing is used. A built-up layer composed of a foil layer is formed. Therefore, from the state shown in FIG. 5 (h), a semi-cured resin layer of a semi-cured resin layer-attached copper foil is laminated on both sides, a circuit 25 is formed, and a third built-up wiring layer Bu3 is provided. A multilayer printed wiring board 1 shown in i) is obtained. At this time, the tensile elastic modulus at 25 ° C. of the insulating resin layer 32 of the third built-up wiring layer Bu3 is less than 5.0 GPa.
  • Example 1 a multilayer printed wiring board having 10 layers as shown in FIG. 6 was manufactured through the following steps.
  • Step 1 In Example 1, a copper-clad laminate (copper foil thickness: 18 ⁇ m, insulating layer thickness: 60 ⁇ m, insulating layer) provided with copper foil on both sides of the insulating layer in the state shown in FIG. : Containing glass cloth, X-direction linear expansion coefficient was 14.0 ppm / ° C., and Y-direction linear expansion coefficient was 12.0 ppm / ° C.). And the copper foil of the outer layer of the said copper clad laminated board is etched, the predetermined inner layer circuit 22 is formed on both surfaces, and the core substrate whose thickness of an insulating layer is 150 micrometers or less as shown in FIG.2 (b) 2 was obtained.
  • Step 2 In this step 2, as shown in FIG. 3C, a copper foil 50 with a semi-cured resin layer (thickness: 30 ⁇ m, copper foil thickness: 18 ⁇ m, semi-cured resin layer: epoxy resin is used.
  • the semi-cured resin layer side 15 of the formed resin film) is brought into contact with and laminated on the surface of the core substrate 2 shown in FIG. 2B, and insulated on both surfaces of the core substrate 2 as shown in FIG.
  • a first built-up layer 3a composed of the resin layer 30 and the copper foil layer 14 was formed.
  • the insulating resin layer of the first built-up layer 3a has an XY direction linear expansion coefficient of 39 ppm / ° C., an X direction linear expansion coefficient (Bx) value of the insulating resin layer, and a Y direction linear expansion coefficient (By).
  • Bx X direction linear expansion coefficient
  • By Y direction linear expansion coefficient
  • Step 2 from the state shown in FIG. 3D, via hole processing, interlayer conductive plating processing, etching processing is performed on the copper foil layer 14 on the surface of the first built-up layer 3a as necessary.
  • the first built-up wiring layer Bu1 having the circuit 23 was obtained, and the first laminated board 51 with the build-up wiring layer shown in FIG.
  • Step 3 In this step 3, a copper foil with a semi-cured resin layer similar to that used for forming the first built-up layer 3a is formed on the circuit forming surfaces on both sides of the laminate 51 with the first build-up wiring layer. 50, the above-mentioned first unit process is repeated twice to provide two layers of the second built-up wiring layer Bu2 and the third built-up wiring layer Bu3, and the built-up wiring layers on both surfaces of the core substrate 2. An eight-layer multilayer printed wiring board comprising Bu1 to Bu3 was obtained.
  • Step 4 In Step 4, the tensile modulus at 25 ° C. after curing on the circuit formation surface of the third built-up wiring layer Bu3 in the outermost layer of the eight-layer multilayer printed wiring board obtained in Step 3 Using the copper foil with a semi-cured resin layer (thickness: 40 ⁇ m, copper foil thickness: 18 ⁇ m) provided with a semi-cured resin layer having a thickness of less than 5.0 GPa, the second unit step is performed once, By providing the built-up wiring layer Bu4, 10 layers of the built-up wiring layers Bu1 to Bu4 are provided on both surfaces of the core substrate, and the outermost layer is provided with an insulating resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa. A 10-layer multilayer printed wiring board provided with a built-up wiring layer was obtained. The circuit provided on the 10-layer multilayer printed wiring board formed a test circuit pattern that imitated a high-density wiring circuit.
  • the 10-layer multilayer printed wiring board obtained here was divided into four to obtain a measurement sample of 12 cm ⁇ 12 cm, and this was measured for the amount of warpage with a Thermoire AXP manufactured by Akrometric.
  • the amount of warpage is 4 measurement samples at each temperature shown in Table 1 in the heating process from 30 ° C. to 260 ° C. and the cooling process from 260 ° C. to 30 ° C. of each measurement sample obtained by dividing into 4 parts.
  • the amount of warpage was measured. Of these four measured values, the measurement data with the least warpage (indicated as “highest data” in Table 1) and the measurement data with the most warpage (in Table 1, “ “Minimum data” is displayed in Table 1. The same applies to the following examples and comparative examples.
  • Example 2 a multilayer printed wiring board having 10 layers as shown in FIG. 6 was manufactured through Steps 1 to 4 similar to Example 1, and the amount of warpage was measured in the same manner as Example 1. Therefore, only different parts will be described.
  • Example 2 a copper foil 50 with a semi-cured resin layer (thickness: 30 ⁇ m, copper foil thickness: 18 ⁇ m, semi-cured resin layer: a resin formed using an epoxy resin, a cyanate resin, and a bismaleimide resin
  • Comparative Example 1 In Comparative Example 1, a 10-layer multilayer printed wiring board similar to that in Example 1 and Example 2 was manufactured, and the amount of warpage was measured in the same manner as in Example 1.
  • Comparative Example 1 a prepreg including a glass cloth having a thickness of 20 ⁇ m as a skeleton material on both surfaces of the core substrate 2 used in Example 1 (thickness that becomes 30 ⁇ m after lamination), a copper foil having a thickness of 18 ⁇ m, The process of forming a test circuit pattern was repeated four times to produce a 10-layer multilayer printed wiring board in which all of the insulating layer was composed of prepreg.
  • the insulating resin layer composed of this prepreg has an X-direction linear expansion coefficient of 14 ppm / ° C., a Y-direction linear expansion coefficient of 12 ppm / ° C., a value of the X-direction linear expansion coefficient (Bx) and a Y-direction linear expansion coefficient (By).
  • the ratio of [Bx] / [By] 1.2, the X-direction tensile elastic modulus at 25 ° C. was 24 GPa.
  • the Y-direction tensile elastic modulus was 22 GPa, and the relative dielectric constant was 4.6.
  • Comparative Example 2 In Comparative Example 2, a 10-layer multilayer printed wiring board similar to Example 1 and Example 2 was manufactured, and the amount of warpage was measured in the same manner as in Example 1.
  • Example 2 the copper with a semi-cured resin layer provided with a semi-cured resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing was used for forming the outermost layer of Example 1 and Example 2.
  • a foil thickness: 40 ⁇ m, copper foil thickness: 18 ⁇ m
  • the copper foil with a semi-cured resin layer is laminated on both surfaces of the core substrate 2 used in Example 1 to form a test circuit pattern. This process was repeated four times to produce a 10-layer multilayer printed wiring board.
  • the warpage amount measurement sample obtained in Comparative Example 2 had a warpage of 1.0 mm or more immediately after production, and thus the warpage amount was not measured in the temperature rising / falling process.
  • Example 1 the amount of warpage between Example and Comparative Example 1 is compared.
  • the 10-layer multilayer printed wiring board in which all of the insulating layers of Comparative Example 1 are composed of prepregs has the least warpage. It can be seen that the variation in warpage is small because the standard deviation is also small. However, when looking at the lowest data with the largest amount of warpage between the example and the comparative example 1, this relationship is reversed.
  • the amount of warpage of the minimum data in Example 1 the maximum value was 164 ⁇ m, the minimum value was 126 ⁇ m, the average value was 140 ⁇ m, and the standard deviation was 13.4 ⁇ m.
  • the amount of warpage of the lowest data in Example 2 was as follows: highest value 191 ⁇ m, lowest value 124 ⁇ m, average value 156 ⁇ m, and standard deviation 18.8 ⁇ m.
  • the maximum value is 227 ⁇ m
  • the minimum value is 145 ⁇ m
  • the average value is 164 ⁇ m
  • the standard deviation is 25.2 ⁇ m. Therefore, when looking at the lowest data with the largest amount of warpage, the 10-layer multilayer printed wiring board in which all of the insulating layers of Comparative Example 1 are made of prepreg has the largest warpage, the large standard deviation, and the large variation in warpage. I can judge.
  • the multilayer printed wiring board according to the present application has less “warping”, “twist”, and “dimensional change” and less variation than the conventional multilayer printed wiring board having a built-up wiring layer. An error can be assumed in advance, and problems in the manufacturing process are less likely to occur. Therefore, the multilayer printed wiring board according to the present application can be easily mounted and can be supplied to the market as a high-quality printed wiring board. Moreover, since the manufacturing method of the multilayer printed wiring board which concerns on this application can use the conventional built-up manufacturing method as it is, it is excellent in the effective utilization of the existing installation.

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Abstract

The purpose of the present invention is to provide a multilayer printed circuit board which mitigates the problems of "warping," "twisting" and "changing size" seen in printed circuit boards obtained by the conventional build-up method, and to provide a manufacturing method thereof. In order to achieve this purpose, a multilayer printed circuit board is adopted which is provided with two more build-up wiring layers on both sides of a core substrate, wherein said core substrate is provided with an inner layer circuit on both sides of the skeletal material-containing insulation layer, the insulation layer being 150μm thick or less, wherein the X-Y direction linear expansion coefficient of the skeletal material-containing insulation layer is 0ppm/°C-20ppm/°C, a first build-up wiring layer and a second build-up wiring layer provided on both sides of the core substrate comprise a copper circuit layer and an insulating resin layer having a X-Y direction linear expansion coefficient of 1ppm/°C-50ppm/°C, and the relation holds that the ratio of the value of the X-direction linear expansion coefficient (Bx) and the value of the Y-direction linear expansion coefficient (By) of the insulating resin layer is 0.9-1.1.

Description

多層プリント配線板及びその製造方法Multilayer printed wiring board and manufacturing method thereof
　本件発明は、多層プリント配線板及びその製造方法に関する。特には、ビルトアップ法により製造した多層プリント配線板に関する。 The present invention relates to a multilayer printed wiring board and a manufacturing method thereof. In particular, the present invention relates to a multilayer printed wiring board manufactured by a built-up method.
　従来から、多層プリント配線板は、信号伝達速度を速くし、プリント配線板としての搭載面積を小さくすると言う目的等を達成するため、広く使用されてきた。この多層プリント配線板は、種々の電子部品を実装して使用されるものである。この多層プリント配線板への電子部品の実装は、半田リフロー法、ワイヤーボンディング法等の種々の方法が使用される。このとき多層プリント配線板に、「反り」・「捻れ」・「寸法変化」があると、良好な電子部品の実装ができず好ましくない。特に、多層プリント配線板の製造方法としてビルトアップ法を用いたとき、加工途中においても、「反り」・「捻れ」・「寸法変化」が発生しやすいため、これらの現象を解消するための種々の技術が提唱されてきた。以下、このような先行技術を例示する。 Conventionally, multilayer printed wiring boards have been widely used to achieve the purpose of increasing the signal transmission speed and reducing the mounting area as a printed wiring board. This multilayer printed wiring board is used by mounting various electronic components. Various methods such as a solder reflow method and a wire bonding method are used for mounting electronic components on the multilayer printed wiring board. At this time, if the multilayer printed wiring board has “warp”, “twist”, and “dimensional change”, it is not preferable because good electronic components cannot be mounted. In particular, when the built-up method is used as a manufacturing method for multilayer printed wiring boards, “warping”, “twisting”, and “dimensional change” are likely to occur even during processing. Technology has been advocated. Such prior art will be exemplified below.
　特許文献１（特開平１１－２６１２２８号公報）には、Ｘ－Ｙ方向およびＺ方向の寸法変化が小さく、表面のうねりおよび反りの少ない多層プリント配線板の提供を目的として、「コア基板に層間樹脂絶縁層と導体層を交互に積層されてなる多層プリント配線板において、コア基板を、ガラス布等の低熱膨張繊維の布にビスマレイミドトリアジン樹脂を含浸した厚さ０．１５ｍｍ以下のプリプレグを６層以上積層して形成する。このとき樹脂含浸プリプレグの１枚あたり厚みを薄くして、枚数を増やすことにより、プリプレグを積層してなるコア基板、即ち、多層プリント配線板のＸ－Ｙ方向の寸法変化、反りを防止する。」という手法を開示している。 Patent Document 1 (Japanese Patent Application Laid-Open No. 11-261228) describes “a core substrate with an interlayer” for the purpose of providing a multilayer printed wiring board with small dimensional changes in the XY direction and Z direction and less surface waviness and warpage. In a multilayer printed wiring board in which a resin insulating layer and a conductor layer are alternately laminated, a prepreg having a thickness of 0.15 mm or less in which a core substrate is impregnated with a bismaleimide triazine resin in a low thermal expansion fiber cloth such as a glass cloth. At this time, by reducing the thickness per sheet of the resin-impregnated prepreg and increasing the number of sheets, the core substrate in which the prepreg is laminated, that is, the multilayer printed wiring board in the XY direction is formed. The technique of preventing dimensional change and warping is disclosed.
　特許文献２（特開２００３－０８６９４１号公報）には、熱履歴による反りの発生を低減することができると共に、最外層の導体層をファインパターンで形成することが容易になるプリント配線板の提供を目的として、「内層回路基板の表面に複数層の絶縁樹脂層と導体層とを交互にビルドアップして設けることによって形成されるプリント配線板において、最外層の絶縁樹脂層はガラスクロスを基材として含有しない樹脂主体の層として形成されていると共に、最外層から２層目の絶縁樹脂層はガラスクロスを基材として含有する層として形成されていることを特徴とするプリント配線板。」を採用している。 Patent Document 2 (Japanese Patent Application Laid-Open No. 2003-086941) provides a printed wiring board that can reduce the occurrence of warping due to thermal history and can easily form the outermost conductor layer with a fine pattern. In the printed wiring board formed by alternately building up a plurality of insulating resin layers and conductor layers on the surface of the inner layer circuit board, the outermost insulating resin layer is based on glass cloth. A printed wiring board characterized in that it is formed as a resin-based layer not contained as a material, and the second insulating resin layer from the outermost layer is formed as a layer containing glass cloth as a base material. Is adopted.
　特許文献３（特開２００４－３４２８２７号公報）には、ＩＶＨ内に樹脂が充填され、樹脂層のみでビルドアップ積層された多層プリント配線板に比べて反り・捻れが小さく、弾性率の高いものが得られ、プリプレグのみで作製された多層プリント配線板に比べて、表面凹凸に優れ、耐熱性、耐マイグレーション性に優れたプリント配線板を得ることを目的として、「ＩＶＨを有する内層板の表裏に有機フィルム基材樹脂組成物或いは基材補強のない樹脂組成物層を形成してＩＶＨの充填を行い、少なくとも最外層は繊維不織布基材補強の樹脂組成物層が形成された構造のプリント配線板とする。」製造方法を採用している。 Patent Document 3 (Japanese Patent Application Laid-Open No. 2004-342827) discloses that a resin is filled in IVH and has less warping / twisting and a higher elastic modulus than a multilayer printed wiring board that is built up and laminated only by a resin layer. For the purpose of obtaining a printed wiring board having excellent surface irregularities, heat resistance, and migration resistance as compared with a multilayer printed wiring board produced only with a prepreg, the front and back of the inner layer board having IVH A printed wiring having a structure in which an organic film base resin composition or a resin composition layer without base material reinforcement is formed and filled with IVH, and at least the outermost layer is a fiber nonwoven base material reinforcing resin composition layer. A manufacturing method is adopted.
　特許文献４（特開２００８－３０７８８６号公報）には、反りを低減した金属張り積層板と多層積層板の製造方法を提供することを目的として、「プリプレグに金属箔を配置して形成される積層体を、所定の成形温度および所定の第１成形圧力で加熱加圧する第１工程と、前記第１工程による前記加熱加圧後における所定の時点から少なくとも５分間以上の期間、圧力比が前記第１成形圧力の０．４以下である第２成形圧力で前記積層体を加圧しつつ、前記積層体の温度を、前記プリプレグが最低溶融粘度となる温度より５℃低い温度以上に保持する第２工程と、前記所定の時点から３０分以上経過した後、前記積層体を冷却して成形する第３工程とを含むことを特徴とする金属張り積層板の製造方法。」を採用する事が開示されている。 Patent Document 4 (Japanese Patent Application Laid-Open No. 2008-307886) discloses that “a metal foil is disposed on a prepreg and formed for the purpose of providing a method for producing a metal-clad laminate and a multilayer laminate with reduced warpage. A first step of heating and pressurizing the laminated body at a predetermined molding temperature and a predetermined first molding pressure, and a pressure ratio of at least 5 minutes from a predetermined time after the heating and pressurizing by the first step While pressing the laminate at a second molding pressure that is 0.4 or less of the first molding pressure, the temperature of the laminate is maintained at a temperature that is 5 ° C. lower than the temperature at which the prepreg has the lowest melt viscosity. It includes two steps and a third step of cooling and forming the laminated body after 30 minutes or more have passed since the predetermined time point. It is disclosed.
特開平１１－２６１２２８号公報Japanese Patent Laid-Open No. 11-261228 特開２００３－０８６９４１号公報Japanese Patent Laid-Open No. 2003-086941 特開２００４－３４２８２７号公報JP 2004-342827 A 特開２００８－３０７８８６号公報JP 2008-307886 A
　しかしながら、上述の特許文献１～特許文献４のいずれに開示の発明に関しても、実操業の中での種々の問題があり、且つ、多層プリント配線板の「反り」・「捻れ」・「寸法変化」の各問題を完全に解決できていないとの指摘があった。上述の各引用文献に開示の発明の問題点を考えると、以下のようになる。 However, the inventions disclosed in any of the above-mentioned Patent Documents 1 to 4 have various problems in actual operation, and “warping”, “twisting”, “dimension change” of the multilayer printed wiring board. "It was pointed out that each of the problems could not be solved completely. Considering the problems of the invention disclosed in each of the above cited references, the following is obtained.
　特許文献１に開示の技術では、「プリプレグを６層以上積層して形成する。｝という制約があり、多層プリント配線板のＺ方向の層構成に制約があるため、多層プリント配線板のＸ－Ｙ方向の寸法変化、反りを防止することはできても、Ｚ方向の厚さを薄くするには一定の限界があった。 In the technique disclosed in Patent Document 1, there is a restriction that “the prepreg is formed by stacking six or more layers.” And the layer configuration in the Z direction of the multilayer printed wiring board is restricted. Although the dimensional change and warpage in the Y direction can be prevented, there is a certain limit to reducing the thickness in the Z direction.
　また、特許文献２に開示の技術によれば、ビルドアップ法で得られるプリント配線板において、「最外層の絶縁樹脂層はガラスクロスを基材として含有しない樹脂主体の層として形成されていること」及び「最外層から２層目の絶縁樹脂層はガラスクロスを基材として含有する層として形成されていること」の２条件を満たす必要がある。 Moreover, according to the technique disclosed in Patent Document 2, in the printed wiring board obtained by the build-up method, “the outermost insulating resin layer is formed as a resin-based layer not containing glass cloth as a base material. And “the second insulating resin layer from the outermost layer is formed as a layer containing glass cloth as a base material” must be satisfied.
　特許文献３に開示の技術によれば、「ＩＶＨを有する内層板の表裏に有機フィルム基材樹脂組成物或いは基材補強のない樹脂組成物層を形成した後にＩＶＨの充填を行うこと。」、及び、「少なくとも最外層は繊維不織布基材補強の樹脂組成物層が形成していること。」の２条件を満たす必要がある。 According to the technique disclosed in Patent Document 3, “filling with IVH after forming an organic film base resin composition or a resin composition layer without base reinforcement on the front and back of the inner layer plate having IVH”, And it is necessary to satisfy the two conditions of “at least the outermost layer is formed of a resin composition layer for reinforcing a nonwoven fabric substrate”.
　更に、特許文献４に開示の技術によれば、「前記第１工程による前記加熱加圧後における所定の時点から少なくとも５分間以上の期間、圧力比が前記第１成形圧力の０．４以下である第２成形圧力で前記積層体を加圧しつつ、前記積層体の温度を、前記プリプレグが最低溶融粘度となる温度より５℃低い温度以上に保持する第２工程と、・・・」とあるように、製造工程が複雑化し、得られる製品の品質にばらつきが発生しやすくなる。 Further, according to the technique disclosed in Patent Document 4, “the pressure ratio is 0.4 or less of the first molding pressure for a period of at least 5 minutes from the predetermined time point after the heating and pressurizing in the first step. There is a second step in which the temperature of the laminate is maintained at a temperature 5 ° C. lower than the temperature at which the prepreg has the lowest melt viscosity while pressing the laminate at a certain second molding pressure. As described above, the manufacturing process becomes complicated, and the quality of the product obtained tends to vary.
　以上のことから理解できるように、従来のビルトアップ法を用いて得られる多層プリント配線板の「反り」・「捻れ」・「寸法変化」という現象を低減し、且つ、これらの現象のばらつきの少ない多層プリント配線板、及び、その製造方法の簡略化が望まれてきた。 As can be understood from the above, the phenomenon of "warping", "twisting", and "dimensional change" of the multilayer printed wiring board obtained by using the conventional built-up method is reduced, and variations in these phenomena are reduced. There has been a demand for a simplified multilayer printed wiring board and a manufacturing method thereof.
　そこで、鋭意研究の結果、本件発明者等は、単なる製造方法の変更、多層プリント配線板の層構成の変更では、ビルトアップ法を用いて得られる多層プリント配線板の「反り」・「捻れ」・「寸法変化」を、ばらつき無く抑制することは困難との認識に達した。その結果、以下の技術思想を採用することで、当該多層プリント配線板に軽度の「反り」・「捻れ」・「寸法変化」があったとしても、プリント配線板製品間におけるばらつきを少なくできることに想到した。以下、本件出願に係る発明の概要に関して述べる。 Therefore, as a result of diligent research, the inventors of the present invention simply changed the manufacturing method, or changed the layer configuration of the multilayer printed wiring board, so that the multilayer printed wiring board obtained by using the built-up method was warped and twisted.・ Recognized that it is difficult to suppress “dimensional changes” without variation. As a result, by adopting the following technical concept, it is possible to reduce variations among printed wiring board products even if the multilayer printed wiring board has slight “warping”, “twist”, and “dimensional change”. I thought. The outline of the invention related to the present application will be described below.
１．多層プリント配線板
　本件出願に係る多層プリント配線板は、コア基板の両面に２層以上のビルトアップ配線層を設けた多層プリント配線板において、当該多層プリント配線板を構成する当該コア基板は、絶縁層の厚さが１５０μｍ以下であり、骨格材入り絶縁層の両面に内層回路を備え、且つ、当該骨格材入り絶縁層のＸ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃であり、当該コア基板の両面に設ける第１ビルトアップ配線層及び当該第１ビルトアップ配線層の表面に設ける第２ビルトアップ配線層は、銅回路層と、Ｘ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃の絶縁樹脂層とからなり、且つ、当該絶縁樹脂層のＸ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値が、［Ｂｘ］／［Ｂｙ］＝０．９～１．１の関係を満たすことを特徴とする。 1. Multilayer printed wiring board The multilayer printed wiring board according to the present application is a multilayer printed wiring board in which two or more built-up wiring layers are provided on both sides of the core board, and the core board constituting the multilayer printed wiring board is insulated. The layer thickness is 150 μm or less, the inner layer circuit is provided on both surfaces of the skeleton material-containing insulating layer, and the XY direction linear expansion coefficient of the skeleton material-containing insulating layer is 0 ppm / ° C. to 20 ppm / ° C. The first built-up wiring layer provided on both surfaces of the core substrate and the second built-up wiring layer provided on the surface of the first built-up wiring layer have a copper circuit layer and an XY direction linear expansion coefficient of 1 ppm / ° C. It consists of an insulating resin layer of 50 ppm / ° C., and the value of the X direction linear expansion coefficient (Bx) and the Y direction linear expansion coefficient (By) of the insulating resin layer is [Bx] / [By] = 0. .9-1.1 relationship Characterized in that the plus.
　本件出願に係る多層プリント配線板の前記第１ビルトアップ配線層及び第２ビルトアップ配線層を構成する絶縁樹脂層は、２５℃における引張弾性率が５ＧＰａ～１０ＧＰａであることが好ましい。 The insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer of the multilayer printed wiring board according to the present application preferably has a tensile elastic modulus at 25 ° C. of 5 GPa to 10 GPa.
　本件出願に係る多層プリント配線板の前記第１ビルトアップ配線層及び第２ビルトアップ配線層を構成する絶縁樹脂層は、厚さが２０μｍ～８０μｍであることが好ましい。 The insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer of the multilayer printed wiring board according to the present application preferably has a thickness of 20 μm to 80 μm.
　本件出願に係る多層プリント配線板の前記第１ビルトアップ配線層及び第２ビルトアップ配線層を構成する絶縁樹脂層は、比誘電率が３．５以下であることが好ましい。 It is preferable that the dielectric constant of the insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer of the multilayer printed wiring board according to the present application is 3.5 or less.
　本件出願に係る多層プリント配線板の最外層に、２５℃における引張弾性率が５．０ＧＰａ未満の絶縁樹脂層を備えるビルトアップ配線層を設けることが好ましい。 It is preferable to provide a built-up wiring layer including an insulating resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa on the outermost layer of the multilayer printed wiring board according to the present application.
２．多層プリント配線板の製造方法
　本件出願に係る多層プリント配線板の製造方法は、以下の２つの製造方法の概念を含んでいる。よって、第１製造方法と第２製造方法と称する。 2. 2. Manufacturing method of multilayer printed wiring board The manufacturing method of the multilayer printed wiring board concerning this application includes the concept of the following two manufacturing methods. Therefore, they are referred to as a first manufacturing method and a second manufacturing method.
＜第１製造方法＞
　この第１製造方法は、以下の工程１～工程３を備えることを特徴とする上述の多層プリント配線板の製造方法である。 <First manufacturing method>
This first manufacturing method is the above-described method for manufacturing a multilayer printed wiring board, comprising the following steps 1 to 3.
工程１：　絶縁層の厚さが１５０μｍ以下であり、Ｘ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃の骨格材入り絶縁層の表面に銅箔層を備える銅張積層板を用いて、内層回路を形成して、コア基板を得る。
工程２：　銅箔の表面に、硬化後の絶縁樹脂層のＸ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃となる半硬化樹脂層を形成した半硬化樹脂層付銅箔を用いて、当該半硬化樹脂層付銅箔の半硬化樹脂層側を、前記コア基板の両面に当接させ積層し、回路形成を行うことで第１ビルドアップ配線層付積層板を得る。
工程３：　第１ビルドアップ配線層付積層板の表面に、当該半硬化樹脂層付銅箔の半硬化樹脂層を当接させ、絶縁樹脂層と銅箔層とからなるビルトアップ層を更に形成し、回路形成を行う操作を第１単位工程として、当該第１ビルドアップ配線層付積層板の両面に対して、この第１単位工程をｎ１回（ｎ１≧１の整数）繰り返して行い、コア基板の両面に（４＋２ｎ１）層の層構成のビルトアップ層を備える多層プリント配線板を得る。 Step 1: Using a copper clad laminate having a copper foil layer on the surface of a skeleton-containing insulating layer having an insulating layer thickness of 150 μm or less and an XY direction linear expansion coefficient of 0 ppm / ° C. to 20 ppm / ° C. Then, an inner layer circuit is formed to obtain a core substrate.
Step 2: Using a copper foil with a semi-cured resin layer in which a semi-cured resin layer having an XY linear expansion coefficient of 1 ppm / ° C. to 50 ppm / ° C. is formed on the surface of the copper foil. Then, the semi-cured resin layer side of the copper foil with the semi-cured resin layer is brought into contact with both surfaces of the core substrate and laminated to obtain a first laminated board with a build-up wiring layer.
Step 3: The semi-cured resin layer of the copper foil with the semi-cured resin layer is brought into contact with the surface of the laminate with the first build-up wiring layer to further form a built-up layer composed of an insulating resin layer and a copper foil layer. Then, an operation for forming a circuit is set as a first unit process, and this first unit process is repeated n 1 times (an integer of n 1 ≧ 1) on both surfaces of the laminated board with the first buildup wiring layer. Then, a multilayer printed wiring board having (4 + 2n 1 ) layer built-up layers on both surfaces of the core substrate is obtained.
＜第２製造方法＞
　この第２製造方法は、以下の工程１～工程４を備えることを特徴とする上述の多層プリント配線板の製造方法である。 <Second manufacturing method>
This second manufacturing method is a method for manufacturing a multilayer printed wiring board as described above, comprising the following steps 1 to 4.
工程１：　絶縁層の厚さが１５０μｍ以下であり、Ｘ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃の骨格材入り絶縁層の表面に銅箔層を備える銅張積層板を用いて、内層回路を形成して、コア基板を得る。
工程２：　銅箔の表面に、硬化後の絶縁樹脂層のＸ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃となる半硬化樹脂層を形成した半硬化樹脂層付銅箔を用いて、当該半硬化樹脂層付銅箔の半硬化樹脂層側を、前記コア基板の両面に当接させ積層し、回路形成を行うことで第１ビルドアップ配線層付積層板を得る。
工程３：　第１ビルドアップ配線層付積層板の表面に、当該半硬化樹脂層付銅箔の半硬化樹脂層を当接させ、絶縁樹脂層と銅箔層とからなるビルトアップ層を更に形成し、回路形成を行う操作を第１単位工程として、当該第１ビルドアップ配線層付積層板の両面に対して、この第１単位工程をｎ１回（ｎ１≧１の整数）繰り返して行い、コア基板の両面に（４＋２ｎ１）層のビルトアップ配線層を備える多層プリント配線板を得る。
工程４：　当該第１単位工程を用いて形成した（４＋２ｎ１）層のビルトアップ配線層の表面に、硬化後に２５℃における引張弾性率が５．０ＧＰａ未満となる半硬化樹脂層を形成した半硬化樹脂層付銅箔を用いて、当該半硬化樹脂層付銅箔の半硬化樹脂層側を当接させ積層し、回路形成を行う操作を第２単位工程として、この第２単位工程をｎ２回（ｎ２≧１の整数）繰り返して行い、コア基板の両面に{４＋２（ｎ１＋ｎ２）}層の層構成のビルトアップ層を備え、且つ、最外層に２５℃における引張弾性率が５．０ＧＰａ未満の絶縁樹脂層を備えるビルトアップ配線層を配した多層プリント配線板を得る。 Step 1: Using a copper clad laminate having a copper foil layer on the surface of a skeleton-containing insulating layer having an insulating layer thickness of 150 μm or less and an XY direction linear expansion coefficient of 0 ppm / ° C. to 20 ppm / ° C. Then, an inner layer circuit is formed to obtain a core substrate.
Step 2: Using a copper foil with a semi-cured resin layer in which a semi-cured resin layer having an XY linear expansion coefficient of 1 ppm / ° C. to 50 ppm / ° C. is formed on the surface of the copper foil. Then, the semi-cured resin layer side of the copper foil with the semi-cured resin layer is brought into contact with both surfaces of the core substrate and laminated to obtain a first laminated board with a build-up wiring layer.
Step 3: The semi-cured resin layer of the copper foil with the semi-cured resin layer is brought into contact with the surface of the laminate with the first build-up wiring layer to further form a built-up layer composed of an insulating resin layer and a copper foil layer. Then, an operation for forming a circuit is set as a first unit process, and this first unit process is repeated n 1 times (an integer of n 1 ≧ 1) on both surfaces of the laminated board with the first buildup wiring layer. A multilayer printed wiring board having (4 + 2n 1 ) built-up wiring layers on both surfaces of the core substrate is obtained.
Step 4: A semi-cured resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing is formed on the surface of the (4 + 2n 1 ) layer of the built-up wiring layer formed using the first unit step. Using the copper foil with a cured resin layer, the second unit process is defined as an operation in which the semi-cured resin layer side of the copper foil with the semi-cured resin layer is brought into contact with each other to perform circuit formation. carried out twice (n 2 ≧ 1 integer) repeatedly, with a built-up layer of the layer structure of both sides of the core substrate {4 + 2 (n 1 + n 2)} layer, and a tensile modulus at 25 ° C. in the outermost layer A multilayer printed wiring board having a built-up wiring layer provided with an insulating resin layer of less than 5.0 GPa is obtained.
　本件出願に係る多層プリント配線板は、当該コア基板の絶縁層のＸ－Ｙ方向線膨張率と、その両面に設けるビルトアップ配線層を構成する絶縁樹脂層のＸ－Ｙ方向線膨張率とが、上述の条件及び関係を捉えることで、コア基板の両面に２層以上のビルトアップ配線層を備える多層プリント配線板の「反り」・「捻れ」・「寸法変化」を、ばらつき無く確実に低減したものとなる。 In the multilayer printed wiring board according to the present application, the linear expansion coefficient in the XY direction of the insulating layer of the core substrate and the linear expansion coefficient in the XY direction of the insulating resin layer constituting the built-up wiring layer provided on both surfaces thereof are obtained. By grasping the above-mentioned conditions and relationships, “warping”, “twisting”, and “dimensional change” of multilayer printed wiring boards with two or more built-up wiring layers on both sides of the core substrate can be reliably reduced without variation. Will be.
本件出願に係る多層プリント配線板の模式断面図である。It is a schematic cross section of the multilayer printed wiring board according to the present application. 本件出願に係る多層プリント配線板の製造工程を説明するための模式図である。It is a schematic diagram for demonstrating the manufacturing process of the multilayer printed wiring board which concerns on this application. 本件出願に係る多層プリント配線板の製造工程を説明するための模式図である。It is a schematic diagram for demonstrating the manufacturing process of the multilayer printed wiring board which concerns on this application. 本件出願に係る多層プリント配線板の製造工程を説明するための模式図である。It is a schematic diagram for demonstrating the manufacturing process of the multilayer printed wiring board which concerns on this application. 本件出願に係る多層プリント配線板の製造工程を説明するための模式図である。It is a schematic diagram for demonstrating the manufacturing process of the multilayer printed wiring board which concerns on this application. 本件出願に係る８層の多層プリント配線板の模式断面図である。It is a schematic cross section of an eight-layer multilayer printed wiring board according to the present application.
　以下、本件出願に係る多層プリント配線板の形態と、本件出願に係る多層プリント配線板の製造方法の形態に関して述べる。 Hereinafter, the form of the multilayer printed wiring board according to the present application and the form of the method for manufacturing the multilayer printed wiring board according to the present application will be described.
１．多層プリント配線板の形態
　本件出願に係る多層プリント配線板１は、コア基板２の両面に２層以上の第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を備え、図１に断面模式図として示す層構成を備えている。この本件出願に係る多層プリント配線板１を構成する「第１ビルトアップ配線層Ｂｕ１」と「第２ビルトアップ配線層Ｂｕ２」とが、以下に述べる条件を満たしていれば、第３層目以降のビルトアップ配線層が、本件発明で言う好ましい条件を満たしていなくとも、「反り」・「捻れ」・「寸法変化」を低減することが可能となる。 1. Form of Multilayer Printed Wiring Board A multilayer printed wiring board 1 according to the present application includes two or more first built-up wiring layers Bu1 and second built-up wiring layers Bu2 on both surfaces of a core substrate 2, and a cross-sectional schematic view in FIG. It has the layer structure shown in the figure. If the “first built-up wiring layer Bu1” and the “second built-up wiring layer Bu2” constituting the multilayer printed wiring board 1 according to the present application satisfy the conditions described below, the third and subsequent layers are used. This built-up wiring layer can reduce “warping”, “twisting”, and “dimensional change” even if the preferred conditions described in the present invention are not satisfied.
　以下、図１を参照しつつ、本件出願に係る多層プリント配線板１の説明を行う。なお、この図１においては、２層の第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を備える層構成として、そこに層間導通手段としてのスキップドビア２１を備える形態を示している。以下の説明においては、できる限り本件出願に係る多層プリント配線板１の構成要素毎に説明する。 Hereinafter, the multilayer printed wiring board 1 according to the present application will be described with reference to FIG. FIG. 1 shows a configuration in which a skipped via 21 serving as an interlayer conduction means is provided as a layer configuration including two first built-up wiring layers Bu1 and second built-up wiring layers Bu2. In the following description, it demonstrates for every component of the multilayer printed wiring board 1 which concerns on this application as much as possible.
コア基板：　ここで、本件出願に係る多層プリント配線板１を構成する当該コア基板２は、絶縁層の厚さが１５０μｍ以下であり、骨格材入り絶縁層の両面に内層回路を備え、且つ、当該骨格材入り絶縁層のＸ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃であることが好ましい。この当該骨格材入り絶縁層のＸ－Ｙ方向線膨張率の下限を０ｐｐｍ／℃としているのは、コア基板２を構成する絶縁層構成樹脂１１及び骨格材１２の種類の組み合わせを考慮しても、この値以下とすることが困難だからである。一方、当該骨格材入り絶縁層のＸ－Ｙ方向線膨張率が２０ｐｐｍ／℃を超えると、「反り」も「捻れ」も顕著になる傾向が高く、プリント配線板としての寸法安定性を確保できなくなる傾向が高くなるため好ましくない。なお、ここで「Ｘ－Ｙ方向線膨張率」として表示しているのは、平面的に見て四角板状のコア基板を想定したときの一辺に沿った方向における膨張率を「Ｘ方向線膨張率」と称し、当該一辺に対する垂直方向の膨張率を「Ｙ方向線膨張率」と称している。 Core substrate: Here, the core substrate 2 constituting the multilayer printed wiring board 1 according to the present application has an insulating layer thickness of 150 μm or less, and has inner layer circuits on both sides of the skeleton-containing insulating layer, and The linear expansion coefficient in the XY direction of the insulating layer containing a skeleton material is preferably 0 ppm / ° C. to 20 ppm / ° C. The lower limit of the linear expansion coefficient in the XY direction of the insulating layer containing the skeleton material is set to 0 ppm / ° C. even in consideration of the combination of the types of the insulating layer constituting resin 11 and the skeleton material 12 constituting the core substrate 2. This is because it is difficult to make this value or less. On the other hand, when the XY linear expansion coefficient of the skeleton-containing insulating layer exceeds 20 ppm / ° C., “warping” and “twisting” tend to be prominent, and dimensional stability as a printed wiring board can be secured. Since the tendency to disappear becomes high, it is not preferable. Here, the “XY expansion coefficient in the XY direction” indicates that the expansion coefficient in the direction along one side when a square plate-like core substrate is assumed in plan view is expressed as “X direction line The expansion coefficient in the direction perpendicular to the one side is referred to as “Y-direction linear expansion coefficient”.
　以上に述べた骨格材入り絶縁層のＸ－Ｙ方向線膨張率の測定は、骨格材入り絶縁層の両面に銅箔を積層した後、銅箔をエッチング除去して、硬化したシート状の骨格材入り絶縁層を得て、これを試料として、ＴＭＡ試験装置を用い、引張荷重法で昇温速度５℃／分の条件で２回測定し、２回目の測定の室温からガラス転移温度までの線膨張率の平均値を算出した値である。 The measurement of the linear expansion coefficient in the XY direction of the skeleton material-containing insulating layer described above is performed by laminating copper foil on both surfaces of the skeleton material-containing insulating layer, and then etching and removing the copper foil to cure the sheet-like skeleton. An insulating layer containing a material is obtained, and this is used as a sample, using a TMA test apparatus, and measured twice by the tensile load method at a temperature rising rate of 5 ° C./min. From the second measurement of room temperature to the glass transition temperature It is the value which calculated the average value of the linear expansion coefficient.
　そして、本件出願に係る多層プリント配線板１の前記コア基板２は、通常、その両面に内層回路２２を備える。この内層回路２２と、コア基板２の外層側に位置する第１ビルトアップ配線層Ｂｕ１の銅回路２３とが、ビアホール、スルーホール等の任意の層間導通手段（図示を省略）で接続して用いられる。 The core substrate 2 of the multilayer printed wiring board 1 according to the present application usually includes inner layer circuits 22 on both sides thereof. The inner layer circuit 22 and the copper circuit 23 of the first built-up wiring layer Bu1 located on the outer layer side of the core substrate 2 are used by being connected by any interlayer conduction means (not shown) such as a via hole or a through hole. It is done.
　また、本件出願に係る多層プリント配線板１の前記コア基板２は、絶縁層の厚さが１５０μｍ以下であることが好ましい。コア基板２の絶縁層の厚さが１５０μｍを超えると、薄いプリント配線板に対する要求は満足し得なくなるため好ましくない。なお、ここで下限値を定めていないが、最も薄い骨格材１２を考えると、現段階では１５μｍが下限値と考える。そして、市場におけるプリント配線板の薄層化要求を考慮すると、前記コア基板２の厚さを１００μｍ以下、更に好ましくは８０μｍ以下である。 Moreover, it is preferable that the core substrate 2 of the multilayer printed wiring board 1 according to the present application has an insulating layer thickness of 150 μm or less. If the thickness of the insulating layer of the core substrate 2 exceeds 150 μm, the requirement for a thin printed wiring board cannot be satisfied, which is not preferable. Although the lower limit is not set here, 15 μm is considered as the lower limit at the present stage when considering the thinnest skeleton material 12. In consideration of the demand for thinner printed wiring boards in the market, the thickness of the core substrate 2 is 100 μm or less, more preferably 80 μm or less.
　そして、ここで言う骨格材１２には、プリント配線板の絶縁層の構成材料として使用されるガラスクロス、ガラス不織布の使用が可能であり、ガラスの材質に関して特段の限定は無い。また、コア基板２の絶縁層構成樹脂１１としては、プリント配線板の絶縁層の構成材料として使用されるエポキシ系樹脂、シアネート系樹脂、マレイミド系樹脂、ポリフェニレンエーテル系樹脂、ポリブタジエン系樹脂、アクリレート系樹脂等の使用が可能であり、特段の限定は無い。 The skeleton material 12 can be made of glass cloth or glass nonwoven fabric used as a constituent material of the insulating layer of the printed wiring board, and there is no particular limitation on the material of the glass. Further, as the insulating layer constituting resin 11 of the core substrate 2, an epoxy resin, a cyanate resin, a maleimide resin, a polyphenylene ether resin, a polybutadiene resin, an acrylate resin used as a constituent material of an insulating layer of a printed wiring board. Resin or the like can be used, and there is no particular limitation.
ビルトアップ配線層：　この第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２は、図１から理解できるように、コア基板の内層回路２２を形成した表面に設けるものである。そして、このときの本件出願に係る多層プリント配線板を構成する当該第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２は、銅回路層２３，２４と、Ｘ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃の絶縁樹脂層３０，３１とからなるものである。ここで、絶縁樹脂層３０，３１のＸ－Ｙ方向線膨張率の下限を１ｐｐｍ／℃としているのは、現実的にみて、この値以下とすることが困難だからである。一方、当該絶縁樹脂層３０，３１のＸ－Ｙ方向線膨張率が５０ｐｐｍ／℃を超えると、「反り」も「捻れ」も顕著になる傾向があり、プリント配線板としての寸法安定性の確保が困難となり好ましくない。 Built-up wiring layer: As can be understood from FIG. 1, the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 are provided on the surface of the core substrate on which the inner layer circuit 22 is formed. The first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 constituting the multilayer printed wiring board according to the present application at this time have copper circuit layers 23 and 24 and an XY direction linear expansion coefficient. Insulating resin layers 30 and 31 of 1 ppm / ° C. to 50 ppm / ° C. Here, the reason why the lower limit of the linear expansion coefficient in the XY direction of the insulating resin layers 30 and 31 is set to 1 ppm / ° C. is that it is difficult to make the lower limit of this value practically. On the other hand, when the linear expansion coefficient in the XY direction of the insulating resin layers 30 and 31 exceeds 50 ppm / ° C., “warp” and “twist” tend to become prominent, and the dimensional stability as a printed wiring board is ensured. Is not preferable.
　ここで言う第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２の絶縁樹脂層３０，３１を構成する樹脂としては、エポキシ系樹脂、シアネート系樹脂、マレイミド系樹脂、ポリフェニレンエーテル系樹脂、ポリアミド樹脂、ポリイミド樹脂、ポリアミドイミド樹脂、ポリブタジエン系樹脂、アクリレート系樹脂等を使用することが可能である。 As the resin constituting the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 mentioned here, epoxy resin, cyanate resin, maleimide resin, polyphenylene ether resin, polyamide Resins, polyimide resins, polyamideimide resins, polybutadiene resins, acrylate resins, and the like can be used.
　以上に述べたビルトアップ配線層のＸ－Ｙ方向線膨張率の測定は、第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２の絶縁樹脂層３０，３１の形成に用いる上述の樹脂成分を用いて、後述する２枚の半硬化樹脂層付銅箔を製造し、これらの樹脂面同士を当接させて積層した後、銅箔をエッチング除去して、硬化したシート状の絶縁樹脂層を得て、上述のＴＭＡ試験装置及び試験条件で測定した値である。 The measurement of the linear expansion coefficient in the XY direction of the built-up wiring layer described above is based on the above-described resin component used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2. Is used to manufacture two semi-cured resin layer-attached copper foils which will be described later, these resin surfaces are brought into contact with each other and laminated, and then the copper foil is etched away and cured sheet-like insulating resin layer And measured with the above-described TMA test apparatus and test conditions.
　以上に述べてきた第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１のＸ－Ｙ方向線膨張率は、上述のように四角状のビルトアップ配線層を想定したときには、Ｘ方向線膨張率（Ｂｘ）と、Ｙ方向線膨張率（Ｂｙ）とに分離して考えることができる。このときのＸ方向線膨張率（Ｂｘ）の値と、Ｙ方向線膨張率（Ｂｙ）の値とが、［Ｂｘ］／［Ｂｙ］＝０．９～１．１の関係を満たすことが好ましく、［Ｂｘ］／［Ｂｙ］＝０．９５～１．０５の関係を満たすことが、より好ましい。この［Ｂｘ］／［Ｂｙ］の値が、この範囲を外れると、第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２自体の中で、Ｘ方向とＹ方向とで線膨張率が大きく異なることとなり、「反り」・「捻れ」・「寸法変化」の小さな多層プリント配線板１を得ることができなくなり、好ましくない。 The XY direction linear expansion coefficient of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 described above is the square built-up wiring layer as described above. Is assumed to be separated into an X-direction linear expansion coefficient (Bx) and a Y-direction linear expansion coefficient (By). It is preferable that the value of the X direction linear expansion coefficient (Bx) and the value of the Y direction linear expansion coefficient (By) satisfy the relationship [Bx] / [By] = 0.9 to 1.1. [Bx] / [By] = 0.95 to 1.05 is more preferable. If the value of [Bx] / [By] is out of this range, the linear expansion coefficient is large in the X direction and the Y direction in the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2. It becomes different and it becomes impossible to obtain the multilayer printed wiring board 1 with small “warping”, “twist”, and “dimensional change”, which is not preferable.
　この第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１のＸ－Ｙ方向線膨張率を調整するため、当該絶縁樹脂層にフィラーとして、シリカ粒子、中空シリカ粒子、アルミナ粒子、タルク等を含有させることも好ましい。このときのフィラーは、平均粒径として２０ｎｍ～１μｍのものを用いることが好ましい。このとき、フィラーの平均粒径の下限値に特段の限定は無いが、工業製品としての実状を考慮して２０ｎｍとしている。一方、当該フィラーの平均粒径が１μｍを超えると、銅箔の粗面の突起部分と、絶縁樹脂層中のフィラーとが接触する可能性が高く、密着性を低下させる傾向があり、好ましくない。そして、当該第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１にフィラーを含有させる場合、当該絶縁樹脂層３０，３１に対し、フィラーを３０重量％～７０重量％の範囲で含有させることが好ましい。このフィラー含有量が３０重量％未満の場合には、第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１のＸ－Ｙ方向線膨張率を調整することが困難となるため好ましくない。一方、当該フィラー含有量が７０重量％を超える場合には、コア基板の備える内層回路間を、フィラーを含有した絶縁樹脂層が埋設することが困難となるため好ましくない。 In order to adjust the linear expansion coefficient in the XY direction of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2, silica particles, hollow It is also preferable to contain silica particles, alumina particles, talc and the like. In this case, it is preferable to use a filler having an average particle diameter of 20 nm to 1 μm. At this time, although there is no special limitation in the lower limit of the average particle diameter of a filler, it is 20 nm in consideration of the actual state as an industrial product. On the other hand, if the average particle size of the filler exceeds 1 μm, the protrusions on the rough surface of the copper foil and the filler in the insulating resin layer are likely to come into contact with each other, which tends to reduce the adhesion, which is not preferable. . When the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 contain a filler, the filler is 30% by weight to the insulating resin layers 30 and 31. It is preferable to make it contain in 70 weight%. When the filler content is less than 30% by weight, the linear expansion coefficient in the XY direction of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 is adjusted. Is not preferable because it becomes difficult. On the other hand, when the filler content exceeds 70% by weight, it is difficult to embed an insulating resin layer containing the filler between the inner layer circuits provided in the core substrate.
　以下、本件出願に係る多層プリント配線板１の前記第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１を特徴付ける物理的特性等に関して述べる。当該絶縁樹脂層３０，３１は、２５℃における引張弾性率が５ＧＰａ～１０ＧＰａであることが好ましい。この絶縁樹脂層３０，３１の２５℃における引張弾性率が５ＧＰａ未満の場合には、多層プリント配線板１としたときの「反り」・「捻れ」・「寸法変化」が大きくなる傾向にあるため好ましくない。一方、この絶縁樹脂層３０，３１の２５℃における引張弾性率が１０ＧＰａを超えると、当該絶縁樹脂層３０，３１が脆くなるため、多層プリント配線板１としたときの僅かな「反り」又は「捻れ」が原因で、部品実装時にビルトアップ配線層にクラックが生じる傾向が高くなり好ましくない。 Hereinafter, physical characteristics that characterize the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application will be described. The insulating resin layers 30 and 31 preferably have a tensile elastic modulus at 25 ° C. of 5 GPa to 10 GPa. When the tensile elastic modulus at 25 ° C. of the insulating resin layers 30 and 31 is less than 5 GPa, “warp”, “twist”, and “dimensional change” when the multilayer printed wiring board 1 is formed tend to increase. It is not preferable. On the other hand, when the tensile elastic modulus at 25 ° C. of the insulating resin layers 30 and 31 exceeds 10 GPa, the insulating resin layers 30 and 31 become brittle. Due to the “twist”, the tendency of the built-up wiring layer to crack during component mounting is increased, which is not preferable.
　なお、ここでいう「２５℃における引張弾性率」は、の測定は、第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２の絶縁樹脂層３０，３１の形成に用いる上述の樹脂成分を用いて、後述する２枚の半硬化樹脂層付銅箔を製造し、これらの樹脂面同士を当接させて積層した後、銅箔をエッチング除去して、硬化したシート状の絶縁樹脂層を得て、これを試料として、粘弾性測定装置（ＤＭＡ）を用いて測定した値である。 The “tensile elastic modulus at 25 ° C.” here refers to the measurement of the resin component used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2. Using the two semi-cured resin layer-attached copper foils, which will be described later, and laminating these resin surfaces in contact with each other, the copper foil was removed by etching, and a cured sheet-like insulating resin layer was obtained. This is a value measured using a viscoelasticity measuring device (DMA) as a sample.
　そして、本件出願に係る多層プリント配線板１の前記第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１の、比誘電率は３．５以下であることが好ましい。以下、この比誘電率を規定した理由に関して説明する。携帯電話等の高周波シグナルを使用する場合の高密度プリント配線板のインピーダンスコントロールを考えると、良好な層間のクロストーク特性の制御が求められる。このクロストーク特性を左右する要素として、回路幅、層間の絶縁距離、絶縁層に用いる樹脂成分の比誘電率等がある。この内、層間の絶縁距離が短い場合、ストリップラインの回路幅を細くする必要があるため、回路形成が困難となる。従って、層間の絶縁距離が短く、太いストリップラインを使用するためには、低い比誘電率の絶縁層を用いる必要がある。即ち、層間の絶縁距離の短い基板（薄いプリント配線板）を用いる場合のインピーダンスコントロールを行うには、低い比誘電率の薄いプリント配線板を用いることが好ましい。このような理由から、本件出願に係る多層プリント配線板１の前記第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１の比誘電率を３．５以下とすることで、高密度プリント配線板のインピーダンスコントロールが行いやすくなる。そして、好ましくは、当該比誘電率を３．１以下にすると、インピーダンスコントロール精度が一段と向上する。更に、当該比誘電率を３．０以下にすると、市場要求を殆ど満たすインピーダンスコントロール精度が確保できるようになる。ここで、第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２の比誘電率は、第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２の絶縁樹脂層３０，３１の形成に用いる上述の樹脂成分を用いて、後述する２枚の半硬化樹脂層付銅箔を製造し、これらの樹脂面同士を当接させて積層した後、銅箔をエッチング除去して、硬化したシート状の絶縁樹脂層を得て、これを試料として、スプリットポスト誘電体共振法（使用周波数：１ＧＨｚ）で測定した値である。 The relative dielectric constant of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application is 3.5 or less. Is preferred. Hereinafter, the reason why the relative permittivity is specified will be described. Considering the impedance control of a high-density printed wiring board in the case of using a high-frequency signal such as a mobile phone, good control of the crosstalk characteristics between layers is required. Factors affecting the crosstalk characteristics include the circuit width, the insulation distance between layers, the relative dielectric constant of the resin component used in the insulation layer, and the like. Among these, when the insulation distance between the layers is short, it is necessary to reduce the circuit width of the strip line, so that circuit formation becomes difficult. Therefore, in order to use a thick strip line with a short insulating distance between layers, it is necessary to use an insulating layer having a low relative dielectric constant. That is, it is preferable to use a thin printed wiring board having a low relative dielectric constant in order to perform impedance control when using a substrate (thin printed wiring board) having a short insulating distance between layers. For this reason, the dielectric constant of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application is 3.5 or less. By doing so, it becomes easy to perform impedance control of the high-density printed wiring board. Preferably, when the relative dielectric constant is 3.1 or less, impedance control accuracy is further improved. Furthermore, when the relative dielectric constant is set to 3.0 or less, impedance control accuracy that almost satisfies the market demand can be secured. Here, the relative dielectric constants of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 are used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2. Using the resin component described above, two copper foils with a semi-cured resin layer, which will be described later, are manufactured, and after laminating these resin surfaces in contact with each other, the copper foil is removed by etching, and the sheet is cured. This is a value measured by a split post dielectric resonance method (use frequency: 1 GHz) using this as a sample.
　また、本件出願に係る多層プリント配線板１の前記第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１は、硬化後のガラス転移温度（Ｔｇ）に特段の限定は無いが、１６０℃未満であることが好ましい。このガラス転移温度（Ｔｇ）を１６０℃未満とすることにより、絶縁樹脂層３０，３１の高温領域で低弾性となる傾向にあり、反りが発生しにくくなるため好ましい。なお、ここでいう「ガラス転移温度」は、第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２の絶縁樹脂層３０，３１の形成に用いる上述の樹脂成分を用いて、後述する２枚の半硬化樹脂層付銅箔を製造し、これらの樹脂面同士を当接させて積層した後、銅箔をエッチング除去して、硬化したシート状の絶縁樹脂層を得て、これを試料として、粘弾性測定装置（ＤＭＡ）を用いて、昇温速度５℃／分の条件で測定した値である。 Further, the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application are specially adapted to the glass transition temperature (Tg) after curing. However, the temperature is preferably less than 160 ° C. By setting the glass transition temperature (Tg) to less than 160 ° C., it tends to be low elasticity in the high temperature region of the insulating resin layers 30 and 31 and warpage is less likely to occur. Note that the “glass transition temperature” here is two sheets to be described later using the above-described resin components used for forming the insulating resin layers 30 and 31 of the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2. After manufacturing the semi-cured resin layered copper foil, the resin surfaces were brought into contact with each other and laminated, and then the copper foil was removed by etching to obtain a cured sheet-like insulating resin layer, which was used as a sample. , Measured using a viscoelasticity measuring device (DMA) under conditions of a temperature rising rate of 5 ° C./min.
　更に、本件出願に係る多層プリント配線板１の前記第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１は、厚さが２０μｍ～８０μｍであることが好ましい。この絶縁樹脂層３０，３１の厚さが２０μｍ未満の場合には、絶縁性を確保することも困難となり、且つ、「反り」・「捻れ」・「寸法変化」が大きくなる傾向にあるため好ましくない。一方、この絶縁樹脂層３０，３１の厚さが８０μｍを超える場合には、薄いプリント配線板に対する要求を満たすことが困難となり、絶縁樹脂層３０，３１の厚さばらつきも大きくなり、むしろ「反り」・「捻れ」・「寸法変化」が大きくなる傾向にあるため好ましくない。そして、前記第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ配線層Ｂｕ２を構成する絶縁樹脂層３０，３１の厚さは、市場におけるプリント配線板の薄層化要求を考慮すると、５０μｍ以下がより好ましく、４０μｍ以下とすることが更に好ましい。 Furthermore, the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 of the multilayer printed wiring board 1 according to the present application preferably have a thickness of 20 μm to 80 μm. . When the thickness of the insulating resin layers 30 and 31 is less than 20 μm, it is difficult to ensure insulation, and “warp”, “twist”, and “dimensional change” tend to increase, which is preferable. Absent. On the other hand, when the thickness of the insulating resin layers 30 and 31 exceeds 80 μm, it becomes difficult to satisfy the requirement for a thin printed wiring board, and the thickness variation of the insulating resin layers 30 and 31 becomes large. ”,“ Twist ”, and“ dimensional change ”tend to increase, which is not preferable. The thickness of the insulating resin layers 30 and 31 constituting the first built-up wiring layer Bu1 and the second built-up wiring layer Bu2 is more preferably 50 μm or less in consideration of the demand for thinner printed wiring boards in the market. Preferably, it is 40 μm or less.
８層以上の多層プリント配線板：　本件出願に係る多層プリント配線板は、最も少ない層構成が６層であり、この６層の多層プリント配線板の外層に、新たなビルトアップ配線層を設けたものであり、この８層以上の多層プリント配線板の最外層に、以下に述べるビルトアップ配線層を設けることが好ましい。 Multi-layer printed wiring board having 8 or more layers: The multilayer printed wiring board according to the present application has 6 layers as the smallest layer structure, and a new built-up wiring layer is provided on the outer layer of the 6-layer multilayer printed wiring board. The built-up wiring layer described below is preferably provided on the outermost layer of the multilayer printed wiring board having eight or more layers.
　この最外層に配置するビルトアップ配線層は、当該ビルトアップ配線層を構成する絶縁樹脂層を２５℃における引張弾性率を５．０ＧＰａ未満の低弾性とすることが好ましい。このように低弾性率の絶縁樹脂層を採用したのは、以下の理由からである。半田ボール等を用いて多層プリント配線板に部品実装を行った後に、誤って当該実装基板を落下させ、床面に衝突した場合、実装基板が非常に強い落下衝撃を受ける。係る場合に、部品実装に用いた半田ボールを配置した実装用回路と絶縁樹脂基材とが接触する面において、上述の落下の如き強い衝撃を受けると、実装部品の重量が、実装用回路を強く押し、回路の縁端部から絶縁樹脂層内へのクラック発生、実装部品の剥離脱落、回路断線等が起こる場合がある。このような不具合を解消するためには、最外層のビルトアップ配線層を構成する絶縁樹脂層を低弾性に設計することが好ましいからである。当該引張弾性率が５．０ＧＰａ未満になると、実装基板となった後に落下が起きても、クラック発生・実装部品の剥離脱落・回路断線等を効果的に防止し、実装基板に良好な耐ドロップ性能を付与できる。このとき、当該引張弾性率が３．５ＧＰａ未満になると、実装基板の耐ドロップ性能が格段に上昇し、当該引張弾性率が３．０ＧＰａ未満になると、更に当該耐ドロップ性能が向上し、実装基板の取り扱い時に落下しても殆ど損傷は起こらなくなる。なお、ここで、当該引張弾性率の下限に関して述べていないが、経験的に見て０．１ＧＰａ程度である。この引張弾性率が０．１ＧＰａ未満の場合には、部品実装時に使用するボンダーの圧力により、実装する位置の回路が押し込まれて沈み込むため好ましくない。 The built-up wiring layer disposed in the outermost layer preferably has an insulating resin layer constituting the built-up wiring layer having a low elasticity with a tensile elastic modulus at 25 ° C. of less than 5.0 GPa. The reason why such an insulating resin layer having a low elastic modulus is employed is as follows. After mounting a component on a multilayer printed wiring board using a solder ball or the like, if the mounting board is accidentally dropped and collides with the floor surface, the mounting board receives a very strong drop impact. In such a case, when the mounting circuit in which the solder balls used for component mounting are placed on the surface where the insulating resin base material is in contact with the mounting circuit, if the impact such as the drop described above is received, the weight of the mounting component will Pressing strongly may cause cracks from the edge of the circuit into the insulating resin layer, peeling off of mounted components, circuit disconnection, and the like. This is because it is preferable to design the insulating resin layer constituting the outermost built-up wiring layer with low elasticity in order to solve such a problem. If the tensile elastic modulus is less than 5.0 GPa, even if it falls after it becomes a mounting board, it effectively prevents cracks, peeling of mounting parts, circuit disconnection, etc., and good drop resistance to the mounting board Can give performance. At this time, when the tensile elastic modulus is less than 3.5 GPa, the drop resistance performance of the mounting substrate is remarkably increased, and when the tensile elastic modulus is less than 3.0 GPa, the drop resistance performance is further improved. Almost no damage will occur even if dropped during handling. Here, although the lower limit of the tensile elastic modulus is not described, it is about 0.1 GPa from experience. When the tensile elastic modulus is less than 0.1 GPa, the circuit at the mounting position is pushed in due to the pressure of the bonder used at the time of component mounting and is not preferable.
　また、この最外層に配置するビルトアップ配線層を構成する絶縁樹脂層は、破断伸び率が５％以上であることが好ましい。破断伸び率が５％未満の場合、ビルトアップ配線層を構成する絶縁樹脂層が脆くなり、上述の引張弾性率が５．０ＧＰａ未満であっても、上述の実装基板の耐ドロップ性能にばらつきが生じる場合がある。ところが、当該絶縁樹脂層の破断伸び率が５％以上になると、ビルトアップ配線層を構成する絶縁樹脂層が、衝撃に対する十分な柔軟性を備えることとなり、良好な耐ドロップ性能が得られる傾向にあるからである。 The insulating resin layer constituting the built-up wiring layer disposed in the outermost layer preferably has a breaking elongation of 5% or more. When the elongation at break is less than 5%, the insulating resin layer constituting the built-up wiring layer becomes brittle, and even if the tensile elastic modulus is less than 5.0 GPa, the drop resistance performance of the mounting board described above varies. May occur. However, when the elongation at break of the insulating resin layer is 5% or more, the insulating resin layer constituting the built-up wiring layer has sufficient flexibility with respect to impact, and a good drop resistance performance tends to be obtained. Because there is.
　ここでいう最外層に配置するビルトアップ配線層の絶縁樹脂層を構成する低弾性の樹脂として、エポキシ系樹脂、シアネート系樹脂、マレイミド系樹脂、ポリフェニレンエーテル系樹脂、ポリアミド樹脂、ポリイミド樹脂、ポリアミドイミド樹脂、ポリブタジエン系樹脂、アクリレート系樹脂、ポリエステル樹脂、フェノキシ樹脂、ポリビニルアセタール樹脂、スチレン－ブタジエン系樹脂等を使用できる。 As the low-elasticity resin that constitutes the insulating resin layer of the built-up wiring layer arranged in the outermost layer here, epoxy resin, cyanate resin, maleimide resin, polyphenylene ether resin, polyamide resin, polyimide resin, polyamideimide Resins, polybutadiene resins, acrylate resins, polyester resins, phenoxy resins, polyvinyl acetal resins, styrene-butadiene resins, and the like can be used.
２．多層プリント配線板の製造形態
＜第１製造方法＞
　この多層プリント配線板の第１製造方法は、以下の工程１～工程３を備えることを特徴とする。以下、図２～図４を参照しつつ、工程毎に説明する。 2. Manufacturing form of multilayer printed wiring board <First manufacturing method>
The first method for producing a multilayer printed wiring board includes the following steps 1 to 3. Hereinafter, each process will be described with reference to FIGS.
工程１：　この工程では、図２（ａ）に示すような、骨格材１２とＸ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃の絶縁樹脂１１とからなる骨格材入り絶縁層１０の表面に銅箔層１４を備える銅張積層板４０を用意する。そして、この銅張積層板４０の銅箔層１４に、必要に応じて、ビアホール加工、層間導通めっき加工、エッチング加工等を施し、所定の内層回路２２を形成して、図２（ｂ）に示した絶縁層の厚さが１５０μｍ以下のコア基板２を得る。 Step 1: In this step, as shown in FIG. 2A, the skeleton material-containing insulating layer 10 comprising the skeleton material 12 and the insulating resin 11 having an XY linear expansion coefficient of 0 ppm / ° C. to 20 ppm / ° C. A copper clad laminate 40 having a copper foil layer 14 on the surface is prepared. Then, the copper foil layer 14 of the copper-clad laminate 40 is subjected to via hole processing, interlayer conductive plating processing, etching processing, or the like as necessary to form a predetermined inner layer circuit 22, as shown in FIG. The core substrate 2 having a thickness of the insulating layer shown is 150 μm or less.
工程２：　この工程では、図３（ｃ）に示すように、半硬化樹脂層付銅箔５０の半硬化樹脂層側１５を、図２（ｂ）に示すコア基板２の表面に当接させ積層し、図３（ｄ）に示すように、コア基板２の両面に絶縁樹脂層３０と銅箔層１４とからなる第１ビルトアップ層３ａを形成する。そして、このときの当該絶縁樹脂層３０は、Ｘ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃であり、且つ、当該絶縁樹脂層のＸ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値が、［Ｂｘ］／［Ｂｙ］＝０．９～１．１の関係を満たすものである。なお、この半硬化樹脂層付銅箔５０は、銅箔１４の表面に、絶縁樹脂層を形成するための樹脂ワニスを塗布し、乾燥させることで製造されるものである。この半硬化樹脂層付銅箔５０の製造方法に関しては、プリント配線板の製造分野における当業者であれば、容易に理解できるため、図面を使用しての説明は省略する。 Step 2: In this step, as shown in FIG. 3C, the semi-cured resin layer side 15 of the copper foil 50 with a semi-cured resin layer is brought into contact with the surface of the core substrate 2 shown in FIG. As shown in FIG. 3D, the first built-up layer 3 a composed of the insulating resin layer 30 and the copper foil layer 14 is formed on both surfaces of the core substrate 2. The insulating resin layer 30 at this time has an XY direction linear expansion coefficient of 1 ppm / ° C. to 50 ppm / ° C., and the X direction linear expansion coefficient (Bx) value of the insulating resin layer and the Y direction. The value of the linear expansion coefficient (By) satisfies the relationship [Bx] / [By] = 0.9 to 1.1. The semi-cured resin layer-attached copper foil 50 is manufactured by applying a resin varnish for forming an insulating resin layer on the surface of the copper foil 14 and drying it. The method for producing the semi-cured resin layer-attached copper foil 50 can be easily understood by those skilled in the art of producing printed wiring boards, and therefore description thereof using drawings is omitted.
　そして、この工程２では、図３（ｄ）に示す状態から、当該第１ビルトアップ層３ａの表面にある銅箔層１４に対し、必要に応じて、ビアホール加工、層間導通めっき加工、エッチング加工等を施して、回路２３を形成し第１ビルトアップ配線層Ｂｕ１を設けることで、図３（ｅ）に示す第１ビルドアップ配線層付積層板５１を得る。 In Step 2, from the state shown in FIG. 3D, via hole processing, interlayer conductive plating processing, etching processing is performed on the copper foil layer 14 on the surface of the first built-up layer 3a as necessary. Etc., the circuit 23 is formed, and the first built-up wiring layer Bu1 is provided to obtain the first buildup wiring layer-equipped laminate 51 shown in FIG.
工程３：　この工程では、当該第１ビルドアップ配線層付積層板５１の両面にある回路形成面に対して、第１単位工程をｎ１回（ｎ１≧１の整数）繰り返して行い、コア基板の両面に（４＋２ｎ１）層のビルトアップ配線層を備える多層プリント配線板を得る。ここでいう第１単位工程とは、「ビルトアップ層の表面に、当該半硬化樹脂層付銅箔の半硬化樹脂層を当接させ、絶縁樹脂層と銅箔層とからなるビルトアップ層を更に形成し、回路形成を行う操作」のことである。 Step 3: In this step, the first unit step is repeated n 1 times (an integer of n 1 ≧ 1) on the circuit forming surfaces on both surfaces of the first build-up wiring layer-equipped laminate 51, and the core A multilayer printed wiring board having (4 + 2n 1 ) built-up wiring layers on both sides of the substrate is obtained. The 1st unit process here is "it makes the semi-hardened resin layer of the copper foil with the said semi-hardened resin layer contact | abut to the surface of a built-up layer, and the built-up layer which consists of an insulating resin layer and a copper foil layer is formed. Furthermore, it is an operation of forming a circuit and forming a circuit.
　この第１単位工程は、図４（ｆ）～図５（ｈ）に示す工程が該当する。即ち、図４（ｆ）に示すように、当該第１ビルドアップ配線層付積層板５１の第１ビルトアップ配線層Ｂｕ１の回路形成面に対して、当該半硬化樹脂層付銅箔５０の半硬化樹脂層１５を当接させ、絶縁樹脂層３１と銅箔層１４とからなる第２ビルトアップ層３ｂを形成し、図４（ｇ）に示すように、コア基板２の両面に２層の第１ビルトアップ配線層Ｂｕ１，第２ビルトアップ層３ｂを備える多層銅張積層板５２を得る。 The first unit process corresponds to the process shown in FIGS. 4 (f) to 5 (h). That is, as shown in FIG. 4 (f), the semi-cured resin layer-attached copper foil 50 half of the circuit-forming surface of the first built-up wiring layer Bu 1 of the first build-up wiring layer-attached laminate 51. The cured resin layer 15 is brought into contact with each other to form the second built-up layer 3b composed of the insulating resin layer 31 and the copper foil layer 14, and two layers are formed on both surfaces of the core substrate 2 as shown in FIG. A multilayer copper clad laminate 52 having the first built-up wiring layer Bu1 and the second built-up layer 3b is obtained.
　そして、図４（ｇ）に示す当該多層銅張積層板５２の両面にある第２ビルトアップ層３ｂの銅箔層１４に対し、ビアホール加工、層間導通めっき加工、エッチング加工等を必要に応じて施し、図５（ｈ）に示すように回路２４を形成して第２ビルトアップ配線層Ｂｕ２を設けた多層プリント配線板１を得る。なお、図５（ｈ）に示したように、層間導通めっき２０を施して、スッキプドビア２１を形成すると、内層側の第１ビルトアップ配線層Ｂｕ１の孔明け加工が省略できるため、第１ビルトアップ配線層Ｂｕ１を形成する際の工程が削減できるため好ましい。 Then, via hole processing, interlayer conductive plating processing, etching processing, or the like is performed on the copper foil layer 14 of the second built-up layer 3b on both surfaces of the multilayer copper clad laminate 52 shown in FIG. Then, as shown in FIG. 5H, the circuit 24 is formed to obtain the multilayer printed wiring board 1 provided with the second built-up wiring layer Bu2. As shown in FIG. 5H, when the interlayer via plating 20 is applied to form the skipped via 21, the first built-up wiring layer Bu1 on the inner layer side can be omitted, so that the first built-up This is preferable because the steps for forming the wiring layer Bu1 can be reduced.
　以上に述べた第１単位工程を、ｎ１回（ｎ１≧１の整数）繰り返して行うと、コア基板の両面に（４＋２ｎ１）層のビルトアップ配線層を備える多層プリント配線板１を得ることができる。 When the first unit process described above is repeated n 1 times (an integer of n 1 ≧ 1), a multilayer printed wiring board 1 having (4 + 2n 1 ) built-up wiring layers on both surfaces of the core substrate is obtained. be able to.
＜第２製造方法＞
　この多層プリント配線板の第２製造方法は、上述の多層プリント配線板の製造方法であり、以下の工程１～工程４を備えることを特徴とする。ここで、工程１～工程３に関しては、上述の第１製造方法と同様である。従って、ここでは異なる工程である工程４に関してのみ述べ、重複した説明は省略する。 <Second manufacturing method>
The second method for manufacturing a multilayer printed wiring board is the above-described method for manufacturing a multilayer printed wiring board, and includes the following steps 1 to 4. Here, Steps 1 to 3 are the same as those in the first manufacturing method described above. Therefore, only the process 4 which is a different process will be described here, and a duplicate description will be omitted.
工程４：　この工程では、第１製造方法の工程３で得られた「コア基板の両面に（４＋２ｎ１）層のビルトアップ配線層を備える多層プリント配線板」の両面の最外層にあるビルトアップ配線層の回路形成面に対して、最外層に２５℃における引張弾性率が５．０ＧＰａ未満の絶縁樹脂層を備えるビルトアップ配線層を備える多層プリント配線板を得る。このとき、硬化後に２５℃における引張弾性率が５．０ＧＰａ未満となる半硬化樹脂層を備える半硬化樹脂層付銅箔の半硬化樹脂層側を、多層プリント配線板の表面に当接させ、積層するという第２単位工程を、ｎ２回（ｎ２≧１の整数）繰り返して行い、コア基板の両面に{４＋２（ｎ１＋ｎ２）}層の層構成のビルトアップ配線層を設けることができる。 Step 4: In this step, the built-up on the outermost layer on both sides of the “multilayer printed wiring board having (4 + 2n 1 ) built-up wiring layers on both sides of the core substrate” obtained in Step 3 of the first manufacturing method. A multilayer printed wiring board provided with a built-up wiring layer provided with an insulating resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa on the outermost layer with respect to the circuit forming surface of the wiring layer is obtained. At this time, the semi-cured resin layer side of the copper foil with a semi-cured resin layer provided with a semi-cured resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing is brought into contact with the surface of the multilayer printed wiring board, The second unit process of stacking is repeated n 2 times (an integer of n 2 ≧ 1), and a built-up wiring layer having a {4 + 2 (n 1 + n 2 )} layer structure is provided on both surfaces of the core substrate. Can do.
　この第２単位工程の製造プロセスは、第１単位工程の製造プロセスと同様である。しかし、ビルトアップ層の形成に用いる半硬化樹脂層付銅箔が異なる。即ち、第２単位工程で用いる半硬化樹脂層付銅箔の半硬化樹脂層には、硬化後において、２５℃における引張弾性率が５．０ＧＰａ未満となるものを用いて、絶縁樹脂層と銅箔層とからなるビルトアップ層を形成する。従って、図５（ｈ）に示す状態から、両面に半硬化樹脂層付銅箔の半硬化樹脂層を積層し、回路２５を形成して第３ビルトアップ配線層Ｂｕ３を設けた、図５（ｉ）に示す多層プリント配線板１が得られる。このときの第３ビルトアップ配線層Ｂｕ３の絶縁樹脂層３２の２５℃における引張弾性率が５．０ＧＰａ未満となっている。 The manufacturing process of the second unit process is the same as the manufacturing process of the first unit process. However, the copper foil with a semi-cured resin layer used for forming the built-up layer is different. That is, for the semi-cured resin layer of the copper foil with a semi-cured resin layer used in the second unit process, a material having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing is used. A built-up layer composed of a foil layer is formed. Therefore, from the state shown in FIG. 5 (h), a semi-cured resin layer of a semi-cured resin layer-attached copper foil is laminated on both sides, a circuit 25 is formed, and a third built-up wiring layer Bu3 is provided. A multilayer printed wiring board 1 shown in i) is obtained. At this time, the tensile elastic modulus at 25 ° C. of the insulating resin layer 32 of the third built-up wiring layer Bu3 is less than 5.0 GPa.
　この実施例１では、以下の工程を経て、図６に示す如き１０層の多層プリント配線板を製造した。 In Example 1, a multilayer printed wiring board having 10 layers as shown in FIG. 6 was manufactured through the following steps.
工程１：　実施例１では、図２（ａ）に示す状態の、絶縁層の両面に、銅箔を備えた銅張積層板（銅箔厚さ：１８μｍ、絶縁層厚さ：６０μｍ、絶縁層：ガラスクロスを含有、Ｘ方向線膨張率が１４．０ｐｐｍ／℃、Ｙ方向線膨張率が１２．０ｐｐｍ／℃）を準備した。そして、当該銅張積層板の外層の銅箔をエッチング加工して、両面に所定の内層回路２２を形成し、図２（ｂ）に示すような、絶縁層の厚さが１５０μｍ以下のコア基板２を得た。 Step 1: In Example 1, a copper-clad laminate (copper foil thickness: 18 μm, insulating layer thickness: 60 μm, insulating layer) provided with copper foil on both sides of the insulating layer in the state shown in FIG. : Containing glass cloth, X-direction linear expansion coefficient was 14.0 ppm / ° C., and Y-direction linear expansion coefficient was 12.0 ppm / ° C.). And the copper foil of the outer layer of the said copper clad laminated board is etched, the predetermined inner layer circuit 22 is formed on both surfaces, and the core substrate whose thickness of an insulating layer is 150 micrometers or less as shown in FIG.2 (b) 2 was obtained.
工程２：　この工程２では、図３（ｃ）に示すように、半硬化樹脂層付銅箔５０（厚さ：３０μｍ、銅箔厚さ：１８μｍ、半硬化樹脂層：エポキシ系樹脂を用いて形成した樹脂皮膜）の半硬化樹脂層側１５を、図２（ｂ）に示すコア基板２の表面に当接させ積層し、図３（ｄ）に示すような、コア基板２の両面に絶縁樹脂層３０と銅箔層１４とからなる第１ビルトアップ層３ａを形成した。このときの第１ビルトアップ層３ａの絶縁樹脂層は、Ｘ－Ｙ方向線膨張率が３９ｐｐｍ／℃、当該絶縁樹脂層のＸ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値の比が［Ｂｘ］／［Ｂｙ］＝１．０、２５℃における引張弾性率が７．０ＧＰａ、比誘電率が３．１、ガラス転移温度（Ｔｇ）が１５０℃であった。 Step 2: In this step 2, as shown in FIG. 3C, a copper foil 50 with a semi-cured resin layer (thickness: 30 μm, copper foil thickness: 18 μm, semi-cured resin layer: epoxy resin is used. The semi-cured resin layer side 15 of the formed resin film) is brought into contact with and laminated on the surface of the core substrate 2 shown in FIG. 2B, and insulated on both surfaces of the core substrate 2 as shown in FIG. A first built-up layer 3a composed of the resin layer 30 and the copper foil layer 14 was formed. In this case, the insulating resin layer of the first built-up layer 3a has an XY direction linear expansion coefficient of 39 ppm / ° C., an X direction linear expansion coefficient (Bx) value of the insulating resin layer, and a Y direction linear expansion coefficient (By). ) Value ratio was [Bx] / [By] = 1.0, the tensile modulus at 25 ° C. was 7.0 GPa, the relative dielectric constant was 3.1, and the glass transition temperature (Tg) was 150 ° C.
　そして、この工程２では、図３（ｄ）に示す状態から、当該第１ビルトアップ層３ａの表面にある銅箔層１４に対し、必要に応じて、ビアホール加工、層間導通めっき加工、エッチング加工等を施して、回路２３を備える第１ビルトアップ配線層Ｂｕ１とし、図３（ｅ）に示す第１ビルドアップ配線層付積層板５１を得た。 In Step 2, from the state shown in FIG. 3D, via hole processing, interlayer conductive plating processing, etching processing is performed on the copper foil layer 14 on the surface of the first built-up layer 3a as necessary. The first built-up wiring layer Bu1 having the circuit 23 was obtained, and the first laminated board 51 with the build-up wiring layer shown in FIG.
工程３：　この工程３では、当該第１ビルドアップ配線層付積層板５１の両面にある回路形成面に対して、第１ビルトアップ層３ａの形成に用いたと同様の半硬化樹脂層付銅箔５０を用いて、上述の第１単位工程を２回繰り返して行い、２層の第２ビルトアップ配線層Ｂｕ２，第３ビルトアップ配線層Ｂｕ３を設け、当該コア基板２の両面にビルトアップ配線層Ｂｕ１～Ｂｕ３を備える８層の多層プリント配線板を得た。 Step 3: In this step 3, a copper foil with a semi-cured resin layer similar to that used for forming the first built-up layer 3a is formed on the circuit forming surfaces on both sides of the laminate 51 with the first build-up wiring layer. 50, the above-mentioned first unit process is repeated twice to provide two layers of the second built-up wiring layer Bu2 and the third built-up wiring layer Bu3, and the built-up wiring layers on both surfaces of the core substrate 2. An eight-layer multilayer printed wiring board comprising Bu1 to Bu3 was obtained.
工程４：　工程４では、工程３で得られた８層の多層プリント配線板の最外層にある第３ビルトアップ配線層Ｂｕ３の回路形成面に対して、硬化後において、２５℃における引張弾性率が５．０ＧＰａ未満となる半硬化樹脂層を備える半硬化樹脂層付銅箔（厚さ：４０μｍ、銅箔厚さ：１８μｍ）を用いて、上述の第２単位工程を１回行い、第４ビルトアップ配線層Ｂｕ４を設けることで、コア基板の両面に１０層のビルトアップ配線層Ｂｕ１～Ｂｕ４を備え、且つ、最外層に２５℃における引張弾性率が５．０ＧＰａ未満の絶縁樹脂層を備えるビルトアップ配線層を配した１０層の多層プリント配線板を得た。なお、この１０層の多層プリント配線板に設けた回路は、高密度配線回路を模したテスト用回路パターンを形成した。 Step 4: In Step 4, the tensile modulus at 25 ° C. after curing on the circuit formation surface of the third built-up wiring layer Bu3 in the outermost layer of the eight-layer multilayer printed wiring board obtained in Step 3 Using the copper foil with a semi-cured resin layer (thickness: 40 μm, copper foil thickness: 18 μm) provided with a semi-cured resin layer having a thickness of less than 5.0 GPa, the second unit step is performed once, By providing the built-up wiring layer Bu4, 10 layers of the built-up wiring layers Bu1 to Bu4 are provided on both surfaces of the core substrate, and the outermost layer is provided with an insulating resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa. A 10-layer multilayer printed wiring board provided with a built-up wiring layer was obtained. The circuit provided on the 10-layer multilayer printed wiring board formed a test circuit pattern that imitated a high-density wiring circuit.
　そして、ここで得られた１０層の多層プリント配線板を４分割して、１２ｃｍ×１２ｃｍの測定用試料とし、これをＡｋｒｏｍｅｔｒｉｘ社製のＴｈｅｒＭｏｉｒｅ　ＡＸＰで反り量を測定した。反り量は、４分割して得られた各測定用試料の３０℃～２６０℃までの加熱過程と、２６０℃～３０℃までの降温過程において、表１に示す各温度で４つの測定用試料の反り量を測定した。そして、この４つの測定値の内、最も最も反りの少ない測定データ（表１では、「最高データ」と表示している。）と、最も反りの発生していた測定データ（表１では、「最低データ」と表示している。）とを、表１に掲載した。以下の実施例及び比較例において、同様である。 Then, the 10-layer multilayer printed wiring board obtained here was divided into four to obtain a measurement sample of 12 cm × 12 cm, and this was measured for the amount of warpage with a Thermoire AXP manufactured by Akrometric. The amount of warpage is 4 measurement samples at each temperature shown in Table 1 in the heating process from 30 ° C. to 260 ° C. and the cooling process from 260 ° C. to 30 ° C. of each measurement sample obtained by dividing into 4 parts. The amount of warpage was measured. Of these four measured values, the measurement data with the least warpage (indicated as “highest data” in Table 1) and the measurement data with the most warpage (in Table 1, “ "Minimum data" is displayed in Table 1. The same applies to the following examples and comparative examples.
　この実施例２では、実施例１と同様の工程１～工程４を経て、図６に示す如き１０層の多層プリント配線板を製造し、実施例１と同様にして反り量を測定した。従って、異なる部分に関してのみ述べる。 In Example 2, a multilayer printed wiring board having 10 layers as shown in FIG. 6 was manufactured through Steps 1 to 4 similar to Example 1, and the amount of warpage was measured in the same manner as Example 1. Therefore, only different parts will be described.
　この実施例２においては、半硬化樹脂層付銅箔５０（厚さ：３０μｍ、銅箔厚さ：１８μｍ、半硬化樹脂層：エポキシ系樹脂とシアネート樹脂とビスマレイミド樹脂とを用いて形成した樹脂皮膜）を用い、実施例１と同様の工程１～工程３を経て形成した第１ビルトアップ配線層Ｂｕ１～第３ビルトアップ配線層Ｂｕ３の絶縁樹脂層３２は、Ｘ－Ｙ方向線膨張率が２４ｐｐｍ／℃、当該絶縁樹脂層のＸ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値の比が［Ｂｘ］／［Ｂｙ］＝１．０、２５℃における引張弾性率が８．９ＧＰａ、比誘電率が３．２、ガラス転移温度（Ｔｇ）が２７０℃であった。 In Example 2, a copper foil 50 with a semi-cured resin layer (thickness: 30 μm, copper foil thickness: 18 μm, semi-cured resin layer: a resin formed using an epoxy resin, a cyanate resin, and a bismaleimide resin The insulating resin layer 32 of the first built-up wiring layer Bu1 to the third built-up wiring layer Bu3 formed through the same steps 1 to 3 as in Example 1 has a linear expansion coefficient in the XY direction. 24 ppm / ° C., the ratio of the X-direction linear expansion coefficient (Bx) to the Y-direction linear expansion coefficient (By) of the insulating resin layer is [Bx] / [By] = 1.0, tensile elasticity at 25 ° C. The rate was 8.9 GPa, the relative dielectric constant was 3.2, and the glass transition temperature (Tg) was 270 ° C.
比較例Comparative example
［比較例１］
　この比較例１では、実施例１及び実施例２と同様の１０層の多層プリント配線板を製造し、実施例１と同様にして反り量を測定した。 [Comparative Example 1]
In Comparative Example 1, a 10-layer multilayer printed wiring board similar to that in Example 1 and Example 2 was manufactured, and the amount of warpage was measured in the same manner as in Example 1.
　この比較例１では、実施例１で用いたコア基板２の両面に、厚さ２０μｍのガラスクロスを骨格材として含むプリプレグ（積層後に厚さ３０μｍとなるもの）と、厚さ１８μｍの銅箔とを重ねて積層し、テスト用回路パターンを形成するという工程を、４回繰り返して、絶縁層の全てをプリプレグで構成した１０層の多層プリント配線板を製造した。このプリプレグで構成した絶縁樹脂層は、Ｘ方向線膨張率が１４ｐｐｍ／℃、Ｙ方向線膨張率が１２ｐｐｍ／℃、当該Ｘ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値の比が［Ｂｘ］／［Ｂｙ］＝１．２、２５℃におけるＸ方向引張弾性率が２４ＧＰａ・Ｙ方向引張弾性率が２２ＧＰａ、比誘電率が４．６であった。 In Comparative Example 1, a prepreg including a glass cloth having a thickness of 20 μm as a skeleton material on both surfaces of the core substrate 2 used in Example 1 (thickness that becomes 30 μm after lamination), a copper foil having a thickness of 18 μm, The process of forming a test circuit pattern was repeated four times to produce a 10-layer multilayer printed wiring board in which all of the insulating layer was composed of prepreg. The insulating resin layer composed of this prepreg has an X-direction linear expansion coefficient of 14 ppm / ° C., a Y-direction linear expansion coefficient of 12 ppm / ° C., a value of the X-direction linear expansion coefficient (Bx) and a Y-direction linear expansion coefficient (By). The ratio of [Bx] / [By] = 1.2, the X-direction tensile elastic modulus at 25 ° C. was 24 GPa. The Y-direction tensile elastic modulus was 22 GPa, and the relative dielectric constant was 4.6.
［比較例２］
　この比較例２では、実施例１及び実施例２と同様の１０層の多層プリント配線板を製造し、実施例１と同様にして反り量を測定した。 [Comparative Example 2]
In Comparative Example 2, a 10-layer multilayer printed wiring board similar to Example 1 and Example 2 was manufactured, and the amount of warpage was measured in the same manner as in Example 1.
　比較例２では、実施例１及び実施例２の最外層の形成に用いた「硬化後において、２５℃における引張弾性率が５．０ＧＰａ未満となる半硬化樹脂層を備える半硬化樹脂層付銅箔（厚さ：４０μｍ、銅箔厚さ：１８μｍ）」を用いて、実施例１で用いたコア基板２の両面に、当該半硬化樹脂層付銅箔を積層し、テスト用回路パターンを形成するという工程を、４回繰り返して、１０層の多層プリント配線板を製造した。このときの絶縁樹脂層は、Ｘ－Ｙ方向線膨張率が７０ｐｐｍ／℃、当該Ｘ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値の比が［Ｂｘ］／［Ｂｙ］＝１．０、２５℃における引張弾性率が３．２ＧＰａ、比誘電率が３．１であった。 In Comparative Example 2, the copper with a semi-cured resin layer provided with a semi-cured resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing was used for forming the outermost layer of Example 1 and Example 2. Using a foil (thickness: 40 μm, copper foil thickness: 18 μm), the copper foil with a semi-cured resin layer is laminated on both surfaces of the core substrate 2 used in Example 1 to form a test circuit pattern. This process was repeated four times to produce a 10-layer multilayer printed wiring board. The insulating resin layer at this time has an XY direction linear expansion coefficient of 70 ppm / ° C., and a ratio of the value of the X direction linear expansion coefficient (Bx) to the value of the Y direction linear expansion coefficient (By) is [Bx] / [ By] = 1.0, the tensile modulus at 25 ° C. was 3.2 GPa, and the relative dielectric constant was 3.1.
　なお、比較例２で得られた反り量の測定用試料は、作成直後の段階で１．０ｍｍ以上の反りが発生していたため、昇温・降温過程における反り量の測定は行わなかった。 The warpage amount measurement sample obtained in Comparative Example 2 had a warpage of 1.0 mm or more immediately after production, and thus the warpage amount was not measured in the temperature rising / falling process.
［実施例と比較例との対比］
　実施例と比較例とを対比可能なように、上述の特性値及び反り量を含め、表１に纏めて示す。 [Contrast between Example and Comparative Example]
Examples and Comparative Examples are summarized in Table 1 including the above-described characteristic values and warpage amounts so that they can be compared.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１を参照しつつ、実施例と比較例１との反り量を比較する。最初に、実施例と比較例１とを、最も反り量の少ない最高データをみると、比較例１の絶縁層の全てをプリプレグで構成した１０層の多層プリント配線板が、最も反りが少なく、標準偏差も小さいため反りのばらつきが小さいことが分かる。ところが、実施例と比較例１との、最も反り量の多い最低データをみてみると、この関係が逆転する。実施例１の最低データの反り量をみると、最高値１６４μｍ、最低値１２６μｍ、平均値１４０μｍ、標準偏差が１３．４μｍであった。そして、実施例２の最低データの反り量をみると、最高値１９１μｍ、最低値１２４μｍ、平均値１５６μｍ、標準偏差が１８．８μｍであった。これに対し、比較例１のの最低データの反り量をみると、最高値２２７μｍ、最低値１４５μｍ、平均値１６４μｍ、標準偏差が２５．２μｍである。従って、最も反り量の多い最低データでみると、比較例１の絶縁層の全てをプリプレグで構成した１０層の多層プリント配線板が、最も反り大きく、標準偏差も大きく、反りのばらつきが大きいと判断できる。 Referring to Table 1, the amount of warpage between Example and Comparative Example 1 is compared. First, looking at the highest data with the least amount of warpage in Example and Comparative Example 1, the 10-layer multilayer printed wiring board in which all of the insulating layers of Comparative Example 1 are composed of prepregs has the least warpage, It can be seen that the variation in warpage is small because the standard deviation is also small. However, when looking at the lowest data with the largest amount of warpage between the example and the comparative example 1, this relationship is reversed. Looking at the amount of warpage of the minimum data in Example 1, the maximum value was 164 μm, the minimum value was 126 μm, the average value was 140 μm, and the standard deviation was 13.4 μm. The amount of warpage of the lowest data in Example 2 was as follows: highest value 191 μm, lowest value 124 μm, average value 156 μm, and standard deviation 18.8 μm. On the other hand, when the amount of warpage of the minimum data of Comparative Example 1 is seen, the maximum value is 227 μm, the minimum value is 145 μm, the average value is 164 μm, and the standard deviation is 25.2 μm. Therefore, when looking at the lowest data with the largest amount of warpage, the 10-layer multilayer printed wiring board in which all of the insulating layers of Comparative Example 1 are made of prepreg has the largest warpage, the large standard deviation, and the large variation in warpage. I can judge.
　これらのことから理解できるのは、比較例１のようにプリプレグのみを使用して製造した多層プリント配線板の場合、同一ロットの製品間で反り量がばらつき、製品としての取り扱いが困難となることがある。これに対し、本件出願に係る多層プリント配線板のように「第１ビルトアップ層」と「第２ビルトアップ層」とが上述の条件を満たしていれば、第３層目以降のビルトアップ配線層にどのような種類の層を配置しても、「反り」・「捻れ」・「寸法変化」を軽減し、且つ、ばらつきが少なくなることで、「反り」・「捻れ」・「寸法変化」の予測が可能となり取り扱い性が向上する。 From these, it can be understood that, in the case of a multilayer printed wiring board manufactured using only a prepreg as in Comparative Example 1, the amount of warpage varies between products of the same lot, making it difficult to handle as a product. There is. On the other hand, if the “first built-up layer” and the “second built-up layer” satisfy the above-mentioned conditions as in the multilayer printed wiring board according to the present application, the built-up wiring in the third layer and thereafter is used. Regardless of what kind of layer is placed on the layer, "warp", "twist", "dimensional change" are reduced, and variations are reduced, resulting in "warp", "twist", "dimensional change" ”Can be predicted, and handling is improved.
　本件出願に係る多層プリント配線板は、従来のビルトアップ配線層を備える多層プリント配線板と比較して、「反り」・「捻れ」・「寸法変化」が小さく、ばらつきが少ないため、製造過程における誤差を予め想定することが可能で、製造過程での問題が生じにくくなる。そのため、本件出願に係る多層プリント配線板は、部品実装が容易であり、高品質のプリント配線板として市場に供給できる。また、本件出願に係る多層プリント配線板の製造方法は、従来のビルトアップ製造法を、そのまま使用することができるため、既存設備の有効利用性に優れている。 The multilayer printed wiring board according to the present application has less “warping”, “twist”, and “dimensional change” and less variation than the conventional multilayer printed wiring board having a built-up wiring layer. An error can be assumed in advance, and problems in the manufacturing process are less likely to occur. Therefore, the multilayer printed wiring board according to the present application can be easily mounted and can be supplied to the market as a high-quality printed wiring board. Moreover, since the manufacturing method of the multilayer printed wiring board which concerns on this application can use the conventional built-up manufacturing method as it is, it is excellent in the effective utilization of the existing installation.
１　多層プリント配線板
２　コア基板
３ａ，３ｂ　ビルトアップ層
１０　骨格材入り絶縁層
１１　コア基板の絶縁層構成樹脂
１２　骨格材
１４　銅箔（層）
１５　絶縁樹脂層
２０　層間導通めっき
２１　スキップドビア
２２　内層回路
２３，２４，２５　銅回路層
３０，３１，３２　絶縁樹脂層
４０　銅張積層板
５０　半硬化樹脂層付銅箔
５１　第１ビルドアップ配線層付積層板
５２　多層銅張積層板
Ｂｕｎ　第ｎビルトアップ配線層（ｎ≧１） DESCRIPTION OF SYMBOLS 1 Multilayer printed wiring board 2 Core board | substrate 3a, 3b Built-up layer 10 Insulating layer 11 containing a skeleton material Insulating layer constituent resin 12 of core board 12 Skeletal material 14 Copper foil (layer)
15 Insulating Resin Layer 20 Interlayer Conductive Plating 21 Skipped Via 22 Inner Layer Circuits 23, 24, 25 Copper Circuit Layers 30, 31, 32 Insulating Resin Layer 40 Copper-Clad Laminate 50 Copper foil 51 with Semi-cured Resin Layer With First Build-up Wiring Layer Laminate 52 Multilayer copper clad laminate Bun nth built-up wiring layer (n ≧ 1)

Claims (7)

  1. コア基板の両面に２層以上のビルトアップ配線層を設けた多層プリント配線板において、
    　当該多層プリント配線板を構成する当該コア基板は、絶縁層の厚さが１５０μｍ以下であり、骨格材入り絶縁層の両面に内層回路を備え、且つ、当該骨格材入り絶縁層のＸ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃であり、
    　当該コア基板の両面に設ける第１ビルトアップ配線層及び当該第１ビルトアップ配線層の表面に設ける第２ビルトアップ配線層は、銅回路層と、Ｘ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃の絶縁樹脂層とからなり、且つ、当該絶縁樹脂層のＸ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値が、［Ｂｘ］／［Ｂｙ］＝０．９～１．１の関係を満たすことを特徴とする多層プリント配線板。     In multilayer printed wiring boards with two or more built-up wiring layers on both sides of the core substrate,
    The core substrate constituting the multilayer printed wiring board has an insulating layer thickness of 150 μm or less, and has inner layer circuits on both sides of the skeleton material-containing insulating layer, and the skeleton material-containing insulating layer in the XY direction. The linear expansion coefficient is 0 ppm / ° C. to 20 ppm / ° C.,
    The first built-up wiring layer provided on both surfaces of the core substrate and the second built-up wiring layer provided on the surface of the first built-up wiring layer have a copper circuit layer and an XY direction linear expansion coefficient of 1 ppm / ° C. It consists of an insulating resin layer of 50 ppm / ° C., and the value of the X direction linear expansion coefficient (Bx) and the Y direction linear expansion coefficient (By) of the insulating resin layer is [Bx] / [By] = 0. A multilayer printed wiring board characterized by satisfying the relationship of 9 to 1.1.
  2. 前記第１ビルトアップ配線層及び第２ビルトアップ配線層を構成する絶縁樹脂層は、２５℃における引張弾性率が５ＧＰａ～１０ＧＰａである請求項１に記載の多層プリント配線板。 2. The multilayer printed wiring board according to claim 1, wherein the insulating resin layers constituting the first built-up wiring layer and the second built-up wiring layer have a tensile elastic modulus at 25 ° C. of 5 GPa to 10 GPa.
  3. 前記第１ビルトアップ配線層及び第２ビルトアップ配線層を構成する絶縁樹脂層は、厚さが２０μｍ～８０μｍである請求項１又は請求項２に記載の多層プリント配線板。 The multilayer printed wiring board according to claim 1 or 2, wherein the insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer has a thickness of 20 袖 m to 80 袖 m.
  4. 前記第１ビルトアップ配線層及び第２ビルトアップ配線層を構成する絶縁樹脂層は、比誘電率が３．５以下である請求項１～請求項３のいずれかに記載の多層プリント配線板。 The multilayer printed wiring board according to any one of claims 1 to 3, wherein an insulating resin layer constituting the first built-up wiring layer and the second built-up wiring layer has a relative dielectric constant of 3.5 or less.
  5. 請求項１～請求項４のいずれかに記載の多層プリント配線板の最外層に、２５℃における引張弾性率が５．０ＧＰａ未満の絶縁樹脂層を備えるビルトアップ配線層を設けたことを特徴とする多層プリント配線板。 A built-up wiring layer comprising an insulating resin layer having a tensile elastic modulus at 25 ° C of less than 5.0 GPa is provided on the outermost layer of the multilayer printed wiring board according to any one of claims 1 to 4. Multilayer printed wiring board.
  6. 請求項１～請求項４のいずれかに記載の多層プリント配線板の製造方法であって、
    　以下の工程１～工程３を備えることを特徴とする多層プリント配線板の製造方法。
    工程１：　Ｘ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃の骨格材入り絶縁層の表面に銅箔層を備える銅張積層板を用いて、内層回路を形成して、絶縁層の厚さが１５０μｍ以下のコア基板を得る
    工程２：　銅箔の表面に、硬化後の絶縁樹脂層のＸ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃であり、且つ、当該絶縁樹脂層のＸ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値が、［Ｂｘ］／［Ｂｙ］＝０．９～１．１の関係を満たす半硬化樹脂層を形成した半硬化樹脂層付銅箔を用いて、当該半硬化樹脂層付銅箔の半硬化樹脂層側を、前記コア基板の両面に当接させ積層し、回路形成を行うことで第１ビルドアップ配線層付積層板を得る。
    工程３：　第１ビルドアップ配線層付積層板の表面に、当該半硬化樹脂層付銅箔の半硬化樹脂層を当接させ、絶縁樹脂層と銅箔層とからなるビルトアップ層を更に形成し、回路形成を行う操作を第１単位工程として、当該第１ビルドアップ配線層付積層板の両面に対して、この第１単位工程をｎ１回（ｎ１≧１の整数）繰り返して行い、コア基板の両面に（４＋２ｎ１）層の層構成のビルトアップ層を備える多層プリント配線板を得る。     A method for producing a multilayer printed wiring board according to any one of claims 1 to 4,
    A method for producing a multilayer printed wiring board, comprising the following steps 1 to 3.
    Step 1: An inner layer circuit is formed using a copper clad laminate having a copper foil layer on the surface of a skeleton-containing insulating layer having an XY direction linear expansion coefficient of 0 ppm / ° C. to 20 ppm / ° C. Step 2 of obtaining a core substrate having a thickness of 150 μm or less: On the surface of the copper foil, the XY direction linear expansion coefficient of the cured insulating resin layer is 1 ppm / ° C. to 50 ppm / ° C., and the insulating resin layer A semi-cured resin layer was formed in which the values of the X-direction linear expansion coefficient (Bx) and the Y-direction linear expansion coefficient (By) satisfy the relationship [Bx] / [By] = 0.9 to 1.1. First build-up wiring by using a copper foil with a semi-cured resin layer and laminating the semi-cured resin layer side of the copper foil with a semi-cured resin layer in contact with both surfaces of the core substrate to form a circuit. A layered laminate is obtained.
    Step 3: The semi-cured resin layer of the copper foil with the semi-cured resin layer is brought into contact with the surface of the laminate with the first build-up wiring layer to further form a built-up layer composed of an insulating resin layer and a copper foil layer. Then, an operation for forming a circuit is set as a first unit process, and this first unit process is repeated n 1 times (an integer of n 1 ≧ 1) on both surfaces of the laminated board with the first buildup wiring layer. Then, a multilayer printed wiring board having (4 + 2n 1 ) layered built-up layers on both surfaces of the core substrate is obtained.
  7. 請求項５に記載の多層プリント配線板の製造方法であって、
    　以下の工程１～工程４を備えることを特徴とする多層プリント配線板の製造方法。
    工程１：　Ｘ－Ｙ方向線膨張率が０ｐｐｍ／℃～２０ｐｐｍ／℃の骨格材入り絶縁層の表面に銅箔層を備える銅張積層板を用いて、内層回路を形成して、絶縁層の厚さが１５０μｍ以下のコア基板を得る
    工程２：　銅箔の表面に、硬化後の絶縁樹脂層のＸ－Ｙ方向線膨張率が１ｐｐｍ／℃～５０ｐｐｍ／℃であり、且つ、当該絶縁樹脂層のＸ方向線膨張率（Ｂｘ）の値とＹ方向線膨張率（Ｂｙ）の値が、［Ｂｘ］／［Ｂｙ］＝０．９～１．１の関係を満たす半硬化樹脂層を形成した半硬化樹脂層付銅箔を用いて、当該半硬化樹脂層付銅箔の半硬化樹脂層側を、前記コア基板の両面に当接させ積層し、回路形成を行うことで第１ビルドアップ配線層付積層板を得る。
    工程３：　第１ビルドアップ配線層付積層板の表面に、当該半硬化樹脂層付銅箔の半硬化樹脂層を当接させ、絶縁樹脂層と銅箔層とからなるビルトアップ層を更に形成し、回路形成を行う操作を第１単位工程として、当該第１ビルドアップ配線層付積層板の両面に対して、この第１単位工程をｎ１回（ｎ１≧１の整数）繰り返して行い、コア基板の両面に（４＋２ｎ１）層のビルトアップ配線層を備える多層プリント配線板を得る。
    工程４：　当該第１単位工程を用いて形成した（４＋２ｎ１）層のビルトアップ配線層の表面に、硬化後に２５℃における引張弾性率が５．０ＧＰａ未満となる半硬化樹脂層を形成した半硬化樹脂層付銅箔を用いて、当該半硬化樹脂層付銅箔の半硬化樹脂層側を当接させ積層し、回路形成を行う操作を第２単位工程として、この第２単位工程をｎ２回（ｎ２≧１の整数）繰り返して行い、コア基板の両面に{４＋２（ｎ１＋ｎ２）}層の層構成のビルトアップ層を備え、且つ、最外層に２５℃における引張弾性率が５．０ＧＰａ未満の絶縁樹脂層を備えるビルトアップ配線層を配した多層プリント配線板を得る。     It is a manufacturing method of the multilayer printed wiring board according to claim 5,
    A method for producing a multilayer printed wiring board, comprising the following steps 1 to 4.
    Step 1: An inner layer circuit is formed using a copper clad laminate having a copper foil layer on the surface of a skeleton-containing insulating layer having an XY direction linear expansion coefficient of 0 ppm / ° C. to 20 ppm / ° C. Step 2 of obtaining a core substrate having a thickness of 150 μm or less: On the surface of the copper foil, the XY direction linear expansion coefficient of the cured insulating resin layer is 1 ppm / ° C. to 50 ppm / ° C., and the insulating resin layer A semi-cured resin layer was formed in which the values of the X-direction linear expansion coefficient (Bx) and the Y-direction linear expansion coefficient (By) satisfy the relationship [Bx] / [By] = 0.9 to 1.1. First build-up wiring by using a copper foil with a semi-cured resin layer and laminating the semi-cured resin layer side of the copper foil with a semi-cured resin layer in contact with both surfaces of the core substrate to form a circuit. A layered laminate is obtained.
    Step 3: The semi-cured resin layer of the copper foil with the semi-cured resin layer is brought into contact with the surface of the laminate with the first build-up wiring layer to further form a built-up layer composed of an insulating resin layer and a copper foil layer. Then, an operation for forming a circuit is set as a first unit process, and this first unit process is repeated n 1 times (an integer of n 1 ≧ 1) on both surfaces of the laminated board with the first buildup wiring layer. A multilayer printed wiring board having (4 + 2n 1 ) built-up wiring layers on both surfaces of the core substrate is obtained.
    Step 4: A semi-cured resin layer having a tensile elastic modulus at 25 ° C. of less than 5.0 GPa after curing is formed on the surface of the (4 + 2n 1 ) layer of the built-up wiring layer formed using the first unit step. Using the copper foil with a cured resin layer, the second unit process is defined as an operation in which the semi-cured resin layer side of the copper foil with the semi-cured resin layer is brought into contact with each other to perform circuit formation. carried out twice (n 2 ≧ 1 integer) repeatedly, with a built-up layer of the layer structure of both sides of the core substrate {4 + 2 (n 1 + n 2)} layer, and a tensile modulus at 25 ° C. in the outermost layer A multilayer printed wiring board having a built-up wiring layer provided with an insulating resin layer of less than 5.0 GPa is obtained.
PCT/JP2013/083266 2012-12-11 2013-12-11 Multilayer printed circuit board and manufacturing method thereof WO2014092137A1 (en)

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KR102097847B1 (en) 2020-04-06
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CN104823530A (en) 2015-08-05
KR20150094625A (en) 2015-08-19
TWI501715B (en) 2015-09-21
TW201448701A (en) 2014-12-16
JP6295206B2 (en) 2018-03-14

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