JPH04208597A - Multilayer printed circuit board - Google Patents
Multilayer printed circuit boardInfo
- Publication number
- JPH04208597A JPH04208597A JP40003390A JP40003390A JPH04208597A JP H04208597 A JPH04208597 A JP H04208597A JP 40003390 A JP40003390 A JP 40003390A JP 40003390 A JP40003390 A JP 40003390A JP H04208597 A JPH04208597 A JP H04208597A
- Authority
- JP
- Japan
- Prior art keywords
- glass cloth
- multilayer printed
- prepreg
- inner layer
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000011521 glass Substances 0.000 claims abstract description 22
- 239000004744 fabric Substances 0.000 claims abstract description 20
- 229920001721 polyimide Polymers 0.000 claims abstract description 16
- 239000009719 polyimide resin Substances 0.000 claims abstract description 16
- 239000003822 epoxy resin Substances 0.000 claims abstract description 15
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 3
- 239000004809 Teflon Substances 0.000 abstract description 4
- 229920006362 Teflon® Polymers 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000011347 resin Substances 0.000 abstract description 4
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 4
- 238000005187 foaming Methods 0.000 abstract 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract 1
- 229910052731 fluorine Inorganic materials 0.000 abstract 1
- 239000011737 fluorine Substances 0.000 abstract 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000035939 shock Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000003365 glass fiber Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 235000011187 glycerol Nutrition 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Abstract
Description
［０００１１ [00011
【産業上の利用分野］本発明は、多層プリント配線板に
関するものである。
［０００２］
【従来の技術】多層プリント配線板は、内層導体が形成
された複数の内層基板とプリプレグが外層銅箔とともに
、真空の高温・高圧下で積層されて形成される。上記積
層が完了すると、図６に示すように、多層プリント配線
板１０の所定の位置にスルーホール６０が明けられ（図
６（ａ））、その後、パネルメッキ層６１の形成（図６
（ｂ））、所定パターンのメツキレジスト６２の形成及
びスルーホールメツキ層６３、ランド６４の形成（図６
（ｃ） ） 、メツキレジスト６２の剥離（図６ （ｄ
） ） 、不要な部分のパネルメッキ層６１のエツチン
グ（図６（ｅ））が順次行われる。
（０００３］上記各内層基板の材質としては、例えばガ
ラス繊維を布状に編んだガラス布にエポキシ樹脂を含浸
させて硬化させたガラス布エポキシ樹脂基材や、あるい
は上記エポキシ樹脂に代えてポリイミド樹脂を採用した
ガラス布ポリイミド樹脂基材（ＰＩ基板）が多用されて
いる。また、上記プリプレグとしては上記ガラス布にエ
ポキシ樹脂あるいはポリイミド樹脂を含浸させて半硬化
状態（Ｂ状態）にしたものが使用される。
［０００４］ところで、近年コンピュータ等の電子機器
の処理速度の高速化が求められる状況にあって該電子機
器に搭載される多層プリント配線板は伝達遅延時間を極
力短縮して、上記要請に応える必要がある。このような
状況に対応するためには多層プリント配線板の実効誘電
率を低くすることが有効であり、そのために内層基板や
プリプレグの材料に誘電率の低い弗素樹脂、例えばテフ
ロンを採用することが考えられる。すなわち、基板とし
てはガラス布を基材とし、弗素樹脂を結合剤に使用する
とともに、プリプレグとして弗素樹脂フィルムの表裏両
面に接着剤としてのポリイミド樹脂あるいはエポキシ樹
脂をコーティングしたものを使用することが試みられて
いる。
［０００５］[Industrial Application Field] The present invention relates to a multilayer printed wiring board. [0002] A multilayer printed wiring board is formed by laminating a plurality of inner layer substrates on which inner layer conductors are formed and a prepreg together with an outer layer copper foil under high temperature and pressure in a vacuum. When the above lamination is completed, as shown in FIG. 6, a through hole 60 is opened at a predetermined position in the multilayer printed wiring board 10 (FIG. 6(a)), and then a panel plating layer 61 is formed (FIG. 6(a)).
(b)) Formation of plating resist 62 in a predetermined pattern, formation of through-hole plating layer 63, and land 64 (FIG.
(c)), Peeling of the plating resist 62 (Fig. 6 (d)
)) Etching of unnecessary portions of the panel plating layer 61 (FIG. 6(e)) is performed sequentially. (0003) The material for each of the above-mentioned inner layer substrates is, for example, a glass cloth epoxy resin base material obtained by impregnating and curing a glass cloth made of glass fibers knitted with an epoxy resin, or a polyimide resin instead of the above-mentioned epoxy resin. A glass cloth polyimide resin base material (PI board) is often used.The prepreg used is the glass cloth impregnated with epoxy resin or polyimide resin to a semi-cured state (B state). [0004] By the way, in recent years there has been a demand for higher processing speeds in electronic devices such as computers, and multilayer printed wiring boards mounted on such electronic devices are designed to shorten transmission delay time as much as possible to meet the above requirements. In order to respond to this situation, it is effective to lower the effective dielectric constant of the multilayer printed wiring board, and for this purpose, fluororesin with a low dielectric constant, such as fluororesin, is used as the material for the inner layer substrate and prepreg. It is conceivable to use Teflon.In other words, use glass cloth as the base material, use fluororesin as the binder, and apply polyimide resin or epoxy resin as an adhesive on both the front and back sides of the fluororesin film as a prepreg. Attempts have been made to use coated materials. [0005]
【発明が解決しようとする課題】しかしながら、上記弗
素樹脂は熱膨張率が大きいため（−該弗素樹脂を基板材
料として使用した場合、多層プリント配線板が例えば部
品実装の際の熱の影響で厚さ方向の膨張量が大きくなる
。特に層数を１０層程度以上の多層プリント配線板にお
いて、この傾向は一層顕著となり、上記多層プリント配
線板の膨張による基板の厚さ方向の引張力によってスル
ーホールメツキ層にひび割れ（バレルクラック）が発生
し、多層プリン＋−Ｃ線板の信頼性が失われる恐れがあ
る。
［０００６１本発明は上記の事情に鑑みてなされたもの
であって、スルーホールメツキ層のバレルクラックの発
生を抑制しくすなわち低膨張率の）、かつ伝達遅延時間
の短い多層プリント配線板を提供することを目的とする
。
［０００７］[Problems to be Solved by the Invention] However, since the above-mentioned fluororesin has a high coefficient of thermal expansion (-) when the fluororesin is used as a substrate material, the thickness of the multilayer printed wiring board may increase due to the influence of heat during component mounting. The amount of expansion in the horizontal direction becomes large.This tendency becomes even more pronounced especially in multilayer printed wiring boards with the number of layers of about 10 or more. Cracks (barrel cracks) may occur in the plating layer, and the reliability of the multilayer printed +-C wire plate may be lost. It is an object of the present invention to provide a multilayer printed wiring board that suppresses the occurrence of barrel cracks in the layers (ie, has a low expansion coefficient) and has a short transmission delay time. [0007]
【課題を解決するための手段】上記の目的を達成するた
めに本発明は内層導体が形成された複数の内層基板とプ
リプレグとを交互に積層してなる多層プリント配線板を
前提技術として、以下の手段を採用する。すなわち、図
１乃至図３に示すように、内層基板１の材質に例えばガ
ラス布基材エポキシ樹脂、またはガラス布基材ポリイミ
ド樹脂等の低膨張率材料を使用し、プリプレグ２に発泡
弗素樹脂を使用するとともに、スルーホールメツキ層１
３の膜厚を４５μｍ以上とした構成とした。
［０００８］[Means for Solving the Problems] In order to achieve the above object, the present invention uses a multilayer printed wiring board formed by alternately laminating a plurality of inner layer substrates on which inner layer conductors are formed and prepregs, and uses the following as a base technology. Adopt the following measures. That is, as shown in FIGS. 1 to 3, the material of the inner layer substrate 1 is a low expansion coefficient material such as a glass cloth base epoxy resin or a glass cloth base polyimide resin, and the prepreg 2 is a foamed fluororesin. Through-hole plating layer 1
The film thickness of No. 3 was set to 45 μm or more. [0008]
【作 用】上記構成において、基板材料として低膨張率
のガラス布基材エポキシ樹脂、またはガラス布基材ポリ
イミド樹脂を採用することにより熱による膨張量を抑制
することができ、従って、スルーホールメツキ層１３に
かかる多層プリント配線板の厚さ方向に生じる引張力を
低減する。
［０００９］また、スルーホールメツキ層１３の膜厚を
４５μｍ以上として該スルーホールメツキ層１３の強度
を向上させる。
［００１０１[Function] In the above structure, the amount of expansion due to heat can be suppressed by using a glass cloth base epoxy resin or a glass cloth base polyimide resin with a low expansion coefficient as the substrate material. The tensile force applied to layer 13 in the thickness direction of the multilayer printed wiring board is reduced. [0009] Furthermore, the strength of the through-hole plating layer 13 is improved by setting the thickness of the through-hole plating layer 13 to 45 μm or more. [00101
【実施例］以下本発明に関し、実施例をもとに詳細に説
明する。図１に示すように、本発明が適用される多層プ
Ｊント配線板の層構造は従来と同様、内層基板１とプリ
プレグ２とを交互に積層し、更に最上層の内層基板１ａ
の上面及び最下層の内層基板１ｂの下面にプリプレグ２
を介して銅箔３を積層した後、例えば真空中で所定の温
度および圧力を加えられることにより、各内層基板１、
プリプレグ２、銅箔３が接着される。
［００１１１本実施例において使用される低誘電率のプ
リプレグ２は、図２に示すように、弗素樹脂、例えば発
泡テフロンフィルム２ａに熱硬化性樹脂２ｂを含浸させ
た後硬化状態とし、さらに該発泡テフロンフィルム２ａ
の表裏両面に熱硬化性のエポキシ樹脂２ｃを積層した構
成とする。また、上記低膨張率の内層基板１は、ガラス
繊維を布状に編んだガラス布の表面にポリイミド樹脂を
含浸させ硬化させたガラス布ポリイミド樹脂基材を使用
し、上記ガラス繊維の材料を誘電率ε＝７程度のＥ−ガ
ラスや更に誘電率ε＝５程度のＤ−ガラスを使用した。
内層基板１の材料として上記弗素樹脂を用いると誘電率
を下げることはできるが、膨張率が大きくなって好まし
くない。
［００１２］尚、本発明では、上記ポリイミド樹脂に代
えてエポキシ樹脂を採用することもできる。上記積層工
程が完了した多層プリント配線板１０は、図３に示すよ
うに、所定の位置にスルーホール１１が明けられ（図３
（ａ） ） 、その後パネルメツキ層１２の形成（図３
（ｂ））、メツキレシス１〜１４の形成および第１のス
ルーホールメツキ層１３ａおよびランド１５ａの形成（
図３（Ｃ） ） 、を順次行う。更に一旦、上記メツキ
レジスト１４を剥離して（図３（ｄ））、再度のメツキ
レジスト１６の形成（図３（ｅ））、第２のスルーホー
ルメツキ層１３ｂ及びランド１５ｂの形成（図３（ｆ）
）、メツキレジスト１６の剥離（図３ （ｇ） ） 、
パネルメッキ層６１のエツチング（図３（ｈ））、を順
次行うことによって、スルーホールメツキ層１３の膜厚
を例えば４５μｍ以上に確保するようにしている。
［００１３１本発明においてはスルーホールメツキ層１
３の形成方法は特に限定しないが、１回のメツキ工程で
４５μｍ以上のメツキ層の膜厚を得ようとするよりも上
記のように２回に分けて行う方が短時間でメツキ形成工
程を完了することができる。ところで、多層プリント配
線板におけるバレルクラック発生頻度の目安を測定する
ために熱衝撃試験を行う。該熱衝撃試験の要領は図５に
示すように、常温から２６０±５℃のグリセリン中に多
層プリント配線板を５秒間浸漬した後、５分間だけ常温
にさらす温度変化を１サイクルとして計４サイクル繰り
返す前処理を行う。更にその後常温から冷却して一６５
℃で１５分間保持した後、昇温しで常温で５分間保持く
じ、さらに昇温しで１２５℃で１５分間保持し、再び常
温で５分間保持する温度変化を１サイクルとした熱スト
レスを所定回数加えるようにした。
［００１４１図４は多層プリント配線板に形成したスル
ーホールメツキ層の膜厚と、バレルクラックが発生する
までの上記熱衝撃試験のサイクル数との関係を示したグ
ラフである。図４において、曲線Ｃ１は上記実施例にお
いて得られた多層プリント配線板１０ （以下基板Ａと
する）の特性曲線であり、比較例として示す曲線Ｏ２は
内層基板としてガラス布基材エポキシ樹脂基材を、プリ
プレグとしてガラス布基材エポキシ樹脂を採用した多層
プラント配線板（以下基板Ｂとする）、同じく比較例と
して示す曲線Ｃ３は内層基板としてガラス布基材ポリイ
ミド樹脂基材をプリプレグとしてガラス布基材ポリイミ
ド樹脂を採用した多層プリント配線板（以下基板Ｃとす
る）の特性曲線である。
［００１５］図４において、上記熱衝撃試験の前処理以
降、例えば１００サイクルの熱ストレスに耐える品質の
基板を得るためのスルーホールメツキ層の膜厚は基板Ｂ
では１４μｍ、基板Ｃでは８μｍ程度であるが、発泡弗
素樹脂をプリプレグに採用した基板Ａでは４５μｍ以上
の膜厚を必要とすることがわかる。その一方で後掲する
表１に示すように、本発明による２つの実施例の伝達遅
延時間Ｔｐｄは比較例として示すポリイミド樹脂を結合
剤として使用した基材および、ポリイミド樹脂を接着剤
として使用したプリプレグに比べて小さくすることがで
きるので、特に高速処理の求められる電子機器に搭載す
る多層プリント配線板に本発明を適用することにより、
バレルクラックの発生を抑制して、接続信頼性を高める
ことができる。
［００１６］
【表１】
［００１７］[Examples] The present invention will be described in detail below based on Examples. As shown in FIG. 1, the layer structure of the multilayer printed wiring board to which the present invention is applied is similar to the conventional one, in which inner layer substrates 1 and prepregs 2 are alternately laminated, and the uppermost layer is an inner layer substrate 1a.
Prepreg 2 on the top surface and the bottom surface of the bottom inner layer substrate 1b.
After laminating the copper foil 3 through the inner layer substrate 1, each inner layer substrate 1,
Prepreg 2 and copper foil 3 are bonded. [00111 As shown in FIG. 2, the prepreg 2 with a low dielectric constant used in this example is made by impregnating a fluororesin, for example, a foamed Teflon film 2a, with a thermosetting resin 2b, and then curing the resin. Teflon film 2a
It has a structure in which thermosetting epoxy resin 2c is laminated on both the front and back sides. In addition, the inner layer substrate 1 with a low expansion coefficient uses a glass cloth polyimide resin base material in which the surface of a glass cloth knitted with glass fibers is impregnated with polyimide resin and cured. E-glass with a dielectric constant ε of about 7 and D-glass with a dielectric constant ε of about 5 were used. If the above-mentioned fluororesin is used as the material for the inner layer substrate 1, the dielectric constant can be lowered, but the coefficient of expansion increases, which is not preferable. [0012] In the present invention, an epoxy resin can also be used instead of the polyimide resin. The multilayer printed wiring board 10 on which the above lamination process has been completed has through holes 11 at predetermined positions, as shown in FIG.
(a) ), then the formation of the panel plating layer 12 (Fig. 3
(b)) Formation of plating layers 1 to 14 and formation of first through-hole plating layer 13a and land 15a (
3(C)) are performed sequentially. Furthermore, the plating resist 14 is once removed (FIG. 3(d)), the plating resist 16 is formed again (FIG. 3(e)), and the second through-hole plating layer 13b and land 15b are formed (FIG. 3(d)). (f)
), peeling of the metal resist 16 (Figure 3 (g)),
By sequentially etching the panel plating layer 61 (FIG. 3(h)), the thickness of the through-hole plating layer 13 is ensured to be, for example, 45 μm or more. [00131 In the present invention, through-hole plating layer 1
The formation method of step 3 is not particularly limited, but rather than trying to obtain a plating layer thickness of 45 μm or more in one plating process, it is easier to perform the plating process in two steps as described above in a shorter time. can be completed. By the way, a thermal shock test is conducted to measure the frequency of occurrence of barrel cracks in a multilayer printed wiring board. As shown in Figure 5, the thermal shock test consists of a total of 4 cycles in which the multilayer printed wiring board is immersed in glycerin at room temperature to 260±5°C for 5 seconds, and then exposed to room temperature for 5 minutes. Perform repeated preprocessing. Furthermore, it is cooled from room temperature to 165
After holding at ℃ for 15 minutes, increasing the temperature and holding at room temperature for 5 minutes, increasing the temperature further and holding at 125℃ for 15 minutes, and again holding at room temperature for 5 minutes, one cycle of temperature change was specified. I added the number of times. [00141 FIG. 4 is a graph showing the relationship between the thickness of the through-hole plating layer formed on the multilayer printed wiring board and the number of cycles of the thermal shock test described above until barrel cracks occur. In FIG. 4, a curve C1 is a characteristic curve of the multilayer printed wiring board 10 (hereinafter referred to as board A) obtained in the above example, and a curve O2 shown as a comparative example is a glass cloth base epoxy resin base as an inner layer board. A multilayer plant wiring board (hereinafter referred to as board B) employing a glass cloth base epoxy resin as a prepreg, and a curve C3 shown as a comparative example employs a glass cloth base polyimide resin base material as an inner layer substrate as a prepreg. This is a characteristic curve of a multilayer printed wiring board (hereinafter referred to as board C) employing polyimide resin as the material. [0015] In FIG. 4, after the pretreatment for the thermal shock test, the thickness of the through-hole plating layer for obtaining a substrate with a quality that can withstand, for example, 100 cycles of thermal stress is as follows for substrate B.
It can be seen that the film thickness is 14 μm for the substrate C, and about 8 μm for the substrate C, but the film thickness for the substrate A, in which a foamed fluororesin is used as the prepreg, is required to be 45 μm or more. On the other hand, as shown in Table 1 below, the transmission delay time Tpd of the two examples according to the present invention is shown as a comparative example: a base material using polyimide resin as a binder, and a base material using polyimide resin as an adhesive. Since it can be made smaller than prepreg, the present invention can be applied to multilayer printed wiring boards installed in electronic equipment that particularly requires high-speed processing.
It is possible to suppress the occurrence of barrel cracks and improve connection reliability. [0016] [Table 1] [0017]
Claims (2)
）とプリプレグ（２）とを交互に積層してなる多層プリ
ント配線板において、上記内層基板（１）の材質に低膨
張率材料を使用し、上記プリプレグ（２）に発泡弗素樹
脂を使用するとともに、スルーホールメッキ層（１３）
の膜厚を４５μｍ以上としたことを特徴とする多層プリ
ント配線板。Claim 1: A plurality of inner layer substrates (1) on which inner layer conductors are formed.
) and prepreg (2) are alternately laminated, a low expansion coefficient material is used for the inner layer substrate (1), a foamed fluororesin is used for the prepreg (2), and , through-hole plating layer (13)
A multilayer printed wiring board characterized by having a film thickness of 45 μm or more.
基材エポキシ樹脂、またはガラス布基材ポリイミド樹脂
を採用したことを特徴とする請求項１に記載の多層プリ
ント配線板。2. The multilayer printed wiring board according to claim 1, wherein the inner layer substrate (1) is made of a glass cloth-based epoxy resin or a glass cloth-based polyimide resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40003390A JPH04208597A (en) | 1990-12-01 | 1990-12-01 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40003390A JPH04208597A (en) | 1990-12-01 | 1990-12-01 | Multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04208597A true JPH04208597A (en) | 1992-07-30 |
Family
ID=18509951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40003390A Pending JPH04208597A (en) | 1990-12-01 | 1990-12-01 | Multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04208597A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002280736A (en) * | 2001-03-21 | 2002-09-27 | Nec Corp | Multilayer printed wiring board and its manufacturing method |
| US8492898B2 (en) | 2007-02-19 | 2013-07-23 | Semblant Global Limited | Printed circuit boards |
| US8995146B2 (en) | 2010-02-23 | 2015-03-31 | Semblant Limited | Electrical assembly and method |
| US9709619B2 (en) | 2012-09-19 | 2017-07-18 | Fujitsu Limited | Printed wiring board, crack prediction device, and crack prediction method |
| US11786930B2 (en) | 2016-12-13 | 2023-10-17 | Hzo, Inc. | Protective coating |
-
1990
- 1990-12-01 JP JP40003390A patent/JPH04208597A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002280736A (en) * | 2001-03-21 | 2002-09-27 | Nec Corp | Multilayer printed wiring board and its manufacturing method |
| US8492898B2 (en) | 2007-02-19 | 2013-07-23 | Semblant Global Limited | Printed circuit boards |
| US9648720B2 (en) | 2007-02-19 | 2017-05-09 | Semblant Global Limited | Method for manufacturing printed circuit boards |
| US8995146B2 (en) | 2010-02-23 | 2015-03-31 | Semblant Limited | Electrical assembly and method |
| US9709619B2 (en) | 2012-09-19 | 2017-07-18 | Fujitsu Limited | Printed wiring board, crack prediction device, and crack prediction method |
| US10605851B2 (en) | 2012-09-19 | 2020-03-31 | Fujitsu Limited | Printed wiring board, crack prediction device, and crack prediction method |
| US11786930B2 (en) | 2016-12-13 | 2023-10-17 | Hzo, Inc. | Protective coating |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990112 |