WO2014073139A1 - Ultraviolet semiconductor light emitting element and method for manufacturing same - Google Patents

Ultraviolet semiconductor light emitting element and method for manufacturing same Download PDF

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Publication number
WO2014073139A1
WO2014073139A1 PCT/JP2013/005484 JP2013005484W WO2014073139A1 WO 2014073139 A1 WO2014073139 A1 WO 2014073139A1 JP 2013005484 W JP2013005484 W JP 2013005484W WO 2014073139 A1 WO2014073139 A1 WO 2014073139A1
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layer
electrode
type
light emitting
semiconductor light
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PCT/JP2013/005484
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French (fr)
Japanese (ja)
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憲路 野口
卓哉 美濃
隆好 高野
椿　健治
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present invention relates to an ultraviolet semiconductor light-emitting element that emits light in a wavelength region of ultraviolet rays (also referred to as ultraviolet light) and a method for manufacturing the same.
  • Ultraviolet semiconductor light-emitting elements are expected to be applied in various fields such as hygiene, medicine, industry, lighting, and precision machinery.
  • an ultraviolet semiconductor light emitting device As an ultraviolet semiconductor light emitting device, a device using a group III nitride semiconductor as a material of a light emitting layer has been researched and developed in various places. As this type of ultraviolet semiconductor light-emitting device, for example, a device in which a laminated film of an n-type layer, a light-emitting layer, and a p-type layer on one surface side of a sapphire substrate has a mesa structure is known.
  • a laminated film of an n-type layer, a light-emitting layer, and a p-type layer is formed on the one surface side of the sapphire substrate, and then a part of the n-type layer is formed by using a photolithography technique and an etching technique. It is formed by patterning the laminated film so as to expose the film.
  • An ultraviolet semiconductor light-emitting device having a mesa structure includes an n-electrode made of a metal electrode electrically connected to an n-type layer and a p-electrode made of a metal electrode electrically connected to a p-type layer. It is arranged side by side on the one surface side.
  • the current flowing between the p electrode and the n electrode tends to flow through a path having a low resistance between the p electrode and the n electrode, so that it is close to the n electrode in the mesa structure.
  • Current concentration occurs at the end of the side. Such current concentration tends to occur particularly when a material such as AlGaN having a high Al composition ratio is used for the n-type layer, or when the area of the ultraviolet semiconductor light emitting device is large.
  • current concentration occurs in the ultraviolet semiconductor light-emitting element, the current does not flow uniformly, causing uneven light emission or causing local heat generation. In the ultraviolet semiconductor light emitting element, such local heat generation causes deterioration of the characteristics of the ultraviolet semiconductor light emitting element, such as a decrease in light emission efficiency, an increase in driving voltage, and a decrease in reliability.
  • the second electrode provided on the p-type layer has a pedestal portion and a first extending portion extending from the pedestal portion as a base point (for example, Japanese Patent No. 4415575). See the publication).
  • the first electrode since the first electrode includes the extending portion in addition to the base portion, it is necessary to increase the area of the exposed portion of the n-type layer, and the area of the light emitting layer is reduced. The light emitting area is reduced.
  • an object of the present invention is to provide an ultraviolet semiconductor light emitting device capable of suppressing current concentration without reducing the light emitting area and a method for manufacturing the same.
  • the ultraviolet semiconductor light-emitting device of the present invention includes a laminated film of an n-type layer, a light-emitting layer, and a p-type layer, an n electrode, a p electrode, and a high resistance layer.
  • the laminated film is laminated on one surface side of the substrate.
  • the laminated film has a mesa structure.
  • the n-electrode is provided on the exposed surface of the n-type layer on the one surface side of the substrate.
  • the p-electrode is provided on the surface side of the p-type layer on the one surface side of the substrate.
  • the p-electrode is formed to cover the p-type layer in a planar shape.
  • the high-resistance layer has a higher resistance than the p-type layer or the p-electrode.
  • the high resistance layer is formed on the surface of the p-type layer in a shape along the shape of the n-electrode on the p-type layer side on the side close to the n-electrode.
  • the high resistance layer has a smaller resistance as the distance from the n electrode increases.
  • a plurality of the high resistance layers are formed on the surface of the p-type layer, and the contact area with the p-type layer is smaller as the high resistance layer is farther from the n-electrode. Is preferred.
  • the high resistance layers are formed on the surface of the p-type layer, and the film thickness is smaller as the high resistance layer is farther from the n electrode.
  • the high resistance layer is preferably composed of a p-type group III nitride semiconductor layer, and has a higher resistance than the p-type layer.
  • the high resistance layer is preferably made of a metal layer or a conductive oxide layer and has a higher resistance than the p electrode.
  • the manufacturing method of the ultraviolet semiconductor light emitting device of the present invention includes the following first to seventh steps.
  • the first step after the substrate is prepared, the n-type layer, the light emitting layer, and the p-type layer are sequentially stacked on one surface side of the substrate.
  • a mesa structure is formed by etching a part of the laminated film of the n-type layer, the light-emitting layer, and the p-type layer halfway in the thickness direction of the n-type layer.
  • a first electrode layer serving as a source of the n-electrode is formed on the exposed surface of the n-type layer.
  • the n-electrode is formed by heat-treating the first electrode layer and the n-type layer.
  • a high resistance layer is formed on the p-type layer.
  • a second electrode layer serving as a source of the p electrode is formed on the p-type layer and the high resistance layer.
  • the p-electrode is formed by heat-treating the second electrode layer and the p-type layer.
  • the fifth step preferably includes the following first step and second step.
  • a metal material layer that forms the basis of the high resistance layer is formed.
  • the second step forms the high resistance layer by heat-treating the metal material layer.
  • the heat treatment temperature in the second step is different from the heat treatment temperature in the seventh step.
  • the fifth step preferably includes the following first step, second step, and third step.
  • a mask layer is formed that covers the surface of the p-type layer except for the region where the high resistance layer is to be formed.
  • the high resistance layer made of a group III nitride semiconductor layer is selectively grown on the surface of the p-type layer.
  • the mask layer is removed.
  • FIG. 1A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 1.
  • FIG. 1B is a schematic cross-sectional view taken along the line XX of FIG. 1A.
  • 1C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 1B.
  • 2A is a main process sectional view for explaining an example of the manufacturing method of the ultraviolet semiconductor light-emitting device of Embodiment 1.
  • FIG. FIG. 2B is a main process cross-sectional view for describing an example of the manufacturing method of the ultraviolet semiconductor light-emitting device of Embodiment 1.
  • FIG. 1A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 1.
  • FIG. 1B is a schematic cross-sectional view taken along the line XX of FIG. 1A.
  • 1C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 1B.
  • 2A is a main process sectional
  • FIG. 3A is a main process sectional view for explaining another example of the method for producing the ultraviolet semiconductor light-emitting device of the first embodiment.
  • FIG. 3B is a main process cross-sectional view for explaining another example of the method for manufacturing the ultraviolet semiconductor light-emitting device of Embodiment 1.
  • FIG. 3C is a main process cross-sectional view for explaining another example of the method for manufacturing the ultraviolet semiconductor light-emitting device of Embodiment 1.
  • 4A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 2.
  • FIG. 4B is a schematic cross-sectional view taken along the line XX of FIG. 4A.
  • 4C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 4B.
  • FIG. 5A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 3.
  • FIG. 5B is a schematic cross-sectional view taken along the line XX of FIG. 5A.
  • FIG. 5C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 5B.
  • FIG. 6A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 4.
  • FIG. 6B is a schematic cross-sectional view taken along the line XX of FIG. 6A.
  • 6C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 6B.
  • the laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 on the one surface 1aa side of the substrate 1 has a mesa structure.
  • the ultraviolet semiconductor light emitting element 10 includes an n electrode 6 provided on the exposed surface 3a of the n-type layer 3 on the one surface 1aa side of the substrate 1, and a surface 5aa side of the p-type layer 5 on the one surface 1aa side of the substrate 1. And a p-electrode 7 provided.
  • the ultraviolet semiconductor light emitting element 10 is a light emitting diode.
  • the ultraviolet semiconductor light emitting element 10 is formed so that the p-electrode 7 covers the p-type layer 5 in a planar shape. Further, in the ultraviolet semiconductor light emitting device 10, the p-type layer 5 or the p-type layer in the n-electrode 6 has a high-resistance layer 8 having a higher resistance than the p-electrode 7 on the side close to the n-electrode 6 on the surface 5aa of the p-type layer 5. It is formed in a shape along the shape on the 5 side. Thereby, the ultraviolet semiconductor light emitting element 10 can suppress current concentration without reducing the light emitting area.
  • the resistance of the high resistance layer 8 is a sheet resistance or an ohmic resistance (contact resistance).
  • “higher resistance than the p-type layer 5” means that the sheet resistance is higher than that of the p-type layer 5.
  • “higher resistance than the p electrode 7” means that the ohmic resistance is higher than that of the p electrode 7.
  • the ultraviolet semiconductor light emitting element 10 preferably includes a buffer layer 2 between the substrate 1 and the n-type layer 3.
  • the substrate 1 is a single crystal substrate for epitaxial growth.
  • a sapphire substrate having one surface 1aa of (0001) plane can be used. That is, as the substrate 1, a c-plane sapphire substrate ( ⁇ -Al 2 O 3 substrate) can be preferably used.
  • the c-plane sapphire substrate preferably has an off angle from (0001) of 0 to 0.2 °.
  • the ultraviolet semiconductor light emitting element 10 when light is extracted from the other surface 1 ab of the substrate 1, a single crystal substrate that is transparent to the ultraviolet light emitted from the light emitting layer 4 may be adopted as the substrate 1. In this case, the ultraviolet semiconductor light emitting element 10 has the other surface 1ab of the substrate 1 as a light extraction surface.
  • the substrate 1 is not limited to a sapphire substrate, but, for example, a gallium oxide substrate ( ⁇ -Ga 2 O 3 substrate), a spinel substrate, a silicon carbide substrate, a zinc oxide substrate, a magnesium oxide substrate, a zirconium boride substrate, a group III nitride system A semiconductor substrate or the like may be used.
  • the ultraviolet semiconductor light emitting element 10 may be removed by lift-off or the like when the single crystal substrate for epitaxial growth used at the time of manufacture is not a translucent substrate capable of transmitting ultraviolet light. In this case, the ultraviolet semiconductor light emitting element 10 is manufactured by attaching a support substrate to the outermost layer side of the single crystal substrate which is the one surface 1aa side of the substrate 1 before removing the single crystal substrate for epitaxial growth. preferable.
  • the buffer layer 2 is provided to reduce threading dislocations in the n-type layer 3 and to reduce residual strain in the n-type layer 3.
  • the buffer layer 2 is composed of an AlN layer, but is not limited to an AlN layer.
  • the buffer layer 2 may be composed of, for example, an AlGaN layer, an AlInN layer, a GaN layer, or the like. If the buffer layer 2 is too thin, threading dislocations tend to be insufficiently reduced. Further, if the buffer layer 2 is too thick, there is a concern that cracks due to lattice mismatch and warping of the wafer on which the plurality of ultraviolet semiconductor light emitting elements 10 are formed become large.
  • the thickness of the buffer layer 2 is preferably set in the range of about 500 nm to 10 ⁇ m, and more preferably set in the range of 1 ⁇ m to 5 ⁇ m.
  • the film thickness of the buffer layer 2 is preferably set so that the surface of the buffer layer 2 is flattened.
  • the wafer is a source of the plurality of ultraviolet semiconductor light emitting elements 10.
  • the n-type layer 3 is for injecting electrons into the light emitting layer 4 and can be composed of an n-type nitride semiconductor layer.
  • the thickness of the n-type layer 3 is set to 2 ⁇ m as an example, but is not particularly limited.
  • the n-type nitride semiconductor layer can be composed of an n-type Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer.
  • the n-type nitride semiconductor layer does not particularly limit the composition ratio of the n-type Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer.
  • the n-type nitride semiconductor layer preferably has a composition ratio that allows the n-type Al z Ga 1 -z N (0 ⁇ z ⁇ 1) layer to suppress absorption of ultraviolet light emitted from the light-emitting layer 4.
  • the n-type nitride semiconductor layer has, for example, an Al composition ratio of the well layer of the light emitting layer 4 of 0.40 and an Al composition ratio of the barrier layer of 0. .55
  • the Al composition ratio z of the n-type Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer can be set to 0.55, which is the same as the Al composition ratio of the barrier layer. .
  • the n-type nitride semiconductor layer is, for example, an n-type Al 0.55 Ga 0.45 N layer. can do.
  • the n-type layer 3 is not limited to a single layer structure, and may have a multilayer structure.
  • the n-type layer 3 may be composed of, for example, an n-type Al 0.7 Ga 0.3 N layer and an n-type Al 0.55 Ga 0.45 N layer on the n-type Al 0.7 Ga 0.3 N layer.
  • the electron concentration of the n-type nitride semiconductor layer may be set, for example, in the range of about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the light emitting layer 4 converts injected carriers into light and has a quantum well structure.
  • the carriers are electrons and holes.
  • the quantum well structure includes a barrier layer and a well layer.
  • barrier layers and well layers are alternately stacked, and the number of well layers is 2, but the number of well layers is not particularly limited.
  • the quantum well structure may be a multiple quantum well structure or a single quantum well structure.
  • the thicknesses of the well layer and the barrier layer are not particularly limited. However, if the thickness of the well layer is too thick, the light emitting layer 4 spatially separates electrons and holes injected into the well layer by a piezo electric field due to lattice mismatch in the quantum well structure, Luminous efficiency decreases.
  • the thickness of the well layer is preferably about 1 nm to 5 nm, more preferably about 1.3 nm to 3 nm.
  • the thickness of the barrier layer is preferably set in the range of about 5 nm to 15 nm, for example.
  • the ultraviolet semiconductor light emitting element 10 can set the thickness of the well layer to 2 nm and the thickness of the barrier layer to 8 nm.
  • the Al composition ratio of the well layer is set so as to emit ultraviolet light having a desired light emission wavelength.
  • the light emitting layer 4 having a well layer composed of Al a Ga 1-a N (0 ⁇ a ⁇ 1) layer has an emission wavelength in the range of 210 nm to 360 nm by changing the Al composition ratio a of the well layer. It is possible to set an arbitrary emission wavelength.
  • the barrier layer is composed of an Al 0.55 Ga 0.45 N layer and the well layer is composed of an Al 0.40 Ga 0.60 N layer, but the composition ratio of the barrier layer and the well layer is limited. Instead, the composition ratios may be set as appropriate according to the desired emission wavelength.
  • the light emitting layer 4 has a single layer structure, and a double hetero structure is formed by the light emitting layer 4 and the layers on the both sides in the thickness direction of the light emitting layer 4 (n-type layer 3, p-type layer 5). You may make it do.
  • the p-type layer 5 includes, for example, a first p-type nitride semiconductor layer formed on the light emitting layer 4 and a second p-type nitride semiconductor formed on the first p-type nitride semiconductor layer. And a third p-type nitride semiconductor layer formed on the second p-type nitride semiconductor layer.
  • Mg is preferable as the acceptor impurity of the first to third p-type nitride semiconductor layers.
  • the first p-type nitride semiconductor layer is provided as an electron block layer.
  • the electron blocking layer prevents electrons that have not been recombined with holes in the light emitting layer 4 out of electrons injected into the light emitting layer 4 from leaking (overflowing) to the second p-type nitride semiconductor layer side. In order to suppress it, it is provided between the light emitting layer 4 and the second p-type nitride semiconductor layer.
  • the electron block layer is composed of a p-type Al c Ga 1-c N (0 ⁇ c ⁇ 1) layer.
  • the composition ratio of the p-type Al c Ga 1-c N (0 ⁇ c ⁇ 1) layer is not particularly limited.
  • the composition ratio of the p-type Al c Ga 1-c N (0 ⁇ c ⁇ 1) layer is such that the band gap energy of the electron block layer is larger than the band gap energy of each of the second p-type nitride semiconductor layer and the barrier layer. It is preferable to set it to be high.
  • the ultraviolet semiconductor light emitting element 10 has an electron blocking layer formed of a p-type Al 0.95 Ga 0.05 N layer.
  • the hole concentration of the electron blocking layer is not particularly limited. Further, the thickness of the electron blocking layer is not particularly limited, but if the film thickness is too thin, the overflow suppressing effect is reduced, and if the film thickness is too thick, the resistance of the ultraviolet semiconductor light emitting element 10 is increased. .
  • the film thickness of the electron block layer varies depending on values such as the Al composition ratio c and the hole concentration. Therefore, although it cannot be generally stated, it should be set within a range of 1 nm to 50 nm. It is preferable to set the thickness in the range of 5 nm to 25 nm.
  • the ultraviolet semiconductor light emitting element 10 can set the thickness of the electron block layer to 15 nm.
  • the second p-type nitride semiconductor layer is for transporting holes to the light emitting layer 4.
  • the second p-type nitride semiconductor layer can be composed of a p-type Al d Ga 1-d N (0 ⁇ d ⁇ 1) layer.
  • the composition ratio of the p-type Al d Ga 1-d N (0 ⁇ d ⁇ 1) layer is not particularly limited as long as it can suppress the absorption of ultraviolet light emitted from the light emitting layer 4.
  • the Al composition ratio of the well layer in the light emitting layer 4 is 0.40 and the Al composition ratio of the barrier layer is 0.55 as described above, p-type Al d Ga 1-d N (0 ⁇ d ⁇ 1)
  • the Al composition ratio d of the layer can be set to 0.55, which is the same as the Al composition ratio a of the barrier layer, for example. That is, in the ultraviolet semiconductor light emitting device 10, when the well layer of the light emitting layer 4 is composed of an Al 0.40 Ga 0.60 N layer, the second p-type nitride semiconductor layer is configured by, for example, a p-type Al 0.55 Ga 0.45 N layer. be able to.
  • the hole concentration of the second p-type nitride semiconductor layer is not particularly limited, and a higher concentration is preferable in the hole concentration range in which the film quality of the second p-type nitride semiconductor layer does not deteriorate.
  • the ultraviolet semiconductor light emitting device 10 has a p-type Al d Ga 1-d N (0 ⁇ d ⁇ 1) layer whose electron concentration is an n-type Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer. Since the concentration is lower than the concentration, if the thickness of the second p-type nitride semiconductor layer is too thick, the resistance of the ultraviolet semiconductor light emitting element 10 becomes too large.
  • the film thickness of the second p-type nitride semiconductor layer is preferably 200 nm or less, and more preferably 100 nm or less.
  • the thickness of the second p-type nitride semiconductor layer is set to 50 nm.
  • the third p-type nitride semiconductor layer is provided as a p-type contact layer.
  • the p-type contact layer is provided in order to reduce the contact resistance with the p-electrode 7 and obtain good ohmic contact with the p-electrode 7.
  • the p-type contact layer is composed of a p-type GaN layer.
  • the p-type contact layer preferably has a higher hole concentration than the second p-type nitride semiconductor layer. By setting the hole concentration of the p-type GaN layer to, for example, about 7 ⁇ 10 17 cm ⁇ 3 , good electrical contact with the p-electrode 7 can be obtained.
  • the hole concentration of the p-type GaN layer is not particularly limited, and may be changed as appropriate within the range of the hole concentration at which good electrical contact with the p electrode 7 is obtained.
  • the thickness of the p-type contact layer is set to 15 nm, but is not limited thereto, and may be set in the range of 10 nm to 150 nm, for example.
  • the nitride semiconductor employed in the p-type layer 5 is not particularly limited as long as it is a group III nitride semiconductor.
  • AlGaInN may be employed.
  • the third p-type nitride semiconductor layer may employ InGaN in addition to AlGaInN.
  • the mesa structure uses a photolithography technique and an etching technique after a laminated film of an n-type layer 3, a light emitting layer 4, and a p-type layer 5 is formed on one surface 1aa side of the substrate 1 by a crystal growth method.
  • the laminated film can be formed by patterning so that a part of the n-type layer 3 is exposed.
  • the crystal growth method is an epitaxial growth method.
  • Epitaxial growth methods include, for example, metal organic vapor phase (MOVPE) method, hydride vapor phase (HVPE) method, molecular beam epitaxy (MBE) method and the like. Can be adopted.
  • the n-electrode 6 is formed so as to cover a region above one corner of the four corners of the substrate 1 on the exposed surface 3a of the n-type layer 3 in a planar shape. Can do.
  • the exposed surface 3a has an area above one of the four corners of the substrate 1 as a quarter-round planar shape, but the planar shape is not particularly limited.
  • the region above one of the four corners of the substrate 1 on the exposed surface 3a of the n-type layer 3 is referred to as an electrode formation region.
  • the planar shape of the n electrode 6 is a quarter circle that is slightly smaller than the electrode formation region of the exposed surface 3a.
  • the planar shape of the n electrode 6 is preferably substantially similar to the electrode forming region of the exposed surface 3a.
  • the n-electrode 6 can be formed by forming a first electrode layer as a base of the n-electrode 6 and then performing a heat treatment (annealing process) between the first electrode layer and the n-type layer 3.
  • the first electrode layer is, for example, a laminated film in which a Ti film having a thickness of 20 nm, an Al film having a thickness of 100 nm, a Ti film having a thickness of 20 nm, and an Au film having a thickness of 200 nm are laminated. Can be configured.
  • the configuration of the first electrode layer and the film thickness of each film are not particularly limited.
  • the ultraviolet semiconductor light emitting element 10 preferably includes a first pad electrode (not shown) made of, for example, an Au film on the n electrode 6.
  • the first pad electrode can be formed after the n electrode 6 is formed.
  • the first pad electrode may not be formed separately from the n electrode 6, but the n electrode 6 may also serve as the first pad electrode.
  • the p electrode 7 is formed by performing a heat treatment (annealing treatment) between the second electrode layer and the p-type layer 5 after forming the second electrode layer that is the base of the p electrode 7.
  • the second electrode layer is configured by a laminated film in which a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm are laminated.
  • the configuration of the second electrode layer and the film thickness of each film are not particularly limited.
  • the ultraviolet semiconductor light emitting element 10 preferably includes a second pad electrode (not shown) made of, for example, an Au film on the p electrode 7.
  • the second pad electrode is preferably formed after the p-electrode 7 is formed.
  • the planar shape of the p electrode 7 is slightly smaller than the surface 5aa of the p-type layer 5.
  • the planar shape of the p-type electrode 7 is preferably substantially similar to the surface 5aa of the p-type layer 5.
  • the material of the high resistance layer 8 is preferably a group III nitride semiconductor, a metal, a conductive oxide, or the like because of the ease of manufacturing the high resistance layer 8 and the ease of resistance control.
  • a III-V group semiconductor or a group IV semiconductor other than the group III nitride semiconductor may be employed as a material of the high resistance layer 8.
  • the resistance of the high resistance layer 8 can be controlled by its material, film forming method, film forming conditions, processing conditions, and the like.
  • the high resistance layer 8 can be constituted by, for example, a p-type group III nitride semiconductor layer. In this case, the high resistance layer 8 only needs to have a higher resistance than the p-type layer 5.
  • the group III nitride semiconductor layer constituting the high-resistance layer 8 for example, a p-type GaN layer (p ⁇ GaN layer) having a higher resistance than the p-type GaN layer constituting the third nitride semiconductor layer is employed. be able to.
  • the group III nitride semiconductor layer constituting the high resistance layer 8 is not limited to the p-type GaN layer, and for example, an InGaN layer, an AlGaN layer, an InAlGaN layer, or the like may be employed. Note that the conductivity type and resistance of the group III nitride semiconductor layer constituting the high resistance layer 8 can be estimated, for example, by performing hole measurement on a sample in which the group III nitride semiconductor layer is grown as a single film. it can. The resistance of the group III nitride semiconductor layer constituting the high resistance layer 8 can be adjusted by appropriately setting growth conditions such as the substrate temperature and the V / III ratio during film formation.
  • the high resistance layer 8 can be composed of a metal layer or a transparent conductive oxide layer, and in this case, it may be higher in resistance than the p electrode 7.
  • the metal layer constituting the high resistance layer 8 for example, a laminated film of a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm can be employed.
  • the film thickness and material of the metal layer constituting the high resistance layer 8 are not particularly limited.
  • the high resistance layer 8 is composed of a conductive oxide layer, for example, ITO, AZO, GZO, IZO or the like can be used as the material of the conductive oxide layer.
  • the high resistance layer 8 can be formed on the surface 5aa of the p-type layer 5 on the side close to the n-electrode 6 and along the shape of the n-electrode 6 on the p-type layer 5 side.
  • the high resistance layer 8 can be formed, for example, in an arc shape along the shape of the n-electrode 6 on the p-type layer 5 side.
  • the comparative ultraviolet semiconductor light emitting device When considering an equivalent circuit of a comparative ultraviolet semiconductor light emitting device that does not include the high resistance layer 8, the comparative ultraviolet semiconductor light emitting device has a long distance between any two points of the n electrode 6 and the p electrode 7. It is considered that the current is easily affected by the resistance of the n-type layer 3. That is, in the ultraviolet semiconductor light emitting device of the comparative example, a larger current flows at the end portion closer to the n electrode 6 in the mesa structure where the distance between any two points of the n electrode 6 and the p electrode 7 is shortened. It becomes easy.
  • the inventors of the present application have found that it is important to improve the conductivity of the n-type layer 3 to fundamentally solve the above problem.
  • AlGaN having a high Al composition ratio includes, for example, an Al composition ratio of 0.4 or more.
  • the inventors of the present application have extracted a new problem that the light emitting area is reduced as a problem of the ultraviolet semiconductor light emitting device adopting the shapes of the first electrode and the second electrode of Patent Document 1 in order to suppress current concentration. did.
  • the inventors of the present application form the high resistance layer 8 at the end near the n electrode 6 in the mesa structure where current concentration is likely to occur, and the influence of the resistance of the n-type layer 3 on the current distribution is reduced. This led to the idea of spreading the current.
  • the ultraviolet semiconductor light emitting element 10 can reduce the resistance difference between the resistance of the current path passing through the region where the high resistance layer 8 is provided and the resistance of the current path passing through the region where the high resistance layer 8 is not provided. It is possible to suppress the occurrence of local current concentration. In short, in the ultraviolet semiconductor light emitting device 10, the current concentration in the current path passing through the region where the high resistance layer 8 is provided is reduced. Therefore, the ultraviolet semiconductor light emitting element 10 can suppress current concentration without reducing the light emitting area.
  • the ultraviolet semiconductor light emitting element 10 can suppress current concentration and suppress uneven light emission without affecting the shapes of the n electrode 6 and the p electrode 7. Further, the ultraviolet semiconductor light emitting device 10 has an n-type layer 3 made of AlGaN having an Al composition ratio of 0.40 or more, or a chip area of 0.35 ⁇ 0. Even when the thickness is 35 ⁇ m 2 or more, current concentration can be suppressed without reducing the light emitting area.
  • Step of introducing the substrate 1 into the reaction furnace After preparing the substrate 1 made of, for example, a c-plane sapphire substrate, the substrate 1 is introduced into the reaction furnace of the MOVPE apparatus. In this step, it is preferable to clean the substrate 1 by performing a pretreatment with chemicals on the substrate 1 before introducing the substrate 1 into the reaction furnace. Also, in this step, after introducing the substrate 1 into the reaction furnace, the inside of the reaction furnace is evacuated, and then a highly purified nitrogen gas or the like is flowed into the reaction furnace to thereby circulate the inside of the reaction furnace with nitrogen gas.
  • the substrate 1 is preferably in a wafer state in which a plurality of ultraviolet semiconductor light emitting elements 10 can be formed.
  • a step of heating the substrate 1 to clean one surface 1aa of the substrate 1 This step raises the substrate temperature, which is the temperature of the substrate 1 introduced into the reaction furnace, to the first specified temperature, Furthermore, one surface 1aa of the substrate 1 is cleaned by heating at the first specified temperature.
  • the first specified temperature is set to 1250 ° C.
  • the substrate temperature is raised to the first specified temperature while maintaining the first specified pressure in the reaction furnace.
  • the one surface 1aa of the substrate 1 is cleaned by heating at the first specified temperature for a first specified time.
  • cleaning can be effectively performed by heating the substrate 1 in a state where H 2 gas is supplied into the reaction furnace.
  • the first specified pressure is set to 10 kPa ⁇ 76 Torr.
  • the first specified temperature is preferably set in a temperature range of 1000 to 1300 ° C., more preferably set in a temperature range of 1050 to 1250 ° C.
  • the first specified time is set to 10 minutes.
  • the values of the first specified pressure and the first specified time are examples, and are not particularly limited.
  • Step of Forming Buffer Layer 2 Al y Ga 1-y N (0 ⁇ y ⁇ 1) is provided by supplying a group III constituent element source gas and a group V constituent element source gas. ) Is a step of forming the buffer layer 2 composed of layers.
  • H 2 gas is preferably used as the carrier gas of each source gas.
  • the second specified pressure is set to 10 kPa which is the same as the first specified pressure
  • the second specified temperature is set to 1250 ° C. which is the same as the first specified temperature. Note that the values of the second specified pressure and the second specified temperature are examples, and are not particularly limited.
  • the buffer layer 2 is an AlN layer in which the Al composition ratio y of the Al y Ga 1-y N (0 ⁇ y ⁇ 1) layer is 1, for example, as a group III source gas Trimethyl aluminum (TMAl) and NH 3 as a group V source gas are supplied into the reaction furnace.
  • TMAl Trimethyl aluminum
  • NH 3 a group V source gas
  • the flow rate of TMAl is set to 0.05 L / min (50 SCCM) in the standard state
  • the flow rate of NH 3 is set to 0.05 L / min (50 SCCM) in the standard state.
  • TMAl and NH 3 are simultaneously fed into the reactor.
  • TMAl and NH 3 can be simultaneously supplied into the reactor to grow the buffer layer 2 made of a single crystal AlN layer.
  • TMAl and trimethylgallium as group III source gases Trimethyl gallium: TMGa
  • NH 3 Trimethyl gallium: TMGa
  • TMAl and trimethylgallium as group III source gases Trimethyl gallium: TMGa
  • NH 3 a group V source gas
  • Step of forming n-type layer 3 This step is a step of forming n-type layer 3 on one surface 1aa side of substrate 1.
  • this step is a step of forming the n-type layer 3 on the buffer layer 2.
  • n-type layer 3 is formed.
  • the source gas for example, a group III source gas, a group V source gas, and an n-type conductivity of an n-type Al z Ga 1 -z N (0 ⁇ z ⁇ 1) layer are used.
  • An impurity source gas that imparts can be used.
  • the third specified pressure is set to 10 kPa, which is the same as the first specified pressure, and the third specified temperature is set to 1200 ° C. Note that the values of the third specified pressure and the third specified temperature are examples, and are not particularly limited.
  • TMAl is used as an Al source gas
  • TMGa is used as a Ga source gas
  • NH 3 is used as an N source gas
  • tetraethylsilane Si is an impurity imparting n-type conductivity
  • tetraethylsilane TESi
  • H 2 gas As the carrier gas for carrying the source gas, it is possible to use H 2 gas.
  • the flow rate of TESi can be 0.0009 L / min (0.9 SCCM) in a standard state.
  • the molar ratio of TMAl in the group III source gas ([TMAl] / ⁇ [TMAl] + [TMGa] ⁇ ) so that the Al composition ratio becomes a desired value (for example, 0.55).
  • a desired value for example, 0.55
  • Each source gas is not particularly limited.
  • triethyl gallium (TEGa) may be used as a Ga source
  • a hydrazine derivative may be used as an N source gas
  • monosilane (SiH 4 ) may be used as a Si source.
  • the flow rate of each source gas is an example, and is not particularly limited.
  • Step of forming the light emitting layer 4 This step is a step of forming the light emitting layer 4 on the n-type layer 3.
  • the group III source gas and the group V source gas are maintained while maintaining the substrate temperature at the fourth specified temperature (predetermined growth temperature) while maintaining the pressure in the reactor at the fourth specified pressure.
  • the supply into the reaction furnace is started to form the light emitting layer 4.
  • the fourth specified pressure can be set to 10 kPa which is the same as the first specified pressure
  • the fourth specified temperature can be set to 1200 ° C. which is the same as the third specified temperature.
  • each value of 4th specified pressure and 4th specified temperature is an example, and it does not specifically limit it.
  • the growth conditions of the well layer and the barrier layer are set so that the well layer of the light emitting layer 4 becomes an Al 0.40 Ga 0.60 N layer and the barrier layer becomes an Al 0.55 Ga 0.45 N layer.
  • the composition ratio of each of the well layer and the barrier layer is not particularly limited.
  • the growth conditions for the well layer and the barrier layer may be set based on the desired composition ratios of the well layer and the barrier layer.
  • TMAl is used as the Al source gas
  • TMGa is used as the Ga source gas
  • NH 3 is used as the N source gas
  • H 2 gas is used as the carrier gas for transporting each source gas.
  • the molar ratio of TMAl in the group III source gas [TMAl] / ⁇ [TMAl] + [TMGa] ⁇ ) is obtained so as to obtain a desired composition ratio. Is set. Further, in the step of forming the light emitting layer 4, the molar ratio in the growth conditions of the well layer is set smaller than the molar ratio in the growth conditions of the barrier layer.
  • the barrier layer is not doped with impurities.
  • impurities such as Si may be doped at a concentration that does not deteriorate the crystal quality of the barrier layer.
  • the Si source gas for example, TESi can be used.
  • Each source gas is not particularly limited.
  • TEGa may be used as a Ga source material
  • a hydrazine derivative may be used as an N source gas
  • SiH 4 may be used as an Si source material.
  • the flow rate of each source gas is an example, and is not particularly limited.
  • Step of forming first p-type nitride semiconductor layer of p-type layer 5 This step is a step of forming a first p-type nitride semiconductor layer serving as an electron blocking layer on light emitting layer 4. .
  • the group III source gas and the group V source gas are added.
  • Supply into the reaction furnace is started to form a first p-type nitride semiconductor layer.
  • the fifth specified pressure is set to 10 kPa which is the same as the first specified pressure
  • the fifth specified temperature is set to 1050 ° C. Note that the values of the fifth specified pressure and the fifth specified temperature are examples, and are not particularly limited.
  • TMAl is used as the Al source gas
  • TMGa is used as the Ga source gas
  • NH 3 is used as the N source gas
  • Mg is an impurity that contributes to p-type conductivity.
  • Biscyclopentadienyl magnesium (Cp 2 Mg) can be used as the gas.
  • H 2 gas can be used as a carrier gas for transporting each source gas.
  • the molar ratio of TMAl in the group III source gas [TMAl] / ⁇ ) is set so that the Al composition ratio becomes a desired value (for example, 0.95).
  • Each source gas is not particularly limited.
  • TEGa may be used as the Ga source material, and a hydrazine derivative may be used as the N source gas.
  • the flow rate of Cp 2 Mg is 0.02 L / min (20 SCCM) in the standard state.
  • the flow rate of each source gas is not particularly limited.
  • Step of forming second p-type nitride semiconductor layer of p-type layer 5 This step is a step of forming a second p-type nitride semiconductor layer on the first p-type nitride semiconductor layer. is there. When the first p-type nitride semiconductor layer is not provided, the second p-type nitride semiconductor layer is formed on the light emitting layer 4.
  • the group III source gas and the group V source gas are added.
  • Supply into the reaction furnace is started to form a second p-type nitride semiconductor layer.
  • the sixth specified pressure can be set to 10 kPa, which is the same as the first specified pressure, and the sixth specified temperature can be set to 1050 ° C.
  • the values of the sixth specified pressure and the sixth specified temperature are merely examples, and are not particularly limited.
  • TMAl is used as an Al source gas
  • TMGa is used as a Ga source gas
  • NH 3 is used as an N source gas
  • Mg is an impurity that imparts p-type conductivity.
  • Cp 2 Mg can be used as the gas
  • H 2 gas can be used as the carrier gas for transporting each source gas.
  • the molar ratio of TMAl in the group III source gas [TMAl] / ⁇ [TMAl] + [TMGa] ⁇ ) so that the Al composition ratio becomes a desired value (for example, 0.55). ) Can be set.
  • the second p-type nitride semiconductor layer can be set to the same molar ratio as the growth condition of the n-type layer 3.
  • the flow rate of Cp 2 Mg can be set to 0.02 L / min (20 SCCM) in a standard state, for example.
  • the flow rate of each source gas is not particularly limited.
  • Step of forming third p-type nitride semiconductor layer of p-type layer 5 This step is a step of forming a third p-type nitride semiconductor to be a p-type contact layer on the second p-type nitride semiconductor layer. It is a process of forming a layer.
  • the group III source gas and the group V source gas are mixed.
  • the supply into the reaction furnace is started, and a third p-type nitride semiconductor layer is formed.
  • the seventh specified pressure can be set to 10 kPa, which is the same as the first specified pressure, and the seventh specified temperature can be set to 1050 ° C. Note that the values of the seventh specified pressure and the seventh specified temperature are examples, and are not particularly limited.
  • TMGa is used as the Ga source gas
  • NH 3 is used as the N source gas
  • Cp 2 Mg is used as the Mg source gas that imparts p-type conductivity.
  • H 2 gas can be used as a carrier gas for transporting each source gas.
  • the growth condition of the third p-type nitride semiconductor layer is basically the same as the growth condition of the second p-type nitride semiconductor layer, except that the supply of TMAl is stopped.
  • the flow rate of Cp 2 Mg is 0.02 L / min (20 SCCM) in the standard state, but it is an example and is not particularly limited.
  • the substrate 1 is introduced into the reaction furnace of the MOVPE apparatus in the process (1), crystal growth is continuously performed in the reaction furnace of the MOVPE apparatus until the process (8) is completed.
  • the substrate temperature is lowered to near room temperature, and the substrate 1 on which the laminated film of the n-type layer 3, the light-emitting layer 4, and the p-type layer 5 is formed is removed from the MOVPE apparatus. Take out.
  • the laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 is formed by the MOVPE method.
  • the laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 is not limited to the MOVPE method, and may be formed by an MBE method, an HVPE method, or the like.
  • all the steps (4) to (8) are collectively referred to as a first step.
  • Step of performing annealing for activating the p-type impurity is a step of activating the p-type impurity of the p-type layer 5 by annealing the p-type layer 5.
  • the p-type impurities in the p-type layer 5 are activated by holding the wafer in the annealing furnace of the annealing apparatus at a predetermined annealing temperature for a predetermined annealing time.
  • the annealing temperature can be set to 750 ° C. and the annealing time can be set to 10 minutes.
  • the values of annealing temperature and annealing time are examples and are not particularly limited.
  • As the annealing apparatus for example, a lamp annealing apparatus, an electric furnace annealing apparatus, or the like can be employed.
  • Step 10 Step of forming mesa structure [second step]
  • a mesa structure is formed in the laminated film of the n-type layer 3, the light-emitting layer 4, and the p-type layer 5 by using a photolithography technique and an etching technique.
  • a first resist layer is formed on a region corresponding to the top surface of the mesa structure on the surface 5aa of the p-type layer 5 by using a photolithography technique.
  • a part of the in-plane of the laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 is used as a p-type with the first resist layer as a mask.
  • a mesa structure is formed by etching from the surface 5aa side of the layer 5 to the middle in the thickness direction of the n-type layer 3.
  • the first resist layer is removed.
  • Etching of the laminated film can be performed, for example, by reactive ion etching.
  • the exposed surface 3a can be provided on the n-type layer 3 by forming the laminated film of the n-type layer 3, the light emitting layer 4 and the p-type layer 5 into a mesa structure.
  • the area and shape of the mesa structure are not particularly limited.
  • Step of forming the first electrode layer that is the source of the n-electrode 6 [third step] In this step, a first electrode layer that forms the base of the n electrode 6 is formed on the exposed surface 3 a of the n-type layer 3.
  • a second resist layer patterned so as to expose only the region where the n electrode 6 is to be formed is exposed on the one surface 1aa side of the substrate 1 is formed.
  • a part of the exposed surface 3 a of the n-type layer 3 becomes a region where the n-electrode 6 is to be formed.
  • the first electrode layer is formed on the one surface 1aa side of the substrate 1 by, for example, electron beam evaporation, and then lift-off is performed. The unnecessary film on the second resist layer and the second resist layer is removed.
  • the first electrode layer may be a stacked film of a Ti film having a thickness of 20 nm, an Al film having a thickness of 100 nm, a Ti film having a thickness of 20 nm, and an Au film having a thickness of 200 nm. it can.
  • the configuration and each film thickness of the first electrode layer are examples, and are not particularly limited.
  • the film-forming method of a 1st electrode layer is not specifically limited.
  • Step of forming n-electrode 6 [fourth step]
  • the n-electrode 6 is formed by heat-treating the first electrode layer and the n-type layer 3.
  • heat treatment is performed so that the contact between the first electrode layer and the n-type layer 3 is ohmic contact.
  • heat treatment for example, RTA (Rapid Thermal Annealing) treatment in an N 2 gas atmosphere is preferable.
  • the RTA treatment conditions may be, for example, a heat treatment temperature of 900 ° C. and a heat treatment time of 1 minute.
  • the conditions for the heat treatment are not particularly limited.
  • Step of forming high resistance layer 8 [fifth step] In this step, the high resistance layer 8 is formed on the p-type layer 5.
  • the method for forming the high resistance layer 8 may be changed as appropriate depending on the material of the high resistance layer 8 and the like.
  • a first step of forming a metal material layer that is the basis of the high resistance layer 8 is performed.
  • a third resist layer patterned so as to expose only a region where the high resistance layer 8 is to be formed on the one surface 1aa side of the substrate 1 is formed.
  • a part of the surface 5aa of the p-type layer 5 is a region where the high resistance layer 8 is to be formed.
  • a metal material layer that is the basis of the high resistance layer 8 is formed by an electron beam evaporation method, and lift-off is performed to thereby form the third resist layer and the third resist layer.
  • the unnecessary film on the resist layer is removed.
  • the unnecessary film is an unnecessary metal film.
  • the metal material layer can be, for example, a stacked film of a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm.
  • the film forming method and film forming conditions for the metal material layer are not limited.
  • the second step of forming the high resistance layer 8 by performing heat treatment on the metal material layer is performed after the first step.
  • the metal material layer is heat-treated so that the contact between the metal material layer and the p-type layer 5 is ohmic contact.
  • the heat treatment conditions can be, for example, an N 2 gas atmosphere, a heat treatment temperature of, for example, 700 ° C., and a heat treatment time of, for example, 10 minutes.
  • the conditions for the heat treatment are not particularly limited.
  • the heat treatment temperature in the second step is different from the heat treatment temperature in the seventh step described later.
  • Ni and Au are used as the material of the metal material layer, but other metals may be adopted.
  • high resistance layer 8 is formed in both the first step and the second step. This is substantially the same as the case where the metal layer is used.
  • a conductive oxide layer that is the basis of the high resistance layer 8 is formed by, for example, an O 2 gas assist electron beam evaporation method, and then the third resist layer is formed. Remove the layer.
  • the conductive oxide layer can be composed of, for example, an ITO layer, an AZO layer, a GZO layer, an IZO layer, or the like.
  • the high resistance layer 8 is formed by heat-treating the conductive oxide layer.
  • the conductive oxide layer is heat-treated so that the contact between the conductive oxide layer and the p-type layer 5 is ohmic contact.
  • the conditions for the heat treatment may be, for example, a mixed gas atmosphere of N 2 gas and O 2 gas, a heat treatment temperature of 500 ° C., and a heat treatment time of 5 minutes.
  • the mixed gas atmosphere for example, the volume ratio of N 2 gas and O 2 gas can be 95: 5.
  • the conditions for the heat treatment are not particularly limited. However, in the method of forming the high resistance layer 8 constituted by the conductive oxide layer, it is preferable that the heat treatment temperature in the second step is different from the heat treatment temperature in the seventh step described later.
  • a second step of patterning the high-resistance material layer 80 is performed using a photolithography technique and an etching technique (FIG. 2B).
  • the group III nitride semiconductor layer is, for example, a p-type GaN layer.
  • the substrate temperature is maintained at the eighth specified temperature while maintaining the pressure in the reactor at the eighth specified pressure.
  • a group III source gas and a group V source gas are started to be supplied into the reaction furnace to form a group III nitride semiconductor layer.
  • the eighth specified pressure can be set to 10 kPa, which is the same as the first specified pressure
  • the eighth specified temperature can be set to 1050 ° C. Note that the values of the eighth specified pressure and the eighth specified temperature are merely examples, and are not particularly limited.
  • TMGa can be used as the Ga source gas
  • NH 3 can be used as the N source gas
  • Cp 2 Mg can be used as a source gas for Mg, which is an impurity imparting p-type conductivity.
  • H 2 gas can be used as a carrier gas for transporting each source gas.
  • the growth condition of the high-resistance material layer 80 is such that the flow rate of Cp 2 Mg is reduced so that the high-resistance layer 8 has a higher resistance than the third p-type nitride semiconductor layer of the p-type layer 5.
  • the point is different.
  • the flow rate of Cp 2 Mg is 0.015 L / min (15 SCCM) in the standard state, but it is an example and is not particularly limited.
  • the high resistance layer 8 is not limited to the p-type GaN layer, and may be a p-type InGaN layer, a p-type AlGaN layer, a p-type InAlGaN layer, or the like.
  • the substrate temperature is lowered to near room temperature after the first step, and the n-type layer 3, the light-emitting layer 4, the p-type layer 5,
  • the substrate 1 on which the laminated film with the resistance material layer 80 is formed is taken out from the MOVPE apparatus.
  • the photolithography technique is used to open the fourth portion of the group III nitride semiconductor layer that is the source of the high resistance layer 8 except for the portion that overlaps the region where the group III nitride semiconductor layer remains.
  • a resist layer is formed.
  • using the fourth resist layer as a mask a region of the high resistance material layer 80 that is not covered by the fourth resist layer is removed by etching to form the high resistance layer 8.
  • the fourth resist layer is removed.
  • the mask layer 9 is formed so as to cover the surface 5aa of the p-type layer 5 other than the region where the high resistance layer 8 is to be formed.
  • the first step is included (see FIG. 3A). After the first step, a second step of selectively growing a high resistance layer 8 made of a p-type group III nitride semiconductor layer on the surface 5aa of the p-type layer 5 is provided (see FIG. 3B). After the second step, a third step of removing the mask layer 9 is provided (see FIG. 3C).
  • an SiO 2 film that is the basis of the mask layer 9 for selective growth is formed on the surface 5aa of the p-type layer 5 by, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition).
  • PECVD Pulsma Enhanced Chemical Vapor Deposition
  • a fifth resist layer is formed by utilizing a photolithography technique, in which a portion of the SiO 2 film that overlaps a region where the high resistance layer 8 is to be formed is opened.
  • the exposed portion of the SiO 2 film a fifth resist layer as a mask, the mask layer 9 made of the patterned SiO2 film is removed by wet etching using a BHF (buffered hydrofluoric acid) form Then, the fifth resist layer is removed.
  • the method for forming the SiO 2 film is not limited to the PECVD method, and other CVD methods can be employed.
  • the material of the mask layer 9 is not limited to SiO 2 .
  • the substrate 1 having the mask layer 9 formed on the outermost layer on the one surface 1aa side of the substrate 1 is again introduced into the reactor of the MOVPE apparatus, and the group III nitride semiconductor is formed on the exposed surface of the p-type layer 5.
  • a high resistance layer 8 made of layers is selectively grown.
  • the group III nitride semiconductor layer is, for example, a p-type GaN layer.
  • the group III raw material is maintained in a state where the substrate temperature is maintained at the ninth specified temperature while maintaining the pressure in the reaction furnace at the ninth specified pressure.
  • the supply of the gas and the group V source gas into the reactor is started to form a group III nitride semiconductor layer.
  • the growth conditions of the high resistance layer 8 can be, for example, the ninth specified pressure is 10 kPa, the same as the first specified pressure, and the ninth specified temperature is 1050 ° C. Note that the values of the ninth specified pressure and the ninth specified temperature are examples, and are not particularly limited.
  • TMGa can be used as the Ga source gas
  • NH 3 can be used as the N source gas
  • Cp 2 Mg can be used as a source gas for Mg, which is an impurity imparting p-type conductivity.
  • H 2 gas can be used as a carrier gas for transporting each source gas.
  • the growth conditions of the high-resistance layer 8 are basically the same as the growth conditions of the third p-type nitride semiconductor layer, and the high-resistance layer 8 is formed from the third p-type nitride semiconductor layer of the p-type layer 5.
  • the difference is that the flow rate of Cp 2 Mg is reduced in order to increase the resistance.
  • the flow rate of Cp 2 Mg is 0.015 L / min (15 SCCM) in a standard state, but is an example and is not particularly limited.
  • the high resistance layer 8 is not limited to the p-type GaN layer, but a p-type InGaN layer, a p-type AlGaN layer, A p-type InAlGaN layer may be used.
  • the substrate 1 having the laminated structure of the n-type layer 3, the light emitting layer 4, the p-type layer 5 and the high resistance layer 8 is taken out from the reactor of the MOVPE apparatus.
  • the mask layer 9 is removed by wet etching. If the material of the mask layer 9 is, for example, SiO 2 , BHF (buffered hydrofluoric acid) can be used as an etchant.
  • the etching damage of the p-type layer 5 is reduced as compared with the case where the high resistance layer 8 is patterned using the photolithography technique and the etching technique. Is possible.
  • Step of forming a second electrode layer that is a source of the p-electrode 7 [Sixth step] In this step, a second electrode layer that forms the source of the p-electrode 7 is formed on the surface 5aa of the p-type layer 5.
  • a sixth resist layer patterned so as to expose only the region where the p electrode 7 is to be formed is exposed on the one surface 1aa side of the substrate 1 is formed.
  • the region where the p-electrode 7 is to be formed is a part of the surface 5aa of the p-type layer 5.
  • the second electrode layer is formed on the one surface 1aa side of the substrate 1 by, for example, electron beam evaporation, and then lift-off is performed. Unnecessary films on the resist layer and the sixth resist layer are removed.
  • the second electrode layer can be, for example, a laminated film of a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm.
  • the configuration and each film thickness of the second electrode layer are examples, and are not particularly limited.
  • the material for the second electrode layer is not particularly limited. Further, the method for forming the second electrode layer is not particularly limited.
  • Step of forming p-electrode 7 [Seventh step] In this step, the p electrode 7 is formed by heat-treating the second electrode layer and the p-type layer 5.
  • heat treatment is performed so that the contact between the second electrode layer and the p-type layer 5 is ohmic contact.
  • the heat treatment conditions may be, for example, an N 2 gas atmosphere, a heat treatment temperature of 500 ° C., and a heat treatment time of 10 minutes, for example.
  • the conditions for the heat treatment are not particularly limited.
  • the respective heat treatment temperatures are set. By making it different, the resistance of the p-electrode 7 and the high resistance layer 8 can be made different. This is presumably because the mode of alloy formation changes due to the difference in heat treatment temperature and the ohmic resistance changes.
  • the first pad electrode and the second pad electrode are formed using photolithography technology and thin film formation technology.
  • the thin film formation technique for example, an electron beam evaporation method or the like can be employed.
  • a wafer on which a plurality of ultraviolet semiconductor light emitting elements 10 are formed is completed.
  • a wafer on which a plurality of ultraviolet semiconductor light emitting elements 10 are formed is completed.
  • the manufacturing method of the above-described ultraviolet semiconductor light emitting device 10 includes the steps of forming the n-electrode 6, forming the high-resistance layer 8, and forming the p-electrode 7 in the order of the heat treatment temperature of each of these steps. It may be changed in consideration of the above.
  • the manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment described above includes the above-described first to seventh steps after the substrate 1 is prepared.
  • the first step is a step of sequentially laminating the n-type layer 3, the light emitting layer 4 and the p-type layer 5 on the one surface 1aa side of the substrate 1.
  • the second step is a step of forming a mesa structure by etching a part of the laminated film of the n-type layer 3, the light emitting layer 4 and the p-type layer 5 in the middle of the thickness direction of the n-type layer 3. is there.
  • the third step is a step of forming a first electrode layer that becomes the source of the n electrode 6 on the exposed surface 3 a of the n-type layer 3.
  • the fourth step is a step of forming the n electrode 6 by heat-treating the first electrode layer and the n-type layer 3.
  • the fifth step is a step of forming the high resistance layer 8 on the p-type layer 5.
  • the sixth step is a step of forming a second electrode layer serving as a source of the p electrode 7 on the p-type layer 5 and the high resistance layer 8.
  • the seventh step is a step of forming the p electrode 7 by heat-treating the second electrode layer and the p-type layer 5.
  • the manufacturing method of the ultraviolet semiconductor light emitting device 10 includes the first step to the seventh step, so that it is possible to provide the ultraviolet semiconductor light emitting device 10 capable of suppressing current concentration without reducing the light emitting area. Become.
  • the fifth step includes the first step of forming a metal material layer that is the basis of the high resistance layer 8, and the heat treatment of the metal material layer to form the high resistance layer 8.
  • a heat treatment temperature in the second step and a heat treatment temperature in the seventh step can be made different.
  • the ultraviolet semiconductor light emitting device 10 of the present embodiment is different from the ultraviolet semiconductor light emitting device 10 of the first embodiment in the arrangement of the high resistance layer 8.
  • symbol is attached
  • the high resistance layer 8 in the ultraviolet semiconductor light emitting element 10 of the present embodiment has a smaller resistance as the distance from the n electrode 6 increases.
  • a plurality of high-resistance layers 8 are formed on the surface 5aa of the p-type layer 5, and the resistance is smaller as the high-resistance layer 8 is farther away from the n-electrode 6.
  • 4A to 4C show an example in which three high resistance layers 8 are formed.
  • the three high resistance layers 8 may be referred to as a high resistance layer 81, a high resistance layer 82, and a high resistance layer 83 in order of increasing distance from the n electrode 6.
  • the number of the high resistance layers 8 is not limited to three and may be any number.
  • the ultraviolet semiconductor light emitting device 10 of the present embodiment has a smaller resistance with respect to the high resistance layer 8 as the distance from the n-electrode 6 increases, so that the current concentration is higher than that of the ultraviolet semiconductor light emitting device 10 of the first embodiment.
  • the current can be made even more uniform, and the uneven emission can be further suppressed.
  • the manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment is substantially the same as the manufacturing method of the ultraviolet semiconductor light emitting device 10 described in the first embodiment, and the number of steps of forming the high resistance layer 8 is the number of the high resistance layers 8. It is different in that it is repeated as many times as it is combined.
  • the process of forming the high resistance layer 8 according to “(13-1) Method of forming the high resistance layer 8 including the metal layer” described in the first embodiment is repeated as many times as described above.
  • the configuration of the metal material layers is the same, and the resistances are in descending order, that is, the high resistance layer 81 and the high resistance layer 82.
  • the high resistance layers 83 are formed in this order, and the formation regions of the high resistance layers 81, 82, 83 and the heat treatment temperatures are made different from each other.
  • the heat treatment temperatures for forming the high resistance layer 81, the high resistance layer 82, and the high resistance layer 83 can be set to 700 ° C., 650 ° C., and 600 ° C., for example. Each heat treatment temperature is preferably different from each other within a temperature range in which ohmic contact between each of the high resistance layers 81, 82, 83 and the p-type layer 5 is obtained.
  • each high resistance layer 81,82,83 is different.
  • the heat treatment time may be varied after setting the heat treatment temperature to be the same.
  • the manufacturing method of the ultraviolet semiconductor light emitting element 10 may vary the heat treatment temperature and the heat treatment time when forming each of the high resistance layers 81, 82, 83.
  • the ultraviolet semiconductor light emitting device 10 of the present embodiment is different from the ultraviolet semiconductor light emitting device 10 of the first embodiment in the arrangement of the high resistance layer 8.
  • symbol is attached
  • the high resistance layer 8 in the ultraviolet semiconductor light emitting element 10 of the present embodiment has a smaller resistance as the distance from the n electrode 6 increases.
  • the ultraviolet semiconductor light emitting element 10 includes a plurality of high resistance layers 8 formed on the surface 5aa of the p-type layer 5 and the higher resistance layer 8 that is farther away from the n-electrode 6 is applied to the p-type layer 5.
  • the contact area is small.
  • the contact area of the high resistance layer 8 with respect to the p-type layer 5 means the occupation ratio of the high resistance layer 8 with respect to the p-type layer 5.
  • the ultraviolet semiconductor light-emitting device 10 can suppress current concentration more, can equalize the current, and can further suppress uneven light emission, as compared with the ultraviolet semiconductor light-emitting device 10 of the first embodiment.
  • the manufacturing method of the ultraviolet semiconductor light emitting device 10 of this embodiment is the same as the manufacturing method of the ultraviolet semiconductor light emitting device 10 of Embodiment 2, and the third resist layer is formed in the step of forming each high resistance layer 8.
  • a photomask used in the photolithography process may be changed as appropriate.
  • the adjacent high resistance layers 8 are separated from each other with respect to the plurality of high resistance layers 8, the adjacent high resistance layers 8 are in contact with each other as in the second embodiment. Compared to such a structure, it is possible to improve the yield during manufacturing.
  • the ultraviolet semiconductor light emitting device 10 of the present embodiment is different from the ultraviolet semiconductor light emitting device 10 of the first embodiment in the arrangement of the high resistance layer 8.
  • symbol is attached
  • the high resistance layer 8 in the ultraviolet semiconductor light emitting element 10 of the present embodiment has a smaller resistance as the distance from the n electrode 6 increases.
  • the ultraviolet semiconductor light emitting element 10 has a plurality of high resistance layers 8 formed on the surface 5aa of the p-type layer 5, and the thickness of the high resistance layer 8 farther from the n-electrode 6 is smaller. ing.
  • the ultraviolet semiconductor light-emitting device 10 can suppress current concentration more, can equalize the current, and can further suppress uneven light emission, as compared with the ultraviolet semiconductor light-emitting device 10 of the first embodiment.
  • the manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment is the same as the manufacturing method of the ultraviolet semiconductor light emitting device 10 of Embodiment 2, and the metal material formed in the first step in the process of forming each high resistance layer 8. What is necessary is just to make the film thickness of a layer mutually different.
  • a photomask used in the photolithography process for forming the third resist layer may be changed as appropriate.
  • the ultraviolet semiconductor light emitting device 10 of each of the above-described embodiments can appropriately set the light emission wavelength of the light emitting layer 4 in the ultraviolet wavelength region, so that it can be used as an alternative light source for ultraviolet light sources such as mercury lamps and excimer lamps. It can be used.
  • the ultraviolet semiconductor light emitting device 10 of the present embodiment is not limited to the high resistance layer 8 constituted by the metal layer in the present embodiment, but also the high resistance layer 8 constituted by the conductive oxide layer described in the first embodiment and the group III nitride. A structure using the high resistance layer 8 formed of a physical semiconductor layer may be appropriately replaced. Moreover, the manufacturing method of the ultraviolet semiconductor light-emitting device 10 of this embodiment is not restricted only to the case where the high resistance layer 8 is formed using photolithography technology and etching technology. While several preferred embodiments of the present invention have been described above, various modifications and variations can be made by those skilled in the art without departing from the true spirit and scope of the present invention, that is, the claims.

Abstract

In this ultraviolet semiconductor light emitting element, a laminated film on one side of a substrate has a mesa structure, said laminated film configured from an n-type layer, a light emitting layer, and a p-type layer. Furthermore, the ultraviolet semiconductor light emitting element is provided with an n electrode that is provided on the exposed surface of the n-type layer, said exposed surface being on the one side of the substrate, and a p electrode that is provided on a p-type layer surface on the one side of the substrate. In the ultraviolet semiconductor light emitting element, the p electrode is formed to planarly cover the p-type layer. Furthermore, in the ultraviolet semiconductor light emitting element, a high-resistance layer having resistance higher than that of the p-type layer or that of the p electrode is formed in a shape along the n electrode shape on the p-type layer side, said high-resistance layer being on the p-type layer surface on the side close to the n electrode.

Description

紫外半導体発光素子およびその製造方法Ultraviolet semiconductor light emitting device and manufacturing method thereof
　本発明は、紫外線（紫外光ともいう）の波長域で発光する紫外半導体発光素子およびその製造方法に関するものである。 The present invention relates to an ultraviolet semiconductor light-emitting element that emits light in a wavelength region of ultraviolet rays (also referred to as ultraviolet light) and a method for manufacturing the same.
　紫外半導体発光素子は、衛生、医療、工業、照明、精密機械などの様々な分野への応用が期待されている。 Ultraviolet semiconductor light-emitting elements are expected to be applied in various fields such as hygiene, medicine, industry, lighting, and precision machinery.
　紫外半導体発光素子としては、発光層の材料としてIII族窒化物半導体を用いたものが各所で研究開発されている。この種の紫外半導体発光素子としては、例えば、サファイア基板の一表面側におけるｎ型層と発光層とｐ型層との積層膜がメサ構造を有するものが知られている。メサ構造は、サファイア基板の上記一表面側にｎ型層と発光層とｐ型層との積層膜を成膜した後で、フォトリソグラフィ技術およびエッチング技術を利用して、ｎ型層の一部を露出させるように上記積層膜をパターニングすることで形成されている。 As an ultraviolet semiconductor light emitting device, a device using a group III nitride semiconductor as a material of a light emitting layer has been researched and developed in various places. As this type of ultraviolet semiconductor light-emitting device, for example, a device in which a laminated film of an n-type layer, a light-emitting layer, and a p-type layer on one surface side of a sapphire substrate has a mesa structure is known. In the mesa structure, a laminated film of an n-type layer, a light-emitting layer, and a p-type layer is formed on the one surface side of the sapphire substrate, and then a part of the n-type layer is formed by using a photolithography technique and an etching technique. It is formed by patterning the laminated film so as to expose the film.
　メサ構造を有する紫外半導体発光素子は、ｎ型層に電気的に接続された金属電極からなるｎ電極と、ｐ型層に電気的に接続された金属電極からなるｐ電極とが、サファイア基板の一表面側で横方向に並んで配置されている。 An ultraviolet semiconductor light-emitting device having a mesa structure includes an n-electrode made of a metal electrode electrically connected to an n-type layer and a p-electrode made of a metal electrode electrically connected to a p-type layer. It is arranged side by side on the one surface side.
　このような紫外半導体発光素子では、ｐ電極とｎ電極との間に流れる電流が、ｐ電極とｎ電極との間において、抵抗が低い経路を流れようとするため、メサ構造におけるｎ電極に近い側の端部に電流集中が発生する。このような電流集中は、高いＡｌの組成比をもつＡｌＧａＮのような材料をｎ型層に用いている場合や、紫外半導体発光素子の面積が大きい場合に特に起こりやすい傾向がある。紫外半導体発光素子は、電流集中が発生すると、電流が均一に流れず発光むらが発生する原因となったり、局所的な発熱の原因となったりする。そして、紫外半導体発光素子は、このような局所的な発熱が、発光効率の低下や、駆動電圧の増加、信頼性の低下など、紫外半導体発光素子の特性を低下させる原因となる。 In such an ultraviolet semiconductor light emitting device, the current flowing between the p electrode and the n electrode tends to flow through a path having a low resistance between the p electrode and the n electrode, so that it is close to the n electrode in the mesa structure. Current concentration occurs at the end of the side. Such current concentration tends to occur particularly when a material such as AlGaN having a high Al composition ratio is used for the n-type layer, or when the area of the ultraviolet semiconductor light emitting device is large. When current concentration occurs in the ultraviolet semiconductor light-emitting element, the current does not flow uniformly, causing uneven light emission or causing local heat generation. In the ultraviolet semiconductor light emitting element, such local heat generation causes deterioration of the characteristics of the ultraviolet semiconductor light emitting element, such as a decrease in light emission efficiency, an increase in driving voltage, and a decrease in reliability.
　そして、半導体発光素子としては、均一な電流拡散、均一な発光を得ることを目的として、ｎ型層に設けられた第１電極が、台座部と該台座部を基点として延伸する第１延伸部とを有し、ｐ型層に設けられた第２電極が、台座部と該台座部を基点として延伸する第１延伸部とを有するものが提案されている（例えば、日本国特許第４４１５５７５号公報を参照）。 And as a semiconductor light-emitting device, the 1st extending | stretching part which the 1st electrode provided in the n-type layer extends | stretched on the basis of this pedestal part for the purpose of obtaining uniform current spreading | diffusion and uniform light emission And the second electrode provided on the p-type layer has a pedestal portion and a first extending portion extending from the pedestal portion as a base point (for example, Japanese Patent No. 4415575). See the publication).
　しかしながら、上述の半導体発光素子では、第１電極が基台部に加えて延伸部を備えているので、ｎ型層の露出部の面積を増加させる必要があり、発光層の面積が減少し、発光面積が減少してしまう。 However, in the above-described semiconductor light emitting device, since the first electrode includes the extending portion in addition to the base portion, it is necessary to increase the area of the exposed portion of the n-type layer, and the area of the light emitting layer is reduced. The light emitting area is reduced.
　そこで、本発明の目的は、発光面積を減少させずに電流集中を抑制することが可能な紫外半導体発光素子およびその製造方法を提供することにある。 Therefore, an object of the present invention is to provide an ultraviolet semiconductor light emitting device capable of suppressing current concentration without reducing the light emitting area and a method for manufacturing the same.
　本発明の紫外半導体発光素子は、ｎ型層と発光層とｐ型層との積層膜と、ｎ電極と、ｐ電極と、高抵抗層とを備えている。前記積層膜は、基板の一表面側で積層されたものである。前記積層膜は、メサ構造を有している。前記ｎ電極は、前記基板の前記一表面側で前記ｎ型層の露出表面に設けられている。前記ｐ電極は、前記基板の前記一表面側で前記ｐ型層の表面側に設けられている。前記ｐ電極は、前記ｐ型層を面状に覆うように形成されている。前記高抵抗層は、前記ｐ型層もしくは前記ｐ電極よりも高抵抗としている。前記高抵抗層は、前記ｐ型層の前記表面において、前記ｎ電極に近い側で前記ｎ電極における前記ｐ型層側の形状に沿った形状に形成されている。これにより、本発明の紫外半導体発光素子においては、発光面積を減少させずに電流集中を抑制することが可能になる、という効果がある。 The ultraviolet semiconductor light-emitting device of the present invention includes a laminated film of an n-type layer, a light-emitting layer, and a p-type layer, an n electrode, a p electrode, and a high resistance layer. The laminated film is laminated on one surface side of the substrate. The laminated film has a mesa structure. The n-electrode is provided on the exposed surface of the n-type layer on the one surface side of the substrate. The p-electrode is provided on the surface side of the p-type layer on the one surface side of the substrate. The p-electrode is formed to cover the p-type layer in a planar shape. The high-resistance layer has a higher resistance than the p-type layer or the p-electrode. The high resistance layer is formed on the surface of the p-type layer in a shape along the shape of the n-electrode on the p-type layer side on the side close to the n-electrode. As a result, the ultraviolet semiconductor light emitting device of the present invention has an effect that current concentration can be suppressed without reducing the light emitting area.
　この紫外半導体発光素子において、前記高抵抗層は、前記ｎ電極からの距離が遠くなるほど抵抗が小さいことが好ましい。 In this ultraviolet semiconductor light emitting device, it is preferable that the high resistance layer has a smaller resistance as the distance from the n electrode increases.
　この紫外半導体発光素子において、前記高抵抗層は、前記ｐ型層の前記表面に複数形成されており、前記ｎ電極からの距離が遠い前記高抵抗層ほど前記ｐ型層に対する接触面積が小さいことが好ましい。 In this ultraviolet semiconductor light emitting device, a plurality of the high resistance layers are formed on the surface of the p-type layer, and the contact area with the p-type layer is smaller as the high resistance layer is farther from the n-electrode. Is preferred.
　この紫外半導体発光素子において、前記高抵抗層は、前記ｐ型層の前記表面に複数形成されており、前記ｎ電極からの距離が遠い前記高抵抗層ほど膜厚が小さいことが好ましい。 In this ultraviolet semiconductor light emitting device, it is preferable that a plurality of the high resistance layers are formed on the surface of the p-type layer, and the film thickness is smaller as the high resistance layer is farther from the n electrode.
　この紫外半導体発光素子において、前記高抵抗層は、ｐ型のIII族窒化物半導体層から
なり、前記ｐ型層よりも高抵抗であることが好ましい。 In this ultraviolet semiconductor light emitting device, the high resistance layer is preferably composed of a p-type group III nitride semiconductor layer, and has a higher resistance than the p-type layer.
　この紫外半導体発光素子において、前記高抵抗層は、金属層もしくは導電性酸化物層からなり、前記ｐ電極よりも高抵抗であることが好ましい。 In this ultraviolet semiconductor light emitting device, the high resistance layer is preferably made of a metal layer or a conductive oxide layer and has a higher resistance than the p electrode.
　本発明の紫外半導体発光素子の製造方法は、以下の第１工程から第７工程を備えている。第１工程は、前記基板を準備した後に、前記基板の一表面側に前記ｎ型層、前記発光層および前記ｐ型層を順次積層する。第２工程は、前記ｎ型層と前記発光層と前記ｐ型層との積層膜の面内の一部を前記ｎ型層の厚み方向の途中までエッチングすることでメサ構造を形成する。第３工程は、前記ｎ型層の前記露出表面上に前記ｎ電極の元になる第１電極層を形成する。第４工程は、前記第１電極層と前記ｎ型層とを熱処理することで前記ｎ電極を形成する。第５工程は、前記ｐ型層上に高抵抗層を形成する。第６工程は、前記ｐ型層と前記高抵抗層上に前記ｐ電極の元になる第２電極層を形成する。第７工程は、前記第２電極層と前記ｐ型層とを熱処理することで前記ｐ電極を形成する。これにより、本発明の紫外半導体発光素子の製造方法においては、発光面積を減少させずに電流集中を抑制することが可能な紫外半導体発光素子を提供できる、という効果がある。 The manufacturing method of the ultraviolet semiconductor light emitting device of the present invention includes the following first to seventh steps. In the first step, after the substrate is prepared, the n-type layer, the light emitting layer, and the p-type layer are sequentially stacked on one surface side of the substrate. In the second step, a mesa structure is formed by etching a part of the laminated film of the n-type layer, the light-emitting layer, and the p-type layer halfway in the thickness direction of the n-type layer. In the third step, a first electrode layer serving as a source of the n-electrode is formed on the exposed surface of the n-type layer. In the fourth step, the n-electrode is formed by heat-treating the first electrode layer and the n-type layer. In the fifth step, a high resistance layer is formed on the p-type layer. In the sixth step, a second electrode layer serving as a source of the p electrode is formed on the p-type layer and the high resistance layer. In the seventh step, the p-electrode is formed by heat-treating the second electrode layer and the p-type layer. Thereby, in the manufacturing method of the ultraviolet semiconductor light-emitting device of this invention, there exists an effect that the ultraviolet semiconductor light-emitting device which can suppress an electric current concentration without reducing a light emission area can be provided.
　この紫外半導体発光素子の製造方法において、前記第５工程は、次の第１ステップと第２ステップとを備えることが好ましい。第１ステップは、前記高抵抗層の元になる金属材料層を形成する。第２ステップは、前記金属材料層を熱処理することで前記高抵抗層を形成する。第２ステップは、前記第２ステップにおける熱処理温度と、前記第７工程における熱処理温度とが異なる。 In this method for manufacturing an ultraviolet semiconductor light emitting device, the fifth step preferably includes the following first step and second step. In the first step, a metal material layer that forms the basis of the high resistance layer is formed. The second step forms the high resistance layer by heat-treating the metal material layer. In the second step, the heat treatment temperature in the second step is different from the heat treatment temperature in the seventh step.
　この紫外半導体発光素子の製造方法において、前記第５工程は、次の第１ステップと第２ステップと第３ステップとを備えることが好ましい。第１ステップは、前記ｐ型層の表面における前記高抵抗層の形成予定領域以外を覆うマスク層を形成する。第２ステップは、前記ｐ型層の前記表面にIII族窒化物半導体層からなる前記高抵抗層を選択成長させる。第３ステップは、前記マスク層を除去する。 In this method for manufacturing an ultraviolet semiconductor light emitting device, the fifth step preferably includes the following first step, second step, and third step. In the first step, a mask layer is formed that covers the surface of the p-type layer except for the region where the high resistance layer is to be formed. In the second step, the high resistance layer made of a group III nitride semiconductor layer is selectively grown on the surface of the p-type layer. In the third step, the mask layer is removed.
　本発明の好ましい実施形態をさらに詳細に記述する。本発明の他の特徴および利点は、以下の詳細な記述および添付図面に関連して一層良く理解されるものである。
図１Ａは、実施形態１の紫外半導体発光素子の平面図である。 図１Ｂは、図１ＡのＸ－Ｘ概略断面図である。 図１Ｃは、図１ＢのＹ－Ｙ断面に対応する概略断面図である。 図２Ａは、実施形態１の紫外半導体発光素子の製造方法の一例を説明するための主要工程断面図である。 図２Ｂは、実施形態１の紫外半導体発光素子の製造方法の一例を説明するための主要工程断面図である。 図３Ａは、実施形態１の紫外半導体発光素子の製造方法の他の例を説明するための主要工程断面図である。 図３Ｂは、実施形態１の紫外半導体発光素子の製造方法の他の例を説明するための主要工程断面図である。 図３Ｃは、実施形態１の紫外半導体発光素子の製造方法の他の例を説明するための主要工程断面図である。 図４Ａは、実施形態２の紫外半導体発光素子の平面図である。 図４Ｂは、図４ＡのＸ－Ｘ概略断面図である。 図４Ｃは、図４ＢのＹ－Ｙ断面に対応する概略断面図である。 図５Ａは、実施形態３の紫外半導体発光素子の平面図である。 図５Ｂは、図５ＡのＸ－Ｘ概略断面図である。 図５Ｃは、図５ＢのＹ－Ｙ断面に対応する概略断面図である。 図６Ａは、実施形態４の紫外半導体発光素子の平面図である。 図６Ｂは、図６ＡのＸ－Ｘ概略断面図である。 図６Ｃは、図６ＢのＹ－Ｙ断面に対応する概略断面図である。 Preferred embodiments of the invention are described in further detail. Other features and advantages of the present invention will be better understood with reference to the following detailed description and accompanying drawings.
1A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 1. FIG. 1B is a schematic cross-sectional view taken along the line XX of FIG. 1A. 1C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 1B. 2A is a main process sectional view for explaining an example of the manufacturing method of the ultraviolet semiconductor light-emitting device of Embodiment 1. FIG. FIG. 2B is a main process cross-sectional view for describing an example of the manufacturing method of the ultraviolet semiconductor light-emitting device of Embodiment 1. FIG. 3A is a main process sectional view for explaining another example of the method for producing the ultraviolet semiconductor light-emitting device of the first embodiment. FIG. 3B is a main process cross-sectional view for explaining another example of the method for manufacturing the ultraviolet semiconductor light-emitting device of Embodiment 1. FIG. 3C is a main process cross-sectional view for explaining another example of the method for manufacturing the ultraviolet semiconductor light-emitting device of Embodiment 1. 4A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 2. FIG. 4B is a schematic cross-sectional view taken along the line XX of FIG. 4A. 4C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 4B. FIG. 5A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 3. FIG. FIG. 5B is a schematic cross-sectional view taken along the line XX of FIG. 5A. FIG. 5C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 5B. FIG. 6A is a plan view of the ultraviolet semiconductor light-emitting device of Embodiment 4. FIG. 6B is a schematic cross-sectional view taken along the line XX of FIG. 6A. 6C is a schematic cross-sectional view corresponding to the YY cross section of FIG. 6B.
　　（実施形態１）
　以下では、本実施形態の紫外半導体発光素子１０について、図１Ａないし図１Ｃに基づいて説明する。 (Embodiment 1)
Below, the ultraviolet semiconductor light emitting element 10 of this embodiment is demonstrated based on FIG. 1A thru | or FIG. 1C.
　紫外半導体発光素子１０は、基板１の一表面１ａａ側におけるｎ型層３と発光層４とｐ型層５との積層膜がメサ構造を有している。また、紫外半導体発光素子１０は、基板１の一表面１ａａ側でｎ型層３の露出表面３ａに設けられたｎ電極６と、基板１の一表面１ａａ側でｐ型層５の表面５ａａ側に設けられたｐ電極７とを備えている。この紫外半導体発光素子１０は、発光ダイオードである。 In the ultraviolet semiconductor light emitting element 10, the laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 on the one surface 1aa side of the substrate 1 has a mesa structure. The ultraviolet semiconductor light emitting element 10 includes an n electrode 6 provided on the exposed surface 3a of the n-type layer 3 on the one surface 1aa side of the substrate 1, and a surface 5aa side of the p-type layer 5 on the one surface 1aa side of the substrate 1. And a p-electrode 7 provided. The ultraviolet semiconductor light emitting element 10 is a light emitting diode.
　紫外半導体発光素子１０は、ｐ電極７が、ｐ型層５を面状に覆うように形成されている。また、紫外半導体発光素子１０は、ｐ型層５もしくはｐ電極７よりも高抵抗の高抵抗層８が、ｐ型層５の表面５ａａにおいてｎ電極６に近い側でｎ電極６におけるｐ型層５側の形状に沿った形状に形成されている。これにより、紫外半導体発光素子１０は、発光面積を減少させずに電流集中を抑制することが可能となる。高抵抗層８の抵抗は、シート抵抗もしくはオーミック抵抗（コンタクト抵抗）である。高抵抗層８において、ｐ型層５よりも高抵抗とは、ｐ型層５よりもシート抵抗が高いことを意味する。また、高抵抗層８において、ｐ電極７よりも高抵抗とは、ｐ電極７よりもオーミック抵抗が高いことを意味する。 The ultraviolet semiconductor light emitting element 10 is formed so that the p-electrode 7 covers the p-type layer 5 in a planar shape. Further, in the ultraviolet semiconductor light emitting device 10, the p-type layer 5 or the p-type layer in the n-electrode 6 has a high-resistance layer 8 having a higher resistance than the p-electrode 7 on the side close to the n-electrode 6 on the surface 5aa of the p-type layer 5. It is formed in a shape along the shape on the 5 side. Thereby, the ultraviolet semiconductor light emitting element 10 can suppress current concentration without reducing the light emitting area. The resistance of the high resistance layer 8 is a sheet resistance or an ohmic resistance (contact resistance). In the high resistance layer 8, “higher resistance than the p-type layer 5” means that the sheet resistance is higher than that of the p-type layer 5. In the high resistance layer 8, “higher resistance than the p electrode 7” means that the ohmic resistance is higher than that of the p electrode 7.
　紫外半導体発光素子１０は、基板１とｎ型層３との間にバッファ層２を備えることが好ましい。 The ultraviolet semiconductor light emitting element 10 preferably includes a buffer layer 2 between the substrate 1 and the n-type layer 3.
　以下では、紫外半導体発光素子１０の各構成要素について詳細に説明する。 Hereinafter, each component of the ultraviolet semiconductor light emitting element 10 will be described in detail.
　基板１は、エピタキシャル成長用の単結晶基板である。この基板１は、一表面１ａａが（０００１）面のサファイア基板を用いることができる。つまり、基板１は、ｃ面サファイア基板（α－Ａｌ2Ｏ3基板）を好適に用いることができる。ｃ面サファイア基板は、（０００１）からのオフ角が、０～０．２°のものが好ましい。紫外半導体発光素子１０は、基板１の他表面１ａｂから光を取り出す場合、基板１として発光層４から放射される紫外光に対して透明な単結晶基板を採用すればよい。この場合、紫外半導体発光素子１０は、基板１の他表面１ａｂが光取り出し面となる。基板１は、サファイア基板に限らず、例えば、酸化ガリウム基板（β－Ｇａ2Ｏ3基板）、スピネル基板、炭化シリコン基板、酸化亜鉛基板、酸化マグネシウム基板、硼化ジルコニウム基板、III族窒化物系半導体基板などを用いてもよい。なお、紫外半導体発光素子１０は、製造時に用いるエピタキシャル成長用の単結晶基板が紫外光を透過可能な透光性基板でない場合、単結晶基板をリフトオフなどにより除去してもよい。この場合、紫外半導体発光素子１０は、製造時において、エピタキシャル成長用の単結晶基板を除去する前に、基板１の一表面１ａａ側となる単結晶基板の最表層側に支持基板を張り合わせるのが好ましい。 The substrate 1 is a single crystal substrate for epitaxial growth. As this substrate 1, a sapphire substrate having one surface 1aa of (0001) plane can be used. That is, as the substrate 1, a c-plane sapphire substrate (α-Al 2 O 3 substrate) can be preferably used. The c-plane sapphire substrate preferably has an off angle from (0001) of 0 to 0.2 °. In the ultraviolet semiconductor light emitting element 10, when light is extracted from the other surface 1 ab of the substrate 1, a single crystal substrate that is transparent to the ultraviolet light emitted from the light emitting layer 4 may be adopted as the substrate 1. In this case, the ultraviolet semiconductor light emitting element 10 has the other surface 1ab of the substrate 1 as a light extraction surface. The substrate 1 is not limited to a sapphire substrate, but, for example, a gallium oxide substrate (β-Ga 2 O 3 substrate), a spinel substrate, a silicon carbide substrate, a zinc oxide substrate, a magnesium oxide substrate, a zirconium boride substrate, a group III nitride system A semiconductor substrate or the like may be used. The ultraviolet semiconductor light emitting element 10 may be removed by lift-off or the like when the single crystal substrate for epitaxial growth used at the time of manufacture is not a translucent substrate capable of transmitting ultraviolet light. In this case, the ultraviolet semiconductor light emitting element 10 is manufactured by attaching a support substrate to the outermost layer side of the single crystal substrate which is the one surface 1aa side of the substrate 1 before removing the single crystal substrate for epitaxial growth. preferable.
　バッファ層２は、ｎ型層３の貫通転位を低減するとともにｎ型層３の残留歪みを低減するために設けてある。バッファ層２は、ＡｌＮ層により構成してあるが、ＡｌＮ層に限らない。バッファ層２は、例えば、ＡｌＧａＮ層やＡｌＩｎＮ層、ＧａＮ層などにより構成してもよい。バッファ層２は、膜厚が薄すぎると、貫通転位の減少が不十分となりやすい。また、バッファ層２は、膜厚が厚すぎると格子不整合に起因したクラックの発生や、複数の紫外半導体発光素子１０を形成するウェハの反りが大きくなる懸念がある。このため、バッファ層２の膜厚は、５００ｎｍ～１０μｍ程度の範囲で設定することが好ましく、１μｍ～５μｍの範囲で設定することが、より好ましい。また、バッファ層２の膜厚は、このバッファ層２の表面が平坦化されるように設定することが好ましい。なお、ウェハは、複数の紫外半導体発光素子１０の元となるものである。 The buffer layer 2 is provided to reduce threading dislocations in the n-type layer 3 and to reduce residual strain in the n-type layer 3. The buffer layer 2 is composed of an AlN layer, but is not limited to an AlN layer. The buffer layer 2 may be composed of, for example, an AlGaN layer, an AlInN layer, a GaN layer, or the like. If the buffer layer 2 is too thin, threading dislocations tend to be insufficiently reduced. Further, if the buffer layer 2 is too thick, there is a concern that cracks due to lattice mismatch and warping of the wafer on which the plurality of ultraviolet semiconductor light emitting elements 10 are formed become large. Therefore, the thickness of the buffer layer 2 is preferably set in the range of about 500 nm to 10 μm, and more preferably set in the range of 1 μm to 5 μm. The film thickness of the buffer layer 2 is preferably set so that the surface of the buffer layer 2 is flattened. The wafer is a source of the plurality of ultraviolet semiconductor light emitting elements 10.
　ｎ型層３は、発光層４へ電子を注入するためのものであり、ｎ型窒化物半導体層により構成することができる。ｎ型層３の膜厚は、一例として２μｍに設定してあるが、特に限定するものではない。ｎ型窒化物半導体層は、ｎ型ＡｌzＧａ1-zＮ（０＜ｚ≦１）層から構成することができる。ｎ型窒化物半導体層は、ｎ型ＡｌzＧａ1-zＮ（０＜ｚ≦１）層の組成比を特に限定するものではない。しかしながら、ｎ型窒化物半導体層は、ｎ型ＡｌzＧａ1-zＮ（０＜ｚ≦１）層が発光層４で発光する紫外光の吸収を抑制できるの組成比であることが好ましい。、ここで、発光層４が量子井戸構造を有する場合、ｎ型窒化物半導体層は、例えば、発光層４における井戸層のＡｌの組成比を０．４０、障壁層のＡｌの組成比を０．５５の組み合わせとすれば、ｎ型ＡｌzＧａ1-zＮ（０＜ｚ≦１）層のＡｌの組成比ｚは、障壁層のＡｌの組成比と同じ０．５５とすることができる。すなわち、発光層４の井戸層がＡｌ0.40Ｇａ0.60Ｎ層からなり、障壁層がＡｌ0.55Ｇａ0.45Ｎ層からなる場合、ｎ型窒化物半導体層は、例えば、ｎ型Ａｌ0.55Ｇａ0.45Ｎ層とすることができる。ｎ型層３は、単層構造に限らず、多層構造でもよい。ｎ型層３は、例えば、ｎ型Ａｌ0.7Ｇａ0.3Ｎ層と、当該ｎ型Ａｌ0.7Ｇａ0.3Ｎ層上のｎ型Ａｌ0.55Ｇａ0.45Ｎ層とで構成してもよい。 The n-type layer 3 is for injecting electrons into the light emitting layer 4 and can be composed of an n-type nitride semiconductor layer. The thickness of the n-type layer 3 is set to 2 μm as an example, but is not particularly limited. The n-type nitride semiconductor layer can be composed of an n-type Al z Ga 1-z N (0 <z ≦ 1) layer. The n-type nitride semiconductor layer does not particularly limit the composition ratio of the n-type Al z Ga 1-z N (0 <z ≦ 1) layer. However, the n-type nitride semiconductor layer preferably has a composition ratio that allows the n-type Al z Ga 1 -z N (0 <z ≦ 1) layer to suppress absorption of ultraviolet light emitted from the light-emitting layer 4. Here, when the light emitting layer 4 has a quantum well structure, the n-type nitride semiconductor layer has, for example, an Al composition ratio of the well layer of the light emitting layer 4 of 0.40 and an Al composition ratio of the barrier layer of 0. .55, the Al composition ratio z of the n-type Al z Ga 1-z N (0 <z ≦ 1) layer can be set to 0.55, which is the same as the Al composition ratio of the barrier layer. . That is, when the well layer of the light emitting layer 4 is made of an Al 0.40 Ga 0.60 N layer and the barrier layer is made of an Al 0.55 Ga 0.45 N layer, the n-type nitride semiconductor layer is, for example, an n-type Al 0.55 Ga 0.45 N layer. can do. The n-type layer 3 is not limited to a single layer structure, and may have a multilayer structure. The n-type layer 3 may be composed of, for example, an n-type Al 0.7 Ga 0.3 N layer and an n-type Al 0.55 Ga 0.45 N layer on the n-type Al 0.7 Ga 0.3 N layer.
　ｎ型窒化物半導体層のドナー不純物としては、例えば、Ｓｉが好ましい。また、ｎ型窒化物半導体層の電子濃度は、例えば、１×１０18～１×１０19ｃｍ-3程度の範囲で設定すればよい。 For example, Si is preferable as the donor impurity of the n-type nitride semiconductor layer. Further, the electron concentration of the n-type nitride semiconductor layer may be set, for example, in the range of about 1 × 10 18 to 1 × 10 19 cm −3 .
　発光層４は、注入されたキャリアを光に変換するものであり、量子井戸構造を有している。ここでは、キャリアは、電子と正孔である。量子井戸構造は、障壁層と井戸層とからなる。量子井戸構造は、障壁層と井戸層とが交互に積層されており、井戸層の数が２であるが、井戸層の数は特に限定するものではない。要するに、量子井戸構造は、多重量子井戸構造でもよいし、単一量子井戸構造でもよい。また、井戸層および障壁層それぞれの膜厚は、特に限定するものではない。ただし、発光層４は、井戸層の膜厚が厚すぎると、井戸層に注入された電子および正孔が、量子井戸構造における格子不整合に起因するピエゾ電界で空間的に分離してしまい、発光効率が低下する。また、発光層４は、井戸層の膜厚が薄すぎると、キャリアの閉じ込め効果が低下し、発光効率が低下する。このため、井戸層の膜厚は、１ｎｍ～５ｎｍ程度が好ましく、１．３ｎｍ～３ｎｍ程度が、より好ましい。また、障壁層の膜厚は、例えば、５ｎｍ～１５ｎｍ程度の範囲で設定することが好ましい。紫外半導体発光素子１０は、一例として、井戸層の膜厚を２ｎｍに設定し、障壁層の膜厚を８ｎｍに設定することができる。 The light emitting layer 4 converts injected carriers into light and has a quantum well structure. Here, the carriers are electrons and holes. The quantum well structure includes a barrier layer and a well layer. In the quantum well structure, barrier layers and well layers are alternately stacked, and the number of well layers is 2, but the number of well layers is not particularly limited. In short, the quantum well structure may be a multiple quantum well structure or a single quantum well structure. Further, the thicknesses of the well layer and the barrier layer are not particularly limited. However, if the thickness of the well layer is too thick, the light emitting layer 4 spatially separates electrons and holes injected into the well layer by a piezo electric field due to lattice mismatch in the quantum well structure, Luminous efficiency decreases. On the other hand, if the thickness of the well layer is too thin, the light-emitting layer 4 has a low carrier confinement effect and a low luminous efficiency. For this reason, the thickness of the well layer is preferably about 1 nm to 5 nm, more preferably about 1.3 nm to 3 nm. Further, the thickness of the barrier layer is preferably set in the range of about 5 nm to 15 nm, for example. For example, the ultraviolet semiconductor light emitting element 10 can set the thickness of the well layer to 2 nm and the thickness of the barrier layer to 8 nm.
　発光層４は、所望の発光波長の紫外光を発光するように井戸層のＡｌの組成比を設定してある。ＡｌaＧａ1-aＮ（０＜ａ≦１）層からなる井戸層を備えた発光層４は、井戸層のＡｌの組成比ａを変化させることにより、発光波長を２１０ｎｍ～３６０ｎｍの範囲で任意の発光波長に設定することが可能である。 In the light emitting layer 4, the Al composition ratio of the well layer is set so as to emit ultraviolet light having a desired light emission wavelength. The light emitting layer 4 having a well layer composed of Al a Ga 1-a N (0 <a ≦ 1) layer has an emission wavelength in the range of 210 nm to 360 nm by changing the Al composition ratio a of the well layer. It is possible to set an arbitrary emission wavelength.
　紫外半導体発光素子１０は、一例として、障壁層をＡｌ0.55Ｇａ0.45Ｎ層により構成し、井戸層をＡｌ0.40Ｇａ0.60Ｎ層により構成してあるが、障壁層および井戸層の各組成比を限定するものではなく、所望の発光波長に応じて各組成比を適宜設定すればよい。紫外半導体発光素子１０は、発光層４を単層構造として、発光層４と発光層４の厚み方向の両側の層（ｎ型層３、ｐ型層５）とでダブルへテロ構造が形成されるようにしてもよい。 In the ultraviolet semiconductor light emitting device 10, as an example, the barrier layer is composed of an Al 0.55 Ga 0.45 N layer and the well layer is composed of an Al 0.40 Ga 0.60 N layer, but the composition ratio of the barrier layer and the well layer is limited. Instead, the composition ratios may be set as appropriate according to the desired emission wavelength. In the ultraviolet semiconductor light emitting device 10, the light emitting layer 4 has a single layer structure, and a double hetero structure is formed by the light emitting layer 4 and the layers on the both sides in the thickness direction of the light emitting layer 4 (n-type layer 3, p-type layer 5). You may make it do.
　ｐ型層５は、例えば、発光層４上に形成された第１のｐ型窒化物半導体層と、この第１のｐ型窒化物半導体層上に形成された第２のｐ型窒化物半導体層と、この第２のｐ型窒化物半導体層上に形成された第３のｐ型窒化物半導体層とを備えた構成とすることができる。第１～第３のｐ型窒化物半導体層のアクセプタ不純物としては、例えば、Ｍｇが好ましい。 The p-type layer 5 includes, for example, a first p-type nitride semiconductor layer formed on the light emitting layer 4 and a second p-type nitride semiconductor formed on the first p-type nitride semiconductor layer. And a third p-type nitride semiconductor layer formed on the second p-type nitride semiconductor layer. As the acceptor impurity of the first to third p-type nitride semiconductor layers, for example, Mg is preferable.
　第１のｐ型窒化物半導体層は、電子ブロック層として設けてある。電子ブロック層は、発光層４へ注入された電子のうち、発光層４中で正孔と再結合されなかった電子が、第２のｐ型窒化物半導体層側へ漏れる（オーバーフローする）のを抑制するために、発光層４と第２のｐ型窒化物半導体層との間に設けてある。電子ブロック層は、ｐ型ＡｌcＧａ1-cＮ（０＜ｃ＜１）層からなる。ｐ型ＡｌcＧａ1-cＮ（０＜ｃ＜１）層の組成比は、特に限定するものではない。ｐ型ＡｌcＧａ1-cＮ（０＜ｃ＜１）層の組成比は、電子ブロック層のバンドギャップエネルギが、第２のｐ型窒化物半導体層および障壁層それぞれのバンドギャップエネルギよりも高くなるように設定することが好ましい。紫外半導体発光素子１０は、一例として、電子ブロック層をｐ型Ａｌ0.95Ｇａ0.05Ｎ層により構成してある。 The first p-type nitride semiconductor layer is provided as an electron block layer. The electron blocking layer prevents electrons that have not been recombined with holes in the light emitting layer 4 out of electrons injected into the light emitting layer 4 from leaking (overflowing) to the second p-type nitride semiconductor layer side. In order to suppress it, it is provided between the light emitting layer 4 and the second p-type nitride semiconductor layer. The electron block layer is composed of a p-type Al c Ga 1-c N (0 <c <1) layer. The composition ratio of the p-type Al c Ga 1-c N (0 <c <1) layer is not particularly limited. The composition ratio of the p-type Al c Ga 1-c N (0 <c <1) layer is such that the band gap energy of the electron block layer is larger than the band gap energy of each of the second p-type nitride semiconductor layer and the barrier layer. It is preferable to set it to be high. As an example, the ultraviolet semiconductor light emitting element 10 has an electron blocking layer formed of a p-type Al 0.95 Ga 0.05 N layer.
　電子ブロック層の正孔濃度は、特に限定するものではない。また、電子ブロック層の膜厚については、特に限定するものではないが、膜厚が薄すぎるとオーバーフロー抑制効果が減少し、膜厚が厚すぎると紫外半導体発光素子１０の抵抗が大きくなってしまう。ここで、電子ブロック層の膜厚については、Ａｌの組成比ｃや正孔濃度などの値によって適した膜厚が変化するので、一概には言えないが、１ｎｍ～５０ｎｍの範囲で設定することが好ましく、５ｎｍ～２５ｎｍの範囲で設定することが、より好ましい。紫外半導体発光素子１０は、一例として、電子ブロック層の膜厚を１５ｎｍに設定することができる。 The hole concentration of the electron blocking layer is not particularly limited. Further, the thickness of the electron blocking layer is not particularly limited, but if the film thickness is too thin, the overflow suppressing effect is reduced, and if the film thickness is too thick, the resistance of the ultraviolet semiconductor light emitting element 10 is increased. . Here, the film thickness of the electron block layer varies depending on values such as the Al composition ratio c and the hole concentration. Therefore, although it cannot be generally stated, it should be set within a range of 1 nm to 50 nm. It is preferable to set the thickness in the range of 5 nm to 25 nm. As an example, the ultraviolet semiconductor light emitting element 10 can set the thickness of the electron block layer to 15 nm.
　第２のｐ型窒化物半導体層は、発光層４へ正孔を輸送するためのものである。第２のｐ型窒化物半導体層は、ｐ型ＡｌdＧａ1-dＮ（０＜ｄ＜１）層から構成することができる。ｐ型ＡｌdＧａ1-dＮ（０＜ｄ＜１）層の組成比は、発光層４で発光する紫外光の吸収を抑制できれる組成比であれば、特に限定するものではない。例えば、上述のように発光層４における井戸層のＡｌの組成比を０．４０、障壁層のＡｌの組成比を０．５５とすれば、ｐ型ＡｌdＧａ1-dＮ（０＜ｄ＜１）層のＡｌの組成比ｄは、例えば、障壁層のＡｌの組成比ａと同じ０．５５とすることができる。すなわち、紫外半導体発光素子１０は、発光層４の井戸層がＡｌ0.40Ｇａ0.60Ｎ層からなる場合、第２のｐ型窒化物半導体層を、例えば、ｐ型Ａｌ0.55Ｇａ0.45Ｎ層により構成することができる。 The second p-type nitride semiconductor layer is for transporting holes to the light emitting layer 4. The second p-type nitride semiconductor layer can be composed of a p-type Al d Ga 1-d N (0 <d <1) layer. The composition ratio of the p-type Al d Ga 1-d N (0 <d <1) layer is not particularly limited as long as it can suppress the absorption of ultraviolet light emitted from the light emitting layer 4. For example, when the Al composition ratio of the well layer in the light emitting layer 4 is 0.40 and the Al composition ratio of the barrier layer is 0.55 as described above, p-type Al d Ga 1-d N (0 <d <1) The Al composition ratio d of the layer can be set to 0.55, which is the same as the Al composition ratio a of the barrier layer, for example. That is, in the ultraviolet semiconductor light emitting device 10, when the well layer of the light emitting layer 4 is composed of an Al 0.40 Ga 0.60 N layer, the second p-type nitride semiconductor layer is configured by, for example, a p-type Al 0.55 Ga 0.45 N layer. be able to.
　第２のｐ型窒化物半導体層の正孔濃度は、特に限定するものではなく、第２のｐ型窒化物半導体層の膜質が劣化しない正孔濃度の範囲において、より高い濃度のほうが好ましい。しかしながら、紫外半導体発光素子１０は、ｐ型ＡｌdＧａ1-dＮ（０＜ｄ＜１）層の正孔濃度がｎ型ＡｌzＧａ1-zＮ（０＜ｚ≦１）層の電子濃度よりも低いので、第２のｐ型窒化物半導体層の膜厚が、厚すぎると、紫外半導体発光素子１０の抵抗が大きくなりすぎる。このため、第２のｐ型窒化物半導体層の膜厚は、２００ｎｍ以下が好ましく、１００ｎｍ以下が、より好ましい。なお、紫外半導体発光素子１０は、一例として、第２のｐ型窒化物半導体層の膜厚を５０ｎｍに設定している。 The hole concentration of the second p-type nitride semiconductor layer is not particularly limited, and a higher concentration is preferable in the hole concentration range in which the film quality of the second p-type nitride semiconductor layer does not deteriorate. However, the ultraviolet semiconductor light emitting device 10 has a p-type Al d Ga 1-d N (0 <d <1) layer whose electron concentration is an n-type Al z Ga 1-z N (0 <z ≦ 1) layer. Since the concentration is lower than the concentration, if the thickness of the second p-type nitride semiconductor layer is too thick, the resistance of the ultraviolet semiconductor light emitting element 10 becomes too large. For this reason, the film thickness of the second p-type nitride semiconductor layer is preferably 200 nm or less, and more preferably 100 nm or less. In the ultraviolet semiconductor light emitting device 10, as an example, the thickness of the second p-type nitride semiconductor layer is set to 50 nm.
　第３のｐ型窒化物半導体層は、ｐ型コンタクト層として設けてある。ｐ型コンタクト層は、ｐ電極７との接触抵抗を下げ、ｐ電極７との良好なオーミック接触を得るために設けてある。ｐ型コンタクト層は、ｐ型ＧａＮ層により構成してある。ｐ型コンタクト層は、第２のｐ型窒化物半導体層よりも正孔濃度を高濃度とすることが好ましい。ｐ型ＧａＮ層の正孔濃度は、例えば、７×１０17ｃｍ-3程度とすることにより、ｐ電極７との良好な電気的接触を得ることが可能である。ただし、ｐ型ＧａＮ層の正孔濃度は、特に限定するものではなく、ｐ電極７との良好な電気的接触が得られる正孔濃度の範囲で適宜変更してもよい。ｐ型コンタクト層の膜厚は、１５ｎｍに設定してあるが、これに限らず、例えば、１０ｎｍ～１５０ｎｍの範囲で設定すればよい。 The third p-type nitride semiconductor layer is provided as a p-type contact layer. The p-type contact layer is provided in order to reduce the contact resistance with the p-electrode 7 and obtain good ohmic contact with the p-electrode 7. The p-type contact layer is composed of a p-type GaN layer. The p-type contact layer preferably has a higher hole concentration than the second p-type nitride semiconductor layer. By setting the hole concentration of the p-type GaN layer to, for example, about 7 × 10 17 cm −3 , good electrical contact with the p-electrode 7 can be obtained. However, the hole concentration of the p-type GaN layer is not particularly limited, and may be changed as appropriate within the range of the hole concentration at which good electrical contact with the p electrode 7 is obtained. The thickness of the p-type contact layer is set to 15 nm, but is not limited thereto, and may be set in the range of 10 nm to 150 nm, for example.
　ｐ型層５で採用する窒化物半導体は、III族窒化物半導体であれば特に限定するものではなく、例えば、ＡｌＧａＩｎＮを採用してもよい。また、第３のｐ型窒化物半導体層は、ＡｌＧａＩｎＮの他に、ＩｎＧａＮを採用してもよい。 The nitride semiconductor employed in the p-type layer 5 is not particularly limited as long as it is a group III nitride semiconductor. For example, AlGaInN may be employed. The third p-type nitride semiconductor layer may employ InGaN in addition to AlGaInN.
　メサ構造は、基板１の一表面１ａａ側にｎ型層３と発光層４とｐ型層５との積層膜を結晶成長法により成膜した後で、フォトリソグラフィ技術およびエッチング技術を利用して、ｎ型層３の一部を露出させるように上記積層膜をパターニングすることで形成できる。結晶成長法は、エピタキシャル成長法である。エピタキシャル成長法としては、例えば、有機金属気相成長（metal organic vapor phase epitaxy：ＭＯＶＰＥ）法、ハイドライド気相成長（hydride vapor phase epitaxy：ＨＶＰＥ）法、分子線エピタキシー（molecular beam epitaxy：ＭＢＥ）法などを採用できる。 The mesa structure uses a photolithography technique and an etching technique after a laminated film of an n-type layer 3, a light emitting layer 4, and a p-type layer 5 is formed on one surface 1aa side of the substrate 1 by a crystal growth method. The laminated film can be formed by patterning so that a part of the n-type layer 3 is exposed. The crystal growth method is an epitaxial growth method. Epitaxial growth methods include, for example, metal organic vapor phase (MOVPE) method, hydride vapor phase (HVPE) method, molecular beam epitaxy (MBE) method and the like. Can be adopted.
　ｎ電極６は、図１Ａに示すように、ｎ型層３の露出表面３ａにおいて基板１の４つの角部のうちの１つの角部の上方にある領域を面状に覆うように形成することができる。露出表面３ａは、基板１の４つの角部のうちの１つの角部の上方にある領域を、４分の１円状の平面形状としてあるが、平面形状を特に限定するものではない。以下では、ｎ型層３の露出表面３ａにおいて基板１の４つの角部のうちの１つの角部の上方にある領域を、電極形成用領域と称する。 As shown in FIG. 1A, the n-electrode 6 is formed so as to cover a region above one corner of the four corners of the substrate 1 on the exposed surface 3a of the n-type layer 3 in a planar shape. Can do. The exposed surface 3a has an area above one of the four corners of the substrate 1 as a quarter-round planar shape, but the planar shape is not particularly limited. Hereinafter, the region above one of the four corners of the substrate 1 on the exposed surface 3a of the n-type layer 3 is referred to as an electrode formation region.
　ｎ電極６の平面形状は、露出表面３ａの電極形成用領域よりも若干小さな４分の１円状としてある。ｎ電極６の平面形状は、露出表面３ａの電極形成用領域と略相似形であるのが好ましい。 The planar shape of the n electrode 6 is a quarter circle that is slightly smaller than the electrode formation region of the exposed surface 3a. The planar shape of the n electrode 6 is preferably substantially similar to the electrode forming region of the exposed surface 3a.
　ｎ電極６は、ｎ電極６の元になる第１電極層を形成してから、この第１電極層とｎ型層３との熱処理（アニール処理）を行うことにより形成することができる。第１電極層は、例えば、膜厚が２０ｎｍのＴｉ膜と、膜厚が１００ｎｍのＡｌ膜と、膜厚が２０ｎｍのＴｉ膜と、膜厚が２００ｎｍのＡｕ膜とが積層された積層膜により構成することができる。第１電極層の構成や各膜の膜厚は、特に限定するものではない。紫外半導体発光素子１０は、ｎ電極６上に、例えばＡｕ膜からなる第１パッド電極（図示せず）を備えるのが好ましい。この第１パッド電極は、ｎ電極６の形成後に、形成することができる。なお、第１パッド電極は、ｎ電極６と別途に形成せずに、ｎ電極６が第１パッド電極を兼ねるようにしてもよい。 The n-electrode 6 can be formed by forming a first electrode layer as a base of the n-electrode 6 and then performing a heat treatment (annealing process) between the first electrode layer and the n-type layer 3. The first electrode layer is, for example, a laminated film in which a Ti film having a thickness of 20 nm, an Al film having a thickness of 100 nm, a Ti film having a thickness of 20 nm, and an Au film having a thickness of 200 nm are laminated. Can be configured. The configuration of the first electrode layer and the film thickness of each film are not particularly limited. The ultraviolet semiconductor light emitting element 10 preferably includes a first pad electrode (not shown) made of, for example, an Au film on the n electrode 6. The first pad electrode can be formed after the n electrode 6 is formed. The first pad electrode may not be formed separately from the n electrode 6, but the n electrode 6 may also serve as the first pad electrode.
　ｐ電極７は、ｐ電極７の元になる第２電極層を形成してから、この第２電極層とｐ型層５との熱処理（アニール処理）を行うことにより形成されている。第２電極層は、例えば、膜厚が２０ｎｍのＮｉ膜と、膜厚が１０ｎｍのＡｕ膜とが積層された積層膜により構成される。第２電極層の構成や各膜の膜厚は、特に限定するものではない。紫外半導体発光素子１０は、ｐ電極７上に、例えばＡｕ膜からなる第２パッド電極（図示せず）を備えるのが好ましい。この第２パッド電極は、ｐ電極７の形成後に、形成することが好ましい。 The p electrode 7 is formed by performing a heat treatment (annealing treatment) between the second electrode layer and the p-type layer 5 after forming the second electrode layer that is the base of the p electrode 7. For example, the second electrode layer is configured by a laminated film in which a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm are laminated. The configuration of the second electrode layer and the film thickness of each film are not particularly limited. The ultraviolet semiconductor light emitting element 10 preferably includes a second pad electrode (not shown) made of, for example, an Au film on the p electrode 7. The second pad electrode is preferably formed after the p-electrode 7 is formed.
　ｐ電極７の平面形状は、ｐ型層５の表面５ａａよりも若干小さな形状に形成されている。ここで、ｐ型電極７の平面形状は、ｐ型層５の表面５ａａと略相似形であるのが好ましい。 The planar shape of the p electrode 7 is slightly smaller than the surface 5aa of the p-type layer 5. Here, the planar shape of the p-type electrode 7 is preferably substantially similar to the surface 5aa of the p-type layer 5.
　高抵抗層８の材料としては、高抵抗層８の作製の容易さや抵抗の制御の容易さから、III族窒化物半導体、金属、導電性酸化物などが好ましい。高抵抗層８の材料としては、他にも、III族窒化物半導体以外のIII-Ｖ族半導体やIV族半導体を採用することも可能である。高抵抗層８は、その材料や成膜方法、成膜条件、処理条件などにより抵抗を制御することが可能である。 The material of the high resistance layer 8 is preferably a group III nitride semiconductor, a metal, a conductive oxide, or the like because of the ease of manufacturing the high resistance layer 8 and the ease of resistance control. In addition, as a material of the high resistance layer 8, a III-V group semiconductor or a group IV semiconductor other than the group III nitride semiconductor may be employed. The resistance of the high resistance layer 8 can be controlled by its material, film forming method, film forming conditions, processing conditions, and the like.
　高抵抗層８は、例えば、ｐ型のIII族窒化物半導体層により構成することができ、この場合、ｐ型層５よりも高抵抗であればよい。高抵抗層８を構成するIII族窒化物半導体層としては、例えば、第３の窒化物半導体層を構成するｐ型ＧａＮ層よりも高抵抗のｐ型ＧａＮ層（ｐ-ＧａＮ層）を採用することができる。高抵抗層８を構成するIII族窒化物半導体層は、ｐ型ＧａＮ層に限らず、例えば、ＩｎＧａＮ層、ＡｌＧａＮ層、ＩｎＡｌＧａＮ層などを採用してもよい。なお、高抵抗層８を構成するIII族窒化物半導体層の導電型および抵抗は、例えば、III族窒化物半導体層を単膜で成長させた試料について、ホール測定を行うことで推測することができる。高抵抗層８を構成するIII族窒化物半導体層の抵抗は、成膜時の基板温度やＶ／III比などの成長条件を適宜設定することにより、調整することができる。 The high resistance layer 8 can be constituted by, for example, a p-type group III nitride semiconductor layer. In this case, the high resistance layer 8 only needs to have a higher resistance than the p-type layer 5. As the group III nitride semiconductor layer constituting the high-resistance layer 8, for example, a p-type GaN layer (p − GaN layer) having a higher resistance than the p-type GaN layer constituting the third nitride semiconductor layer is employed. be able to. The group III nitride semiconductor layer constituting the high resistance layer 8 is not limited to the p-type GaN layer, and for example, an InGaN layer, an AlGaN layer, an InAlGaN layer, or the like may be employed. Note that the conductivity type and resistance of the group III nitride semiconductor layer constituting the high resistance layer 8 can be estimated, for example, by performing hole measurement on a sample in which the group III nitride semiconductor layer is grown as a single film. it can. The resistance of the group III nitride semiconductor layer constituting the high resistance layer 8 can be adjusted by appropriately setting growth conditions such as the substrate temperature and the V / III ratio during film formation.
　また、高抵抗層８は、金属層もしくは透明導電性酸化物層により構成することができ、この場合、ｐ電極７よりも高抵抗であればよい。高抵抗層８を構成する金属層としては、例えば、膜厚が２０ｎｍのＮｉ膜と膜厚が１０ｎｍのＡｕ膜との積層膜を採用することができる。高抵抗層８を構成する金属層の膜厚や材料は、特に限定するものではない。また、高抵抗層８は、導電性酸化物層により構成する場合、導電性酸化物層の材料として、例えば、ＩＴＯ、ＡＺＯ、ＧＺＯ、ＩＺＯなどを用いることができる。 Further, the high resistance layer 8 can be composed of a metal layer or a transparent conductive oxide layer, and in this case, it may be higher in resistance than the p electrode 7. As the metal layer constituting the high resistance layer 8, for example, a laminated film of a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm can be employed. The film thickness and material of the metal layer constituting the high resistance layer 8 are not particularly limited. Further, when the high resistance layer 8 is composed of a conductive oxide layer, for example, ITO, AZO, GZO, IZO or the like can be used as the material of the conductive oxide layer.
　高抵抗層８は、ｐ型層５の表面５ａａにおいてｎ電極６に近い側でｎ電極６におけるｐ型層５側の形状に沿った形状に形成することができる。高抵抗層８は、たとえば、ｎ電極６におけるｐ型層５側の形状に沿った弧状の形状に形成することができる。 The high resistance layer 8 can be formed on the surface 5aa of the p-type layer 5 on the side close to the n-electrode 6 and along the shape of the n-electrode 6 on the p-type layer 5 side. The high resistance layer 8 can be formed, for example, in an arc shape along the shape of the n-electrode 6 on the p-type layer 5 side.
　ところで、本願発明者らは、課題を解決するべく、鋭意研究、検討を行った。その結果、本願発明者らは、電流集中が特に起こりやすい、メサ構造におけるｎ電極６に近い側の端部の抵抗制御が上記課題の解決に重要であるという結論に至った。 By the way, the inventors of the present application conducted intensive studies and studies to solve the problems. As a result, the inventors of the present application have come to the conclusion that resistance control at the end close to the n-electrode 6 in the mesa structure, where current concentration is particularly likely, is important for solving the above problem.
　高抵抗層８を備えていない比較例の紫外半導体発光素子の等価回路を考えた場合、比較例の紫外半導体発光素子は、ｎ電極６とｐ電極７との任意の２点間の距離が長くなるほど、電流がｎ型層３の抵抗の影響を受けやすい、と考えられる。すなわち、比較例の紫外半導体発光素子は、ｎ電極６とｐ電極７との任意の２点間の距離が短くなる、メサ構造におけるｎ電極６に近い側の端部で、より大きな電流が流れやすくなる。本願発明者らは、上記課題の根本的な解決にはｎ型層３の伝導性を向上させることが重要であるという知見を得ている。しかしながら、比較例の紫外半導体発光素子では、とりわけ高いＡｌの組成比をもつＡｌＧａＮのような材料をｎ型層３に用いる場合、上記課題を解決できる程度に伝導性を向上させることは困難である。なお、ｎ型層３において、Ａｌの組成比が高いＡｌＧａＮとは、たとえば、Ａｌの組成比が０．４以上ものが挙げられる。また、本願発明者らは、電流集中を抑制するために特許文献１の第１電極および第２電極の形状を採用した紫外半導体発光素子の課題として、発光面積が減少するという新たな課題を抽出した。そして、本願発明者らは、電流集中の起こりやすい、メサ構造におけるｎ電極６に近い側の端部に高抵抗層８を形成し、ｎ型層３の抵抗が電流分布に与える影響を小さくして、電流を拡散させる、という考えに至った。　紫外半導体発光素子１０は、高抵抗層８を設けている領域を通る電流経路の抵抗と高抵抗層８を設けていない領域を通る電流経路の抵抗との抵抗差を小さくすることが可能となり、局所的な電流集中が発生するのを抑制することが可能となる。要するに、紫外半導体発光素子１０は、高抵抗層８を設けている領域を通る電流経路の電流集中が緩和される。よって、紫外半導体発光素子１０では、発光面積を減少させずに電流集中を抑制することが可能となる。したがって、紫外半導体発光素子１０は、ｎ電極６およびｐ電極７の形状に影響を及ぼすことなく、電流集中を抑制でき且つ発光むらを抑制することが可能となる。また、紫外半導体発光素子１０は、ｎ型層３にＡｌの組成比が０．４０以上のＡｌＧａＮを用いている場合や、チップ面積が一般的な青色発光ダイオードと同様に０．３５×０．３５μｍ2以上であっても、発光面積を減少させずに電流集中を抑制することが可能となる。 When considering an equivalent circuit of a comparative ultraviolet semiconductor light emitting device that does not include the high resistance layer 8, the comparative ultraviolet semiconductor light emitting device has a long distance between any two points of the n electrode 6 and the p electrode 7. It is considered that the current is easily affected by the resistance of the n-type layer 3. That is, in the ultraviolet semiconductor light emitting device of the comparative example, a larger current flows at the end portion closer to the n electrode 6 in the mesa structure where the distance between any two points of the n electrode 6 and the p electrode 7 is shortened. It becomes easy. The inventors of the present application have found that it is important to improve the conductivity of the n-type layer 3 to fundamentally solve the above problem. However, in the ultraviolet semiconductor light emitting device of the comparative example, when a material such as AlGaN having a high Al composition ratio is used for the n-type layer 3, it is difficult to improve the conductivity to the extent that the above problem can be solved. . In the n-type layer 3, AlGaN having a high Al composition ratio includes, for example, an Al composition ratio of 0.4 or more. In addition, the inventors of the present application have extracted a new problem that the light emitting area is reduced as a problem of the ultraviolet semiconductor light emitting device adopting the shapes of the first electrode and the second electrode of Patent Document 1 in order to suppress current concentration. did. The inventors of the present application form the high resistance layer 8 at the end near the n electrode 6 in the mesa structure where current concentration is likely to occur, and the influence of the resistance of the n-type layer 3 on the current distribution is reduced. This led to the idea of spreading the current. The ultraviolet semiconductor light emitting element 10 can reduce the resistance difference between the resistance of the current path passing through the region where the high resistance layer 8 is provided and the resistance of the current path passing through the region where the high resistance layer 8 is not provided. It is possible to suppress the occurrence of local current concentration. In short, in the ultraviolet semiconductor light emitting device 10, the current concentration in the current path passing through the region where the high resistance layer 8 is provided is reduced. Therefore, the ultraviolet semiconductor light emitting element 10 can suppress current concentration without reducing the light emitting area. Therefore, the ultraviolet semiconductor light emitting element 10 can suppress current concentration and suppress uneven light emission without affecting the shapes of the n electrode 6 and the p electrode 7. Further, the ultraviolet semiconductor light emitting device 10 has an n-type layer 3 made of AlGaN having an Al composition ratio of 0.40 or more, or a chip area of 0.35 × 0. Even when the thickness is 35 μm 2 or more, current concentration can be suppressed without reducing the light emitting area.
　以下、本実施形態の紫外半導体発光素子１０の製造方法について説明する。 Hereinafter, a method for manufacturing the ultraviolet semiconductor light emitting device 10 of the present embodiment will be described.
　（１）基板１を反応炉に導入する工程
　この工程では、例えばｃ面サファイア基板からなる基板１を準備した後、この基板１をＭＯＶＰＥ装置の反応炉内に導入する。この工程では、反応炉への基板１の導入前に、基板１に対して薬品による前処理を行うことにより、基板１を清浄化することが好ましい。また、この工程では、反応炉へ基板１を導入した後、反応炉の内部の真空引きを行い、その後、高純度化された窒素ガスなどを反応炉内へ流すことによって反応炉内を窒素ガスで満たしてから、排気するようにしてもよい。これにより、この工程では、基板１を導入する際に意図せず混入した空気などの気体を排気することが可能となる。なお、基板１は、紫外半導体発光素子１０を複数形成することが可能なウェハ状態のものが好ましい。 (1) Step of introducing the substrate 1 into the reaction furnace In this step, after preparing the substrate 1 made of, for example, a c-plane sapphire substrate, the substrate 1 is introduced into the reaction furnace of the MOVPE apparatus. In this step, it is preferable to clean the substrate 1 by performing a pretreatment with chemicals on the substrate 1 before introducing the substrate 1 into the reaction furnace. Also, in this step, after introducing the substrate 1 into the reaction furnace, the inside of the reaction furnace is evacuated, and then a highly purified nitrogen gas or the like is flowed into the reaction furnace to thereby circulate the inside of the reaction furnace with nitrogen gas. It is also possible to exhaust after filling with Thereby, in this process, it is possible to exhaust a gas such as air that is not intentionally mixed when the substrate 1 is introduced. The substrate 1 is preferably in a wafer state in which a plurality of ultraviolet semiconductor light emitting elements 10 can be formed.
　（２）基板１を加熱して基板１の一表面１ａａを清浄化する工程
　この工程は、反応炉内に導入された基板１の温度である基板温度を、第１規定温度まで昇温し、さらに、この第１規定温度での加熱により基板１の一表面１ａａを清浄化する。第１規定温度は、１２５０℃に設定している。 (2) A step of heating the substrate 1 to clean one surface 1aa of the substrate 1 This step raises the substrate temperature, which is the temperature of the substrate 1 introduced into the reaction furnace, to the first specified temperature, Furthermore, one surface 1aa of the substrate 1 is cleaned by heating at the first specified temperature. The first specified temperature is set to 1250 ° C.
　より具体的に説明すれば、この工程では、反応炉内の圧力を第１規定圧力に減圧した後、反応炉内を第１規定圧力に保ちながら基板温度を第１規定温度まで上昇させてから、この第１規定温度で第１規定時間の加熱を行うことにより基板１の一表面１ａａを清浄化する。この工程では、反応炉内へＨ2ガスを供給した状態で基板１を加熱することにより、清浄化を効果的に行うことができる。 More specifically, in this step, after reducing the pressure in the reaction furnace to the first specified pressure, the substrate temperature is raised to the first specified temperature while maintaining the first specified pressure in the reaction furnace. The one surface 1aa of the substrate 1 is cleaned by heating at the first specified temperature for a first specified time. In this step, cleaning can be effectively performed by heating the substrate 1 in a state where H 2 gas is supplied into the reaction furnace.
　第１規定圧力は、１０ｋＰａ≒７６Ｔｏｒｒに設定している。第１規定温度は、１０００～１３００℃の温度範囲で設定することが好ましく、１０５０～１２５０℃の温度範囲で設定することが、より好ましい。第１規定時間は、１０分間に設定している。なお、第１規定圧力および第１規定時間それぞれの値は、一例であり、特に限定するものではない。 The first specified pressure is set to 10 kPa≈76 Torr. The first specified temperature is preferably set in a temperature range of 1000 to 1300 ° C., more preferably set in a temperature range of 1050 to 1250 ° C. The first specified time is set to 10 minutes. The values of the first specified pressure and the first specified time are examples, and are not particularly limited.
　（３）バッファ層２を形成する工程
　この工程は、III族の構成元素の原料ガスとＶ族の構成元素の原料ガスとを供給することによってＡｌyＧａ1-yＮ（０＜ｙ≦１）層からなるバッファ層２を形成する工程である。ここにおいて、各原料ガスそれぞれのキャリアガスとしては、例えば、Ｈ2ガスを採用することが好ましい。 (3) Step of Forming Buffer Layer 2 In this step, Al y Ga 1-y N (0 <y ≦ 1) is provided by supplying a group III constituent element source gas and a group V constituent element source gas. ) Is a step of forming the buffer layer 2 composed of layers. Here, for example, H 2 gas is preferably used as the carrier gas of each source gas.
　この工程では、例えば、反応炉内の圧力を第２規定圧力に保ちながら基板温度を第２規定温度（所定の成長温度）に保持した状態で、ＡｌyＧａ1-yＮ（０＜ｙ≦１）層のIII族の原料ガスおよびＶ族の原料ガスを反応炉内へ供給開始して、バッファ層２を形成する。バッファ層２を形成する工程では、第２規定圧力を第１規定圧力と同じ１０ｋＰａとし、第２規定温度を第１規定温度と同じ１２５０℃としている。なお、第２規定圧力および第２規定温度それぞれの値は、一例であり、特に限定するものではない。 In this step, for example, with the substrate temperature maintained at the second specified temperature (predetermined growth temperature) while maintaining the pressure in the reactor at the second specified pressure, Al y Ga 1-y N (0 <y ≦ 1) The supply of Group III source gas and Group V source gas into the reactor is started, and the buffer layer 2 is formed. In the step of forming the buffer layer 2, the second specified pressure is set to 10 kPa which is the same as the first specified pressure, and the second specified temperature is set to 1250 ° C. which is the same as the first specified temperature. Note that the values of the second specified pressure and the second specified temperature are examples, and are not particularly limited.
　この工程では、例えば、バッファ層２をＡｌyＧａ1-yＮ（０＜ｙ≦１）層のＡｌの組成比ｙが１の、ＡｌＮ層とする場合、例えば、III族の原料ガスとしてのトリメチルアルミニウム（trimethyl aluminum：ＴＭＡｌ）と、Ｖ族の原料ガスとしてのＮＨ3とを反応炉内へ供給する。この場合には、例えば、ＴＭＡｌの流量を標準状態で０．０５Ｌ／ｍｉｎ（５０ＳＣＣＭ）に設定し、且つ、ＮＨ3の流量を標準状態で０．０５Ｌ／ｍｉｎ（５０ＳＣＣＭ）に設定してから、ＴＭＡｌとＮＨ3とを反応炉内へ同時に供給開始する。この工程では、ＴＭＡｌとＮＨ3とを反応炉内へ同時に供給開始して単結晶のＡｌＮ層からなるバッファ層２を成長させることができる。 In this step, for example, when the buffer layer 2 is an AlN layer in which the Al composition ratio y of the Al y Ga 1-y N (0 <y ≦ 1) layer is 1, for example, as a group III source gas Trimethyl aluminum (TMAl) and NH 3 as a group V source gas are supplied into the reaction furnace. In this case, for example, the flow rate of TMAl is set to 0.05 L / min (50 SCCM) in the standard state, and the flow rate of NH 3 is set to 0.05 L / min (50 SCCM) in the standard state. TMAl and NH 3 are simultaneously fed into the reactor. In this step, TMAl and NH 3 can be simultaneously supplied into the reactor to grow the buffer layer 2 made of a single crystal AlN layer.
　また、バッファ層２を形成する工程では、ＡｌyＧａ1-yＮ（０＜ｙ≦１）層のＡｌの組成比ｙを１未満とする場合、III族の原料ガスとしてのＴＭＡｌおよびトリメチルガリウム（trimethyl gallium：ＴＭＧａ）と、Ｖ族の原料ガスとしてのＮＨ3とを反応炉内へ供給すればよい。この場合には、Ａｌの組成比ｙが所望の値（０＜ｙ＜１）となるようにIII族の原料ガスにおけるＴＭＡｌのモル比（〔ＴＭＡｌ〕／｛〔ＴＭＡｌ〕＋〔ＴＭＧａ〕｝）などを設定すればよい。 Further, in the step of forming the buffer layer 2, when the Al composition ratio y of the Al y Ga 1-y N (0 <y ≦ 1) layer is less than 1, TMAl and trimethylgallium as group III source gases (Trimethyl gallium: TMGa) and NH 3 as a group V source gas may be supplied into the reaction furnace. In this case, the molar ratio of TMAl in the group III source gas ([TMAl] / {[TMAl] + [TMGa]}) so that the composition ratio y of Al becomes a desired value (0 <y <1). And so on.
　（４）ｎ型層３を形成する工程
　この工程は、基板１の一表面１ａａ側にｎ型層３を形成する工程である。なお、基板１の一表面１ａａ上にバッファ層２が形成されている場合、この工程は、バッファ層２上にｎ型層３を形成する工程である。 (4) Step of forming n-type layer 3 This step is a step of forming n-type layer 3 on one surface 1aa side of substrate 1. When the buffer layer 2 is formed on the one surface 1aa of the substrate 1, this step is a step of forming the n-type layer 3 on the buffer layer 2.
　この工程では、例えば、反応炉内の圧力を第３規定圧力に保ちながら基板温度を第３規定温度（所定の成長温度）に保持した状態で、原料ガスを反応炉内へ供給開始して、ｎ型層３を形成する。ｎ型層３を形成する工程では、原料ガスとして、たとえば、ｎ型ＡｌzＧａ1-zＮ（０＜ｚ≦１）層のIII族の原料ガス、Ｖ族の原料ガスおよびｎ型導電性を付与する不純物の原料ガスを用いることができる。この工程では、第３規定圧力を第１規定圧力と同じ１０ｋＰａとし、第３規定温度を１２００℃としている。なお、第３規定圧力および第３規定温度それぞれの値は、一例であり、特に限定するものではない。 In this step, for example, in a state where the substrate temperature is maintained at the third specified temperature (predetermined growth temperature) while maintaining the pressure in the reaction furnace at the third specified pressure, supply of the source gas into the reaction furnace is started, An n-type layer 3 is formed. In the step of forming the n-type layer 3, as the source gas, for example, a group III source gas, a group V source gas, and an n-type conductivity of an n-type Al z Ga 1 -z N (0 <z ≦ 1) layer are used. An impurity source gas that imparts can be used. In this step, the third specified pressure is set to 10 kPa, which is the same as the first specified pressure, and the third specified temperature is set to 1200 ° C. Note that the values of the third specified pressure and the third specified temperature are examples, and are not particularly limited.
　ｎ型層３を形成する工程では、Ａｌの原料ガスとしてＴＭＡｌ、Ｇａの原料ガスとしてＴＭＧａ、Ｎの原料ガスとしてＮＨ3、ｎ型導電性を付与する不純物であるＳｉの原料ガスとしてテトラエチルシラン（tetraethylsilane：ＴＥＳｉ）を用いることができる。また、各原料ガスを輸送するためのキャリアガスとしては、Ｈ2ガスを用いることができる。ここで、ＴＥＳｉの流量は、標準状態で０．０００９Ｌ／ｍｉｎ（０．９ＳＣＣＭ）とすることができる。また、この工程では、Ａｌの組成比が所望の値（例えば、０．５５）となるようにIII族の原料ガスにおけるＴＭＡｌのモル比（〔ＴＭＡｌ〕／｛〔ＴＭＡｌ〕＋〔ＴＭＧａ〕｝）を設定している。なお、各原料ガスは、特に限定するものではなく、例えば、Ｇａの原料としてトリエチルガリウム（triethyl gallium：ＴＥＧａ）、Ｎの原料ガスとしてヒドラジン誘導体、Ｓｉの原料としてモノシラン（ＳｉＨ4）を用いてもよい。また、各原料ガスそれぞれの流量は、一例であり、特に限定するものではない。 In the step of forming the n-type layer 3, TMAl is used as an Al source gas, TMGa is used as a Ga source gas, NH 3 is used as an N source gas, and tetraethylsilane (Si is an impurity imparting n-type conductivity). tetraethylsilane: TESi) can be used. As the carrier gas for carrying the source gas, it is possible to use H 2 gas. Here, the flow rate of TESi can be 0.0009 L / min (0.9 SCCM) in a standard state. In this step, the molar ratio of TMAl in the group III source gas ([TMAl] / {[TMAl] + [TMGa]}) so that the Al composition ratio becomes a desired value (for example, 0.55). Is set. Each source gas is not particularly limited. For example, triethyl gallium (TEGa) may be used as a Ga source, a hydrazine derivative may be used as an N source gas, and monosilane (SiH 4 ) may be used as a Si source. Good. Moreover, the flow rate of each source gas is an example, and is not particularly limited.
　（５）発光層４を形成する工程
　この工程は、ｎ型層３上に発光層４を形成する工程である。 (5) Step of forming the light emitting layer 4 This step is a step of forming the light emitting layer 4 on the n-type layer 3.
　この工程では、例えば、反応炉内の圧力を第４規定圧力に保ちながら基板温度を第４規定温度（所定の成長温度）に保持した状態で、III族の原料ガスおよびＶ族の原料ガスを反応炉内へ供給開始して、発光層４を形成する。発光層４を形成する工程では、第４規定圧力を第１規定圧力と同じ１０ｋＰａとし、第４規定温度を第３規定温度と同じ１２００℃とすることができる。なお、第４規定圧力および第４規定温度それぞれの値は、一例であり、特に限定するものではない。 In this step, for example, the group III source gas and the group V source gas are maintained while maintaining the substrate temperature at the fourth specified temperature (predetermined growth temperature) while maintaining the pressure in the reactor at the fourth specified pressure. The supply into the reaction furnace is started to form the light emitting layer 4. In the step of forming the light emitting layer 4, the fourth specified pressure can be set to 10 kPa which is the same as the first specified pressure, and the fourth specified temperature can be set to 1200 ° C. which is the same as the third specified temperature. In addition, each value of 4th specified pressure and 4th specified temperature is an example, and it does not specifically limit it.
　この工程では、一例として、発光層４の井戸層がＡｌ0.40Ｇａ0.60Ｎ層となり、障壁層がＡｌ0.55Ｇａ0.45Ｎ層となるように井戸層および障壁層それぞれの成長条件を設定している。なお、井戸層および障壁層それぞれの組成比は、特に限定するものではない。この工程では、井戸層および障壁層それぞれの所望の組成比に基づいて、井戸層および障壁層それぞれの成長条件を設定すればよい。 In this step, for example, the growth conditions of the well layer and the barrier layer are set so that the well layer of the light emitting layer 4 becomes an Al 0.40 Ga 0.60 N layer and the barrier layer becomes an Al 0.55 Ga 0.45 N layer. The composition ratio of each of the well layer and the barrier layer is not particularly limited. In this step, the growth conditions for the well layer and the barrier layer may be set based on the desired composition ratios of the well layer and the barrier layer.
　発光層４を形成する工程では、Ａｌの原料ガスとしてＴＭＡｌ、Ｇａの原料ガスとしてＴＭＧａ、Ｎの原料ガスとしてＮＨ3を用い、各原料ガスを輸送するためのキャリアガスとしてＨ2ガスを用いることができる。ここで、発光層４の井戸層の成長条件については、所望の組成比が得られるように、III族の原料ガスにおけるＴＭＡｌのモル比（〔ＴＭＡｌ〕／｛〔ＴＭＡｌ〕＋〔ＴＭＧａ〕｝）を設定している。また、発光層４を形成する工程では、井戸層の成長条件における上記モル比を、障壁層の成長条件における上記モル比よりも小さく設定している。なお、本実施形態の紫外半導体発光素子１０では、障壁層に不純物をドーピングしていないが、これに限らず、障壁層の結晶品質が劣化しない程度の濃度でＳｉなどの不純物をドーピングしてもよい。ここで、Ｓｉの原料ガスとしては、例えば、ＴＥＳｉを用いることができる。各原料ガスは、特に限定するものではなく、例えば、Ｇａの原料としてＴＥＧａ、Ｎの原料ガスとしてヒドラジン誘導体、Ｓｉの原料としてＳｉＨ4を用いてもよい。また、各原料ガスそれぞれの流量は、一例であり、特に限定するものではない。 In the step of forming the light emitting layer 4, TMAl is used as the Al source gas, TMGa is used as the Ga source gas, NH 3 is used as the N source gas, and H 2 gas is used as the carrier gas for transporting each source gas. Can do. Here, regarding the growth conditions of the well layer of the light emitting layer 4, the molar ratio of TMAl in the group III source gas ([TMAl] / {[TMAl] + [TMGa]}) is obtained so as to obtain a desired composition ratio. Is set. Further, in the step of forming the light emitting layer 4, the molar ratio in the growth conditions of the well layer is set smaller than the molar ratio in the growth conditions of the barrier layer. In the ultraviolet semiconductor light emitting device 10 of the present embodiment, the barrier layer is not doped with impurities. However, the present invention is not limited to this, and impurities such as Si may be doped at a concentration that does not deteriorate the crystal quality of the barrier layer. Good. Here, as the Si source gas, for example, TESi can be used. Each source gas is not particularly limited. For example, TEGa may be used as a Ga source material, a hydrazine derivative may be used as an N source gas, and SiH 4 may be used as an Si source material. Moreover, the flow rate of each source gas is an example, and is not particularly limited.
　（６）ｐ型層５の第１のｐ型窒化物半導体層を形成する工程
　この工程は、発光層４上に電子ブロック層となる第１のｐ型窒化物半導体層を形成する工程である。 (6) Step of forming first p-type nitride semiconductor layer of p-type layer 5 This step is a step of forming a first p-type nitride semiconductor layer serving as an electron blocking layer on light emitting layer 4. .
　この工程では、例えば、反応炉内の圧力を第５規定圧力に保ちながら基板温度を第５規定温度（所定の成長温度）に保持した状態で、III族の原料ガスおよびＶ族の原料ガスを反応炉内へ供給開始して、第１のｐ型窒化物半導体層を形成する。第１のｐ型窒化物半導体層を形成する工程では、第５規定圧力を第１規定圧力と同じ１０ｋＰａとし、第５規定温度を１０５０℃としている。なお、第５規定圧力および第５規定温度それぞれの値は、一例であり、特に限定するものではない。 In this step, for example, with the substrate temperature maintained at the fifth specified temperature (predetermined growth temperature) while maintaining the pressure in the reactor at the fifth specified pressure, the group III source gas and the group V source gas are added. Supply into the reaction furnace is started to form a first p-type nitride semiconductor layer. In the step of forming the first p-type nitride semiconductor layer, the fifth specified pressure is set to 10 kPa which is the same as the first specified pressure, and the fifth specified temperature is set to 1050 ° C. Note that the values of the fifth specified pressure and the fifth specified temperature are examples, and are not particularly limited.
　第１のｐ型窒化物半導体層を形成する工程では、Ａｌの原料ガスとしてＴＭＡｌ、Ｇａの原料ガスとしてＴＭＧａ、Ｎの原料ガスとしてＮＨ3、ｐ型導電性に寄与する不純物であるＭｇの原料ガスとしてビスシクロペンタジエニルマグネシウム（Ｃｐ2Ｍｇ）を用いることができる。また、この工程では、各原料ガスを輸送するためのキャリアガスとしてＨ2ガスを用いることができる。第１のｐ型窒化物半導体層を形成する工程では、Ａｌの組成比が所望の値（例えば、０．９５）となるようにIII族の原料ガスにおけるＴＭＡｌのモル比（〔ＴＭＡｌ〕／｛〔ＴＭＡｌ〕＋〔ＴＭＧａ〕｝）を設定することができる。各原料ガスは、特に限定するものではなく、例えば、Ｇａの原料としてＴＥＧａ、Ｎの原料ガスとしてヒドラジン誘導体を用いてもよい。Ｃｐ2Ｍｇの流量は、標準状態で０．０２Ｌ／ｍｉｎ（２０ＳＣＣＭ）としている。各原料ガスの流量は、特に限定するものではない。 In the step of forming the first p-type nitride semiconductor layer, TMAl is used as the Al source gas, TMGa is used as the Ga source gas, NH 3 is used as the N source gas, and Mg is an impurity that contributes to p-type conductivity. Biscyclopentadienyl magnesium (Cp 2 Mg) can be used as the gas. In this step, H 2 gas can be used as a carrier gas for transporting each source gas. In the step of forming the first p-type nitride semiconductor layer, the molar ratio of TMAl in the group III source gas ([TMAl] / {) is set so that the Al composition ratio becomes a desired value (for example, 0.95). [TMAl] + [TMGa]}) can be set. Each source gas is not particularly limited. For example, TEGa may be used as the Ga source material, and a hydrazine derivative may be used as the N source gas. The flow rate of Cp 2 Mg is 0.02 L / min (20 SCCM) in the standard state. The flow rate of each source gas is not particularly limited.
　（７）ｐ型層５の第２のｐ型窒化物半導体層を形成する工程
　この工程は、第１のｐ型窒化物半導体層上に第２のｐ型窒化物半導体層を形成する工程である。なお、第１のｐ型窒化物半導体層を設けていない場合には、発光層４上に第２のｐ型窒化物半導体層を形成する工程となる。 (7) Step of forming second p-type nitride semiconductor layer of p-type layer 5 This step is a step of forming a second p-type nitride semiconductor layer on the first p-type nitride semiconductor layer. is there. When the first p-type nitride semiconductor layer is not provided, the second p-type nitride semiconductor layer is formed on the light emitting layer 4.
　この工程では、例えば、反応炉内の圧力を第６規定圧力に保ちながら基板温度を第６規定温度（所定の成長温度）に保持した状態で、III族の原料ガスおよびＶ族の原料ガスを反応炉内へ供給開始して、第２のｐ型窒化物半導体層を形成する。第２のｐ型窒化物半導体層を形成する工程では、第６規定圧力を第１規定圧力と同じ１０ｋＰａとし、第６規定温度を１０５０℃とすることができる。なお、第６規定圧力および第６規定温度それぞれの値は、一例であり、特に限定するものではない。 In this step, for example, with the substrate temperature maintained at the sixth specified temperature (predetermined growth temperature) while maintaining the pressure in the reactor at the sixth specified pressure, the group III source gas and the group V source gas are added. Supply into the reaction furnace is started to form a second p-type nitride semiconductor layer. In the step of forming the second p-type nitride semiconductor layer, the sixth specified pressure can be set to 10 kPa, which is the same as the first specified pressure, and the sixth specified temperature can be set to 1050 ° C. The values of the sixth specified pressure and the sixth specified temperature are merely examples, and are not particularly limited.
　第２のｐ型窒化物半導体層を形成する工程では、Ａｌの原料ガスとしてＴＭＡｌ、Ｇａの原料ガスとしてＴＭＧａ、Ｎの原料ガスとしてＮＨ3、ｐ型導電性を付与する不純物であるＭｇの原料ガスとしてＣｐ2Ｍｇを用い、各原料ガスを輸送するためのキャリアガスとしてはＨ2ガスを用いることができる。ここで、この工程では、Ａｌの組成比が所望の値（例えば、０．５５）となるようにIII族の原料ガスにおけるＴＭＡｌのモル比（〔ＴＭＡｌ〕／｛〔ＴＭＡｌ〕＋〔ＴＭＧａ〕｝）を設定することができる。第２のｐ型窒化物半導体層は、Ａｌの組成比がｎ型層３におけるＡｌの組成比と同じ場合、ｎ型層３の成長条件と同じモル比に設定することができる。第２のｐ型窒化物半導体層を形成する工程では、Ｃｐ2Ｍｇの流量は、例えば、標準状態で０．０２Ｌ／ｍｉｎ（２０ＳＣＣＭ）とすることができる。各原料ガスの流量は、特に限定するものではない。 In the step of forming the second p-type nitride semiconductor layer, TMAl is used as an Al source gas, TMGa is used as a Ga source gas, NH 3 is used as an N source gas, and Mg is an impurity that imparts p-type conductivity. Cp 2 Mg can be used as the gas, and H 2 gas can be used as the carrier gas for transporting each source gas. Here, in this step, the molar ratio of TMAl in the group III source gas ([TMAl] / {[TMAl] + [TMGa]}) so that the Al composition ratio becomes a desired value (for example, 0.55). ) Can be set. When the Al composition ratio is the same as the Al composition ratio in the n-type layer 3, the second p-type nitride semiconductor layer can be set to the same molar ratio as the growth condition of the n-type layer 3. In the step of forming the second p-type nitride semiconductor layer, the flow rate of Cp 2 Mg can be set to 0.02 L / min (20 SCCM) in a standard state, for example. The flow rate of each source gas is not particularly limited.
　（８）ｐ型層５の第３のｐ型窒化物半導体層を形成する工程
　この工程は、第２のｐ型窒化物半導体層上にｐ型コンタクト層となる第３のｐ型窒化物半導体層を形成する工程である。 (8) Step of forming third p-type nitride semiconductor layer of p-type layer 5 This step is a step of forming a third p-type nitride semiconductor to be a p-type contact layer on the second p-type nitride semiconductor layer. It is a process of forming a layer.
　この工程では、例えば、反応炉内の圧力を第７規定圧力に保ちながら基板温度を第７規定温度（所定の成長温度）に保持した状態で、III族の原料ガスおよびＶ族の原料ガスを反応炉内へ供給開始して、第３のｐ型窒化物半導体層を形成する。第３のｐ型窒化物半導体層を形成する工程では、第７規定圧力を第１規定圧力と同じ１０ｋＰａとし、第７規定温度を１０５０℃とすることができる。なお、第７規定圧力および第７規定温度それぞれの値は、一例であり、特に限定するものではない。 In this step, for example, with the substrate temperature maintained at the seventh specified temperature (predetermined growth temperature) while maintaining the pressure in the reactor at the seventh specified pressure, the group III source gas and the group V source gas are mixed. The supply into the reaction furnace is started, and a third p-type nitride semiconductor layer is formed. In the step of forming the third p-type nitride semiconductor layer, the seventh specified pressure can be set to 10 kPa, which is the same as the first specified pressure, and the seventh specified temperature can be set to 1050 ° C. Note that the values of the seventh specified pressure and the seventh specified temperature are examples, and are not particularly limited.
　第３のｐ型窒化物半導体層を形成する工程では、Ｇａの原料ガスとしてＴＭＧａ、Ｎの原料ガスとしてＮＨ3、ｐ型導電性を付与する不純物であるＭｇの原料ガスとして、Ｃｐ2Ｍｇを用い、各原料ガスを輸送するためのキャリアガスとしてＨ2ガスを用いることができる。なお、第３のｐ型窒化物半導体層の成長条件は、基本的に第２のｐ型窒化物半導体層の成長条件と同じであり、ＴＭＡｌの供給を停止している点が異なる。第３のｐ型窒化物半導体層を形成する工程では、Ｃｐ2Ｍｇの流量は、標準状態で０．０２Ｌ／ｍｉｎ（２０ＳＣＣＭ）としているが、一例であり、特に限定するものではない。 In the step of forming the third p-type nitride semiconductor layer, TMGa is used as the Ga source gas, NH 3 is used as the N source gas, and Cp 2 Mg is used as the Mg source gas that imparts p-type conductivity. H 2 gas can be used as a carrier gas for transporting each source gas. The growth condition of the third p-type nitride semiconductor layer is basically the same as the growth condition of the second p-type nitride semiconductor layer, except that the supply of TMAl is stopped. In the step of forming the third p-type nitride semiconductor layer, the flow rate of Cp 2 Mg is 0.02 L / min (20 SCCM) in the standard state, but it is an example and is not particularly limited.
　（１）の工程においてＭＯＶＰＥ装置の反応炉内に基板１を導入した後、（８）の工程が終了するまでは、ＭＯＶＰＥ装置の反応炉内で連続的に結晶成長を行う。そして、ｐ型層５の成長が終わった後、基板温度を室温付近まで降温させ、ｎ型層３と発光層４とｐ型層５との積層膜が形成されている基板１をＭＯＶＰＥ装置から取り出す。要するに、本実施形態の紫外半導体発光素子１０の製造方法では、ｎ型層３と発光層４とｐ型層５との積層膜を、ＭＯＶＰＥ法により形成している。ｎ型層３と発光層４とｐ型層５との積層膜は、ＭＯＶＰＥ法に限らず、ＭＢＥ法や、ＨＶＰＥ法などにより形成してもよい。なお、本実施形態の紫外半導体発光素子１０の製造方法では、（４）～（８）の全ての工程を合わせて第１工程と称する。 After the substrate 1 is introduced into the reaction furnace of the MOVPE apparatus in the process (1), crystal growth is continuously performed in the reaction furnace of the MOVPE apparatus until the process (8) is completed. After the growth of the p-type layer 5 is finished, the substrate temperature is lowered to near room temperature, and the substrate 1 on which the laminated film of the n-type layer 3, the light-emitting layer 4, and the p-type layer 5 is formed is removed from the MOVPE apparatus. Take out. In short, in the method for manufacturing the ultraviolet semiconductor light emitting device 10 of the present embodiment, the laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 is formed by the MOVPE method. The laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 is not limited to the MOVPE method, and may be formed by an MBE method, an HVPE method, or the like. In the method for manufacturing the ultraviolet semiconductor light emitting device 10 of this embodiment, all the steps (4) to (8) are collectively referred to as a first step.
　（９）ｐ型不純物を活性化するためのアニールを行う工程
　この工程は、ｐ型層５をアニールすることにより、ｐ型層５のｐ型不純物を活性化する工程である。この工程では、アニール装置のアニール炉内において所定のアニール温度で所定のアニール時間だけ保持することにより、ｐ型層５のｐ型不純物を活性化する。ｐ型不純物を活性化するためのアニールを行う工程では、アニール温度を７５０℃、アニール時間を１０分に設定することができる。アニール温度やアニール時間の値は、一例であり、特に限定するものではない。アニール装置としては、例えば、ランプアニール装置、電気炉アニール装置などを採用することができる。 (9) Step of performing annealing for activating the p-type impurity This step is a step of activating the p-type impurity of the p-type layer 5 by annealing the p-type layer 5. In this step, the p-type impurities in the p-type layer 5 are activated by holding the wafer in the annealing furnace of the annealing apparatus at a predetermined annealing temperature for a predetermined annealing time. In the step of annealing for activating the p-type impurity, the annealing temperature can be set to 750 ° C. and the annealing time can be set to 10 minutes. The values of annealing temperature and annealing time are examples and are not particularly limited. As the annealing apparatus, for example, a lamp annealing apparatus, an electric furnace annealing apparatus, or the like can be employed.
　（１０）メサ構造を形成する工程〔第２工程〕
　この工程では、フォトリソグラフィ技術およびエッチング技術を利用して、ｎ型層３と発光層４とｐ型層５との積層膜にメサ構造を形成する。具体的には、まず、ｐ型層５の表面５ａａにおいてメサ構造の上面に対応する領域上に、フォトリソグラフィ技術を利用して第１のレジスト層を形成する。この工程では、第１のレジスト層を形成した後、ｎ型層３と発光層４とｐ型層５との積層膜の面内の一部を、第１のレジスト層をマスクとして、ｐ型層５の表面５ａａ側からｎ型層３の厚み方向の途中までエッチングすることによってメサ構造を形成する。この工程では、メサ構造を形成した後、第１のレジスト層を除去する。積層膜のエッチングは、例えば、反応性イオンエッチングにより行うことができる。この工程では、ｎ型層３と発光層４とｐ型層５との積層膜をメサ構造とすることで、ｎ型層３に露出表面３ａを設けることができる。なお、メサ構造の面積および形状は、特に限定するものではない。 (10) Step of forming mesa structure [second step]
In this step, a mesa structure is formed in the laminated film of the n-type layer 3, the light-emitting layer 4, and the p-type layer 5 by using a photolithography technique and an etching technique. Specifically, first, a first resist layer is formed on a region corresponding to the top surface of the mesa structure on the surface 5aa of the p-type layer 5 by using a photolithography technique. In this step, after forming the first resist layer, a part of the in-plane of the laminated film of the n-type layer 3, the light emitting layer 4, and the p-type layer 5 is used as a p-type with the first resist layer as a mask. A mesa structure is formed by etching from the surface 5aa side of the layer 5 to the middle in the thickness direction of the n-type layer 3. In this step, after the mesa structure is formed, the first resist layer is removed. Etching of the laminated film can be performed, for example, by reactive ion etching. In this step, the exposed surface 3a can be provided on the n-type layer 3 by forming the laminated film of the n-type layer 3, the light emitting layer 4 and the p-type layer 5 into a mesa structure. The area and shape of the mesa structure are not particularly limited.
　（１１）ｎ電極６の元になる第１電極層を形成する工程〔第３工程〕
　この工程では、ｎ型層３の露出表面３ａ上にｎ電極６の元になる第１電極層を形成する。 (11) Step of forming the first electrode layer that is the source of the n-electrode 6 [third step]
In this step, a first electrode layer that forms the base of the n electrode 6 is formed on the exposed surface 3 a of the n-type layer 3.
　より具体的に説明すれば、この工程では、まず、基板１の一表面１ａａ側においてｎ電極６の形成予定領域のみが露出するようにパターニングされた第２のレジスト層を形成する。ｎ型層３の露出表面３ａの一部は、ｎ電極６の形成予定領域となる。第１電極層を形成する工程は、第２のレジスト層を形成した後、基板１の一表面１ａａ側に第１電極層を例えば電子ビーム蒸着法により成膜してから、リフトオフを行うことにより、第２のレジスト層および第２のレジスト層上の不要膜を除去する。 More specifically, in this step, first, a second resist layer patterned so as to expose only the region where the n electrode 6 is to be formed is exposed on the one surface 1aa side of the substrate 1 is formed. A part of the exposed surface 3 a of the n-type layer 3 becomes a region where the n-electrode 6 is to be formed. In the step of forming the first electrode layer, after forming the second resist layer, the first electrode layer is formed on the one surface 1aa side of the substrate 1 by, for example, electron beam evaporation, and then lift-off is performed. The unnecessary film on the second resist layer and the second resist layer is removed.
　第１電極層は、例えば、膜厚が２０ｎｍのＴｉ膜と、膜厚が１００ｎｍのＡｌ膜と、膜厚が２０ｎｍのＴｉ膜と、膜厚が２００ｎｍのＡｕ膜との積層膜とすることができる。第１電極層の構成および各膜厚は、一例であり、特に限定するものではない。また、第１電極層の成膜方法は、特に限定するものではない。 For example, the first electrode layer may be a stacked film of a Ti film having a thickness of 20 nm, an Al film having a thickness of 100 nm, a Ti film having a thickness of 20 nm, and an Au film having a thickness of 200 nm. it can. The configuration and each film thickness of the first electrode layer are examples, and are not particularly limited. Moreover, the film-forming method of a 1st electrode layer is not specifically limited.
　（１２）ｎ電極６を形成する工程〔第４工程〕
　この工程では、第１電極層とｎ型層３とを熱処理することでｎ電極６を形成する。 (12) Step of forming n-electrode 6 [fourth step]
In this step, the n-electrode 6 is formed by heat-treating the first electrode layer and the n-type layer 3.
　より具体的に説明すれば、ｎ電極６を形成する工程では、第１電極層とｎ型層３との接触がオーミック接触となるように、熱処理を行う。熱処理としては、例えば、Ｎ2ガス雰囲気中でのＲＴＡ（Rapid Thermal Annealing）処理が好ましい。ＲＴＡ処理の条件は、例えば、熱処理温度を９００℃、熱処理時間を１分とすればよい。熱処理の条件は、特に限定するものではない。 More specifically, in the step of forming the n-electrode 6, heat treatment is performed so that the contact between the first electrode layer and the n-type layer 3 is ohmic contact. As the heat treatment, for example, RTA (Rapid Thermal Annealing) treatment in an N 2 gas atmosphere is preferable. The RTA treatment conditions may be, for example, a heat treatment temperature of 900 ° C. and a heat treatment time of 1 minute. The conditions for the heat treatment are not particularly limited.
　（１３）高抵抗層８を形成する工程〔第５工程〕
　この工程では、ｐ型層５上に高抵抗層８を形成する。高抵抗層８の形成方法は、高抵抗層８の材料などの違いによって適宜変更すればよい。 (13) Step of forming high resistance layer 8 [fifth step]
In this step, the high resistance layer 8 is formed on the p-type layer 5. The method for forming the high resistance layer 8 may be changed as appropriate depending on the material of the high resistance layer 8 and the like.
　（１３－１）金属層により構成する高抵抗層８の形成方法
　この場合には、まず、高抵抗層８の元になる金属材料層を形成する第１ステップを行う。第１ステップでは、基板１の一表面１ａａ側における高抵抗層８の形成予定領域のみが露出するようにパターニングされた第３のレジスト層を形成する。ｐ型層５の表面５ａａの一部は、高抵抗層８の形成予定領域となる。第１ステップでは、第３のレジスト層を形成した後、高抵抗層８の元になる金属材料層を電子ビーム蒸着法により成膜し、リフトオフを行うことにより第３のレジスト層および当該第３のレジスト層上の不要膜を除去する。この第１ステップでは、不要膜が不要な金属膜である。金属材料層は、例えば、膜厚が２０ｎｍのＮｉ膜と、膜厚が１０ｎｍのＡｕ膜との積層膜とすることができる。金属材料層の成膜方法や成膜条件は、限定するものではない。 (13-1) Method of Forming High Resistance Layer 8 Consists of Metal Layer In this case, first, a first step of forming a metal material layer that is the basis of the high resistance layer 8 is performed. In the first step, a third resist layer patterned so as to expose only a region where the high resistance layer 8 is to be formed on the one surface 1aa side of the substrate 1 is formed. A part of the surface 5aa of the p-type layer 5 is a region where the high resistance layer 8 is to be formed. In the first step, after the third resist layer is formed, a metal material layer that is the basis of the high resistance layer 8 is formed by an electron beam evaporation method, and lift-off is performed to thereby form the third resist layer and the third resist layer. The unnecessary film on the resist layer is removed. In the first step, the unnecessary film is an unnecessary metal film. The metal material layer can be, for example, a stacked film of a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm. The film forming method and film forming conditions for the metal material layer are not limited.
　金属層により構成する高抵抗層８の形成方法では、第１ステップの後、金属材料層を熱処理することで高抵抗層８を形成する第２ステップを行う。この第２ステップでは、金属材料層とｐ型層５との接触がオーミック接触となるように、金属材料層を熱処理する。金属層により構成する高抵抗層８の形成方法では、熱処理の条件として、例えば、雰囲気をＮ2ガス雰囲気、熱処理温度を例えば７００℃、熱処理時間を例えば１０分とすることができる。熱処理の条件は、特に限定するものではない。ただし、金属層により構成する高抵抗層８の形成方法では、第２ステップにおける熱処理温度と、後述の第７工程における熱処理温度とは異ならせるのが好ましい。 In the method of forming the high resistance layer 8 formed of the metal layer, the second step of forming the high resistance layer 8 by performing heat treatment on the metal material layer is performed after the first step. In this second step, the metal material layer is heat-treated so that the contact between the metal material layer and the p-type layer 5 is ohmic contact. In the method of forming the high resistance layer 8 formed of the metal layer, the heat treatment conditions can be, for example, an N 2 gas atmosphere, a heat treatment temperature of, for example, 700 ° C., and a heat treatment time of, for example, 10 minutes. The conditions for the heat treatment are not particularly limited. However, in the method of forming the high resistance layer 8 constituted by the metal layer, it is preferable that the heat treatment temperature in the second step is different from the heat treatment temperature in the seventh step described later.
　この工程では、金属材料層の材料としてＮｉとＡｕを用いたが、それら以外の金属を採用してもよい。 In this step, Ni and Au are used as the material of the metal material layer, but other metals may be adopted.
　（１３－２）導電性酸化物層により構成する高抵抗層８の形成方法
　導電性酸化物層により構成する高抵抗層８の形成方法では、第１ステップ、第２ステップとも高抵抗層８を金属層により構成する場合と略同じである。第１ステップでは、第３のレジスト層を形成した後、高抵抗層８の元になる導電性酸化物層を、例えばＯ2ガスアシストの電子ビーム蒸着法により形成し、その後、第３のレジスト層を除去する。導電性酸化物層は、例えば、ＩＴＯ層、ＡＺＯ層、ＧＺＯ層、ＩＺＯ層などにより構成することができる。 (13-2) Method for Forming High Resistance Layer 8 Constructed from Conductive Oxide Layer In the method for forming high resistance layer 8 composed of a conductive oxide layer, high resistance layer 8 is formed in both the first step and the second step. This is substantially the same as the case where the metal layer is used. In the first step, after the third resist layer is formed, a conductive oxide layer that is the basis of the high resistance layer 8 is formed by, for example, an O 2 gas assist electron beam evaporation method, and then the third resist layer is formed. Remove the layer. The conductive oxide layer can be composed of, for example, an ITO layer, an AZO layer, a GZO layer, an IZO layer, or the like.
　第２ステップでは、導電性酸化物層を熱処理することで高抵抗層８を形成する。この第２ステップでは、導電性酸化物層とｐ型層５との接触がオーミック接触となるように、導電性酸化物層を熱処理する。熱処理の条件は、例えば、雰囲気をＮ2ガスとＯ2ガスとの混合ガス雰囲気、熱処理温度を５００℃、熱処理時間を５分とすればよい。混合ガス雰囲気は、例えば、Ｎ2ガスとＯ2ガスとの体積比を９５：５とすることができる。熱処理の条件は、特に限定するものではない。ただし、導電性酸化物層により構成する高抵抗層８の形成方法では、第２ステップにおける熱処理温度と、後述の第７工程における熱処理温度とを異ならせることが好ましい。 In the second step, the high resistance layer 8 is formed by heat-treating the conductive oxide layer. In this second step, the conductive oxide layer is heat-treated so that the contact between the conductive oxide layer and the p-type layer 5 is ohmic contact. The conditions for the heat treatment may be, for example, a mixed gas atmosphere of N 2 gas and O 2 gas, a heat treatment temperature of 500 ° C., and a heat treatment time of 5 minutes. In the mixed gas atmosphere, for example, the volume ratio of N 2 gas and O 2 gas can be 95: 5. The conditions for the heat treatment are not particularly limited. However, in the method of forming the high resistance layer 8 constituted by the conductive oxide layer, it is preferable that the heat treatment temperature in the second step is different from the heat treatment temperature in the seventh step described later.
　（１３－３）III族窒化物半導体層により構成する高抵抗層８の形成方法
　（１３－３－１）フォトリソグラフィ技術およびエッチング技術を利用して高抵抗層８を形成する場合
　この場合は、ｐ型層５の第３のｐ型窒化物半導体層を形成する工程の後に、ｐ型層５の表面５ａａ上にIII族窒化物半導体層からなる高抵抗材料層８０をＭＯＶＰＥ装置の反応炉内で形成する第１ステップを行う（図２Ａ）。高抵抗材料層８０は、高抵抗層８の元になるものである。この第１ステップの後に、フォトリソグラフィ技術およびエッチング技術を利用して、高抵抗材料層８０をパターニングする第２ステップを行う（図２Ｂ）。III族窒化物半導体層は、例えば、ｐ型ＧａＮ層である。 (13-3) Method of forming high-resistance layer 8 composed of a group III nitride semiconductor layer (13-3-1) In the case of forming high-resistance layer 8 using photolithography technology and etching technology In this case, After the step of forming the third p-type nitride semiconductor layer of the p-type layer 5, the high resistance material layer 80 made of a group III nitride semiconductor layer is formed on the surface 5aa of the p-type layer 5 in the reactor of the MOVPE apparatus. The first step of forming is performed (FIG. 2A). The high resistance material layer 80 is a source of the high resistance layer 8. After this first step, a second step of patterning the high-resistance material layer 80 is performed using a photolithography technique and an etching technique (FIG. 2B). The group III nitride semiconductor layer is, for example, a p-type GaN layer.
　フォトリソグラフィ技術およびエッチング技術を利用して高抵抗層８を形成する場合、第１ステップでは、反応炉内の圧力を第８規定圧力に保ちながら基板温度を第８規定温度に保持した状態で、III族の原料ガスおよびＶ族の原料ガスを反応炉内へ供給開始して、III族窒化物半導体層を形成する。ここでは、第８規定圧力を第１規定圧力と同じ１０ｋＰａとし、第８規定温度を１０５０℃とすることができる。なお、第８規定圧力および第８規定温度それぞれの値は、一例であり、特に限定するものではない。 When the high resistance layer 8 is formed using photolithography technology and etching technology, in the first step, the substrate temperature is maintained at the eighth specified temperature while maintaining the pressure in the reactor at the eighth specified pressure. A group III source gas and a group V source gas are started to be supplied into the reaction furnace to form a group III nitride semiconductor layer. Here, the eighth specified pressure can be set to 10 kPa, which is the same as the first specified pressure, and the eighth specified temperature can be set to 1050 ° C. Note that the values of the eighth specified pressure and the eighth specified temperature are merely examples, and are not particularly limited.
　この第１ステップでは、Ｇａの原料ガスとしてＴＭＧａ、Ｎの原料ガスとしてＮＨ3を用いることができる。第１ステップでは、ｐ型導電性を付与する不純物であるＭｇの原料ガスとしてＣｐ2Ｍｇを用いることができる。第１ステップでは、各原料ガスを輸送するためのキャリアガスとしてＨ2ガスを用いることができる。III族窒化物半導体層により高抵抗層８を構成する場合、高抵抗材料層８０の成長条件は、基本的に第３のｐ型窒化物半導体層の成長条件と略同じにすることができる。また、高抵抗材料層８０の成長条件は、高抵抗層８をｐ型層５の第３のｐ型窒化物半導体層よりも高抵抗とするために、Ｃｐ2Ｍｇの流量を少なくしている点が異なる。III族窒化物半導体層により高抵抗層８を構成する場合、Ｃｐ2Ｍｇの流量は、標準状態で０．０１５Ｌ／ｍｉｎ（１５ＳＣＣＭ）としているが、一例であり、特に限定するものではない。なお、III族窒化物半導体層により高抵抗層８を構成する場合、高抵抗層８は、ｐ型ＧａＮ層に限らず、ｐ型ＩｎＧａＮ層、ｐ型ＡｌＧａＮ層、ｐ型ＩｎＡｌＧａＮ層などでもよい。 In this first step, TMGa can be used as the Ga source gas, and NH 3 can be used as the N source gas. In the first step, Cp 2 Mg can be used as a source gas for Mg, which is an impurity imparting p-type conductivity. In the first step, H 2 gas can be used as a carrier gas for transporting each source gas. When the high resistance layer 8 is formed of a group III nitride semiconductor layer, the growth conditions of the high resistance material layer 80 can be basically the same as the growth conditions of the third p-type nitride semiconductor layer. The growth condition of the high-resistance material layer 80 is such that the flow rate of Cp 2 Mg is reduced so that the high-resistance layer 8 has a higher resistance than the third p-type nitride semiconductor layer of the p-type layer 5. The point is different. In the case where the high resistance layer 8 is formed of a group III nitride semiconductor layer, the flow rate of Cp 2 Mg is 0.015 L / min (15 SCCM) in the standard state, but it is an example and is not particularly limited. In the case where the high resistance layer 8 is formed of a group III nitride semiconductor layer, the high resistance layer 8 is not limited to the p-type GaN layer, and may be a p-type InGaN layer, a p-type AlGaN layer, a p-type InAlGaN layer, or the like.
　フォトリソグラフィ技術およびエッチング技術を利用して高抵抗層８を形成する方法では、第１ステップの後、基板温度を室温付近まで降温させ、ｎ型層３と発光層４とｐ型層５と高抵抗材料層８０との積層膜が形成されている基板１をＭＯＶＰＥ装置から取り出す。 In the method of forming the high resistance layer 8 using the photolithography technique and the etching technique, the substrate temperature is lowered to near room temperature after the first step, and the n-type layer 3, the light-emitting layer 4, the p-type layer 5, The substrate 1 on which the laminated film with the resistance material layer 80 is formed is taken out from the MOVPE apparatus.
　第２ステップでは、フォトリソグラフィ技術を利用して、高抵抗層８の元となるIII族窒化物半導体層のうち、III族窒化物半導体層を残す領域に重なる部位以外が開口された第４のレジスト層を形成する。第２ステップでは、第４のレジスト層をマスクとして、高抵抗材料層８０のうち第４のレジスト層に覆われていない領域をエッチング除去して高抵抗層８を形成する。第２ステップでは、高抵抗層８を形成した後、第４のレジスト層を除去する。 In the second step, the photolithography technique is used to open the fourth portion of the group III nitride semiconductor layer that is the source of the high resistance layer 8 except for the portion that overlaps the region where the group III nitride semiconductor layer remains. A resist layer is formed. In the second step, using the fourth resist layer as a mask, a region of the high resistance material layer 80 that is not covered by the fourth resist layer is removed by etching to form the high resistance layer 8. In the second step, after the high resistance layer 8 is formed, the fourth resist layer is removed.
　（１３－３－２）選択成長法を用いて高抵抗層８を形成する場合
　この場合は、ｐ型層５の表面５ａａにおける高抵抗層８の形成予定領域以外を覆うマスク層９を形成する第１ステップを備える（図３Ａを参照）。第１ステップの後では、ｐ型層５の表面５ａａにｐ型のIII族窒化物半導体層からなる高抵抗層８を選択成長させる第２ステップを備える（図３Ｂを参照）。第２ステップの後では、マスク層９を除去する第３ステップを備える（図３Ｃを参照）。 (13-3-2) In the case where the high resistance layer 8 is formed using the selective growth method In this case, the mask layer 9 is formed so as to cover the surface 5aa of the p-type layer 5 other than the region where the high resistance layer 8 is to be formed. The first step is included (see FIG. 3A). After the first step, a second step of selectively growing a high resistance layer 8 made of a p-type group III nitride semiconductor layer on the surface 5aa of the p-type layer 5 is provided (see FIG. 3B). After the second step, a third step of removing the mask layer 9 is provided (see FIG. 3C).
　第１ステップでは、ｐ型層５の表面５ａａに選択成長用のマスク層９の元になるＳｉＯ2膜を、例えば、ＰＥＣＶＤ(Plasma Enhanced Chemical Vapor Deposition)法により形成する。この第１ステップでは、フォトリソグラフィ技術を利用して、ＳｉＯ2膜のうち高抵抗層８の形成予定領域に重なる部位が開口された第５のレジスト層を形成する。第１ステップでは、第５のレジスト層をマスクとしてＳｉＯ2膜の露出部位を、ＢＨＦ（バッファードフッ酸）を用いたウェットエッチングにより除去することでパターニングされたＳｉＯ２膜からなるマスク層９を形成し、その後、第５のレジスト層を除去する。なお、ＳｉＯ2膜の形成方法は、ＰＥＣＶＤ法に限らず、他のＣＶＤ法などを採用することができる。また、マスク層９の材料は、ＳｉＯ2に限らない。 In the first step, an SiO 2 film that is the basis of the mask layer 9 for selective growth is formed on the surface 5aa of the p-type layer 5 by, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition). In this first step, a fifth resist layer is formed by utilizing a photolithography technique, in which a portion of the SiO 2 film that overlaps a region where the high resistance layer 8 is to be formed is opened. In the first step, the exposed portion of the SiO 2 film a fifth resist layer as a mask, the mask layer 9 made of the patterned SiO2 film is removed by wet etching using a BHF (buffered hydrofluoric acid) form Then, the fifth resist layer is removed. The method for forming the SiO 2 film is not limited to the PECVD method, and other CVD methods can be employed. The material of the mask layer 9 is not limited to SiO 2 .
　第２ステップでは、基板１の一表面１ａａ側の最表層にマスク層９が形成された基板１を再びＭＯＶＰＥ装置の反応炉に導入し、ｐ型層５の露出表面上にIII族窒化物半導体層からなる高抵抗層８を選択成長させる。III族窒化物半導体層は、例えば、ｐ型ＧａＮ層である。 In the second step, the substrate 1 having the mask layer 9 formed on the outermost layer on the one surface 1aa side of the substrate 1 is again introduced into the reactor of the MOVPE apparatus, and the group III nitride semiconductor is formed on the exposed surface of the p-type layer 5. A high resistance layer 8 made of layers is selectively grown. The group III nitride semiconductor layer is, for example, a p-type GaN layer.
　選択成長法を用いて高抵抗層８を形成する場合、第２ステップでは、反応炉内の圧力を第９規定圧力に保ちながら基板温度を第９規定温度に保持した状態で、III族の原料ガスおよびＶ族の原料ガスを反応炉内へ供給開始して、III族窒化物半導体層を形成する。高抵抗層８の成長条件は、例えば、第９規定圧力を第１規定圧力と同じ１０ｋＰａとし、第９規定温度を１０５０℃とすることができる。なお、第９規定圧力および第９規定温度それぞれの値は、一例であり、特に限定するものではない。 When the high resistance layer 8 is formed using the selective growth method, in the second step, the group III raw material is maintained in a state where the substrate temperature is maintained at the ninth specified temperature while maintaining the pressure in the reaction furnace at the ninth specified pressure. The supply of the gas and the group V source gas into the reactor is started to form a group III nitride semiconductor layer. The growth conditions of the high resistance layer 8 can be, for example, the ninth specified pressure is 10 kPa, the same as the first specified pressure, and the ninth specified temperature is 1050 ° C. Note that the values of the ninth specified pressure and the ninth specified temperature are examples, and are not particularly limited.
　選択成長法を用いて高抵抗層８を形成する場合、第２ステップでは、Ｇａの原料ガスとしてＴＭＧａ、Ｎの原料ガスとしてＮＨ3を用いることができる。第２ステップでは、ｐ型導電性を付与する不純物であるＭｇの原料ガスとしてＣｐ2Ｍｇを用いることができる。第２ステップでは、各原料ガスを輸送するためのキャリアガスとしてＨ2ガスを用いることができる。高抵抗層８の成長条件は、基本的に第３のｐ型窒化物半導体層の成長条件と略同じであり、高抵抗層８をｐ型層５の第３のｐ型窒化物半導体層よりも高抵抗とするために、Ｃｐ2Ｍｇの流量を少なくしている点が異なる。Ｃｐ2Ｍｇの流量は、標準状態で０．０１５Ｌ／ｍｉｎ（１５ＳＣＣＭ）としているが、一例であり、特に限定するものではない。なお、選択成長法を用いて形成したIII族窒化物半導体層により高抵抗層８を構成する場合、高抵抗層８は、ｐ型ＧａＮ層に限らず、ｐ型ＩｎＧａＮ層、ｐ型ＡｌＧａＮ層、ｐ型ＩｎＡｌＧａＮ層などでもよい。 When the high resistance layer 8 is formed using the selective growth method, in the second step, TMGa can be used as the Ga source gas, and NH 3 can be used as the N source gas. In the second step, Cp 2 Mg can be used as a source gas for Mg, which is an impurity imparting p-type conductivity. In the second step, H 2 gas can be used as a carrier gas for transporting each source gas. The growth conditions of the high-resistance layer 8 are basically the same as the growth conditions of the third p-type nitride semiconductor layer, and the high-resistance layer 8 is formed from the third p-type nitride semiconductor layer of the p-type layer 5. However, the difference is that the flow rate of Cp 2 Mg is reduced in order to increase the resistance. The flow rate of Cp 2 Mg is 0.015 L / min (15 SCCM) in a standard state, but is an example and is not particularly limited. In the case where the high resistance layer 8 is composed of a group III nitride semiconductor layer formed using a selective growth method, the high resistance layer 8 is not limited to the p-type GaN layer, but a p-type InGaN layer, a p-type AlGaN layer, A p-type InAlGaN layer may be used.
　第２ステップでは、ｎ型層３、発光層４、ｐ型層５および高抵抗層８の積層構造を有する基板１をＭＯＶＰＥ装置の反応炉から取り出す。 In the second step, the substrate 1 having the laminated structure of the n-type layer 3, the light emitting layer 4, the p-type layer 5 and the high resistance layer 8 is taken out from the reactor of the MOVPE apparatus.
　選択成長法を用いて高抵抗層８を形成する場合、第３ステップでは、マスク層９をウェットエッチングにより、エッチング除去する。マスク層９の材料が例えばＳｉＯ2であれば、エッチャントとしてＢＨＦ（バッファードフッ酸）を用いることができる。 When the high resistance layer 8 is formed using the selective growth method, in the third step, the mask layer 9 is removed by wet etching. If the material of the mask layer 9 is, for example, SiO 2 , BHF (buffered hydrofluoric acid) can be used as an etchant.
　選択成長法を用いて高抵抗層８を形成する場合には、フォトリソグラフィ技術およびエッチング技術を利用して高抵抗層８をパターニングする場合に比べて、ｐ型層５のエッチングダメージを低減することが可能となる。 In the case where the high resistance layer 8 is formed using the selective growth method, the etching damage of the p-type layer 5 is reduced as compared with the case where the high resistance layer 8 is patterned using the photolithography technique and the etching technique. Is possible.
　（１４）ｐ電極７の元になる第２電極層を形成する工程〔第６工程〕
　この工程では、ｐ型層５の表面５ａａ上にｐ電極７の元になる第２電極層を形成する。 (14) Step of forming a second electrode layer that is a source of the p-electrode 7 [Sixth step]
In this step, a second electrode layer that forms the source of the p-electrode 7 is formed on the surface 5aa of the p-type layer 5.
　より具体的に説明すれば、この工程では、まず、基板１の一表面１ａａ側においてｐ電極７の形成予定領域のみが露出するようにパターニングされた第６のレジスト層を形成する。なお、ｐ電極７の形成予定領域は、ｐ型層５の表面５ａａの一部としている。この工程では、第６のレジスト層を形成した後、基板１の一表面１ａａ側に第２電極層を、例えば、電子ビーム蒸着法により成膜してから、リフトオフを行うことにより、第６のレジスト層および第６のレジスト層上の不要膜を除去する。 More specifically, in this step, first, a sixth resist layer patterned so as to expose only the region where the p electrode 7 is to be formed is exposed on the one surface 1aa side of the substrate 1 is formed. The region where the p-electrode 7 is to be formed is a part of the surface 5aa of the p-type layer 5. In this step, after the sixth resist layer is formed, the second electrode layer is formed on the one surface 1aa side of the substrate 1 by, for example, electron beam evaporation, and then lift-off is performed. Unnecessary films on the resist layer and the sixth resist layer are removed.
　第２電極層は、例えば、膜厚が２０ｎｍのＮｉ膜と膜厚が１０ｎｍのＡｕ膜との積層膜とすることができる。第２電極層の構成および各膜厚は、一例であり、特に限定するものではない。また、第２電極層の材料は、特に限定するものではない。また、第２電極層の成膜方法は、特に限定するものではない。 The second electrode layer can be, for example, a laminated film of a Ni film having a thickness of 20 nm and an Au film having a thickness of 10 nm. The configuration and each film thickness of the second electrode layer are examples, and are not particularly limited. The material for the second electrode layer is not particularly limited. Further, the method for forming the second electrode layer is not particularly limited.
　（１５）ｐ電極７を形成する工程〔第７工程〕
　この工程では、第２電極層とｐ型層５とを熱処理することでｐ電極７を形成する。 (15) Step of forming p-electrode 7 [Seventh step]
In this step, the p electrode 7 is formed by heat-treating the second electrode layer and the p-type layer 5.
　より具体的に説明すれば、ｐ電極７を形成する工程では、第２電極層とｐ型層５との接触がオーミック接触となるように、熱処理を行う。この熱処理の条件は、例えば、雰囲気をＮ2ガス雰囲気、熱処理温度を例えば５００℃、熱処理時間を例えば１０分とすればよい。熱処理の条件は、特に限定するものではない。本実施形態の紫外半導体発光素子１０の製造方法では、ｐ電極７の元になる第２電極層と高抵抗層８の元になる金属材料層とを同じ構成とする場合、それぞれの熱処理温度を異ならせることで、ｐ電極７と高抵抗層８との抵抗を異ならせることができる。これは、熱処理温度の違いにより合金形成の態様が変わりオーミック抵抗が変化するためであると推考される。 More specifically, in the step of forming the p-electrode 7, heat treatment is performed so that the contact between the second electrode layer and the p-type layer 5 is ohmic contact. The heat treatment conditions may be, for example, an N 2 gas atmosphere, a heat treatment temperature of 500 ° C., and a heat treatment time of 10 minutes, for example. The conditions for the heat treatment are not particularly limited. In the manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment, when the second electrode layer that is the source of the p electrode 7 and the metal material layer that is the source of the high resistance layer 8 have the same configuration, the respective heat treatment temperatures are set. By making it different, the resistance of the p-electrode 7 and the high resistance layer 8 can be made different. This is presumably because the mode of alloy formation changes due to the difference in heat treatment temperature and the ohmic resistance changes.
　（１６）第１パッド電極および第２パッド電極を形成する工程
　この工程では、フォトリソグラフィ技術および薄膜形成技術を利用して第１パッド電極および第２パッド電極を形成する。薄膜形成技術としては、例えば、電子ビーム蒸着法などを採用することができる。　この工程が終了することにより、紫外半導体発光素子１０が複数形成されたウェハが完成する。要するに、上述の（１）～（１６）の工程を順次行うことにより、紫外半導体発光素子１０が複数形成されたウェハが完成する。 (16) Step of Forming First Pad Electrode and Second Pad Electrode In this step, the first pad electrode and the second pad electrode are formed using photolithography technology and thin film formation technology. As the thin film formation technique, for example, an electron beam evaporation method or the like can be employed. By completing this step, a wafer on which a plurality of ultraviolet semiconductor light emitting elements 10 are formed is completed. In short, by sequentially performing the steps (1) to (16), a wafer on which a plurality of ultraviolet semiconductor light emitting elements 10 are formed is completed.
　（１７）ウェハから個々の紫外半導体発光素子に分割する工程
　この工程は、ダイシング工程であり、ウェハをダイシングソーなどによって分割することで、個々の紫外半導体発光素子１０に形成する。これにより、１枚のウェハから複数の紫外半導体発光素子１０を得ることができる。紫外半導体発光素子１０のチップサイズとしては、例えば、３５０μｍ□や１ｍｍ□などが挙げられるが、特に限定するものではない。 (17) Process of Dividing from Wafer into Individual Ultraviolet Semiconductor Light Emitting Elements This process is a dicing process, and the wafer is divided into dicing saws to form individual ultraviolet semiconductor light emitting elements 10. Thereby, a plurality of ultraviolet semiconductor light emitting elements 10 can be obtained from one wafer. Examples of the chip size of the ultraviolet semiconductor light emitting element 10 include 350 μm □ and 1 mm □, but are not particularly limited.
　上述の紫外半導体発光素子１０の製造方法は、ｎ電極６を形成する工程と、高抵抗層８を形成する工程と、ｐ電極７を形成する工程との順序を、これらの各工程の熱処理温度などを考慮して変更してもよい。 The manufacturing method of the above-described ultraviolet semiconductor light emitting device 10 includes the steps of forming the n-electrode 6, forming the high-resistance layer 8, and forming the p-electrode 7 in the order of the heat treatment temperature of each of these steps. It may be changed in consideration of the above.
　以上説明した本実施形態の紫外半導体発光素子１０の製造方法は、基板１を準備した後に、上述の第１工程～第７工程を備える。第１工程は、基板１の一表面１ａａ側にｎ型層３、発光層４およびｐ型層５を順次積層する工程である。第２工程は、ｎ型層３と発光層４とｐ型層５との積層膜の面内の一部をｎ型層３の厚み方向の途中までエッチングすることでメサ構造を形成する工程である。第３工程は、ｎ型層３の露出表面３ａ上にｎ電極６の元になる第１電極層を形成する工程である。第４工程は、第１電極層とｎ型層３とを熱処理することでｎ電極６を形成する工程である。第５工程は、ｐ型層５上に高抵抗層８を形成する工程である。第６工程は、ｐ型層５と高抵抗層８上にｐ電極７の元になる第２電極層を形成する工程である。第７工程は、第２電極層とｐ型層５とを熱処理することでｐ電極７を形成する工程である。 The manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment described above includes the above-described first to seventh steps after the substrate 1 is prepared. The first step is a step of sequentially laminating the n-type layer 3, the light emitting layer 4 and the p-type layer 5 on the one surface 1aa side of the substrate 1. The second step is a step of forming a mesa structure by etching a part of the laminated film of the n-type layer 3, the light emitting layer 4 and the p-type layer 5 in the middle of the thickness direction of the n-type layer 3. is there. The third step is a step of forming a first electrode layer that becomes the source of the n electrode 6 on the exposed surface 3 a of the n-type layer 3. The fourth step is a step of forming the n electrode 6 by heat-treating the first electrode layer and the n-type layer 3. The fifth step is a step of forming the high resistance layer 8 on the p-type layer 5. The sixth step is a step of forming a second electrode layer serving as a source of the p electrode 7 on the p-type layer 5 and the high resistance layer 8. The seventh step is a step of forming the p electrode 7 by heat-treating the second electrode layer and the p-type layer 5.
　紫外半導体発光素子１０の製造方法は、第１工程～第７工程を備えることにより、発光面積を減少させずに電流集中を抑制することが可能な紫外半導体発光素子１０を提供することが可能となる。 The manufacturing method of the ultraviolet semiconductor light emitting device 10 includes the first step to the seventh step, so that it is possible to provide the ultraviolet semiconductor light emitting device 10 capable of suppressing current concentration without reducing the light emitting area. Become.
　紫外半導体発光素子１０の製造方法では、第５工程が、高抵抗層８の元になる金属材料層を形成する第１ステップと、この金属材料層を熱処理することで高抵抗層８を形成する第２ステップとを備え、第２ステップにおける熱処理温度と、第７工程における熱処理温度とを異ならせることができる。これにより、紫外半導体発光素子１０の製造方法では、金属材料層と第２電極層とで同じ材料を採用することが可能となる。 In the method for manufacturing the ultraviolet semiconductor light emitting device 10, the fifth step includes the first step of forming a metal material layer that is the basis of the high resistance layer 8, and the heat treatment of the metal material layer to form the high resistance layer 8. A heat treatment temperature in the second step and a heat treatment temperature in the seventh step can be made different. Thereby, in the manufacturing method of the ultraviolet semiconductor light emitting element 10, it becomes possible to employ the same material for the metal material layer and the second electrode layer.
　（実施形態２）
　以下では、本実施形態の紫外半導体発光素子１０について図４Ａないし図４Ｃに基づいて説明する。 (Embodiment 2)
Below, the ultraviolet semiconductor light-emitting device 10 of this embodiment is demonstrated based on FIG. 4A thru | or FIG. 4C.
　本実施形態の紫外半導体発光素子１０は、高抵抗層８の配置が実施形態１の紫外半導体発光素子１０とは相違する。なお、実施形態１と同様の構成要素については、同様の符号を付して説明を省略する。 The ultraviolet semiconductor light emitting device 10 of the present embodiment is different from the ultraviolet semiconductor light emitting device 10 of the first embodiment in the arrangement of the high resistance layer 8. In addition, about the component similar to Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.
　本実施形態の紫外半導体発光素子１０における高抵抗層８は、ｎ電極６からの距離が遠くなるほど抵抗が小さい。その具体例として、高抵抗層８は、ｐ型層５の表面５ａａに複数形成されており、ｎ電極６からの距離が遠い高抵抗層８ほど抵抗が小さくなっている。図４Ａないし図４Ｃでは、３つの高抵抗層８が形成されている例である。以下の説明では、説明の便宜上、３つの高抵抗層８について、ｎ電極６からの距離が近い順に、高抵抗層８１、高抵抗層８２、高抵抗層８３と称することもある。なお、高抵抗層８の数は、３つに限定するものではなく、複数であればよい。 The high resistance layer 8 in the ultraviolet semiconductor light emitting element 10 of the present embodiment has a smaller resistance as the distance from the n electrode 6 increases. As a specific example, a plurality of high-resistance layers 8 are formed on the surface 5aa of the p-type layer 5, and the resistance is smaller as the high-resistance layer 8 is farther away from the n-electrode 6. 4A to 4C show an example in which three high resistance layers 8 are formed. In the following description, for convenience of description, the three high resistance layers 8 may be referred to as a high resistance layer 81, a high resistance layer 82, and a high resistance layer 83 in order of increasing distance from the n electrode 6. Note that the number of the high resistance layers 8 is not limited to three and may be any number.
　本実施形態の紫外半導体発光素子１０では、３つの高抵抗層８の抵抗値を比較すれば、〔高抵抗層８１〕＞〔高抵抗層８２〕＞〔高抵抗層８３〕となっている。 In the ultraviolet semiconductor light emitting device 10 of this embodiment, when the resistance values of the three high resistance layers 8 are compared, [high resistance layer 81]> [high resistance layer 82]> [high resistance layer 83].
　本実施形態の紫外半導体発光素子１０は、高抵抗層８に関して、ｎ電極６からの距離が遠くなるほど抵抗が小さくなっているので、実施形態１の紫外半導体発光素子１０に比べて、電流集中をより抑制できて電流の均一化を図れ、且つ発光むらをより抑制することが可能となる。 The ultraviolet semiconductor light emitting device 10 of the present embodiment has a smaller resistance with respect to the high resistance layer 8 as the distance from the n-electrode 6 increases, so that the current concentration is higher than that of the ultraviolet semiconductor light emitting device 10 of the first embodiment. The current can be made even more uniform, and the uneven emission can be further suppressed.
　本実施形態の紫外半導体発光素子１０の製造方法は、実施形態１で説明した紫外半導体発光素子１０の製造方法と略同じであり、高抵抗層８を形成する工程を高抵抗層８の数に合わせた回数だけ繰り返す点などが相違する。 The manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment is substantially the same as the manufacturing method of the ultraviolet semiconductor light emitting device 10 described in the first embodiment, and the number of steps of forming the high resistance layer 8 is the number of the high resistance layers 8. It is different in that it is repeated as many times as it is combined.
　具体的は、実施形態１において説明した「（１３－１）金属層により構成する高抵抗層８の形成方法」により高抵抗層８を形成する工程を上述の回数だけ繰り返す。ここで、本実施形態の紫外半導体発光素子１０の製造方法では、複数の高抵抗層８に関して、金属材料層の構成を同じとし、抵抗の高い順、つまり、高抵抗層８１、高抵抗層８２、高抵抗層８３の順に形成するようにし、各高抵抗層８１，８２，８３の形成領域および各熱処理温度を互いに異ならせる。高抵抗層８１、高抵抗層８２および高抵抗層８３それぞれを形成する際の熱処理温度は、例えば、７００℃、６５０℃および６００℃とすることができる。各熱処理温度は、各高抵抗層８１，８２，８３それぞれとｐ型層５とのオーミック接触が得られる温度範囲で互いに異ならせることが好ましい。なお、本実施形態の紫外半導体発光素子１０の製造方法では、各高抵抗層８１，８２，８３それぞれを形成する際の熱処理温度を異ならせているが、各高抵抗層８１，８２，８３の熱処理温度を同じに設定した上で、熱処理時間を異ならせてもよい。また、紫外半導体発光素子１０の製造方法は、各高抵抗層８１，８２，８３それぞれを形成する際の熱処理温度および熱処理時間を異ならせてもよい。 Specifically, the process of forming the high resistance layer 8 according to “(13-1) Method of forming the high resistance layer 8 including the metal layer” described in the first embodiment is repeated as many times as described above. Here, in the manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment, regarding the plurality of high resistance layers 8, the configuration of the metal material layers is the same, and the resistances are in descending order, that is, the high resistance layer 81 and the high resistance layer 82. The high resistance layers 83 are formed in this order, and the formation regions of the high resistance layers 81, 82, 83 and the heat treatment temperatures are made different from each other. The heat treatment temperatures for forming the high resistance layer 81, the high resistance layer 82, and the high resistance layer 83 can be set to 700 ° C., 650 ° C., and 600 ° C., for example. Each heat treatment temperature is preferably different from each other within a temperature range in which ohmic contact between each of the high resistance layers 81, 82, 83 and the p-type layer 5 is obtained. In addition, in the manufacturing method of the ultraviolet semiconductor light emitting element 10 of this embodiment, although the heat processing temperature at the time of forming each high resistance layer 81,82,83 is varied, each high resistance layer 81,82,83 is different. The heat treatment time may be varied after setting the heat treatment temperature to be the same. Moreover, the manufacturing method of the ultraviolet semiconductor light emitting element 10 may vary the heat treatment temperature and the heat treatment time when forming each of the high resistance layers 81, 82, 83.
　（実施形態３）
　以下では、本実施形態の紫外半導体発光素子１０について図５Ａないし図５Ｃに基づいて説明する。 (Embodiment 3)
Below, the ultraviolet semiconductor light-emitting device 10 of this embodiment is demonstrated based on FIG. 5A thru | or FIG. 5C.
　本実施形態の紫外半導体発光素子１０は、高抵抗層８の配置が実施形態１の紫外半導体発光素子１０とは相違する。なお、実施形態１と同様の構成要素については、同様の符号を付して説明を省略する。 The ultraviolet semiconductor light emitting device 10 of the present embodiment is different from the ultraviolet semiconductor light emitting device 10 of the first embodiment in the arrangement of the high resistance layer 8. In addition, about the component similar to Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.
　本実施形態の紫外半導体発光素子１０における高抵抗層８は、ｎ電極６からの距離が遠くなるほど抵抗が小さい。その具体例として、紫外半導体発光素子１０は、高抵抗層８が、ｐ型層５の表面５ａａに複数形成されており、ｎ電極６からの距離が遠い高抵抗層８ほどｐ型層５に対する接触面積が小さくなっている。言い換えれば、ｐ型層５に対する高抵抗層８の接触面積とは、ｐ型層５に対する高抵抗層８の占有率を意味している。これにより、紫外半導体発光素子１０は、実施形態１の紫外半導体発光素子１０に比べて、電流集中をより抑制できて電流の均一化を図れ、且つ発光むらをより抑制することが可能となる。 The high resistance layer 8 in the ultraviolet semiconductor light emitting element 10 of the present embodiment has a smaller resistance as the distance from the n electrode 6 increases. As a specific example, the ultraviolet semiconductor light emitting element 10 includes a plurality of high resistance layers 8 formed on the surface 5aa of the p-type layer 5 and the higher resistance layer 8 that is farther away from the n-electrode 6 is applied to the p-type layer 5. The contact area is small. In other words, the contact area of the high resistance layer 8 with respect to the p-type layer 5 means the occupation ratio of the high resistance layer 8 with respect to the p-type layer 5. Thereby, the ultraviolet semiconductor light-emitting device 10 can suppress current concentration more, can equalize the current, and can further suppress uneven light emission, as compared with the ultraviolet semiconductor light-emitting device 10 of the first embodiment.
　本実施形態の紫外半導体発光素子１０の製造方法は、実施形態２の紫外半導体発光素子１０と製造方法と同様であり、各高抵抗層８それぞれを形成する工程において第３のレジスト層を形成するフォトリソグラフィ工程で用いるフォトマスクを適宜変更すればよい。 The manufacturing method of the ultraviolet semiconductor light emitting device 10 of this embodiment is the same as the manufacturing method of the ultraviolet semiconductor light emitting device 10 of Embodiment 2, and the third resist layer is formed in the step of forming each high resistance layer 8. A photomask used in the photolithography process may be changed as appropriate.
　また、本実施形態の紫外半導体発光素子１０では、複数の高抵抗層８に関して、隣り合う高抵抗層８同士を離間させてあるので、実施形態２のように隣り合う高抵抗層８同士が接するような構造に比べて、製造時の歩留まりの向上を図ることが可能となる。 Further, in the ultraviolet semiconductor light emitting device 10 of the present embodiment, since the adjacent high resistance layers 8 are separated from each other with respect to the plurality of high resistance layers 8, the adjacent high resistance layers 8 are in contact with each other as in the second embodiment. Compared to such a structure, it is possible to improve the yield during manufacturing.
　（実施形態４）
　以下では、本実施形態の紫外半導体発光素子１０について図６Ａないし図６Ｃに基づいて説明する。 (Embodiment 4)
Below, the ultraviolet semiconductor light-emitting device 10 of this embodiment is demonstrated based on FIG. 6A thru | or FIG. 6C.
　本実施形態の紫外半導体発光素子１０は、高抵抗層８の配置が実施形態１の紫外半導体発光素子１０とは相違する。なお、実施形態１と同様の構成要素については、同様の符号を付して説明を省略する。 The ultraviolet semiconductor light emitting device 10 of the present embodiment is different from the ultraviolet semiconductor light emitting device 10 of the first embodiment in the arrangement of the high resistance layer 8. In addition, about the component similar to Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.
　本実施形態の紫外半導体発光素子１０における高抵抗層８は、ｎ電極６からの距離が遠くなるほど抵抗が小さい。その具体例として、紫外半導体発光素子１０は、高抵抗層８が、ｐ型層５の表面５ａａに複数形成されており、ｎ電極６からの距離が遠い高抵抗層８ほど膜厚が小さくなっている。これにより、紫外半導体発光素子１０は、実施形態１の紫外半導体発光素子１０に比べて、電流集中をより抑制できて電流の均一化を図れ、且つ発光むらをより抑制することが可能となる。 The high resistance layer 8 in the ultraviolet semiconductor light emitting element 10 of the present embodiment has a smaller resistance as the distance from the n electrode 6 increases. As a specific example, the ultraviolet semiconductor light emitting element 10 has a plurality of high resistance layers 8 formed on the surface 5aa of the p-type layer 5, and the thickness of the high resistance layer 8 farther from the n-electrode 6 is smaller. ing. Thereby, the ultraviolet semiconductor light-emitting device 10 can suppress current concentration more, can equalize the current, and can further suppress uneven light emission, as compared with the ultraviolet semiconductor light-emitting device 10 of the first embodiment.
　本実施形態の紫外半導体発光素子１０の製造方法は、実施形態２の紫外半導体発光素子１０と製造方法と同様であり、各高抵抗層８それぞれを形成する工程において第１ステップで形成する金属材料層の膜厚を互いに異ならせればよい。また、第１ステップにおいて、第３のレジスト層を形成するフォトリソグラフィ工程で用いるフォトマスクを適宜変更すればよい。 The manufacturing method of the ultraviolet semiconductor light emitting device 10 of the present embodiment is the same as the manufacturing method of the ultraviolet semiconductor light emitting device 10 of Embodiment 2, and the metal material formed in the first step in the process of forming each high resistance layer 8. What is necessary is just to make the film thickness of a layer mutually different. In the first step, a photomask used in the photolithography process for forming the third resist layer may be changed as appropriate.
　上述の各実施形態の紫外半導体発光素子１０は、発光層４の発光波長を紫外線の波長域において適宜設定することができるので、照明用途、水銀ランプや、エキシマランプなどの紫外光源の代替光源として用いることが可能となる。 The ultraviolet semiconductor light emitting device 10 of each of the above-described embodiments can appropriately set the light emission wavelength of the light emitting layer 4 in the ultraviolet wavelength region, so that it can be used as an alternative light source for ultraviolet light sources such as mercury lamps and excimer lamps. It can be used.
　本実施形態の紫外半導体発光素子１０は、本実施形態における金属層により構成する高抵抗層８だけでなく、実施形態１で説明した導電性酸化物層により構成する高抵抗層８やIII族窒化物半導体層により構成する高抵抗層８を用いた構成に適宜に置き換えてもよい。また、本実施形態の紫外半導体発光素子１０の製造方法は、フォトリソグラフィ技術およびエッチング技術を利用して高抵抗層８を形成する場合だけに限られない。以上では、本発明の幾つかの好ましい実施形態について記述したが、この発明の本来の精神および範囲、即ち請求の範囲を逸脱することなく、当業者によって様々な修正や変形が可能である。 The ultraviolet semiconductor light emitting device 10 of the present embodiment is not limited to the high resistance layer 8 constituted by the metal layer in the present embodiment, but also the high resistance layer 8 constituted by the conductive oxide layer described in the first embodiment and the group III nitride. A structure using the high resistance layer 8 formed of a physical semiconductor layer may be appropriately replaced. Moreover, the manufacturing method of the ultraviolet semiconductor light-emitting device 10 of this embodiment is not restricted only to the case where the high resistance layer 8 is formed using photolithography technology and etching technology. While several preferred embodiments of the present invention have been described above, various modifications and variations can be made by those skilled in the art without departing from the true spirit and scope of the present invention, that is, the claims.

Claims (9)

  1. 　基板の一表面側におけるｎ型層と発光層とｐ型層との積層膜がメサ構造を有し、前記基板の前記一表面側で前記ｎ型層の露出表面に設けられたｎ電極と、前記基板の前記一表面側で前記ｐ型層の表面側に設けられたｐ電極とを備え、前記ｐ電極が、前記ｐ型層を面状に覆うように形成され、前記ｐ型層もしくは前記ｐ電極よりも高抵抗の高抵抗層が、前記ｐ型層の前記表面において前記ｎ電極に近い側で前記ｎ電極における前記ｐ型層側の形状に沿った形状に形成されてなることを特徴とする紫外半導体発光素子。 A laminated film of an n-type layer, a light emitting layer, and a p-type layer on one surface side of the substrate has a mesa structure, and an n electrode provided on the exposed surface of the n-type layer on the one surface side of the substrate; A p-electrode provided on the surface side of the p-type layer on the one surface side of the substrate, wherein the p-electrode is formed so as to cover the p-type layer in a plane, and the p-type layer or the A high-resistance layer having a higher resistance than the p-electrode is formed on the surface of the p-type layer on the side close to the n-electrode and along the shape on the p-type layer side of the n-electrode. An ultraviolet semiconductor light emitting device.
  2. 　前記高抵抗層は、前記ｎ電極からの距離が遠くなるほど抵抗が小さいことを特徴とする請求項１記載の紫外半導体発光素子。 2. The ultraviolet semiconductor light emitting device according to claim 1, wherein the high resistance layer has a smaller resistance as the distance from the n electrode increases.
  3. 　前記高抵抗層は、前記ｐ型層の前記表面に複数形成されており、前記ｎ電極からの距離が遠い前記高抵抗層ほど前記ｐ型層に対する接触面積が小さいことを特徴とする請求項２記載の紫外半導体発光素子。 The high resistance layer is formed in plural on the surface of the p-type layer, and the contact area with the p-type layer is smaller as the high resistance layer is farther from the n-electrode. The ultraviolet semiconductor light emitting element as described.
  4. 　前記高抵抗層は、前記ｐ型層の前記表面に複数形成されており、前記ｎ電極からの距離が遠い前記高抵抗層ほど膜厚が小さいことを特徴とする請求項２記載の紫外半導体発光素子。 3. The ultraviolet semiconductor light emitting device according to claim 2, wherein a plurality of the high resistance layers are formed on the surface of the p-type layer, and the film thickness is smaller as the high resistance layer is farther from the n electrode. element.
  5. 　前記高抵抗層は、ｐ型のIII族窒化物半導体層からなり、前記ｐ型層よりも高抵抗であることを特徴とする請求項１乃至４のいずれか１項に記載の紫外半導体発光素子。 5. The ultraviolet semiconductor light-emitting element according to claim 1, wherein the high-resistance layer is made of a p-type group III nitride semiconductor layer and has a higher resistance than the p-type layer. .
  6. 　前記高抵抗層は、金属層もしくは導電性酸化物層からなり、前記ｐ電極よりも高抵抗であることを特徴とする請求項１乃至４のいずれか１項に記載の紫外半導体発光素子。 The ultraviolet semiconductor light emitting element according to any one of claims 1 to 4, wherein the high resistance layer is made of a metal layer or a conductive oxide layer and has a higher resistance than the p electrode.
  7. 　請求項１乃至６のいずれか１項に記載の紫外半導体発光素子の製造方法であって、前記基板を準備した後に、前記基板の一表面側に前記ｎ型層、前記発光層および前記ｐ型層を順次積層する第１工程と、前記ｎ型層と前記発光層と前記ｐ型層との積層膜の面内の一部を前記ｎ型層の厚み方向の途中までエッチングすることでメサ構造を形成する第２工程と、前記ｎ型層の前記露出表面上に前記ｎ電極の元になる第１電極層を形成する第３工程と、前記第１電極層と前記ｎ型層とを熱処理することで前記ｎ電極を形成する第４工程と、前記ｐ型層上に高抵抗層を形成する第５工程と、前記ｐ型層と前記高抵抗層上に前記ｐ電極の元になる第２電極層を形成する第６工程と、前記第２電極層と前記ｐ型層とを熱処理することで前記ｐ電極を形成する第７工程とを備えることを特徴とする紫外半導体発光素子の製造方法。 It is a manufacturing method of the ultraviolet semiconductor light-emitting device of any one of Claims 1 thru | or 6, Comprising: After preparing the said board | substrate, the said n-type layer, the said light emitting layer, and the said p-type on the one surface side of the said board | substrate. A first step of sequentially stacking layers, and a mesa structure by etching a portion of the n-type layer, the light-emitting layer, and the p-type layer in a plane in the thickness direction of the n-type layer. A second step of forming a first electrode layer, a third step of forming a first electrode layer as a source of the n electrode on the exposed surface of the n-type layer, and heat-treating the first electrode layer and the n-type layer. A fourth step of forming the n-electrode, a fifth step of forming a high-resistance layer on the p-type layer, and a source of the p-electrode on the p-type layer and the high-resistance layer. A sixth step of forming a two-electrode layer, and forming the p-electrode by heat-treating the second electrode layer and the p-type layer Seventh step of the manufacturing method of the ultraviolet semiconductor light emitting element characterized by comprising that.
  8. 　前記第５工程は、前記高抵抗層の元になる金属材料層を形成する第１ステップと、前記金属材料層を熱処理することで前記高抵抗層を形成する第２ステップとを備え、前記第２ステップにおける熱処理温度と、前記第７工程における熱処理温度とが異なることを特徴とする請求項７記載の紫外半導体発光素子の製造方法。 The fifth step includes a first step of forming a metal material layer that is a source of the high resistance layer, and a second step of forming the high resistance layer by heat-treating the metal material layer. 8. The method for manufacturing an ultraviolet semiconductor light-emitting element according to claim 7, wherein a heat treatment temperature in two steps is different from a heat treatment temperature in the seventh step.
  9. 　前記第５工程は、前記ｐ型層の表面における前記高抵抗層の形成予定領域以外を覆うマスク層を形成する第１ステップと、前記ｐ型層の前記表面にｐ型のIII族窒化物半導体層からなる前記高抵抗層を選択成長させる第２ステップと、前記マスク層を除去する第３ステップとを備えることを特徴とする請求項７記載の紫外半導体発光素子の製造方法。 The fifth step includes a first step of forming a mask layer covering the surface of the p-type layer other than a region where the high resistance layer is to be formed, and a p-type group III nitride semiconductor on the surface of the p-type layer. 8. The method of manufacturing an ultraviolet semiconductor light emitting element according to claim 7, further comprising a second step of selectively growing the high resistance layer made of a layer and a third step of removing the mask layer.
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