WO2014024754A1 - Circuit board for semiconductor package and method for producing same - Google Patents

Circuit board for semiconductor package and method for producing same Download PDF

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Publication number
WO2014024754A1
WO2014024754A1 PCT/JP2013/070783 JP2013070783W WO2014024754A1 WO 2014024754 A1 WO2014024754 A1 WO 2014024754A1 JP 2013070783 W JP2013070783 W JP 2013070783W WO 2014024754 A1 WO2014024754 A1 WO 2014024754A1
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WO
WIPO (PCT)
Prior art keywords
plating
semiconductor package
circuit board
semiconductor chip
mounting surface
Prior art date
Application number
PCT/JP2013/070783
Other languages
French (fr)
Japanese (ja)
Inventor
英紀 岡本
良治 河合
智也 大地
太志 杉本
庸二 滝井
Original Assignee
三菱瓦斯化学株式会社
日本サーキット工業株式会社
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Application filed by 三菱瓦斯化学株式会社, 日本サーキット工業株式会社 filed Critical 三菱瓦斯化学株式会社
Priority to JP2014529450A priority Critical patent/JPWO2014024754A1/en
Publication of WO2014024754A1 publication Critical patent/WO2014024754A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Definitions

  • the present invention relates to a circuit board for a semiconductor package on which a semiconductor chip is mounted, which is used for a circuit board used in an electronic device, an electric device, a computer, a communication device, and the like, and a manufacturing method thereof.
  • FIG. 6 is a schematic diagram showing an example of the configuration of a conventional circuit board for a semiconductor package.
  • a circuit board (100) for a semiconductor package covers a wiring board (103) in which through holes (TH) and a wiring pattern (102) are formed on an insulating base (101), and covers this.
  • a solder chip mounting surface (S2) connected to the substrate for the integrated circuit and a semiconductor chip mounting surface (S1) on which the semiconductor chip is mounted.
  • an electrode part (105) in which a part of the solder resist (104) is opened and a part of the wiring pattern (102) is exposed is formed on the semiconductor chip mounting surface (S1).
  • solder ball mounting surface (S2) On the solder ball mounting surface (S2), a part of the solder resist (104) is opened to expose a part of the wiring pattern (102), and a solder ball pad (106) is formed on the exposed wiring pattern (102).
  • a circuit board (100) for a semiconductor package is usually obtained by applying and drying a solder resist (104) on both surfaces of the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2) of the wiring substrate (103). It is manufactured by exposing to UV through a mask, developing to form an opening, and providing an electrode portion (105) and a solder ball pad (106) in the opening.
  • FIGS. 7 (a) and 7 (b) are schematic views showing an example of the configuration of a semiconductor package using the semiconductor package circuit board (100) shown in FIG.
  • the semiconductor package (900, 900 ′) shown in FIGS. 7A and 7B has the semiconductor chip (200, 200 ′) mounted on the semiconductor chip mounting surface (S1) of the circuit board for semiconductor package (100). It is formed by electrically connecting the two.
  • wire bonding, flip chip bonding, and the like can be cited as a method of electrical connection between the semiconductor package circuit board (100) and the semiconductor chip (200, 200 ′. From the above, flip chip bonding is preferably used. In the example shown in FIGS.
  • the semiconductor package circuit board (100) and the semiconductor chip (200, 200 ') are electrically connected using flip chip bonding.
  • bumps (201, 201 ′) formed in advance on the electrode portions of the semiconductor chip (200, 200 ′) are used and electrically connected to the electrode portions (105) of the circuit board (100) for the semiconductor package. Is a way to connect.
  • the electrode part (105) of the semiconductor chip mounting surface (S1) used for flip chip bonding is called a flip chip bump pad.
  • the bumps (201, 201 ') of the semiconductor chip (200, 200') are formed by a pillar such as gold or copper or solder. FIG.
  • FIG. 7A shows an example using a semiconductor chip (200) having bumps (201) made of solder
  • FIG. 7 (b) shows a semiconductor chip (200 ′) having bumps (201 ′) made of pillars.
  • the example used is shown.
  • the bumps (201, 201 ′) of the semiconductor chip (200, 200 ′) and the semiconductor package circuit board (100) are usually mounted.
  • Flip-chip bump pads (105) are brought into contact with each other, and the electrode portions are bonded together by a treatment such as heating.
  • solder balls (300) for connecting the semiconductor package and the integrated circuit board are attached to the solder ball pads (106).
  • the solder ball (300) is generally attached by bringing the solder ball (300) into contact with the solder ball pad (106) and joining them by a process such as heating.
  • the number of electrodes of the semiconductor chip (200, 200 ′) is increased, and the bumps (201, 201 ′) formed on the electrodes are also increased in density and size.
  • the movement toward high-density mounting of semiconductor chips (200, 200 ′) is expanding.
  • FIG. 8 is a schematic view showing an example of the configuration of a semiconductor package circuit board (100 ′′) having embedded bumps
  • FIG. 9 is a semiconductor package (100 ′′) using the semiconductor package circuit board (100 ′′) of FIG. 900 ").
  • the semiconductor package circuit board (100") of FIG. 8 has a bump (107) formed by electrolytic plating on a flip chip bump pad (105).
  • the connecting surface is set at a position equal to or higher than the surface of the solder resist (104).
  • FIG. 9 shows an example in which a semiconductor chip (200 ′) having bumps (201 ′) made of pillars is used, but FIG.
  • the configuration is the same.
  • an electroplating bus line (108) is previously provided on the wiring circuit on the semiconductor mounting surface (S1) side of the circuit board for semiconductor package (100A).
  • the bus line (108) is a wiring in the work panel for supplying a current necessary for electrolytic plating to the flip chip bump pad (105) at a predetermined position of the circuit board for semiconductor package (100A).
  • bus line (108) is used only when the embedded bump (107) is formed by electrolytic plating, and becomes unnecessary after the completion of the semiconductor package circuit board (100A).
  • the existence of such an extra bus line (108) greatly hinders the increase in wiring density.
  • it is conceivable to remove the bus line (108) by means of a laser or the like after the completion of the semiconductor package circuit board (100A) it is difficult to remove all of the bus line (108). There is also a problem of adversely affecting the operation. Further, even if the bus line is removed afterwards, the area after removal cannot be used for wiring formation, and therefore the reduction in wiring density is inevitable.
  • a bus line is not formed on the semiconductor chip mounting surface (S1), and an electroless copper plating film for feeding (on the solder ball mounting surface (S2) (see FIG. 10B). 109) and using this as a power supply layer, current is supplied to the solder ball pad (106) and the flip chip bump pad (105) electrically connected (via the wiring pattern (102)).
  • a circuit board (100B) for a semiconductor package in which embedded bumps (107) are formed by electrolytic plating has been studied (for example, Patent Document 2 (Japanese Patent Laid-Open No. 2011-61179)).
  • the wiring that is electrically connected to the solder ball pad (106) on the solder ball mounting surface (S2) (that is, the wiring that connects the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2)). Since current can only be supplied to the flip chip bump pads (105a) connected to the pattern (102), they are not electrically connected to the solder ball pads (106) (that is, the semiconductor chip mounting surfaces (S1) are connected to each other). There is a problem that current cannot be supplied to the flip chip bump pad (105b) connected to the wiring pattern (102) to be connected, and the embedded bump (107) cannot be formed.
  • the present invention has been made in view of such a problem, and without providing excessive wiring such as a bus line, an electrode portion that facilitates conduction with a semiconductor chip is easily and reliably formed in all the blind vias.
  • an object is to provide a circuit board for a semiconductor package.
  • the present inventors reduced the diameter of the blind via using a laser, formed an electroless plating film on the semiconductor chip mounting surface, and supplied an electric current for electrolytic plating, and By forming the surface connection pads by via filling electroplating, the surface connection pads can be easily and reliably formed in all the blind vias without providing extra wiring such as bus lines, and electrical connection with the semiconductor chip is achieved.
  • the present inventors have found that the above-mentioned problems can be solved by increasing the wiring density of the semiconductor package.
  • the gist of the present invention is a method of manufacturing a circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface, (1) A step of forming a solder resist on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material; (2) A step of forming a blind via having a hole diameter of 100 ⁇ m or less by a laser with respect to the solder resist on the semiconductor chip mounting surface side formed in (1), (3) A step of forming an electroless plating film on the solder resist surface on the semiconductor chip mounting surface side having the blind via formed in (2), (4) A step of forming an electroplating layer by performing via filling by electrolytic plating on a solder resist blind via having an electroless plating film formed on the surface thereof in (3), and (5) For portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side, the electrolytic plating layer formed in the above (4) and the electroless plating film formed in the above (3) are removed by etching
  • Another gist of the present invention resides in a circuit board for a semiconductor package manufactured by the above method.
  • Another gist of the present invention is a circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface, (A) a wiring board in which through holes and wiring patterns are formed on an insulating substrate; (B) a solder resist formed on the surface of the wiring board and having a plurality of blind vias on each of the semiconductor chip mounting surface and the solder ball mounting surface; (C) a plurality of surface layer connection pads provided in the plurality of blind vias on the semiconductor chip mounting surface and connected to the wiring pattern; (D) provided with a plurality of blind vias on the solder ball mounting surface, and provided with a plurality of solder ball pads connected to the wiring pattern; and (I) At least a part of the surface layer connection pad is electrically connected to a wiring pattern that is not electrically connected to the solder ball pad, (Ii)
  • the present invention resides in a semiconductor package circuit board, which is used for manufacturing a semiconductor package substrate but is not used as a wiring pattern and does not have a bus
  • Another gist of the present invention is the semiconductor package circuit board described above, and a semiconductor chip provided on a semiconductor chip mounting surface of the semiconductor package circuit board, and soldered to a solder ball pad of the semiconductor package circuit board.
  • a ball is provided and electrical connection between the surface layer connection pad of the circuit board for semiconductor package and the semiconductor chip is ensured.
  • Another gist of the present invention includes an integrated circuit substrate and the semiconductor package disposed on the integrated circuit substrate, wherein conduction between the solder balls of the semiconductor package and the integrated circuit substrate is provided. Remains in a secured, integrated circuit.
  • ⁇ layer connection pads are easily and surely formed in all the blind vias without providing excessive wiring such as bus lines, and electrical connection with the semiconductor chip is achieved. Can be secured. Moreover, the diameter of the blind via can be reduced by the laser without impairing the conduction with the semiconductor chip, which can contribute to the high density wiring of the semiconductor package.
  • the circuit board for a semiconductor package of the present invention is an excellent circuit board for a semiconductor package capable of achieving both easy and reliable conduction when mounting a semiconductor chip and high wiring density of the semiconductor package. It can be suitably used for manufacturing packages and integrated circuits.
  • FIGS. 1A to 1G are flowcharts showing a manufacturing procedure of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
  • 2 (a) to 2 (f) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to an embodiment of the present invention. Further, the description will be applied to the description of the manufacturing procedure of the semiconductor package circuit board in the first embodiment.
  • 2 (g) to 2 (j) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to an embodiment of the present invention. Further, the description will be applied to the description of the manufacturing procedure of the semiconductor package circuit board in the first embodiment.
  • 3A to 3F are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to another embodiment of the present invention. Also, the description will be made for the description of the manufacturing procedure of the circuit board for semiconductor package in the second embodiment.
  • 3 (g) to 3 (j) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to another embodiment of the present invention. Also, the description will be made for the description of the manufacturing procedure of the circuit board for semiconductor package in the second embodiment.
  • FIG. 4 is a schematic diagram showing an example of the configuration of the circuit board for a semiconductor package of the present invention.
  • FIG. 5A1 and 5A2 are an SEM surface photograph and an optical cross-sectional photograph of the surface layer connection pad 14 region of the semiconductor package circuit board 16 fabricated in Example 1, respectively.
  • ) And (b2) are an SEM surface photograph and an optical cross-sectional photograph of the surface layer connection pad (14) region of the semiconductor package circuit board (18) fabricated in Example 2, respectively.
  • FIG. 6 is a schematic diagram showing an example of the configuration of a conventional circuit board for a semiconductor package.
  • FIGS. 7A and 7B are schematic views showing an example of the configuration of a semiconductor package using the semiconductor package circuit board of FIG.
  • FIG. 8 is a schematic diagram showing an example of the configuration of a circuit board for a semiconductor package having a conventional embedded bump.
  • FIG. 9 is a schematic diagram showing an example of the configuration of a semiconductor package using the conventional circuit board for a semiconductor package having embedded bumps shown in FIG.
  • FIGS. 10A and 10B are diagrams for explaining a conventional method of forming embedded bumps.
  • One aspect of the present invention relates to a method of manufacturing a circuit board for a semiconductor package having a surface layer connection pad in a blind via.
  • the solder ball pad is electrically connected (that is, the wiring connecting the semiconductor chip mounting surface and the solder ball mounting surface). Since the current can be supplied only to the flip chip bump pad (connected to the pattern), the flip chip bump is not electrically connected to the solder ball pad (that is, connected to the wiring pattern connecting the semiconductor chip mounting surfaces). There was a problem that embedded pads could not be formed on the pads.
  • the current for electrolytic plating is directly applied to the wiring pattern exposed in the blind via from the electroless plating film formed on the semiconductor chip mounting surface. This is used to perform via filling by electrolytic plating.
  • the surface layer connection pad for ensuring the resistance can be easily and reliably formed, and can contribute to the high density wiring of the semiconductor package.
  • the method for manufacturing a circuit board for a semiconductor package of the present invention includes the following steps.
  • the process which shows "*" at the beginning is an arbitrary process.
  • (1) A step of forming a solder resist on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
  • (2) A step of forming a blind via having a hole diameter of 100 ⁇ m or less by laser with respect to the solder resist on the semiconductor chip mounting surface side formed in (1).
  • * (2 ′) A step of subjecting the solder resist having the blind via formed in (2) to a surface roughening treatment.
  • (3) A step of forming an electroless plating film on the surface of the solder resist on the semiconductor chip mounting surface side having the blind via formed in (2).
  • the semiconductor package circuit board has a semiconductor chip mounting surface (S1) on which a semiconductor chip is mounted and a solder ball mounting surface (S2) connected to the integrated circuit substrate, as shown in FIG. .
  • S1 semiconductor chip mounting surface
  • S2 solder ball mounting surface
  • the wiring board used in the manufacturing method of the present invention is one in which through holes and wiring patterns are formed on an insulating base material.
  • an insulating base material any insulating material used in conventional semiconductor packages or the like can be used. Examples include organic materials such as epoxy resin, cyanate resin, bismaleimide triazine resin, polyamide resin, polyimide resin, polyester resin, polyphenylene ether resin, E glass, D glass, S glass, T glass, NE glass, quartz, etc. An inorganic material etc. are mentioned. One of these materials may be used alone, or two or more thereof may be used in any combination. Examples of the form of the insulating substrate include woven fabric, nonwoven fabric, roving, chopped strand mat, and surfacing mat.
  • Examples of the shape of the insulating substrate include a plate shape and a film shape.
  • the thickness of the insulating base material is arbitrary and may be appropriately selected depending on the application, configuration, etc., but a range of usually 10 ⁇ m or more, particularly 20 ⁇ m or more is preferable.
  • a wiring substrate used in the manufacturing method of the present invention is manufactured.
  • any conventionally known method is used, and examples thereof include a mechanical drill method and a laser method.
  • Arbitrary known methods are also used to form wiring patterns. Examples include subtractive methods (panel plating and etching methods), pattern plating methods (methods based on ultrathin metal foils), and semi-additive methods. (Method of attaching an electroless metal on an insulating base material to form a base metal) is not limited thereto.
  • the conductive material from which the wiring pattern is based is not particularly limited, but usually a metal such as copper or aluminum, preferably copper is used. Further, usually, the necessary conduction between the front and back sides is ensured by forming a metal layer on the inner surface of the through hole.
  • metal foil or a metal film metal foil or metal films, such as copper and aluminum, for example, Preferably copper foil or a copper film is mentioned. In particular, electrolytic copper foil, rolled copper foil, copper alloy film and the like are suitable.
  • the metal foil or metal film may be subjected to a known surface treatment such as nickel treatment or cobalt treatment.
  • the thickness of the metal foil or metal film is arbitrary, and may be appropriately selected according to the use or configuration, but is usually 1 ⁇ m or more, preferably 10 ⁇ m or more.
  • a wiring pattern is formed.
  • the method include a subtractive method and a pattern plating method, and any method may be used in the present invention.
  • electroless plating for example, electroless copper plating using a palladium catalyst
  • electrolytic plating for example, electrolytic copper plating
  • Plating resist is laminated on top, and after patterning the plating resist by exposure and development using a pattern mask film, the plating metal in the absence of plating resist is removed by etching, and finally the plating resist is removed, thereby wiring.
  • the pattern plating method a plating resist is first laminated on a metal-clad laminate, and after patterning the plating resist by exposure and development using a pattern mask film, only the pattern portion is subjected to electrolytic plating, and further required. Accordingly, the wiring pattern is formed by performing plating that serves as a resist metal for etching, removing the plating resist, and etching unnecessary metal.
  • the thickness of the wiring pattern is arbitrary, and may be appropriately selected according to the use and configuration, but is usually in the range of 1 ⁇ m or more, particularly 5 ⁇ m or more.
  • steps such as cleaning, soft etching, half etching, desmearing, and surface roughening may be added.
  • steps such as cleaning, soft etching, half etching, desmearing, and surface roughening may be added.
  • metal layers such as a wiring pattern
  • FIG. 1 (a) An example of the manufacturing procedure of the wiring board is shown in the flowcharts of FIGS.
  • a metal-clad laminate (3) having a metal foil (2) on both sides of an insulating substrate (1) is prepared (FIG. 1 (a)).
  • Through holes (TH) are formed in the metal-clad laminate (3), and half-etching and desmearing are performed (FIG. 1 (b)).
  • Electroless plating is performed on the entire surface including the inside of the through hole (TH) of the metal-clad laminate (3) to form an electroless plating layer (4) (FIG. 1 (c)).
  • Electroless plating is performed using the electroless plating layer (4) as a power supply layer to form an electrolytic plating layer (5) (FIG. 1 (d)).
  • a plating resist (6) is laminated on both surfaces of this laminate, and patterning is performed by exposure and development using a pattern mask film (FIG. 1 (e)).
  • the electroless plating layer (4) and the electrolytic plating layer (5) in the region where the plating resist (6) is absent are removed by etching (FIG. 1 (f)).
  • the plating resist (6) is removed to obtain a wiring board (7) (FIG. 1 (g)).
  • this procedure is merely an example, and the manufacturing procedure of the wiring board is not limited to this.
  • a multilayer wiring board in which conduction between the front and back sides is ensured through blind vias and inner vias can be obtained.
  • such a multilayer wiring board is also preferably used.
  • Step (1) Formation of solder resist In this step, a solder resist is formed on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
  • the solder resist material is not limited as long as it is a solder resist material usually used for printed circuit boards and circuit boards for semiconductor packages. Examples include a thermosetting or photocurable resist material made of an epoxy resin, a photocurable resist material made of an acrylic-epoxy resin, or the like. Specific examples include PSR-4000 (liquid form) and PFR-800 (film form) manufactured by Taiyo Ink Co., Ltd.
  • the solder resist is formed by laminating a solder resist material on the surface of the wiring board, and patterning and curing the solder resist material as necessary.
  • a liquid resist material it is applied to the wiring board surface and dried by drying.
  • a coating method generally used coating methods such as a screen printing method, a roll coater method, a spray coater method, a curtain coater method, a dip coater method and the like are used.
  • lamination is performed by laminating or vacuum pressing on the surface of the wiring board.
  • the solder resist material is cured by applying an appropriate stimulus according to the type of the solder resist material, for example, irradiation with light such as UV (ultraviolet) light or heating.
  • the solder resist is patterned by forming a masking pattern on the resist material layer, curing the resist material of the patterned portion by light irradiation, and then non-curing resist material of the masking portion. This can be done by removing.
  • the method for removing the non-cured solder resist material can be appropriately selected depending on the type of the solder resist material, and examples thereof include a method using sodium carbonate (sodium carbonate). Further, post-curing by heating or UV light may be performed.
  • the thickness of the solder resist is not limited as long as the wiring pattern can be covered without exposing it to the surface, but it is usually 5 ⁇ m or more, especially 10 ⁇ m or more because it is necessary to completely cover the wiring pattern. preferable. On the other hand, from the viewpoint of reducing the energy consumption during laser processing as much as possible, it is usually 50 ⁇ m or less, preferably 30 ⁇ m or less.
  • blind vias are formed by laser on the solder resist on the semiconductor chip mounting surface side formed in (1).
  • the laser used for forming the blind via is not particularly limited as long as it is a laser generally used for forming a via on a printed wiring board or a circuit board for a semiconductor package.
  • a carbon dioxide laser, a UV laser, or the like is used.
  • Trepanning is a method of drilling while rotating the laser beam on the circumference (concentric or spiral) during drilling, and is a method commonly used when machining holes larger than the beam diameter. is there.
  • a shape in which the wall of the opening is almost vertical and the diameter of the opening (solder resist surface) is the same as the diameter of the bottom (wiring pattern surface) for example, in FIG.
  • Taper shape for example, a shape as shown in FIG.
  • the diameter of the blind via is usually 100 ⁇ m or less, preferably 80 ⁇ m or less, more preferably 50 ⁇ m or less, from the viewpoint of high integration of a semiconductor package or the like. According to the manufacturing method of the present invention, even such fine blind vias are preferable because the surface layer connection pads can be easily and reliably formed and the conduction with the semiconductor chip can be ensured. However, from the viewpoint of ensuring the conduction with the semiconductor chip, the lower limit of the diameter of the blind via is usually 5 ⁇ m or more, preferably 10 ⁇ m or more.
  • a larger blind via having a diameter exceeding 100 ⁇ m may be formed.
  • a part of the blind via formed in the solder resist is a fine blind via having a diameter of 100 ⁇ m or less, a remarkable effect can be obtained by applying the present invention.
  • the blind via is usually formed so as to penetrate the solder resist and expose the wiring pattern (metal layer) below it. For this reason, the depth of the blind via is usually the same as the thickness of the solder resist on the wiring pattern.
  • Process (2 ′) surface roughening treatment In this step, a surface roughening process is performed on the solder resist having the blind via formed in (2).
  • this process is arbitrary, it is preferable to implement this process from a viewpoint which performs formation of the electroless-plating film in postscript (3) suitably.
  • Surface roughening methods include physical treatment by spraying fine particles, such as chemical treatment, etching using a solution containing potassium permanganate or potassium chromate, plasma treatment, jet scrub treatment, sandblast treatment, etc. The physical process which performs roughening is mentioned. Among these, the jet scrub method is preferable because roughening can be performed easily and uniformly.
  • Step (3) Formation of electroless plating film In this step, an electroless plating film is formed on the surface of the solder resist on the semiconductor chip mounting surface side having the blind via formed in (2). Since the wiring pattern (metal layer) is exposed inside the blind via, an electroless plating film is formed on the exposed wiring pattern (metal layer). As a result, a power supply layer for electrolytic plating described later (4) can be secured on the solder resist surface on the semiconductor chip mounting surface side and the surface of the wiring pattern (metal layer) exposed inside the blind via.
  • the metal used as the material for electroless plating is not particularly limited, copper, nickel, tin, and the like are preferable, and copper is particularly preferable.
  • the method of electroless plating is not particularly limited, and a conventionally known method may be appropriately used. Usually, after making a metal catalyst adhere to the plating object surface, the method of processing with a plating solution is mentioned.
  • the metal catalyst examples include metals such as Pd, Ag, Pt, Au, Ni, and Co. In the case of electroless copper plating, palladium (Pd) is particularly preferable. These may be used individually by 1 type and may use 2 or more types together by arbitrary ratios and combinations.
  • the method for attaching the metal catalyst to the surface of the plating target include a method of immersing the plating target in an activator solution containing the metal catalyst and a method of depositing the metal catalyst on the plating target.
  • the amount of the metal catalyst is not particularly limited, but is preferably in the range of usually 0.1 to 2 mg / mm 2 per unit surface.
  • the composition of the plating solution is not particularly limited.
  • an electroless copper plating solution usually, copper ions and / or a salt thereof (such as copper sulfate) and a reducing agent (such as formaldehyde) And a complexing agent (for example, Rochelle salt (sodium potassium tartrate) or EDTA (ethylenediaminetetraacetic acid)) is used.
  • a complexing agent for example, Rochelle salt (sodium potassium tartrate) or EDTA (ethylenediaminetetraacetic acid)
  • the treatment is usually performed by immersing the plating object in the plating solution.
  • the thickness of the electroless copper plating film is arbitrary and may be selected as appropriate. However, from the viewpoint of ensuring conduction, it is usually 0.2 ⁇ m or more, preferably 1.0 ⁇ m or more.
  • the upper limit is not particularly limited, but is usually about 2 ⁇ m or less.
  • Step (3'-1) Formation of plating resist In this step, the plating resist is formed on both surfaces of the circuit board having the solder resist on which the electroless plating film is formed on the surface in (3). Although this step (3′-1) and steps (3′-2) and (4 ′) described later are optional, the removal amount of electrolytic plating and electroless plating can be reduced to increase the surface layer connection pad height. From the viewpoint of bringing the thickness closer to the solder resist surface, it is preferable to carry out this step.
  • the material for the plating resist is not particularly limited as long as it is a plating resist material that is usually used for printed circuit boards and circuit boards for semiconductor packages. It is preferable to use a stable material that does not dissolve or peel off. In addition, when removing the plating resist in the following (4 ′), it can be removed by a method different from the method of removing the solder resist material so that even the solder resist of the lower layer is not removed together. It is preferable to use materials. Examples of such a plating resist material include solid materials such as an alkali developing type photosensitive film (dry film).
  • the dry film examples include the Sunfort (registered trademark) series (made by Asahi Kasei E-materials), the RY series (made by Hitachi Chemical Co., Ltd.), the Liston series (made by DuPont MRC dry film). It is done.
  • the plating resist is formed by laminating plating resist materials on both sides of the circuit board.
  • the plating resist material is in the form of a film (dry film)
  • the dry resist film is laminated or vacuum-pressed on the surface of the circuit board.
  • the thickness of the plating resist is arbitrary and may be selected as appropriate. From the viewpoint of preventing plating overhang, it is usually 15 ⁇ m or more, preferably 20 ⁇ m or more, and from the viewpoint of the resolution of the dry film. Is usually in the range of 40 ⁇ m or less, particularly 30 ⁇ m or less.
  • Plating resist opening formation In this step, an opening is formed with respect to the plating resist formed in (3′-1) so that at least the blind via of the solder resist on the semiconductor chip mounting surface side is exposed.
  • a light (UV) curable material is used as the plating resist material
  • a masking pattern is formed on the resist material layer, and the resist material in the patterned portion is cured by light irradiation. Thereafter, the uncured resist material in the masking portion can be removed.
  • the method for removing the non-cured plating resist can be appropriately selected depending on the type of the plating resist, and examples thereof include a method such as treatment with an alkaline aqueous solution such as sodium carbonate.
  • the shape of the opening formed in the plating resist on the semiconductor chip mounting surface side is arbitrary, and may be any shape as long as at least the blind via of the solder resist is exposed. That is, only the blind via portion may be substantially opened, the entire semiconductor chip mounting surface may be opened (that is, all the plating resist on the semiconductor chip mounting surface may be removed), or other shapes of openings may be formed. Good.
  • substantially opening only the portion of the blind via, in the postscript (4) formation of the electrolytic plating layer in the portion other than the blind via is suppressed, and the amount of etching required in the postscript (5) is reduced.
  • the circuit board for a semiconductor package having such a thick surface layer connection pad has an advantage that it is easy to ensure electrical continuity with the semiconductor chip (this mode will be described later with reference to FIGS. 2A to 2J). To do.) On the other hand, if all of the plating resist on the semiconductor chip mounting surface is removed, there is an advantage that the labor of patterning the plating resist on the semiconductor chip mounting surface can be saved, and a circuit board for a semiconductor package can be more easily manufactured (such a case). Such a mode will be described later with reference to FIGS. 3 (a) to 3 (j).
  • via filling is performed by electrolytic plating on the solder resist blind via having the electroless plating film formed on the surface in (3) to form an electrolytic plating layer.
  • the electrolytic plating layer is applied to the semiconductor chip mounting surface while supplying power using the electroless plating film as a power feeding layer.
  • the metal used as the material for electrolytic plating is not particularly limited, copper, nickel, tin and the like are preferable, and copper is particularly preferable.
  • the electrolytic plating layer is formed so that the electrolytic plating layer in the blind via portion and the electrolytic plating layer in the other portion have almost the same height.
  • the inside of the blind via can be filled with electrolytic plating (this is referred to as “via filling”).
  • via filling the method of filled plating is not particularly limited, for example, the method described in JP-A-11-145621 can be used.
  • the surface to be plated (semiconductor chip mounting surface) is immersed in a copper sulfate plating bath and in contact with the copper sulfate plating bath, and the surface to be plated is used as a cathode. This is performed by applying an electric current from an external power source to the anode immersed in the copper sulfate plating bath.
  • a copper sulfate plating bath called a high-throw bath with a low copper concentration and a high sulfuric acid concentration in order to improve the throwing power.
  • a copper sulfate plating bath in which the copper concentration is further lowered and the sulfuric acid concentration is increased as compared with the conventional high-throw bath is used, and the current density of the cathode (cathode) is made lower than before.
  • Electrolytic plating is performed. Thereby, plating is preferentially formed inside the blind via, and via filling by filled plating is achieved.
  • the mass ratio of copper sulfate / sulfuric acid in the copper sulfate plating bath is usually 30 or less, preferably 8.33 or less.
  • plating is preferentially formed inside the blind via, and via filling by filled plating is achieved.
  • the mass ratio of copper sulfate / sulfuric acid is usually 0.66 or more, preferably 1.5 or more.
  • the copper sulfate plating bath is prepared by dissolving copper sulfate and sulfuric acid using water or the like as a solvent so that the mass ratio of copper sulfate / sulfuric acid is the above ratio.
  • the amount of copper sulfate used relative to the solvent is usually 100 g / L or more, preferably 150 g / L or more, and usually 300 g / L or less, preferably 250 g / L or less.
  • the amount of sulfuric acid used in the solvent is usually 10 g / L or more, preferably 30 g / L or more, and usually 150 g / L or less, preferably 100 g / L or less.
  • the chlorine ion content is usually 20 mg / L or more, preferably 30 mg / L or more, and usually 70 mg / L or less, especially 50 mg / L or less.
  • the copper sulfate plating bath may contain other components.
  • other components include brighteners, carriers, and leveling agents.
  • brighteners include sulfur-containing organic compounds such as thiourea and thiocarbamate.
  • the carrier include polyoxyalkylene glycol.
  • leveling agents include polyamines. The amount of these components used is the same as before.
  • the current density of the cathode (cathode) during electrolytic plating is usually 5 A / dm 2 or less, preferably 3 A / dm 2 or less.
  • plating is preferentially formed inside the blind via, and via filling by filled plating is achieved.
  • it is usually preferably 0.5 A / dm 2 or more, and more preferably 1 A / dm 2 or more.
  • the temperature at the time of electroplating is not particularly limited, it is preferably 15 ° C. or higher, particularly 20 ° C. or higher, and usually 30 ° C. or lower, especially 25 ° C. or lower.
  • the time of electrolytic plating is not limited, but at least the inside of the blind via is filled with filled plating, and the difference in height of the electrolytic plating layer between the blind via portion and the other portions is almost eliminated and it is carried out until it is substantially flat. Good.
  • the thickness of the electroplating layer is not particularly limited, but the thickness of the electroplating layer other than the blind via is usually 3 ⁇ m or more, preferably 5 ⁇ m or more, and usually 40 ⁇ m or less, especially 30 ⁇ m or less. is there.
  • the thickness of the electrolytic plating layer in the blind via portion is substantially equal to the sum of the thickness of the electrolytic plating layer in the portion other than the blind via and the depth of the blind via (that is, the thickness of the solder resist on the wiring pattern). Therefore, the thickness is much larger than the thickness of the electrolytic plating layer in the portion other than the blind via.
  • Step (4 ′) Plating resist removal In this step, the plating resist formed in (3′-1) is removed.
  • the plating resist can be removed by appropriately selecting a technique that can remove the plating resist material and that does not adversely affect electrolytic plating or solder resist such as erosion or modification. Examples include treatment with an alkaline aqueous solution such as an aqueous sodium hydroxide solution or an amine-based aqueous solution.
  • Etching removal of surplus plating, formation of surface layer connection pad In this step, the excess electrolytic plating layer (formed in (4) above) and the electroless plating film (formed in (3) above) deposited on portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side are etched. To remove the solder resist. This eliminates conduction between blind vias and achieves electrical independence between blind vias.
  • the electrolytic plating layer filled in the blind via according to the above (4) is much thicker than the electrolytic plating layer in the portion other than the blind via. It is not removed by an etching amount enough to remove the layer and the electroless plating film, but remains in the blind via.
  • a surface layer connection pad is formed by the electrolytic plating layer and the electroless plating film remaining in the blind via.
  • the etching method is not particularly limited, and any conventionally known method can be used.
  • etching is performed using a copper etchant.
  • the copper etchant those capable of selectively etching the copper plating layer are suitable, and among them, a hydrogen peroxide / sulfuric acid based etchant is preferred. Examples include SE-07 (Mitsubishi Gas Chemical Co., Ltd.), CPE-700 (Mitsubishi Gas Chemical Co., Ltd.), CPE-810 (Mitsubishi Gas Chemical Co., Ltd.), CPE-770D (Mitsubishi Gas Chemical Co., Ltd.). ), CPE-800 (Mitsubishi Gas Chemical Co., Ltd.), CPE-820 (Mitsubishi Gas Chemical Co., Ltd.) and the like.
  • the etching conditions are not limited, but the electrolytic plating layer and the electroless plating film in the portion other than the blind via are removed, and the electrolytic plating layer and the electroless plating film in the blind via portion remain, What is necessary is just to select suitably so that the surface layer connection pad of desired thickness may be formed.
  • preferable etching conditions are as follows: It is as follows. That is, the copper etching solution exemplified above is adjusted to a hydrogen peroxide concentration of 5.0 to 30 g / L, a sulfuric acid concentration of 10 to 100 g / L, and a copper concentration of about 10 to 50 g / L. It is preferable to apply the above-mentioned means, treat the solder resist surface at a temperature of about 20 to 40 ° C. until it is exposed, and then wash with an aqueous solution of sodium hydroxide, sulfuric acid or the like.
  • the metal catalyst is removed.
  • an appropriate metal removal solution may be selected and used. Examples include removal solutions such as nitric acid / chlorine ion / cationic polymer type, nitrate / inorganic acid salt or its salt type, mercapto compound type, nitrogen-containing aliphatic organic compound / iodine-containing inorganic compound type, hydrochloric acid type removing solution, etc. use.
  • Mekku Remover PJ-9710 made by Mec Co., Ltd.
  • Mekku Remover PJ-9720 made by Mec Co., Ltd.
  • Melstrip PD-3110 made by Meltex Co., Ltd.
  • Dynemat PD-280 Dynemat PD-280 (Daiwa Kasei) Co., Ltd.
  • Parastrip IC made by Atotech Co., Ltd.
  • a surface treatment is performed on the exposed portion of the electrolytic plating in the blind via after the etching of (5).
  • this step is optional, it is preferable to carry out this step from the viewpoint of poor connection due to corrosion of the surface connection pad surface.
  • the type of surface treatment is not particularly limited because it is appropriately selected depending on the use of the semiconductor package substrate and the mounting method of the semiconductor chip, but is not limited to electroless tin plating, electroless gold plating, electroless nickel gold plating, electroless Nickel palladium gold plating treatment, organic rust prevention treatment and the like are used.
  • the electroless tin plating treatment is preferably performed by immersion treatment using, for example, a substitution tin plating bath or a substitution reduction tin plating bath.
  • the electroless gold plating treatment is preferably performed by immersion treatment using, for example, a displacement gold plating bath.
  • the electroless nickel gold plating treatment is preferably performed by dipping treatment in the order of electroless nickel plating and electroless gold plating using, for example, a reduced nickel plating bath, a displacement gold plating bath or a reduced gold plating bath.
  • the electroless nickel palladium gold plating treatment uses, for example, a reduced nickel plating bath, a reduced palladium plating bath, a displacement gold plating bath or a reduced gold plating bath, in the order of electroless nickel plating, electroless palladium plating, and electroless gold plating. It is preferable to carry out by immersion treatment.
  • the method for manufacturing a circuit board for a semiconductor package of the present invention may have an optional step in addition to the above-described steps. For example, after forming the solder resist in the step (1), the solder resist on the solder ball mounting surface is opened by patterning separately from the blind via formation on the semiconductor chip mounting surface side solder resist in the step (2). It is preferable to carry out a surface treatment such as formation of an electroplating layer, formation of an electrolytic plating layer, or a treatment such as attachment of a solder ball.
  • FIGS. 2A An example of a method for manufacturing a semiconductor package circuit board of the present invention is shown in the flowcharts of FIGS.
  • a wiring board (7) in which through holes and wiring patterns are formed on an insulating base material is prepared (FIG. 2A).
  • a solder resist (8) is formed on the surface of the wiring board (7) (step (1)), the solder resist on the solder ball mounting surface (S2) is patterned, the wiring pattern is exposed, and a solder ball pad (9) Is formed (FIG. 2B).
  • An electrolytic plating layer (10) is formed on the solder ball pad (9) as a surface treatment layer (FIG. 2 (c)).
  • a blind via (BV) is formed on the semiconductor chip mounting surface (S1) side solder resist with a laser (step (2): FIG. 2 (d)).
  • the wiring pattern (2) in the blind via (BV) is exposed.
  • step (2 ′) after subjecting the solder resist on the semiconductor chip mounting surface (S1) side to surface roughening (step (2 ′)), the surface of the solder resist (and the surface of the wiring pattern (2) exposed in the blind via (BV)) ) To form an electroless plating film (11) (step (3): FIG. 2 (e)).
  • a plating resist (12) is formed on both surfaces of the wiring board (step (3'-1)), and openings (O) are formed so that the solder resist blind vias on the semiconductor chip mounting surface (S1) side are exposed.
  • step (3′-2) FIG. 2 (f)
  • blind via (BV) via filling is performed by electrolytic plating to form an electrolytic plating layer (13) (step (4): FIG. 2 (g)).
  • the plating resist (12) is removed (step (4 ′): FIG. 2 (h)).
  • a surface layer connection pad (14) comprising an electrolytic plating layer (13) and an electroless plating film (11) is formed in the via (BV) (step (5): FIG. 2 (i)). Thereafter, the surface layer connection pad (14) is subjected to a surface treatment to form an electroless plating layer (15), thereby producing a circuit board (16) for a semiconductor package (step (5 ′): FIG. 2 (j). )).
  • FIGS. 3A to 3J Another specific example of the method for manufacturing a circuit board for a semiconductor package of the present invention is shown in the flowcharts of FIGS.
  • the procedures of FIGS. 3A to 3J are the same as the procedures of FIGS. 2A to 2J except for the points described below. That is, a plating resist is formed only on the solder ball mounting surface (S2) side of the wiring board (step (3′-2): FIG. 3 (f)). This increases the amount of the electrolytic plating layer (13) and the electroless plating film (11) to be removed by etching in the step (5) (FIGS. 3 (h) and (i)), so that the resulting surface layer Although the thickness of the connection pad (14) is smaller than that of the above example (FIG. 3 (j)), the semiconductor package circuit board (18) can be obtained by a simpler operation.
  • the above manufacturing method is merely an example, and the manufacturing method of the circuit board for a semiconductor package of the present invention is not limited to this.
  • circuit board for semiconductor packages Another aspect of the present invention relates to a circuit board for a semiconductor package manufactured by the method for manufacturing a circuit board for a semiconductor package of the present invention.
  • the semiconductor package circuit board (16, 18) of the present invention has a semiconductor chip mounting surface (S1) and a solder ball mounting surface (S2), (A) a wiring substrate (7) in which a through hole (TH) and a wiring pattern (2) are formed on an insulating substrate (1); (B) a solder resist (8) formed on the surface of the wiring board (7) and having a plurality of blind vias (BV) on each of the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2); (C) a plurality of surface layer connection pads (14) provided in the plurality of blind vias (BV) on the semiconductor chip mounting surface (S1) and electrically connected to the wiring pattern; (D) A plurality of solder ball pads (9) provided on the plurality of blind vias (BV) on the solder ball mounting surface (S2) and connected to the wiring pattern.
  • S1 semiconductor chip mounting surface
  • S2 solder ball mounting surface
  • A a wiring substrate (7) in which a through hole (TH) and a wiring pattern (2) are formed on
  • a surface treatment layer reference numerals 10, 15, and 17 in FIGS. 2 and 3
  • the details of each component are as described above in the method for manufacturing a circuit board for a semiconductor package of the present invention.
  • the circuit board (16, 18) for a semiconductor package of the present invention has a blind via (BV) formed on a wiring pattern (2a) connecting the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2). ) As well as the blind vias (BV) formed on the wiring pattern (2b) connecting the semiconductor chip mounting surfaces (S1) to each other, have the surface layer connection pads (14).
  • the semiconductor package circuit board (16, 18) of the present invention at least a part of the surface layer connection pads is electrically connected to the wiring pattern that is not electrically connected to the solder ball pads. Thereby, conduction
  • Such a configuration is a conventional technique in which a current is supplied from the electroless plating film on the solder ball mounting surface into the blind via and a buried bump is formed by electrolytic plating (FIG. 10B: Patent Document 2 (JP 2011-61179 A). ) Etc.) is a configuration that could not be achieved.
  • the semiconductor package circuit boards (16, 18) of the present invention are used in the manufacture of general semiconductor package circuit boards (for example, for surface treatment of flip chip bump pads, formation of embedded bumps, surface treatment, etc.). Although used, it is not used as a wiring pattern and does not have unnecessary bus lines.
  • the bus line for forming the embedded bump FIG. 10A: Patent Document 1 (Japanese Patent Laid-Open No. 52-12575), etc.)
  • the presence of such an unnecessary bus line is caused by the high wiring height.
  • the configuration of the present invention that eliminates the need for such bus lines is very advantageous in terms of increasing the wiring density and stabilizing the operation.
  • the wiring of the circuit board for semiconductor package can be made higher in density than in the past.
  • the bump pitch (distance between the bump centers) of the circuit board for semiconductor package can be set to 200 ⁇ m or less, particularly 130 ⁇ m or less, for example.
  • the circuit board for semiconductor package of the present invention is clearly differentiated in configuration from the circuit board for semiconductor package having embedded bumps manufactured by the prior art, and has a very remarkable effect. Is clear.
  • a semiconductor package of the present invention includes the above-described semiconductor package circuit board of the present invention and a semiconductor chip provided on a semiconductor chip mounting surface of the semiconductor package circuit board, and a surface layer connection pad of the semiconductor package circuit board; It has a configuration in which conduction with a semiconductor chip is ensured.
  • semiconductor chips such as a CPU and a semiconductor memory (SRAM, DRAM, etc.). These semiconductor chips are appropriately selected according to the specifications and applications of the target semiconductor package, and are arranged on the semiconductor chip mounting surface of the semiconductor package circuit board to form electrical continuity with the semiconductor package circuit board.
  • Examples of the method for forming electrical connection between the circuit board for semiconductor package and the semiconductor chip include wire bonding and flip chip bonding. From the viewpoint of integration of the semiconductor chip and miniaturization of the semiconductor package, the semiconductor package according to the present invention.
  • flip chip bonding is preferable.
  • flip chip bonding is a method of electrically connecting a bump formed in advance on an electrode portion of a semiconductor chip to an electrode portion (flip chip bump pad) of a circuit board for a semiconductor package.
  • pillars and solder balls made of metal such as gold or copper are used as the bumps of the electrode portions of the semiconductor chip, and these are appropriately selected according to the specifications and applications of the target semiconductor package.
  • the semiconductor package of the present invention is configured by bringing the electrode portions (bumps) of the semiconductor chip into contact with the surface layer connection pads of the semiconductor package circuit board of the present invention and electrically connecting them. Thereby, electrical continuity with the electrode part (bump) of the semiconductor chip can be ensured easily and reliably when the semiconductor chip is mounted.
  • the semiconductor chip is fixed to the circuit board for semiconductor package by means such as adhesion in a state where conduction is ensured.
  • various processes such as mounting of other electronic components and storage in a housing may be added as necessary.
  • An integrated circuit of the present invention includes an integrated circuit substrate and the above-described semiconductor package of the present invention disposed on the integrated circuit substrate, and electrical connection between a solder ball of the semiconductor package and the integrated circuit substrate is provided. It has a secured configuration.
  • the integrated circuit substrate is a substrate on which an integrated circuit is configured by mounting a semiconductor package or the like.
  • a through hole and a circuit pattern are formed on an insulating base material, and an electrode portion for ensuring electrical connection between the circuit pattern and the semiconductor package is formed.
  • connection by solder balls is mainly used to form continuity in manufacturing.
  • the connection by the solder ball is a method of connecting the solder ball of the semiconductor package and the electrode part of the substrate for the integrated circuit with the solder ball. Specific conditions and the like are appropriately selected according to the specifications and application of the target integrated circuit.
  • the semiconductor package is fixed to the integrated circuit substrate by means of adhesion or the like in a state where conduction is ensured.
  • FIGS. 1 (a) to 1 (g) a wiring board having through holes and wiring patterns formed on an insulating base material was produced (note that FIG. 1 is used to explain an embodiment of the present invention). This figure is also used to explain the manufacturing procedure of the wiring board in the reference example.) Specifically, it is as follows.
  • a copper-clad laminate (3) having a copper foil (2) (thickness 12 ⁇ m) on both sides of an insulating substrate (1) (thickness 0.1 mm) (CCL-HL832HS manufactured by Mitsubishi Gas Chemical Co., Ltd.) was prepared (FIG. 1 (a)).
  • a through hole (TH) hole diameter ⁇ 100 ⁇ m
  • TH hole diameter ⁇ 100 ⁇ m
  • SE-07 half etching solution SE-07 (Mitsubishi Gas Chemical Co., Ltd.).
  • the foil (2) was etched to a thickness of 5 ⁇ m, and desmeared with an alkali swelling treatment liquid / permanganate treatment liquid (FIG. 1B).
  • a palladium catalyst was attached to the entire surface including the inside of the through hole (TH) of the copper-clad laminate (3) using an activator Neogant U (manufactured by Atotech Co., Ltd.) (0.1 mg / dm2), and printing was performed. Electroless copper plating was performed using Gantt P-DK (Atotech Co., Ltd.) to form an electroless copper plating layer (4) (thickness 1 ⁇ m) containing a palladium catalyst (FIG. 1 (c)).
  • electrolytic panel plating with copper was performed to form an electrolytic copper plating layer (5) (thickness: 15 ⁇ m) (FIG. 1 (d)).
  • a plating resist (dry film) (6) was laminated on both sides, exposed and developed using a pattern mask film, and patterning of the plating resist (dry film) (6) was performed (FIG. 1 (e)). .
  • etching was performed with a copper chloride solution to remove the electroless copper plating layer (4) and the electrolytic copper plating layer (5) in the region where the plating resist (dry film) (6) does not exist (FIG. 1 (f )).
  • the plating resist (dry film) (6) was removed with caustic soda solution to obtain a wiring board (7) in which through holes (TH) and a wiring pattern (2) were formed on the insulating base material (FIG. 1 (g)).
  • Example 1 -Fabrication of circuit boards for semiconductor packages: Using the wiring board (7) obtained by the procedure of the reference example, a semiconductor package circuit board (16) was produced as described below in accordance with the procedure shown in FIGS.
  • FIG. 2 is a diagram used to explain the embodiment of the present invention, but it is also used to explain the manufacturing procedure of the circuit board for semiconductor package in Example 1.
  • a wiring board (7) obtained by the procedure of the reference example was prepared (FIG. 2 (a)), and the surface of the electrolytic copper plating layer (5) was etched with etch bond CZ-8100 (MEC Co., Ltd.).
  • photosensitive solder resist ink PSR-4000AUS308 manufactured by Taiyo Ink Manufacturing Co., Ltd.
  • the solder resist layer (8) having a solder ball pad (9) on the solder ball mounting surface is exposed by UV exposure through a pattern mask and developed with a sodium carbonate aqueous solution to expose the wiring pattern (2).
  • An electrolytic nickel plating layer and an electrolytic gold plating layer (10) were formed on the surface of the solder ball pad (9) of the obtained solder resist layer (8) using a bus line (FIG. 2 (c)). Thereafter, blind vias (BV) (opening diameter ⁇ 50 ⁇ m, bottom diameter ⁇ 30 ⁇ m) were formed in the solder resist layer (8) on the semiconductor chip mounting surface by trepanning using a UV-YAG laser (step (2): FIG. 2 (d)).
  • BV blind vias
  • the surface of the solder resist layer (8) is roughened by applying a jet scrub process (Permis # 240, 60 seconds) (step (2 ′)), and then the entire surface is activated by an activator Neogant U (manufactured by Atotech Co., Ltd.).
  • a palladium catalyst was adhered (0.1 mg / dm 2 ), electroless copper plating was applied to the entire surface by Print Gantt P-DK (Atotech Co., Ltd.), and an electroless copper plating film (11) containing the palladium catalyst (thickness) 1 ⁇ m) was formed (step (3): FIG. 2 (e)).
  • a plating resist (dry film) (12) is laminated on both surfaces (step (3'-1)), exposed and developed using a pattern mask film, and plating on the blind via (BV) portion of the semiconductor chip mounting surface
  • the resist (dry film) (12) was removed.
  • the entire surface of the solder ball was left with a plating resist (dry film) (12) (step (3'-2): FIG. 2 (f)).
  • the surface layer connection pad (14) was formed by performing a palladium removal process by MEC Co., Ltd. (step (5): FIG. 2 (i)).
  • Electroless nickel plating 5 ⁇ m) by Nicolon GIB (Okuno Pharmaceutical Co., Ltd.
  • electroless palladium plating (0.06 ⁇ m) by Neoparabright (High Purity Chemical Co., Ltd.)
  • Gobright TWX-40 Uemura Industry Co., Ltd.
  • Electroless gold plating 0.1 ⁇ m was applied to form an electroless nickel / palladium / gold plating layer (15) (step (5 ′): FIG. 2 (j)).
  • the semiconductor package circuit board (16) was produced by the above procedure.
  • the conduction between the surface connection pads (14) connected by the wiring pattern (2) and the conduction between the surface layer connection pads (14) was verified by a conduction tester (Yokogawa Electric Corporation 7555). There was no connection failure.
  • Example 2 -Fabrication of circuit boards for semiconductor packages: Using the wiring board (7) obtained by the procedure of the reference example, a semiconductor package circuit board (18) was produced according to the procedure shown in FIGS. 3 (a) to 3 (j). Although it is a figure used to explain the embodiment, it is also used for explanation of the manufacturing procedure of the circuit board for semiconductor package in Example 2. The procedure is the same as the procedure of the first embodiment shown in FIGS. 2A to 2J except for the points described below.
  • the opening diameter of the blind via (BV) was set to 45 ⁇ m and the bottom diameter was set to 25 ⁇ m.
  • the plating resist (12) is not formed on the semiconductor chip mounting surface (S1), and only the solder ball mounting surface (S2). A plating resist (12) was formed on the substrate.
  • electroless tin plating (thickness 1.5 ⁇ m) is applied by Stanatech 2000V (manufactured by Atotech Japan Co., Ltd.) An electrolytic tin plating layer (17) was formed.
  • the connection between the surface connection pads (14) connected by the wiring pattern (2) and the connection between the surface layer connection pads (14) was verified by the same method as in Example 1, and no connection failure occurred.
  • the present invention it is possible to easily and inexpensively manufacture a semiconductor package circuit board in which surface connection pads are formed in all the blind vias without providing extra wiring such as a bus line.
  • the obtained circuit board for a semiconductor package can achieve both easy and reliable conduction when mounting a semiconductor chip and high wiring density of the semiconductor package.
  • the present invention has great applicability in the field of semiconductor packages and integrated circuits.

Abstract

(1) A solder resist is formed on a surface of a wiring substrate obtained by forming through holes and wiring patterns to an insulating substrate; (2) blind vias are formed in the solder resist on a semiconductor chip mounting side by laser, each via having a diameter of 100 μm or smaller; (3) an electroless plated coating is formed on a surface of the solder resist on the semiconductor chip mounting side having the blind vias; (4) the blind vias of the solder resist having the electroless plated coating formed on the surface thereof are subjected to via filling by electrolytic plating whereby electrolytic plated layers are formed with respect to the blind vias; and (5) the electrolytic plated layers and the electroless plated coating are removed by etching from areas other than the blind vias on the surface of the solder resist on the semiconductor chip mounting side, so that the solder resist is exposed, whereby a surface connection pad formed with the electrolytic plated layer and the electroless plated coating is formed in each blind via.

Description

半導体パッケージ用回路基板及びその製造方法Circuit board for semiconductor package and manufacturing method thereof
　本発明は、電子機器、電気機器、コンピュータ、通信機器等に用いられる回路基板に用いられる、半導体チップを搭載する半導体パッケージ用回路基板及びその製造方法に関する。 The present invention relates to a circuit board for a semiconductor package on which a semiconductor chip is mounted, which is used for a circuit board used in an electronic device, an electric device, a computer, a communication device, and the like, and a manufacturing method thereof.
　図６は、従来の半導体パッケージ用回路基板の構成の例を示す模式図である。図６に示すように、半導体パッケージ用回路基板（１００）は、絶縁性基材（１０１）にスルーホール（ＴＨ）及び配線パターン（１０２）が形成された配線基板（１０３）と、これを被覆するソルダーレジスト（１０４）とを備えて構成されるとともに、半導体チップを搭載される半導体チップ搭載面（Ｓ１）と、集積回路用基板に連結されるはんだボール搭載面（Ｓ２）を有する。半導体チップ搭載面（Ｓ１）には、ソルダーレジスト（１０４）の一部が開口されて配線パターン（１０２）の一部が露出した電極部（１０５）が形成される。はんだボール搭載面（Ｓ２）には、ソルダーレジスト（１０４）の一部が開口されて配線パターン（１０２）の一部が露出するとともに、露出した配線パターン（１０２）にはんだボールパッド（１０６）が設けられる。斯かる半導体パッケージ用回路基板（１００）は通常、配線基板（１０３）の半導体チップ搭載面（Ｓ１）及びはんだボール搭載面（Ｓ２）の両面にソルダーレジスト（１０４）を塗布・乾燥した後、パターンマスクを介してＵＶ露光し、現像して開口を形成し、当該開口に電極部（１０５）及びはんだボールパッド（１０６）を設けることにより作製される。 FIG. 6 is a schematic diagram showing an example of the configuration of a conventional circuit board for a semiconductor package. As shown in FIG. 6, a circuit board (100) for a semiconductor package covers a wiring board (103) in which through holes (TH) and a wiring pattern (102) are formed on an insulating base (101), and covers this. And a solder chip mounting surface (S2) connected to the substrate for the integrated circuit and a semiconductor chip mounting surface (S1) on which the semiconductor chip is mounted. On the semiconductor chip mounting surface (S1), an electrode part (105) in which a part of the solder resist (104) is opened and a part of the wiring pattern (102) is exposed is formed. On the solder ball mounting surface (S2), a part of the solder resist (104) is opened to expose a part of the wiring pattern (102), and a solder ball pad (106) is formed on the exposed wiring pattern (102). Provided. Such a circuit board (100) for a semiconductor package is usually obtained by applying and drying a solder resist (104) on both surfaces of the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2) of the wiring substrate (103). It is manufactured by exposing to UV through a mask, developing to form an opening, and providing an electrode portion (105) and a solder ball pad (106) in the opening.
　図７（ａ）及び（ｂ）は何れも、図６に示す半導体パッケージ用回路基板（１００）を用いた半導体パッケージの構成の例を示す模式図である。図７（ａ）及び（ｂ）に示す半導体パッケージ（９００，９００’）は、半導体パッケージ用回路基板（１００）の半導体チップ搭載面（Ｓ１）に半導体チップ（２００，２００’）を搭載し、両者を電気的に接続することにより形成される。ここで、半導体パッケージ用回路基板（１００）と半導体チップ（２００，２００’）との電気的接続の手法としては、ワイヤーボンディング、フリップチップボンディング等の手法が挙げられるが、高集積化等の目的からは、フリップチップボンディングが好ましく用いられる。図７（ａ）及び（ｂ）に示す例では、フリップチップボンディングを用いて半導体パッケージ用回路基板（１００）と半導体チップ（２００，２００’）とを電気的に接続している。フリップチップボンディングとは、半導体チップ（２００，２００’）の電極部に予め形成したバンプ（２０１，２０１’）を用い、これを半導体パッケージ用回路基板（１００）の電極部（１０５）と電気的に接続する方法である。特に、フリップチップボンディングに使用される半導体チップ搭載面（Ｓ１）の電極部（１０５）は、フリップチップバンプパッドと呼ばれる。半導体チップ（２００，２００’）のバンプ（２０１，２０１’）は、金や銅等のピラーやはんだによって形成される。図７（ａ）でははんだからなるバンプ（２０１）を有する半導体チップ（２００）を用いた例を示し、図７（ｂ）ではピラーからなるバンプ（２０１’）を有する半導体チップ（２００’）を用いた例を示している。半導体パッケージ用回路基板（１００）に半導体チップ（２００，２００’）を実装する工程では、通常、半導体チップ（２００，２００’）のバンプ（２０１，２０１’）と、半導体パッケージ用回路基板（１００）のフリップチップバンプパッド（１０５）とを接触させ、加熱などによる処理で電極部同士を接合する。更に、半導体パッケージと集積回路基板を接続する為のはんだボール（３００）が、はんだボールパッド（１０６）に取り付けられる。はんだボール（３００）の取り付けは、はんだボールパッド（１０６）にはんだボール（３００）を接触させて、加熱などによる処理で接合する方法が一般的である。 7 (a) and 7 (b) are schematic views showing an example of the configuration of a semiconductor package using the semiconductor package circuit board (100) shown in FIG. The semiconductor package (900, 900 ′) shown in FIGS. 7A and 7B has the semiconductor chip (200, 200 ′) mounted on the semiconductor chip mounting surface (S1) of the circuit board for semiconductor package (100). It is formed by electrically connecting the two. Here, as a method of electrical connection between the semiconductor package circuit board (100) and the semiconductor chip (200, 200 ′), wire bonding, flip chip bonding, and the like can be cited. From the above, flip chip bonding is preferably used. In the example shown in FIGS. 7A and 7B, the semiconductor package circuit board (100) and the semiconductor chip (200, 200 ') are electrically connected using flip chip bonding. In the flip chip bonding, bumps (201, 201 ′) formed in advance on the electrode portions of the semiconductor chip (200, 200 ′) are used and electrically connected to the electrode portions (105) of the circuit board (100) for the semiconductor package. Is a way to connect. In particular, the electrode part (105) of the semiconductor chip mounting surface (S1) used for flip chip bonding is called a flip chip bump pad. The bumps (201, 201 ') of the semiconductor chip (200, 200') are formed by a pillar such as gold or copper or solder. FIG. 7A shows an example using a semiconductor chip (200) having bumps (201) made of solder, and FIG. 7 (b) shows a semiconductor chip (200 ′) having bumps (201 ′) made of pillars. The example used is shown. In the process of mounting the semiconductor chip (200, 200 ′) on the semiconductor package circuit board (100), the bumps (201, 201 ′) of the semiconductor chip (200, 200 ′) and the semiconductor package circuit board (100) are usually mounted. ) Flip-chip bump pads (105) are brought into contact with each other, and the electrode portions are bonded together by a treatment such as heating. Further, solder balls (300) for connecting the semiconductor package and the integrated circuit board are attached to the solder ball pads (106). The solder ball (300) is generally attached by bringing the solder ball (300) into contact with the solder ball pad (106) and joining them by a process such as heating.
　近年、半導体チップ（２００，２００’）の微細化に伴い、半導体チップ（２００，２００’）の電極の数が増加し、電極に形成するバンプ（２０１，２０１’）も高密度化かつ小型化するなど、半導体チップ（２００，２００’）の高密度実装に向けた動きが拡がっている。しかし、ソルダーレジスト（１０４）を塗布・乾燥した後、パターンマスクを介してＵＶ露光し、現像してソルダーレジスト（１０４）の一部を開口し、半導体パッケージ用回路基板（１００）のフリップチップバンプパッド（１０５）を形成する方法では、小径のフリップチップバンプパッド（１０５）を高密度に形成しようとした場合、正常に露光できない課題や、現像時に使用する薬液が小径のフリップチップバンプパッド（１０５）内に入り込みづらく、現像し切れずソルダーレジスト残渣となり実装時に導通不良となってしまう等の課題がある。また、開口が形成できたとしても、半導体チップ搭載面（Ｓ１）のソルダーレジスト（１０４）表面とフリップチップバンプパッド（１０５）の接続面との間にソルダーレジスト（１０４）厚さ分の高さの差が生じてしまう等の課題があり、高密度での実装に対応できない懸念がある。 In recent years, with the miniaturization of the semiconductor chip (200, 200 ′), the number of electrodes of the semiconductor chip (200, 200 ′) is increased, and the bumps (201, 201 ′) formed on the electrodes are also increased in density and size. For example, the movement toward high-density mounting of semiconductor chips (200, 200 ′) is expanding. However, after applying and drying the solder resist (104), UV exposure is performed through a pattern mask, development is performed to open a part of the solder resist (104), and the flip chip bump of the circuit board for semiconductor package (100) In the method of forming the pad (105), when the small-diameter flip chip bump pad (105) is to be formed at a high density, there are problems that cannot be normally exposed, and the chemical solution used during development is a small-diameter flip chip bump pad (105). ) Is difficult to enter, and cannot be completely developed, resulting in a solder resist residue, resulting in poor conduction during mounting. Even if the opening can be formed, the height corresponding to the thickness of the solder resist (104) between the surface of the solder resist (104) on the semiconductor chip mounting surface (S1) and the connection surface of the flip chip bump pad (105). There is a problem that a difference between the two may occur, and there is a concern that the mounting at a high density cannot be supported.
　斯かる課題を解決するために、埋め込みバンプを有する半導体パッケージ用回路基板が提案され、一部実用化されている。図８は、埋め込みバンプを有する半導体パッケージ用回路基板（１００”）の構成の例を示す模式図であり、図９は、図８の半導体パッケージ用回路基板（１００”）を用いた半導体パッケージ（９００”）の構成の例を示す模式図である。図８の半導体パッケージ用回路基板（１００”）は、フリップチップバンプパッド（１０５）上に電解めっきで埋め込みバンプ（１０７）が形成されており、その接続面がソルダーレジスト（１０４）表面と同等又はより高い位置に設定されている。斯かる埋め込みバンプ（１０７）を設けることにより、図９に示すように、半導体チップ（２００’）の実装時に容易且つ確実に、半導体チップ（２００’）のバンプ（２０１’）との導通を確保した半導体パッケージ（９００”）とすることができる。なお、図９ではピラーからなるバンプ（２０１’）を有する半導体チップ（２００’）を用いた例を示しているが、図７（ａ）のようにはんだからなるバンプ（２０１）を有する半導体チップ（２００）を用いる場合も、その構成は同様である。 In order to solve such a problem, a circuit board for a semiconductor package having embedded bumps has been proposed and partially put into practical use. FIG. 8 is a schematic view showing an example of the configuration of a semiconductor package circuit board (100 ″) having embedded bumps, and FIG. 9 is a semiconductor package (100 ″) using the semiconductor package circuit board (100 ″) of FIG. 900 "). The semiconductor package circuit board (100") of FIG. 8 has a bump (107) formed by electrolytic plating on a flip chip bump pad (105). The connecting surface is set at a position equal to or higher than the surface of the solder resist (104). By providing such an embedded bump (107), as shown in FIG. 9, it is ensured easily and reliably that the semiconductor chip (200 ′) is electrically connected to the bump (201 ′) as shown in FIG. FIG. 9 shows an example in which a semiconductor chip (200 ′) having bumps (201 ′) made of pillars is used, but FIG. Thus, when using the semiconductor chip (200) having the bump (201) made of solder, the configuration is the same.
　埋め込みバンプ（１０７）を形成するためには、半導体パッケージ用回路基板（１００）のフリップチップバンプパッド（１０５）に、電解めっき用の電流を供給することが必要となる。斯かる給電の手法としては、図１０（ａ）に示すように、半導体パッケージ用回路基板（１００Ａ）の半導体搭載面（Ｓ１）側の配線回路に、電解めっき用のバスライン（１０８）を予め配置しておく手法が挙げられる（例えば特許文献１（特開昭５２－１２５７５）等）。バスライン（１０８）とは、半導体パッケージ用回路基板（１００Ａ）の所定位置のフリップチップバンプパッド（１０５）に、電解めっきに必要な電流を供給するためのワークパネル内配線のことである。しかし、斯かるバスライン（１０８）は、電解めっきによる埋め込みバンプ（１０７）の形成時にしか使用されず、半導体パッケージ用回路基板（１００Ａ）の完成後には不要となってしまう。斯かる余分なバスライン（１０８）の存在は、配線の高密度化において大きな妨げとなる。また、半導体パッケージ用回路基板（１００Ａ）の完成後にバスライン（１０８）をレーザー等の手段により除去することも考えられるが、全てを除去することは難しく、残存したバスライン（１０８）が半導体パッケージの動作に悪影響を与えてしまうという課題もある。また、バスラインを事後的に除去しても、除去後の領域を配線形成に使用できる訳ではないため、配線密度の低下は避けられない。 In order to form the embedded bump (107), it is necessary to supply a current for electrolytic plating to the flip chip bump pad (105) of the circuit board (100) for the semiconductor package. As such a power feeding method, as shown in FIG. 10A, an electroplating bus line (108) is previously provided on the wiring circuit on the semiconductor mounting surface (S1) side of the circuit board for semiconductor package (100A). There is a method of arranging them (for example, Patent Document 1 (Japanese Patent Laid-Open No. 52-12575)). The bus line (108) is a wiring in the work panel for supplying a current necessary for electrolytic plating to the flip chip bump pad (105) at a predetermined position of the circuit board for semiconductor package (100A). However, such a bus line (108) is used only when the embedded bump (107) is formed by electrolytic plating, and becomes unnecessary after the completion of the semiconductor package circuit board (100A). The existence of such an extra bus line (108) greatly hinders the increase in wiring density. Although it is conceivable to remove the bus line (108) by means of a laser or the like after the completion of the semiconductor package circuit board (100A), it is difficult to remove all of the bus line (108). There is also a problem of adversely affecting the operation. Further, even if the bus line is removed afterwards, the area after removal cannot be used for wiring formation, and therefore the reduction in wiring density is inevitable.
　斯かる課題を解決するため、半導体チップ搭載面（Ｓ１）にバスラインを形成せず、図１０（ｂ）に示すように、はんだボール搭載面（Ｓ２）に給電用の無電解銅めっき被膜（１０９）を形成し、これを給電層として用いることにより、はんだボールパッド（１０６）と（配線パターン（１０２）を介して）電気的に接続されたフリップチップバンプパッド（１０５）に電流を供給し、電解めっきで埋め込みバンプ（１０７）を形成した半導体パッケージ用回路基板（１００Ｂ）も検討されている（例えば特許文献２（特開２０１１－６１１７９）等）。しかし、この手法では、はんだボール搭載面（Ｓ２）のはんだボールパッド（１０６）と電気的に接続された（即ち、半導体チップ搭載面（Ｓ１）とはんだボール搭載面（Ｓ２）とを接続する配線パターン（１０２）に連結された）フリップチップバンプパッド（１０５ａ）にしか電流を供給できないため、はんだボールパッド（１０６）と電気的に接続されていない（即ち、半導体チップ搭載面（Ｓ１）同士を接続する配線パターン（１０２）に連結された）フリップチップバンプパッド（１０５ｂ）には電流を供給できず、埋め込みバンプ（１０７）を形成できないという課題がある。 In order to solve such a problem, a bus line is not formed on the semiconductor chip mounting surface (S1), and an electroless copper plating film for feeding (on the solder ball mounting surface (S2) (see FIG. 10B). 109) and using this as a power supply layer, current is supplied to the solder ball pad (106) and the flip chip bump pad (105) electrically connected (via the wiring pattern (102)). Also, a circuit board (100B) for a semiconductor package in which embedded bumps (107) are formed by electrolytic plating has been studied (for example, Patent Document 2 (Japanese Patent Laid-Open No. 2011-61179)). However, in this method, the wiring that is electrically connected to the solder ball pad (106) on the solder ball mounting surface (S2) (that is, the wiring that connects the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2)). Since current can only be supplied to the flip chip bump pads (105a) connected to the pattern (102), they are not electrically connected to the solder ball pads (106) (that is, the semiconductor chip mounting surfaces (S1) are connected to each other). There is a problem that current cannot be supplied to the flip chip bump pad (105b) connected to the wiring pattern (102) to be connected, and the embedded bump (107) cannot be formed.
特開昭５２－１２５７５号公報JP 52-12575 A 特開２０１１－６１１７９号公報JP 2011-611179 A
　上記背景から、バスライン等の余剰な配線を設けることなく、全てのブラインドビア内に簡便且つ確実に、半導体チップとの導通を容易にする電極部を形成することが求められてきた。 From the above background, it has been required to easily and reliably form an electrode portion that facilitates conduction with a semiconductor chip in all blind vias without providing excessive wiring such as a bus line.
　本発明は斯かる課題に鑑みてなされたもので、バスライン等の余剰な配線を設けることなく、全てのブラインドビア内に簡便且つ確実に、半導体チップとの導通を容易にする電極部を形成することが可能な、優れた半導体パッケージ用回路基板の製造方法を提供するとともに、半導体チップ実装時の容易且つ確実な導通確保と、半導体パッケージの配線高密度化とを共に達成可能な、優れた半導体パッケージ用回路基板を提供することを目的とする。 The present invention has been made in view of such a problem, and without providing excessive wiring such as a bus line, an electrode portion that facilitates conduction with a semiconductor chip is easily and reliably formed in all the blind vias. In addition to providing an excellent method for manufacturing a circuit board for a semiconductor package, it is possible to achieve both easy and reliable conduction when mounting a semiconductor chip and high wiring density of a semiconductor package. An object is to provide a circuit board for a semiconductor package.
　本発明者等は、上記課題に鑑み鋭意検討の結果、レーザーを用いてブラインドビアを小径化するとともに、半導体チップ搭載面に無電解めっき被膜を形成して電解めっき用の電流を供給し、且つ、ビアフィリング電解めっきによって表層接続パッドを形成することにより、バスライン等の余剰な配線を設けることなく、全てのブラインドビア内に簡便且つ確実に表層接続パッドを形成し、半導体チップとの導通を確保することが可能となるとともに、半導体パッケージの配線高密度化も達成でき、上記課題が解決できることを見出し、本発明に想到した。 As a result of intensive studies in view of the above problems, the present inventors reduced the diameter of the blind via using a laser, formed an electroless plating film on the semiconductor chip mounting surface, and supplied an electric current for electrolytic plating, and By forming the surface connection pads by via filling electroplating, the surface connection pads can be easily and reliably formed in all the blind vias without providing extra wiring such as bus lines, and electrical connection with the semiconductor chip is achieved. As a result, the present inventors have found that the above-mentioned problems can be solved by increasing the wiring density of the semiconductor package.
　即ち、本発明の要旨は、半導体チップ搭載面及びはんだボール搭載面を有する半導体パッケージ用回路基板を製造する方法であって、
（１）絶縁性基材にスルーホール及び配線パターンが形成されてなる配線基板の表面に、ソルダーレジストを形成する工程、
（２）前記（１）で形成された半導体チップ搭載面側のソルダーレジストに対して、レーザーにより穴径１００μｍ以下のブラインドビアを形成する工程、
（３）前記（２）で形成されたブラインドビアを有する半導体チップ搭載面側のソルダーレジスト表面に、無電解めっき被膜を形成する工程、
（４）前記（３）で表面に無電解めっき被膜を形成されたソルダーレジストのブラインドビアに対して、電解めっきによりビアフィリングを行い、電解めっき層を形成する工程、及び、
（５）半導体チップ搭載面側のソルダーレジスト表面のブラインドビア以外の部分について、前記（４）で形成された電解めっき層、及び、前記（３）で形成された無電解めっき被膜をエッチングにより除去し、ソルダーレジストを露出させることにより、ブラインドビア内に電解めっき層及び無電解めっき被膜からなる表層接続パッドを形成する工程、
を有する方法に存する。 That is, the gist of the present invention is a method of manufacturing a circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface,
(1) A step of forming a solder resist on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material;
(2) A step of forming a blind via having a hole diameter of 100 μm or less by a laser with respect to the solder resist on the semiconductor chip mounting surface side formed in (1),
(3) A step of forming an electroless plating film on the solder resist surface on the semiconductor chip mounting surface side having the blind via formed in (2),
(4) A step of forming an electroplating layer by performing via filling by electrolytic plating on a solder resist blind via having an electroless plating film formed on the surface thereof in (3), and
(5) For portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side, the electrolytic plating layer formed in the above (4) and the electroless plating film formed in the above (3) are removed by etching. And, by exposing the solder resist, forming a surface connection pad made of an electrolytic plating layer and an electroless plating film in the blind via,
The method has the following.
　また、本発明の別の要旨は、上記の方法で製造された半導体パッケージ用回路基板に存する。 Further, another gist of the present invention resides in a circuit board for a semiconductor package manufactured by the above method.
　また、本発明の別の要旨は、半導体チップ搭載面及びはんだボール搭載面を有する半導体パッケージ用回路基板であって、
（ａ）絶縁性基材にスルーホール及び配線パターンが形成されてなる配線基板と、
（ｂ）配線基板の表面に形成され、半導体チップ搭載面及びはんだボール搭載面の各々に複数のブラインドビアを有するソルダーレジストと、
（ｃ）半導体チップ搭載面の複数のブラインドビアに設けられ、配線パターンと導通してなる複数の表層接続パッドと、
（ｄ）はんだボール搭載面の複数のブラインドビアに設けられ、配線パターンと導通してなる複数のはんだボールパッドとを備え、且つ、
（ｉ）表層接続パッドの少なくとも一部が、はんだボールパッドと導通していない配線パターンと導通してなるとともに、
（ii）半導体パッケージ用基板の製造に使用されるが配線パターンとしては使用されない、バスラインを有さない
ことを特徴とする、半導体パッケージ用回路基板に存する。 Another gist of the present invention is a circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface,
(A) a wiring board in which through holes and wiring patterns are formed on an insulating substrate;
(B) a solder resist formed on the surface of the wiring board and having a plurality of blind vias on each of the semiconductor chip mounting surface and the solder ball mounting surface;
(C) a plurality of surface layer connection pads provided in the plurality of blind vias on the semiconductor chip mounting surface and connected to the wiring pattern;
(D) provided with a plurality of blind vias on the solder ball mounting surface, and provided with a plurality of solder ball pads connected to the wiring pattern; and
(I) At least a part of the surface layer connection pad is electrically connected to a wiring pattern that is not electrically connected to the solder ball pad,
(Ii) The present invention resides in a semiconductor package circuit board, which is used for manufacturing a semiconductor package substrate but is not used as a wiring pattern and does not have a bus line.
　また、本発明の別の要旨は、上記の半導体パッケージ用回路基板と、半導体パッケージ用回路基板の半導体チップ搭載面に設けられる半導体チップとを備え、前記半導体パッケージ用回路基板のはんだボールパッドにはんだボールが設けられ、前記半導体パッケージ用回路基板の表層接続パッドと前記半導体チップとの導通が確保された、半導体パッケージに存する。 Another gist of the present invention is the semiconductor package circuit board described above, and a semiconductor chip provided on a semiconductor chip mounting surface of the semiconductor package circuit board, and soldered to a solder ball pad of the semiconductor package circuit board. In the semiconductor package, a ball is provided and electrical connection between the surface layer connection pad of the circuit board for semiconductor package and the semiconductor chip is ensured.
　また、本発明の別の要旨は、集積回路用基板と、前記集積回路用基板上に配置された上記の半導体パッケージとを備え、前記半導体パッケージのはんだボールと前記集積回路用基板との導通が確保された、集積回路に存する。 Another gist of the present invention includes an integrated circuit substrate and the semiconductor package disposed on the integrated circuit substrate, wherein conduction between the solder balls of the semiconductor package and the integrated circuit substrate is provided. Remains in a secured, integrated circuit.
　本発明の半導体パッケージ用回路基板の製造方法によれば、バスライン等の余剰な配線を設けることなく、全てのブラインドビア内に簡便且つ確実に表層接続パッドを形成し、半導体チップとの導通を確保することができる。また、半導体チップとの導通を損なうことなく、レーザーによってブラインドビアを小径化でき、半導体パッケージの配線高密度化にも寄与し得る。 According to the method for manufacturing a circuit board for a semiconductor package of the present invention, surface layer connection pads are easily and surely formed in all the blind vias without providing excessive wiring such as bus lines, and electrical connection with the semiconductor chip is achieved. Can be secured. Moreover, the diameter of the blind via can be reduced by the laser without impairing the conduction with the semiconductor chip, which can contribute to the high density wiring of the semiconductor package.
　また、本発明の半導体パッケージ用回路基板は、半導体チップ実装時の容易且つ確実な導通確保と、半導体パッケージの配線高密度化とを共に達成可能な、優れた半導体パッケージ用回路基板であり、半導体パッケージ及び集積回路の作製に好適に使用できる。 The circuit board for a semiconductor package of the present invention is an excellent circuit board for a semiconductor package capable of achieving both easy and reliable conduction when mounting a semiconductor chip and high wiring density of the semiconductor package. It can be suitably used for manufacturing packages and integrated circuits.
図１（ａ）～（ｇ）は、絶縁性基材にスルーホール及び配線パターンが形成された配線基板の製造手順を示すフローチャートである。また、参考例における配線基板の製造手順の説明にも流用する。FIGS. 1A to 1G are flowcharts showing a manufacturing procedure of a wiring board in which through holes and wiring patterns are formed on an insulating base material. In addition, it is also used for explanation of the manufacturing procedure of the wiring board in the reference example. 図２（ａ）～（ｆ）は、本発明の一実施形態に係る半導体パッケージ用回路基板の製造手順を示すフローチャートである。また、実施例１における半導体パッケージ用回路基板の製造手順の説明にも流用する。2 (a) to 2 (f) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to an embodiment of the present invention. Further, the description will be applied to the description of the manufacturing procedure of the semiconductor package circuit board in the first embodiment. 図２（ｇ）～（ｊ）は、本発明の一実施形態に係る半導体パッケージ用回路基板の製造手順を示すフローチャートである。また、実施例１における半導体パッケージ用回路基板の製造手順の説明にも流用する。2 (g) to 2 (j) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to an embodiment of the present invention. Further, the description will be applied to the description of the manufacturing procedure of the semiconductor package circuit board in the first embodiment. 図３（ａ）～（ｆ）は、本発明の別の実施形態に係る半導体パッケージ用回路基板の製造手順を示すフローチャートである。また、実施例２における半導体パッケージ用回路基板の製造手順の説明にも流用する。FIGS. 3A to 3F are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to another embodiment of the present invention. Also, the description will be made for the description of the manufacturing procedure of the circuit board for semiconductor package in the second embodiment. 図３（ｇ）～（ｊ）は、本発明の別の実施形態に係る半導体パッケージ用回路基板の製造手順を示すフローチャートである。また、実施例２における半導体パッケージ用回路基板の製造手順の説明にも流用する。3 (g) to 3 (j) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to another embodiment of the present invention. Also, the description will be made for the description of the manufacturing procedure of the circuit board for semiconductor package in the second embodiment. 図４は、本発明の半導体パッケージ用回路基板の構成の例を示す模式図である。FIG. 4 is a schematic diagram showing an example of the configuration of the circuit board for a semiconductor package of the present invention. 図５（ａ１）及び（ａ２）は夫々、実施例１で作製された半導体パッケージ用回路基板（１６）の表層接続パッド（１４）領域のＳＥＭ表面写真及び光学断面写真であり、図５（ｂ１）及び（ｂ２）は夫々、実施例２で作製された半導体パッケージ用回路基板（１８）の表層接続パッド（１４）領域のＳＥＭ表面写真及び光学断面写真である。FIGS. 5A1 and 5A2 are an SEM surface photograph and an optical cross-sectional photograph of the surface layer connection pad 14 region of the semiconductor package circuit board 16 fabricated in Example 1, respectively. ) And (b2) are an SEM surface photograph and an optical cross-sectional photograph of the surface layer connection pad (14) region of the semiconductor package circuit board (18) fabricated in Example 2, respectively. 図６は、従来の半導体パッケージ用回路基板の構成の例を示す模式図である。FIG. 6 is a schematic diagram showing an example of the configuration of a conventional circuit board for a semiconductor package. 図７（ａ）及び（ｂ）は何れも、図６の半導体パッケージ用回路基板を用いた半導体パッケージの構成の例を示す模式図である。FIGS. 7A and 7B are schematic views showing an example of the configuration of a semiconductor package using the semiconductor package circuit board of FIG. 図８は、従来の埋め込みバンプを有する半導体パッケージ用回路基板の構成の例を示す模式図である。FIG. 8 is a schematic diagram showing an example of the configuration of a circuit board for a semiconductor package having a conventional embedded bump. 図９は、図８の従来の埋め込みバンプを有する半導体パッケージ用回路基板を用いた半導体パッケージの構成の例を示す模式図である。FIG. 9 is a schematic diagram showing an example of the configuration of a semiconductor package using the conventional circuit board for a semiconductor package having embedded bumps shown in FIG. 図１０（ａ）及び（ｂ）は何れも、従来の埋め込みバンプの形成法を説明するための図である。FIGS. 10A and 10B are diagrams for explaining a conventional method of forming embedded bumps.
［半導体パッケージ用回路基板の製造方法］
　本発明の一側面は、ブラインドビア内に表層接続パッドを有する半導体パッケージ用回路基板の製造方法に関する。 [Method of Manufacturing Circuit Board for Semiconductor Package]
One aspect of the present invention relates to a method of manufacturing a circuit board for a semiconductor package having a surface layer connection pad in a blind via.
　上述のように、従来、半導体パッケージ用回路基板のフリップチップバンプパッド上に、電解めっきにより埋め込みバンプを形成する手法としては、半導体搭載面側の配線回路に予め配置されたバスラインを通じて直接、フリップチップバンプパッドに電流を供給し、これを用いて電解めっきにより埋め込みバンプを形成する手法（図１０（ａ）：特許文献１（特開昭５２－１２５７５）等）や、はんだボール搭載面に形成した無電解めっき被膜から、はんだボールパッド及び配線パターンを介して、フリップチップバンプパッドに電流を供給し、これを用いて電解めっきにより埋め込みバンプを形成する手法（図１０（ｂ）：特許文献２（特開２０１１－６１１７９）等）が存在した。 As described above, conventionally, as a method of forming embedded bumps on a flip chip bump pad of a circuit board for a semiconductor package by electrolytic plating, a flip is directly performed through a bus line arranged in advance on a wiring circuit on a semiconductor mounting surface side. A method of supplying a current to a chip bump pad and using this to form a buried bump by electrolytic plating (FIG. 10 (a): Patent Document 1 (Japanese Patent Laid-Open No. 52-12575), etc.) or forming on a solder ball mounting surface A method of supplying current from the electroless plating film to the flip chip bump pad via the solder ball pad and the wiring pattern, and using this to form a buried bump by electrolytic plating (FIG. 10B: Patent Document 2) (Japanese Patent Laid-Open No. 2011-61179).
　しかし、前者の既設バスラインを給電に用いる手法では、電解めっきによる埋め込みバンプ形成時にしか使用されず、半導体パッケージ用回路基板の完成後には不要となる余分なバスラインを設ける必要があるため、配線高密度化の大きな妨げとなるのに加えて、半導体パッケージ用回路基板の完成後にバスラインをレーザー等の手段により除去しようとしても、全てを除去することは難しく、半導体パッケージ用回路基板の完成後に残存するバスラインが半導体パッケージの動作に悪影響を与えてしまう、という課題があった。 However, in the former method using the existing bus line for power supply, it is used only when forming embedded bumps by electrolytic plating, and it is necessary to provide an unnecessary bus line after the completion of the circuit board for semiconductor package. In addition to greatly hindering high density, it is difficult to remove all the bus lines by means such as laser after the completion of the semiconductor package circuit board. There is a problem that the remaining bus line adversely affects the operation of the semiconductor package.
　また、後者のはんだボール搭載面に形成された無電解めっき被膜を給電に用いる手法では、はんだボールパッドと電気的に接続された（即ち、半導体チップ搭載面とはんだボール搭載面とを接続する配線パターンに連結された）フリップチップバンプパッドにしか電流を供給できないため、はんだボールパッドと電気的に接続されていない（即ち、半導体チップ搭載面同士を接続する配線パターンに連結された）フリップチップバンプパッドには埋め込みバンプを形成できない、という課題があった。 In the latter method using the electroless plating film formed on the solder ball mounting surface for feeding, the solder ball pad is electrically connected (that is, the wiring connecting the semiconductor chip mounting surface and the solder ball mounting surface). Since the current can be supplied only to the flip chip bump pad (connected to the pattern), the flip chip bump is not electrically connected to the solder ball pad (that is, connected to the wiring pattern connecting the semiconductor chip mounting surfaces). There was a problem that embedded pads could not be formed on the pads.
　これに対して、本発明の半導体パッケージ用回路基板の製造方法によれば、半導体チップ搭載面に形成した無電解めっき被膜から直接、ブラインドビア内に露出した配線パターン上に電解めっき用の電流を供給し、これを用いて電解めっきによるビアフィリングを行う。これにより、レーザー形成された小径のブラインドビアについても、余剰バスライン配設による弊害を防ぎつつ、（はんだボールパッドとの電通の有無を問わず）全てのブラインドビア内に、半導体パッケージとの導通を確保するための表層接続パッドを、簡便且つ確実に形成することができ、半導体パッケージの配線高密度化に寄与し得る。 In contrast, according to the method for manufacturing a circuit board for a semiconductor package of the present invention, the current for electrolytic plating is directly applied to the wiring pattern exposed in the blind via from the electroless plating film formed on the semiconductor chip mounting surface. This is used to perform via filling by electrolytic plating. As a result, even with laser-formed small-diameter blind vias, conduction to the semiconductor package is possible in all blind vias (regardless of whether or not there is electrical communication with the solder ball pads), while preventing the harmful effects of surplus bus lines. The surface layer connection pad for ensuring the resistance can be easily and reliably formed, and can contribute to the high density wiring of the semiconductor package.
　具体的に、本発明の半導体パッケージ用回路基板の製造方法は、以下の工程を備える。なお、冒頭に「＊」を示す工程は、任意の工程である。
（１）絶縁性基材にスルーホール及び配線パターンが形成されてなる配線基板の表面に、ソルダーレジストを形成する工程。
（２）前記（１）で形成された半導体チップ搭載面側のソルダーレジストに対して、レーザーにより穴径１００μｍ以下のブラインドビアを形成する工程。
＊（２’）前記（２）で形成されたブラインドビアを有するソルダーレジストに対して表面粗化処理を施す工程。
（３）前記（２）で形成されたブラインドビアを有する半導体チップ搭載面側のソルダーレジスト表面に、無電解めっき被膜を形成する工程。
＊（３’－１）前記（３）で表面に無電解めっき被膜を形成されたソルダーレジストを有する配線基板の両面に、めっきレジストを形成する工程。
＊（３’－２）前記（３’－１）で形成されためっきレジストに対して、少なくとも半導体チップ搭載面側のソルダーレジストのブラインドビアが露出するように、開口部を形成する工程。
（４）前記（３）で表面に無電解めっき被膜を形成されたソルダーレジストのブラインドビアに対して、電解めっきによりビアフィリングを行い、電解めっき層を形成する工程。
＊（４’）前記（３’－１）で形成されためっきレジストを除去する工程。
（５）半導体チップ搭載面側のソルダーレジスト表面のブラインドビア以外の部分について、前記（４）で形成された電解めっき層、及び、前記（３）で形成された無電解めっき被膜をエッチングにより除去し、ソルダーレジストを露出させることにより、ブラインドビア内に電解めっき層及び無電解めっき被膜からなる表層接続パッドを形成する工程。
＊（５’）前記（５）のエッチング後におけるブラインドビア内の表層接続パッドに表面処理を施す工程。 Specifically, the method for manufacturing a circuit board for a semiconductor package of the present invention includes the following steps. In addition, the process which shows "*" at the beginning is an arbitrary process.
(1) A step of forming a solder resist on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
(2) A step of forming a blind via having a hole diameter of 100 μm or less by laser with respect to the solder resist on the semiconductor chip mounting surface side formed in (1).
* (2 ′) A step of subjecting the solder resist having the blind via formed in (2) to a surface roughening treatment.
(3) A step of forming an electroless plating film on the surface of the solder resist on the semiconductor chip mounting surface side having the blind via formed in (2).
* (3′-1) A step of forming a plating resist on both surfaces of a wiring board having a solder resist having an electroless plating film formed on the surface in (3).
* (3′-2) A step of forming an opening so that at least the blind via of the solder resist on the semiconductor chip mounting surface side is exposed to the plating resist formed in (3′-1).
(4) A step of forming an electroplating layer by performing via filling by electrolytic plating on the solder resist blind via having the electroless plating film formed on the surface in (3).
* (4 ′) A step of removing the plating resist formed in (3′-1).
(5) For portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side, the electrolytic plating layer formed in the above (4) and the electroless plating film formed in the above (3) are removed by etching. And forming a surface layer connection pad made of an electrolytic plating layer and an electroless plating film in the blind via by exposing the solder resist.
* (5 ′) A step of performing a surface treatment on the surface layer connection pad in the blind via after the etching in (5).
　以下、本発明の製造方法に用いられる配線基板について説明した上で、本発明の製造方法の各工程について説明する。
　なお、半導体パッケージ用回路基板は、図６等に示すように、半導体チップを搭載される半導体チップ搭載面（Ｓ１）と、集積回路用基板に連結されるはんだボール搭載面（Ｓ２）とを有する。以下の記載では、本発明の製造方法に用いられる配線基板、及びその途中工程で得られる積層体についても、最終的に作製される半導体パッケージ用回路基板との対応に基づいて、各面を夫々半導体チップ搭載面（Ｓ１）及びはんだボール搭載面（Ｓ２）というものとする。 Hereinafter, after explaining the wiring board used in the manufacturing method of the present invention, each step of the manufacturing method of the present invention will be described.
The semiconductor package circuit board has a semiconductor chip mounting surface (S1) on which a semiconductor chip is mounted and a solder ball mounting surface (S2) connected to the integrated circuit substrate, as shown in FIG. . In the following description, each surface of the wiring board used in the manufacturing method of the present invention and the laminated body obtained in the intermediate process are also described based on the correspondence with the finally produced semiconductor package circuit board. The semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2) are assumed.
・配線基板：
　本発明の製造方法に用いられる配線基板は、絶縁性基材にスルーホール及び配線パターンが形成されたものである。
　絶縁性基材の材料としては、従来の半導体パッケージ等に使用される任意の絶縁性材料が使用できる。例としては、エポキシ樹脂、シアネート樹脂、ビスマレイミドトリアジン樹脂、ポリアミド樹脂、ポリイミド樹脂、ポリエステル樹脂、ポリフェニレンエーテル樹脂等の有機材料、Ｅガラス、Ｄガラス、Ｓガラス、Ｔガラス、ＮＥガラス、クォーツ等の無機材料等が挙げられる。これらの材料は一種を単独で用いてもよく、二種以上を任意の組み合わせで用いてもよい。絶縁性基材の形態としては、織布、不織布、ロービング、チョップドストランドマット、サーフェシングマット等が挙げられる。絶縁性基材の形状としては、板状、フィルム状等が挙げられる。絶縁性基材の厚さは任意であり、用途や構成等に応じて適宜選択すればよいが、通常１０μｍ以上、中でも２０μｍ以上の範囲が好適である。 ・ Wiring board:
The wiring board used in the manufacturing method of the present invention is one in which through holes and wiring patterns are formed on an insulating base material.
As an insulating base material, any insulating material used in conventional semiconductor packages or the like can be used. Examples include organic materials such as epoxy resin, cyanate resin, bismaleimide triazine resin, polyamide resin, polyimide resin, polyester resin, polyphenylene ether resin, E glass, D glass, S glass, T glass, NE glass, quartz, etc. An inorganic material etc. are mentioned. One of these materials may be used alone, or two or more thereof may be used in any combination. Examples of the form of the insulating substrate include woven fabric, nonwoven fabric, roving, chopped strand mat, and surfacing mat. Examples of the shape of the insulating substrate include a plate shape and a film shape. The thickness of the insulating base material is arbitrary and may be appropriately selected depending on the application, configuration, etc., but a range of usually 10 μm or more, particularly 20 μm or more is preferable.
　斯かる絶縁性基材にスルーホール及び配線パターンを形成することにより、本発明の製造方法に用いられる配線基板が作製される。スルーホールの形成には、従来公知の任意の手法が用いられ、例としてはメカニカルドリルによる手法、レーザーによる手法が挙げられる。配線パターンの形成にも、従来公知の任意の手法が用いられ、例としてはサブトラクティブ法（パネルメッキ・エッチング法）、パターンメッキ法（極薄金属箔を基礎金属とする手法）、セミアディティブ法（絶縁基材上に無電解金属を付着させ基礎金属とする方法）が挙げられるが、これらに限定されるものではない。配線パターンの元となる導電性材料は特に限定されないが、通常は銅やアルミニウム等の金属、好ましくは銅が用いられる。また、通常はスルーホール内部表面にも金属層を形成することにより、必要な表裏の導通が確保される。 By forming a through hole and a wiring pattern in such an insulating base material, a wiring substrate used in the manufacturing method of the present invention is manufactured. For forming the through hole, any conventionally known method is used, and examples thereof include a mechanical drill method and a laser method. Arbitrary known methods are also used to form wiring patterns. Examples include subtractive methods (panel plating and etching methods), pattern plating methods (methods based on ultrathin metal foils), and semi-additive methods. (Method of attaching an electroless metal on an insulating base material to form a base metal) is not limited thereto. The conductive material from which the wiring pattern is based is not particularly limited, but usually a metal such as copper or aluminum, preferably copper is used. Further, usually, the necessary conduction between the front and back sides is ensured by forming a metal layer on the inner surface of the through hole.
　中でも、配線基板の作製法としては、絶縁性基材の片面又は両面に金属箔又は金属フィルムが積層された金属張積層板を用い、或いは必要に応じてこれを複数枚積層した多層積層板等を用い、これにスルーホール形成工程及び配線パターン形成工程を施すことによる手法が好ましい。金属箔又は金属フィルムとしては、例えば銅やアルミニウム等の金属箔又は金属フィルム、好ましくは銅箔又は銅フィルムが挙げられる。特に電解銅箔、圧延銅箔、銅合金フィルム等が好適である。金属箔又は金属フィルムには、例えばニッケル処理やコバルト処理等、公知の表面処理が施されていてもよい。金属箔又は金属フィルムの厚さは任意であり、用途や構成等に応じて適宜選択すればよいが、通常１μｍ以上、中でも１０μｍ以上の範囲が好適である。 Among them, as a method for producing a wiring board, a metal-clad laminate in which a metal foil or a metal film is laminated on one side or both sides of an insulating substrate, or a multilayer laminate in which a plurality of the laminates are laminated as necessary, etc. The method by which a through-hole formation process and a wiring pattern formation process are given to this is preferable. As metal foil or a metal film, metal foil or metal films, such as copper and aluminum, for example, Preferably copper foil or a copper film is mentioned. In particular, electrolytic copper foil, rolled copper foil, copper alloy film and the like are suitable. The metal foil or metal film may be subjected to a known surface treatment such as nickel treatment or cobalt treatment. The thickness of the metal foil or metal film is arbitrary, and may be appropriately selected according to the use or configuration, but is usually 1 μm or more, preferably 10 μm or more.
　斯かる金属張積層板にスルーホールを形成した後、配線パターン形成が行われる。その手法としては、サブトラクティブ法とパターンメッキ法とが挙げられるが、本発明では何れを用いてもよい。サブトラクティブ法は、まず金属張積層板の全面に無電解めっき（例えばパラジウム触媒を用いた無電解銅めっき等）を施し、続いて全面に電解めっき（例えば電解銅めっき等）を施し、めっき金属上にめっきレジストをラミネートし、パターンマスクフィルムを用いた露光・現像によりめっきレジストをパターン化した後、めっきレジスト不在領域のめっき金属をエッチングで除去し、最後にめっきレジストを除去することにより、配線パターンを形成する手法である。一方、パターンメッキ法は、まず金属張積層板上にめっきレジストをラミネートし、パターンマスクフィルムを用いた露光・現像によりめっきレジストをパターン化した後、パターン部のみに電解めっきを施し、更に必要に応じてエッチングのレジスト金属となるめっきを施し、めっきレジストを除去し、不要の金属をエッチングすることにより、配線パターンを形成する手法である。配線パターンの厚さは任意であり、用途や構成等に応じて適宜選択すればよいが、通常１μｍ以上、中でも５μｍ以上の範囲が好適である。 After forming a through hole in such a metal-clad laminate, a wiring pattern is formed. Examples of the method include a subtractive method and a pattern plating method, and any method may be used in the present invention. In the subtractive method, first, electroless plating (for example, electroless copper plating using a palladium catalyst) is performed on the entire surface of the metal-clad laminate, and then electrolytic plating (for example, electrolytic copper plating) is performed on the entire surface to form a plated metal. Plating resist is laminated on top, and after patterning the plating resist by exposure and development using a pattern mask film, the plating metal in the absence of plating resist is removed by etching, and finally the plating resist is removed, thereby wiring. This is a method of forming a pattern. On the other hand, in the pattern plating method, a plating resist is first laminated on a metal-clad laminate, and after patterning the plating resist by exposure and development using a pattern mask film, only the pattern portion is subjected to electrolytic plating, and further required. Accordingly, the wiring pattern is formed by performing plating that serves as a resist metal for etching, removing the plating resist, and etching unnecessary metal. The thickness of the wiring pattern is arbitrary, and may be appropriately selected according to the use and configuration, but is usually in the range of 1 μm or more, particularly 5 μm or more.
　なお、上記各工程に加えて、洗浄、ソフトエッチング、ハーフエッチング、デスミヤ、表面粗化等の工程が付加される場合もある。中でも、本発明の製造方法に供するための前処理として、配線パターン等の金属層の密着性付与処理を行うことが好ましい。 In addition to the above steps, steps such as cleaning, soft etching, half etching, desmearing, and surface roughening may be added. Especially, it is preferable to perform the adhesion provision process of metal layers, such as a wiring pattern, as pre-processing for using for the manufacturing method of this invention.
　配線基板の作製手順の一例を、図１（ａ）～（ｇ）のフローチャートに示す。まず、絶縁性基材（１）の両面に金属箔（２）を有する金属張積層板（３）を用意する（図１（ａ））。この金属張積層板（３）にスルーホール（ＴＨ）を形成し、ハーフエッチング、デスミヤ処理を施す（図１（ｂ））。この金属張積層板（３）のスルーホール（ＴＨ）内を含む全面に無電解めっきを施し、無電解めっき層（４）を形成する（図１（ｃ））。この無電解めっき層（４）を電源供給層として電解めっきを施し、電解めっき層（５）を形成する（図１（ｄ））。この積層体の両面にめっきレジスト（６）をラミネートし、パターンマスクフィルムを用いた露光・現像によりパターン化を行う（図１（ｅ））。めっきレジスト（６）が不在の領域の無電解めっき層（４）及び電解めっき層（５）をエッチングで除去する（図１（ｆ））。最後にめっきレジスト（６）を除去し、配線基板（７）を得る（図１（ｇ））。但し、本手順はあくまでも一例であって、配線基板の作製手順はこれに限定されるものではない。 An example of the manufacturing procedure of the wiring board is shown in the flowcharts of FIGS. First, a metal-clad laminate (3) having a metal foil (2) on both sides of an insulating substrate (1) is prepared (FIG. 1 (a)). Through holes (TH) are formed in the metal-clad laminate (3), and half-etching and desmearing are performed (FIG. 1 (b)). Electroless plating is performed on the entire surface including the inside of the through hole (TH) of the metal-clad laminate (3) to form an electroless plating layer (4) (FIG. 1 (c)). Electroless plating is performed using the electroless plating layer (4) as a power supply layer to form an electrolytic plating layer (5) (FIG. 1 (d)). A plating resist (6) is laminated on both surfaces of this laminate, and patterning is performed by exposure and development using a pattern mask film (FIG. 1 (e)). The electroless plating layer (4) and the electrolytic plating layer (5) in the region where the plating resist (6) is absent are removed by etching (FIG. 1 (f)). Finally, the plating resist (6) is removed to obtain a wiring board (7) (FIG. 1 (g)). However, this procedure is merely an example, and the manufacturing procedure of the wiring board is not limited to this.
　また、こうして形成された配線基板を複数積層することにより、ブラインドビア及びインナービアを通じて表裏の導通を確保した多層配線基板とすることもできる。本発明の製造方法では、斯かる多層配線基板も好適に使用される。 Further, by stacking a plurality of wiring boards formed in this way, a multilayer wiring board in which conduction between the front and back sides is ensured through blind vias and inner vias can be obtained. In the manufacturing method of the present invention, such a multilayer wiring board is also preferably used.
・工程（１）ソルダーレジストの形成：
　本工程では、絶縁性基材にスルーホール及び配線パターンが形成されてなる配線基板の表面に、ソルダーレジストを形成する。
　ソルダーレジストの材料としては、プリント配線板や半導体パッケージ用回路基板に通常使用されるソルダーレジスト材料であればよく、限定されるものではない。例としては、エポキシ樹脂等からなる熱硬化性又は光硬化性レジスト材料や、アクリル－エポキシ樹脂等からなる光硬化性レジスト材料等が挙げられる。具体例としては、太陽インキ株式会社製のＰＳＲ－４０００（液状）やＰＦＲ－８００（フィルム状）等が挙げられる。 Step (1) Formation of solder resist:
In this step, a solder resist is formed on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
The solder resist material is not limited as long as it is a solder resist material usually used for printed circuit boards and circuit boards for semiconductor packages. Examples include a thermosetting or photocurable resist material made of an epoxy resin, a photocurable resist material made of an acrylic-epoxy resin, or the like. Specific examples include PSR-4000 (liquid form) and PFR-800 (film form) manufactured by Taiyo Ink Co., Ltd.
　ソルダーレジストの形成は、ソルダーレジスト材料を配線基板表面に積層した後、必要に応じてこれをパターン化し、硬化させることにより行う。液状のレジスト材料の場合、配線基板表面に塗布し、乾燥することにより積層する。塗布の方法としては、一般に用いられている塗布方法、例えばスクリーン印刷法、ロールコーター法、スプレーコーター法、カーテンコーター法、ディップコーター法等が用いられる。フィルム状のレジスト材料の場合、配線基板表面にラミネート又は真空プレスすることにより積層する。ソルダーレジスト材料の硬化は、ソルダーレジスト材料の種類に応じた適切な刺激の印加、例えばＵＶ（紫外）光等の光照射や加熱等により行う。ソルダーレジストのパターン化は、例えば光硬化性レジスト材料の場合、レジスト材料層の上にマスキングパターンを形成し、光照射によりパターン化部分のレジスト材料を硬化させた後、マスキング部分の非硬化レジスト材料を除去することにより行うことができる。非硬化ソルダーレジスト材料を除去するための手法は、ソルダーレジスト材料の種類により適宜選択することが可能であるが、例えば炭酸ソーダ（炭酸ナトリウム）等を用いた方法等が挙げられる。また、加熱やＵＶ光による後硬化を実施してもよい。 The solder resist is formed by laminating a solder resist material on the surface of the wiring board, and patterning and curing the solder resist material as necessary. In the case of a liquid resist material, it is applied to the wiring board surface and dried by drying. As a coating method, generally used coating methods such as a screen printing method, a roll coater method, a spray coater method, a curtain coater method, a dip coater method and the like are used. In the case of a film-like resist material, lamination is performed by laminating or vacuum pressing on the surface of the wiring board. The solder resist material is cured by applying an appropriate stimulus according to the type of the solder resist material, for example, irradiation with light such as UV (ultraviolet) light or heating. For example, in the case of a photo-curable resist material, the solder resist is patterned by forming a masking pattern on the resist material layer, curing the resist material of the patterned portion by light irradiation, and then non-curing resist material of the masking portion. This can be done by removing. The method for removing the non-cured solder resist material can be appropriately selected depending on the type of the solder resist material, and examples thereof include a method using sodium carbonate (sodium carbonate). Further, post-curing by heating or UV light may be performed.
　ソルダーレジストの厚みとしては、配線パターンを表面に露出させることなく被覆できる厚みであれば限定されないが、配線パターンを完全に被覆する必要がある理由から、通常５μｍ以上、中でも１０μｍ以上とすることが好ましい。一方、レーザー加工時のエネルギー消費量をできるだけ少なくする観点からは、通常５０μｍ以下、中でも３０μｍ以下とすることが好ましい。 The thickness of the solder resist is not limited as long as the wiring pattern can be covered without exposing it to the surface, but it is usually 5 μm or more, especially 10 μm or more because it is necessary to completely cover the wiring pattern. preferable. On the other hand, from the viewpoint of reducing the energy consumption during laser processing as much as possible, it is usually 50 μm or less, preferably 30 μm or less.
・工程（２）ブラインドビアの形成：
　本工程では、前記（１）で形成された半導体チップ搭載面側のソルダーレジストに対して、レーザーによりブラインドビアを形成する。
　ブラインドビアの形成に使用されるレーザーは、プリント配線板や半導体パッケージ用回路基板のビア形成に一般に使用されるレーザーであれば、特に限定されない。例としては、炭酸ガスレーザー、ＵＶレーザー等が用いられる。この中でも、微細なブラインドビアの加工が可能なＵＶレーザーを用いることが好ましい。 Process (2) Blind via formation:
In this step, blind vias are formed by laser on the solder resist on the semiconductor chip mounting surface side formed in (1).
The laser used for forming the blind via is not particularly limited as long as it is a laser generally used for forming a via on a printed wiring board or a circuit board for a semiconductor package. As an example, a carbon dioxide laser, a UV laser, or the like is used. Among these, it is preferable to use a UV laser capable of processing a fine blind via.
　ＵＶレーザーによるブラインドビア形成時の加工方法は、特に限定されないが、トレパニング加工を用いるのが好ましい。トレパニング加工とは、穿孔時にレーザービームを円周上（同心円状又はらせん状）に回転させながら孔あけ加工を行う方法で、ビーム径より大きな孔を加工する際に一般的に利用される方法である。トレパニング加工を行うことにより、開口部の壁がほぼ垂直であり、開口部（ソルダーレジスト表面）の径と底部（配線パターン表面）の径とが同程度である形状（例えば前述の図８等に示す形状）のブラインドビアのみならず、開口部（ソルダーレジスト表面）の径よりも底部（配線パターン表面）の径の方が小さいテーパー形状（例えば後述の図２（ｄ）に示すような形状）のブラインドビアを形成することも可能になる。特に後者のようなテーパー形状のブラインドビアによれば、半導体チップとの導通がより容易になるので好ましい。 Although the processing method at the time of forming the blind via by UV laser is not particularly limited, it is preferable to use trepanning. Trepanning is a method of drilling while rotating the laser beam on the circumference (concentric or spiral) during drilling, and is a method commonly used when machining holes larger than the beam diameter. is there. By performing the trepanning process, a shape in which the wall of the opening is almost vertical and the diameter of the opening (solder resist surface) is the same as the diameter of the bottom (wiring pattern surface) (for example, in FIG. Taper shape (for example, a shape as shown in FIG. 2D described later) in which the diameter of the bottom (wiring pattern surface) is smaller than the diameter of the opening (solder resist surface) as well as the blind via of the shape shown in FIG. It is also possible to form a blind via. In particular, a tapered blind via like the latter is preferable because conduction with a semiconductor chip becomes easier.
　ブラインドビアの径は、半導体パッケージ等の高集積化の観点から、通常１００μｍ以下、好ましくは８０μｍ以下、より好ましくは５０μｍ以下とする。本発明の製造方法によれば、斯かる微細なブラインドビアであっても、簡便且つ確実に表層接続パッドを形成し、半導体チップとの導通を確保することが可能となるので好ましい。但し、半導体チップとの導通を確実に確保する観点からは、ブラインドビアの径の下限は通常５μｍ以上、中でも１０μｍ以上とすることが好ましい。 The diameter of the blind via is usually 100 μm or less, preferably 80 μm or less, more preferably 50 μm or less, from the viewpoint of high integration of a semiconductor package or the like. According to the manufacturing method of the present invention, even such fine blind vias are preferable because the surface layer connection pads can be easily and reliably formed and the conduction with the semiconductor chip can be ensured. However, from the viewpoint of ensuring the conduction with the semiconductor chip, the lower limit of the diameter of the blind via is usually 5 μm or more, preferably 10 μm or more.
　但し、上述した１００μｍ以下の径を有する微細なブラインドビアに加えて、１００μｍを超える径を有するより大きなブラインドビアを形成してもよい。言い換えれば、ソルダーレジストに形成されるブラインドビアのうち少なくとも一部が、１００μｍ以下の径を有する微細なブラインドビアであれば、本発明を適用することにより顕著な効果を得ることが可能である。 However, in addition to the fine blind via having a diameter of 100 μm or less as described above, a larger blind via having a diameter exceeding 100 μm may be formed. In other words, if at least a part of the blind via formed in the solder resist is a fine blind via having a diameter of 100 μm or less, a remarkable effect can be obtained by applying the present invention.
　また、ブラインドビアは、通常はソルダーレジストを貫通し、その下の配線パターン（金属層）が露出するように形成される。このため、ブラインドビアの深さは、通常は配線パターン上のソルダーレジストの厚みと同じとなる。 Also, the blind via is usually formed so as to penetrate the solder resist and expose the wiring pattern (metal layer) below it. For this reason, the depth of the blind via is usually the same as the thickness of the solder resist on the wiring pattern.
・工程（２’）表面粗化処理：
　本工程では、前記（２）で形成されたブラインドビアを有するソルダーレジストに対して、表面粗化処理を施す。なお、本工程は任意であるが、後記（３）における無電解めっき被膜の形成を好適に行う観点からは、本工程を実施することが好ましい。表面粗化処理の手法としては、過マンガン酸カリウムやクロム酸カリウムを含有する溶液を使用してエッチングを行う化学的処理、プラズマ処理やジェットスクラブ処理、サンドブラスト処理等の微粒子を吹き付けて物理的に粗化を行う物理的処理が挙げられる。中でも、簡易且つ均一に粗化ができる点から、ジェットスクラブ法が好ましい。 Process (2 ′) surface roughening treatment:
In this step, a surface roughening process is performed on the solder resist having the blind via formed in (2). In addition, although this process is arbitrary, it is preferable to implement this process from a viewpoint which performs formation of the electroless-plating film in postscript (3) suitably. Surface roughening methods include physical treatment by spraying fine particles, such as chemical treatment, etching using a solution containing potassium permanganate or potassium chromate, plasma treatment, jet scrub treatment, sandblast treatment, etc. The physical process which performs roughening is mentioned. Among these, the jet scrub method is preferable because roughening can be performed easily and uniformly.
・工程（３）無電解めっき被膜の形成：
　本工程では、前記（２）で形成されたブラインドビアを有する半導体チップ搭載面側のソルダーレジスト表面に、無電解めっき被膜を形成する。なお、ブラインドビア内部では配線パターン（金属層）が露出しているため、当該露出した配線パターン（金属層）上に無電解めっき被膜が形成されることになる。これにより、半導体チップ搭載面側のソルダーレジスト表面、及び、ブラインドビア内部に露出した配線パターン（金属層）の表面に、後記（４）の電解めっき用の給電層を確保することができる。 Step (3) Formation of electroless plating film:
In this step, an electroless plating film is formed on the surface of the solder resist on the semiconductor chip mounting surface side having the blind via formed in (2). Since the wiring pattern (metal layer) is exposed inside the blind via, an electroless plating film is formed on the exposed wiring pattern (metal layer). As a result, a power supply layer for electrolytic plating described later (4) can be secured on the solder resist surface on the semiconductor chip mounting surface side and the surface of the wiring pattern (metal layer) exposed inside the blind via.
　無電解めっきの材料となる金属は、特に制限されるものではないが、銅、ニッケル、すず等が好ましく、中でも銅が特に好ましい。
　無電解めっきの手法は、特に制限されるものではなく、従来公知の手法を適宜用いればよい。通常は、めっき対象表面に金属触媒を付着させた後、めっき液で処理する手法が挙げられる。 Although the metal used as the material for electroless plating is not particularly limited, copper, nickel, tin, and the like are preferable, and copper is particularly preferable.
The method of electroless plating is not particularly limited, and a conventionally known method may be appropriately used. Usually, after making a metal catalyst adhere to the plating object surface, the method of processing with a plating solution is mentioned.
　金属触媒としては、Ｐｄ、Ａｇ、Ｐｔ、Ａｕ、Ｎｉ、Ｃｏ等の金属が挙げられるが、無電解銅めっきの場合、特にパラジウム（Ｐｄ）が好ましい。これらは１種を単独で使用してもよく、２種以上を任意の比率及び組み合わせで併用してもよい。金属触媒をめっき対象表面に付着させる手法としては、金属触媒を含むアクチベータ溶液にめっき対象を浸漬する方法やめっき対象に金属触媒を蒸着する方法が挙げられる。金属触媒の量は、特に制限されるものではないが、単位表面当たり通常０．１～２ｍｇ／ｍｍ２の範囲とすることが好ましい。 Examples of the metal catalyst include metals such as Pd, Ag, Pt, Au, Ni, and Co. In the case of electroless copper plating, palladium (Pd) is particularly preferable. These may be used individually by 1 type and may use 2 or more types together by arbitrary ratios and combinations. Examples of the method for attaching the metal catalyst to the surface of the plating target include a method of immersing the plating target in an activator solution containing the metal catalyst and a method of depositing the metal catalyst on the plating target. The amount of the metal catalyst is not particularly limited, but is preferably in the range of usually 0.1 to 2 mg / mm 2 per unit surface.
　めっき液の組成は、特に制限されるものではないが、例えば無電解銅メッキ液の場合、通常は、銅イオン及び／又はその塩（例えば硫酸銅等）と、還元剤（例えばホルムアルデヒド等）と、錯化剤（例えばロッシェル塩（酒石酸ナトリウムカリウム）又はＥＤＴＡ（エチレンジアミン四酢酸）等）とを含有するものが用いられる。めっき液による処理を行う手法は特に制限されないが、通常はめっき対象をめっき液に浸漬することにより処理を行う。 The composition of the plating solution is not particularly limited. For example, in the case of an electroless copper plating solution, usually, copper ions and / or a salt thereof (such as copper sulfate) and a reducing agent (such as formaldehyde) And a complexing agent (for example, Rochelle salt (sodium potassium tartrate) or EDTA (ethylenediaminetetraacetic acid)) is used. Although the method for performing the treatment with the plating solution is not particularly limited, the treatment is usually performed by immersing the plating object in the plating solution.
　無電解銅めっき被膜の厚さは任意であり、適宜選択すればよいが、導通確保の観点からは、通常０．２μｍ以上、中でも１．０μｍ以上が好適である。上限は特に制限はないが、通常は２μｍ以下程度が一般的である。 The thickness of the electroless copper plating film is arbitrary and may be selected as appropriate. However, from the viewpoint of ensuring conduction, it is usually 0.2 μm or more, preferably 1.0 μm or more. The upper limit is not particularly limited, but is usually about 2 μm or less.
・工程（３’－１）めっきレジストの形成：
　本工程では、前記（３）で表面に無電解めっき被膜を形成されたソルダーレジストを有する回路基板の両面に、めっきレジストを形成する。なお、本工程（３’－１）並びに後述の工程（３’－２）及び（４’）は任意であるが、電解めっき及び無電解めっきの除去量を小さくして、表層接続パッドの高さをよりソルダーレジスト表面に近づける観点からは、本工程を実施することが好ましい。 -Step (3'-1) Formation of plating resist:
In this step, the plating resist is formed on both surfaces of the circuit board having the solder resist on which the electroless plating film is formed on the surface in (3). Although this step (3′-1) and steps (3′-2) and (4 ′) described later are optional, the removal amount of electrolytic plating and electroless plating can be reduced to increase the surface layer connection pad height. From the viewpoint of bringing the thickness closer to the solder resist surface, it is preferable to carry out this step.
　めっきレジストの材料としては、プリント配線板や半導体パッケージ用回路基板に通常使用されるめっきレジスト材料であればよく、限定されるものではないが、後記（４）の電解めっき等の処理で変形、溶解、剥離等することのない、安定な材料を使用することが好ましい。また、後記（４’）でめっきレジストを除去する際に、その下層のソルダーレジストまでもが一緒に除去されてしまうことのないよう、ソルダーレジストの材料の除去法とは異なる手法で除去可能な材料を使用することが好ましい。斯かるめっきレジスト材料の例としては、アルカリ現像形感光性フィルム（ドライフィルム）等の固形材料等が挙げられる。ドライフィルムの具体例としては、サンフォート（登録商標）シリーズ（旭化成イーマテリアルズ社製）、ＲＹシリーズ（日立化成工業株式会社製）、リストンシリーズ（デュポンＭＲＣドライフィルム株式会社製）等が挙げられる。 The material for the plating resist is not particularly limited as long as it is a plating resist material that is usually used for printed circuit boards and circuit boards for semiconductor packages. It is preferable to use a stable material that does not dissolve or peel off. In addition, when removing the plating resist in the following (4 ′), it can be removed by a method different from the method of removing the solder resist material so that even the solder resist of the lower layer is not removed together. It is preferable to use materials. Examples of such a plating resist material include solid materials such as an alkali developing type photosensitive film (dry film). Specific examples of the dry film include the Sunfort (registered trademark) series (made by Asahi Kasei E-materials), the RY series (made by Hitachi Chemical Co., Ltd.), the Liston series (made by DuPont MRC dry film). It is done.
　めっきレジストは、めっきレジスト材料を回路基板の両面に積層することにより行う。めっきレジスト材料がフィルム状（ドライフィルム）の場合、回路基板の表面にドライフィルムをラミネート又は真空プレスすることにより積層する。 The plating resist is formed by laminating plating resist materials on both sides of the circuit board. When the plating resist material is in the form of a film (dry film), the dry resist film is laminated or vacuum-pressed on the surface of the circuit board.
　めっきレジストの厚さは任意であり、適宜選択すればよいが、めっきのオーバーハングを防止する観点からは、通常１５μｍ以上、中でも２０μｍ以上が好適であり、また、ドライフィルムの解像性の観点からは、通常４０μｍ以下、中でも３０μｍ以下の範囲が好適である。 The thickness of the plating resist is arbitrary and may be selected as appropriate. From the viewpoint of preventing plating overhang, it is usually 15 μm or more, preferably 20 μm or more, and from the viewpoint of the resolution of the dry film. Is usually in the range of 40 μm or less, particularly 30 μm or less.
・工程（３’－２）めっきレジストの開口部形成：
　本工程では、前記（３’－１）で形成されためっきレジストに対して、少なくとも半導体チップ搭載面側のソルダーレジストのブラインドビアが露出するように、開口部を形成する。斯かる開口部の形成は、例えば、めっきレジスト材料として光（ＵＶ）硬化性の材料を用いる場合、レジスト材料層の上にマスキングパターンを形成し、光照射によりパターン化部分のレジスト材料を硬化させた後、マスキング部分の非硬化レジスト材料を除去することにより行うことができる。非硬化めっきレジストの除去の手法は、めっきレジストの種類により適宜選択可能であるが、例えば炭酸ナトリウム等のアルカリ性水溶液による処理等の手法が挙げられる。 -Step (3'-2) Plating resist opening formation:
In this step, an opening is formed with respect to the plating resist formed in (3′-1) so that at least the blind via of the solder resist on the semiconductor chip mounting surface side is exposed. For example, when a light (UV) curable material is used as the plating resist material, a masking pattern is formed on the resist material layer, and the resist material in the patterned portion is cured by light irradiation. Thereafter, the uncured resist material in the masking portion can be removed. The method for removing the non-cured plating resist can be appropriately selected depending on the type of the plating resist, and examples thereof include a method such as treatment with an alkaline aqueous solution such as sodium carbonate.
　なお、本工程において、半導体チップ搭載面側のめっきレジストに形成される開口部の形状は任意であり、少なくともソルダーレジストのブラインドビアが露出する形状であればよい。すなわち、実質的にブラインドビアの部分のみを開口してもよく、半導体チップ搭載面全体を開口（即ち、半導体チップ搭載面のめっきレジストを全て除去）してもよく、その他の形状の開口としてもよい。特に、実質的にブラインドビアの部分のみを開口することにより、後記（４）において、ブラインドビア以外の部分における電解めっき層の形成が抑制され、後記（５）において必要なエッチングの量を低減することができ、惹いてはソルダーレジスト表面と表層接続パッド上面の高さの差がより小さい表層接続パッドを形成することができる。斯かる厚めの構成の表層接続パッドを有する半導体パッケージ用回路基板は、半導体チップとの導通を確保し易いという利点がある（斯かる態様については図２（ａ）～（ｊ）を用いて後述する。）。一方、半導体チップ搭載面のめっきレジストを全て除去すれば、半導体チップ搭載面のめっきレジストをパターン化する手間を省くことができ、より簡便に半導体パッケージ用回路基板を作製できるという利点がある（斯かる態様については図３（ａ）～（ｊ）を用いて後述する。）。 In this step, the shape of the opening formed in the plating resist on the semiconductor chip mounting surface side is arbitrary, and may be any shape as long as at least the blind via of the solder resist is exposed. That is, only the blind via portion may be substantially opened, the entire semiconductor chip mounting surface may be opened (that is, all the plating resist on the semiconductor chip mounting surface may be removed), or other shapes of openings may be formed. Good. In particular, by substantially opening only the portion of the blind via, in the postscript (4), formation of the electrolytic plating layer in the portion other than the blind via is suppressed, and the amount of etching required in the postscript (5) is reduced. As a result, a surface layer connection pad having a smaller difference in height between the solder resist surface and the upper surface of the surface layer connection pad can be formed. The circuit board for a semiconductor package having such a thick surface layer connection pad has an advantage that it is easy to ensure electrical continuity with the semiconductor chip (this mode will be described later with reference to FIGS. 2A to 2J). To do.) On the other hand, if all of the plating resist on the semiconductor chip mounting surface is removed, there is an advantage that the labor of patterning the plating resist on the semiconductor chip mounting surface can be saved, and a circuit board for a semiconductor package can be more easily manufactured (such a case). Such a mode will be described later with reference to FIGS. 3 (a) to 3 (j).
・工程（４）電解めっきによるビアフィリング：
　本工程では、前記（３）で表面に無電解めっき被膜を形成されたソルダーレジストのブラインドビアに対して、電解めっきによりビアフィリングを行い、電解めっき層を形成する。具体的には、無電解めっき被膜を給電層として電源を供給しながら、半導体チップ搭載面に電解めっき層を施す。電解めっきの材料となる金属は、特に制限されるものではないが、銅、ニッケル、錫等が好ましく、中でも銅が特に好ましい。 -Process (4) Via filling by electrolytic plating:
In this step, via filling is performed by electrolytic plating on the solder resist blind via having the electroless plating film formed on the surface in (3) to form an electrolytic plating layer. Specifically, the electrolytic plating layer is applied to the semiconductor chip mounting surface while supplying power using the electroless plating film as a power feeding layer. Although the metal used as the material for electrolytic plating is not particularly limited, copper, nickel, tin and the like are preferable, and copper is particularly preferable.
　本工程では、フィルドめっきという手法を用いることにより、ブラインドビア部分の電解めっき層とそれ以外の部分の電解めっき層とがほぼ同じ高さとなるように、電解めっき層を形成する。これにより、ブラインドビアの内部を電解めっきで充填する（これを「ビアフィリング」という。）ことが可能となる。フィルドめっきの手法は特に限定されないが、例えば特開平１１－１４５６２１等に記載の手法を用いることができる。 In this step, by using a method called filled plating, the electrolytic plating layer is formed so that the electrolytic plating layer in the blind via portion and the electrolytic plating layer in the other portion have almost the same height. As a result, the inside of the blind via can be filled with electrolytic plating (this is referred to as “via filling”). Although the method of filled plating is not particularly limited, for example, the method described in JP-A-11-145621 can be used.
　例として、電解銅めっきでビアフィリングを行う場合、めっき対象表面（半導体チップ搭載面）を、硫酸銅めっき浴に浸漬させ、硫酸銅めっき浴と接触させた状態で、めっき対象表面をカソードとし、硫酸銅めっき浴に浸漬させたアノードとの間に、外部電源から電流を印加することにより行う。 As an example, when performing via filling by electrolytic copper plating, the surface to be plated (semiconductor chip mounting surface) is immersed in a copper sulfate plating bath and in contact with the copper sulfate plating bath, and the surface to be plated is used as a cathode. This is performed by applying an electric current from an external power source to the anode immersed in the copper sulfate plating bath.
　なお、従来の回路基板のスルーホールめっきやビア充填用の電解銅めっきには、均一電着性を改善するため、銅濃度を低く、硫酸濃度を高くした、ハイスロー浴と呼ばれる硫酸銅めっき浴が用いられてきた。これに対して、本発明では、従来のハイスロー浴よりも更に銅濃度を低下させ、硫酸濃度を高めた硫酸銅めっき浴を使用し、且つ、陰極（カソード）の電流密度を従来よりも低くして電解めっきを行う。これにより、ブラインドビア内部に優先的にめっきが形成され、フィルドめっきによるビアフィリングが達成される。 In addition, in conventional electrolytic copper plating for through-hole plating and via filling of circuit boards, there is a copper sulfate plating bath called a high-throw bath with a low copper concentration and a high sulfuric acid concentration in order to improve the throwing power. Has been used. On the other hand, in the present invention, a copper sulfate plating bath in which the copper concentration is further lowered and the sulfuric acid concentration is increased as compared with the conventional high-throw bath is used, and the current density of the cathode (cathode) is made lower than before. Electrolytic plating is performed. Thereby, plating is preferentially formed inside the blind via, and via filling by filled plating is achieved.
　具体的に、硫酸銅めっき浴における硫酸銅／硫酸の質量比は、通常３０以下、好ましくは８．３３以下の範囲とする。これにより、ブラインドビア内部に優先的にめっきが形成され、フィルドめっきによるビアフィリングが達成される。但し、めっき形成速度を促進し、めっき時間を短縮する観点からは、硫酸銅／硫酸の質量比を通常０．６６以上、中でも１．５以上とすることが好ましい。 Specifically, the mass ratio of copper sulfate / sulfuric acid in the copper sulfate plating bath is usually 30 or less, preferably 8.33 or less. Thereby, plating is preferentially formed inside the blind via, and via filling by filled plating is achieved. However, from the viewpoint of accelerating the plating formation rate and shortening the plating time, the mass ratio of copper sulfate / sulfuric acid is usually 0.66 or more, preferably 1.5 or more.
　硫酸銅めっき浴は、水等を溶媒として、硫酸銅／硫酸の質量比が上記比率となるように、硫酸銅及び硫酸を溶解させることにより調製される。溶媒に対する硫酸銅の使用量は、通常１００ｇ／Ｌ以上、中でも１５０ｇ／Ｌ以上、また、通常３００ｇ／Ｌ以下、中でも２５０ｇ／Ｌ以下の範囲が好ましい。溶媒に対する硫酸の使用量は、通常１０ｇ／Ｌ以上、中でも３０ｇ／Ｌ以上、また、通常１５０ｇ／Ｌ以下、中でも１００ｇ／Ｌ以下の範囲が好ましい。また、塩素イオン含量は、通常２０ｍｇ／Ｌ以上、中でも３０ｍｇ／Ｌ以上、また、通常７０ｍｇ／Ｌ以下、中でも５０ｍｇ／Ｌ以下の範囲が好ましい。 The copper sulfate plating bath is prepared by dissolving copper sulfate and sulfuric acid using water or the like as a solvent so that the mass ratio of copper sulfate / sulfuric acid is the above ratio. The amount of copper sulfate used relative to the solvent is usually 100 g / L or more, preferably 150 g / L or more, and usually 300 g / L or less, preferably 250 g / L or less. The amount of sulfuric acid used in the solvent is usually 10 g / L or more, preferably 30 g / L or more, and usually 150 g / L or less, preferably 100 g / L or less. Further, the chlorine ion content is usually 20 mg / L or more, preferably 30 mg / L or more, and usually 70 mg / L or less, especially 50 mg / L or less.
　硫酸銅めっき浴には、上記の成分に加えて、他の成分を含有させてもよい。他の成分としては、光沢剤、担体、レベリング剤等が挙げられる。光沢剤の例としては、チオ尿素、チオカルバーメート等の含イオウ有機化合物等が挙げられる。担体の例としては、ポリオキシアルキレングリコール等が挙げられる。レベリング剤の例としては、ポリアミン等が挙げられる。これらの成分の使用量は、従来と同様である。 In addition to the above components, the copper sulfate plating bath may contain other components. Examples of other components include brighteners, carriers, and leveling agents. Examples of brighteners include sulfur-containing organic compounds such as thiourea and thiocarbamate. Examples of the carrier include polyoxyalkylene glycol. Examples of leveling agents include polyamines. The amount of these components used is the same as before.
　電解めっき時の陰極（カソード）の電流密度は、通常５Ａ／ｄｍ２以下、好ましくは３Ａ／ｄｍ２以下とする。この電流密度で電解めっきを行うことにより、ブラインドビア内部に優先的にめっきが形成され、フィルドめっきによるビアフィリングが達成される。但し、めっき形成速度を促進し、めっき時間を短縮する観点からは、通常０．５Ａ／ｄｍ２以上、中でも１Ａ／ｄｍ２以上とすることが好ましい。
　電解めっき時の温度は特に制限されないが、通常１５℃以上、中でも２０℃以上、また、通常３０℃以下、中でも２５℃以下の範囲とすることが好ましい。 The current density of the cathode (cathode) during electrolytic plating is usually 5 A / dm 2 or less, preferably 3 A / dm 2 or less. By performing electrolytic plating at this current density, plating is preferentially formed inside the blind via, and via filling by filled plating is achieved. However, from the viewpoint of accelerating the plating formation rate and shortening the plating time, it is usually preferably 0.5 A / dm 2 or more, and more preferably 1 A / dm 2 or more.
Although the temperature at the time of electroplating is not particularly limited, it is preferably 15 ° C. or higher, particularly 20 ° C. or higher, and usually 30 ° C. or lower, especially 25 ° C. or lower.
　電解めっきの時間は限定されないが、少なくともブラインドビア内部がフィルドめっきによって充填され、ブラインドビア部分とそれ以外の部分との電解めっき層の高低差が殆どなくなり、実質的に平坦となるまで実施すればよい。 The time of electrolytic plating is not limited, but at least the inside of the blind via is filled with filled plating, and the difference in height of the electrolytic plating layer between the blind via portion and the other portions is almost eliminated and it is carried out until it is substantially flat. Good.
　電解めっき層の厚さも特に限定されないが、ブラインドビア以外の部分の電解めっき層の厚さが、通常３μｍ以上、中でも５μｍ以上、また、通常４０μｍ以下、中でも３０μｍ以下の範囲であることが好適である。一方、ブラインドビア部分の電解めっき層の厚さは、ブラインドビア以外の部分の電解めっき層の厚さと、ブラインドビアの深さ（即ち、配線パターン上のソルダーレジストの厚み）との和にほぼ等しくなるため、ブラインドビア以外の部分の電解めっき層の厚さよりも遥かに大きくなる。 The thickness of the electroplating layer is not particularly limited, but the thickness of the electroplating layer other than the blind via is usually 3 μm or more, preferably 5 μm or more, and usually 40 μm or less, especially 30 μm or less. is there. On the other hand, the thickness of the electrolytic plating layer in the blind via portion is substantially equal to the sum of the thickness of the electrolytic plating layer in the portion other than the blind via and the depth of the blind via (that is, the thickness of the solder resist on the wiring pattern). Therefore, the thickness is much larger than the thickness of the electrolytic plating layer in the portion other than the blind via.
・工程（４’）めっきレジストの除去：
　本工程では、前記（３’－１）で形成されためっきレジストを除去する。めっきレジストの除去は、めっきレジスト材料を除去し得るとともに、電解めっきやソルダーレジストには浸食や変性等の悪影響を与えない手法を、適宜選択して用いることができる。例としては、水酸化ナトリウム水溶液やアミン系水溶液等のアルカリ性水溶液による処理等が挙げられる。 Step (4 ′) Plating resist removal:
In this step, the plating resist formed in (3′-1) is removed. The plating resist can be removed by appropriately selecting a technique that can remove the plating resist material and that does not adversely affect electrolytic plating or solder resist such as erosion or modification. Examples include treatment with an alkaline aqueous solution such as an aqueous sodium hydroxide solution or an amine-based aqueous solution.
・工程（５）余剰めっきのエッチング除去、表層接続パッドの形成：
　本工程では、半導体チップ搭載面側のソルダーレジスト表面のブラインドビア以外の部分に析出した余剰な電解めっき層（前記（４）で形成）及び無電解めっき被膜（前記（３）で形成）をエッチングにより除去し、ソルダーレジストを露出させる。これによって、ブラインドビア間の導通が解消され、ブラインドビア間の電気的な独立性が達成される。ここで、上述のように、前記（４）によりブラインドビア内に充填形成された電解めっき層は、ブラインドビア以外の部分の電解めっき層よりも遥かに厚いため、ブラインドビア以外の部分の電解めっき層及び無電解めっき被膜が除去される程度のエッチング量では除去されず、ブラインドビア内に残存する。従って、ブラインドビア以外の部分の電解めっき層及び無電解めっき被膜は全て除去され、且つ、ブラインドビア部分の電解めっき層及び無電解めっき被膜は残存するような条件で、エッチングを実施することにより、ブラインドビア内に残存した電解めっき層及び無電解めっき被膜によって、表層接続パッドが形成されることになる。 -Process (5) Etching removal of surplus plating, formation of surface layer connection pad:
In this step, the excess electrolytic plating layer (formed in (4) above) and the electroless plating film (formed in (3) above) deposited on portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side are etched. To remove the solder resist. This eliminates conduction between blind vias and achieves electrical independence between blind vias. Here, as described above, the electrolytic plating layer filled in the blind via according to the above (4) is much thicker than the electrolytic plating layer in the portion other than the blind via. It is not removed by an etching amount enough to remove the layer and the electroless plating film, but remains in the blind via. Therefore, by performing the etching under conditions such that the electrolytic plating layer and the electroless plating film in the portion other than the blind via are all removed, and the electrolytic plating layer and the electroless plating film in the blind via portion remain, A surface layer connection pad is formed by the electrolytic plating layer and the electroless plating film remaining in the blind via.
　エッチングの手法は特に限定されず、従来公知の任意の手法を使用することが可能である。例えば、電解銅めっきでビアフィリングを行った場合には、銅エッチング液を用いてエッチングを行なう。銅エッチング液としては、銅めっき層を選択的にエッチング可能なものが好適であり、中でも過酸化水素・硫酸系のエッチング液が好ましい。例としては、ＳＥ－０７（三菱ガス化学株式会社製）、ＣＰＥ－７００（三菱ガス化学株式会社製）、ＣＰＥ－８１０（三菱ガス化学株式会社製）、ＣＰＥ－７７０Ｄ（三菱ガス化学株式会社製）、ＣＰＥ－８００（三菱ガス化学株式会社製）、ＣＰＥ－８２０（三菱ガス化学株式会社製）等が挙げられる。 The etching method is not particularly limited, and any conventionally known method can be used. For example, when via filling is performed by electrolytic copper plating, etching is performed using a copper etchant. As the copper etchant, those capable of selectively etching the copper plating layer are suitable, and among them, a hydrogen peroxide / sulfuric acid based etchant is preferred. Examples include SE-07 (Mitsubishi Gas Chemical Co., Ltd.), CPE-700 (Mitsubishi Gas Chemical Co., Ltd.), CPE-810 (Mitsubishi Gas Chemical Co., Ltd.), CPE-770D (Mitsubishi Gas Chemical Co., Ltd.). ), CPE-800 (Mitsubishi Gas Chemical Co., Ltd.), CPE-820 (Mitsubishi Gas Chemical Co., Ltd.) and the like.
　エッチングの条件は、制限されるものではないが、ブラインドビア以外の部分の電解めっき層及び無電解めっき被膜が除去されるとともに、ブラインドビア部分の電解めっき層及び無電解めっき被膜が残存して、所望の厚みの表層接続パッドが形成されるように、適宜選択すればよい。 The etching conditions are not limited, but the electrolytic plating layer and the electroless plating film in the portion other than the blind via are removed, and the electrolytic plating layer and the electroless plating film in the blind via portion remain, What is necessary is just to select suitably so that the surface layer connection pad of desired thickness may be formed.
　一例として、後述の実施例１のように、厚さが１μｍの無電解銅めっき被膜と、ブラインドビア以外の部分の厚さが１５μｍの電解銅めっき層を除去する場合、好適なエッチング条件は以下の通りである。即ち、上記例示の銅エッチング液等を、過酸化水素の濃度が５．０～３０ｇ／Ｌ、硫酸濃度が１０～１００ｇ／Ｌ、銅濃度が１０～５０ｇ／Ｌ程度に調整し、噴霧・浸漬等の手段で適用し、２０～４０℃程度の温度でソルダーレジスト表面が露出するまで処理した後、水酸化ナトリウム、硫酸等の水溶液等を用いて洗浄することが好ましい。 As an example, when removing an electroless copper plating film having a thickness of 1 μm and an electrolytic copper plating layer having a thickness of 15 μm other than a blind via as in Example 1 described later, preferable etching conditions are as follows: It is as follows. That is, the copper etching solution exemplified above is adjusted to a hydrogen peroxide concentration of 5.0 to 30 g / L, a sulfuric acid concentration of 10 to 100 g / L, and a copper concentration of about 10 to 50 g / L. It is preferable to apply the above-mentioned means, treat the solder resist surface at a temperature of about 20 to 40 ° C. until it is exposed, and then wash with an aqueous solution of sodium hydroxide, sulfuric acid or the like.
　以上はあくまでも一例であるが、当業者であれば、電解めっき層及び無電解めっき被膜の種類や厚み、ソルダーレジストの種類や厚み（ブラインドビアの深さ）等の種々の因子を考慮して、上述の条件を適宜変更する等により、適切な条件を決定することが可能である。 The above is merely an example, but those skilled in the art will consider various factors such as the type and thickness of the electrolytic plating layer and the electroless plating film, the type and thickness of the solder resist (the depth of the blind via), Appropriate conditions can be determined by appropriately changing the above-described conditions.
　また、上記工程（３）でパラジウム等の金属触媒を用いて無電解めっきを行った場合には、金属触媒の除去を行う。金属触媒の除去には、適切な金属除去液を選択して用いればよい。例としては、硝酸・塩素イオン・カチオン性ポリマー系、硝酸塩・無機酸塩またはその塩系、メルカプト化合物系、含窒素脂肪族有機化合物・含ヨウ素無機化合物系、塩酸系除去液等の除去液を使用する。具体例としては、メックリムーバーＰＪ－９７１０（メック株式会社製）やメックリムーバーＰＪ－９７２０（メック株式会社製）、メルストリップＰＤ－３１１０（メルテックス株式会社製）、ダインスマットＰＤ－２８０（大和化成株式会社性）、パラストリップＩＣ（アトテック株式会社製）等が挙げられる。特に、金属触媒としてパラジウムを使用した場合には、ブラインドビア内に残存する電解めっき層及び無電解めっき被膜を溶解しないよう、銅を溶解し難いパラジウム除去液を使用するのが好ましい。 In addition, when electroless plating is performed using a metal catalyst such as palladium in the above step (3), the metal catalyst is removed. For removal of the metal catalyst, an appropriate metal removal solution may be selected and used. Examples include removal solutions such as nitric acid / chlorine ion / cationic polymer type, nitrate / inorganic acid salt or its salt type, mercapto compound type, nitrogen-containing aliphatic organic compound / iodine-containing inorganic compound type, hydrochloric acid type removing solution, etc. use. Specific examples include Mekku Remover PJ-9710 (made by Mec Co., Ltd.), Mekku Remover PJ-9720 (made by Mec Co., Ltd.), Melstrip PD-3110 (made by Meltex Co., Ltd.), Dynemat PD-280 (Daiwa Kasei) Co., Ltd.), Parastrip IC (made by Atotech Co., Ltd.), etc. In particular, when palladium is used as the metal catalyst, it is preferable to use a palladium removing solution that hardly dissolves copper so as not to dissolve the electrolytic plating layer and the electroless plating film remaining in the blind via.
・工程（５’）表面処理：
　本工程では、前記（５）のエッチング後におけるブラインドビア内の電解めっき露出部に、表面処理を施す。本工程は任意であるが、表層接続パッド表面の腐食による接続不良等の観点からは、本工程を実施することが好ましい。表面処理の種類は、半導体パッケージ基板の用途や半導体チップの実装方式により適宜選択されるため、特に限定されないが、無電解錫めっき処理、無電解金めっき処理、無電解ニッケル金めっき処理、無電解ニッケルパラジウム金めっき処理、及び有機防錆処理等が用いられる。 -Process (5 ') surface treatment:
In this step, a surface treatment is performed on the exposed portion of the electrolytic plating in the blind via after the etching of (5). Although this step is optional, it is preferable to carry out this step from the viewpoint of poor connection due to corrosion of the surface connection pad surface. The type of surface treatment is not particularly limited because it is appropriately selected depending on the use of the semiconductor package substrate and the mounting method of the semiconductor chip, but is not limited to electroless tin plating, electroless gold plating, electroless nickel gold plating, electroless Nickel palladium gold plating treatment, organic rust prevention treatment and the like are used.
　無電解錫めっき処理は、例えば、置換錫めっき浴、置換還元錫めっき浴を用い、浸漬処理により行うことが好ましい。 The electroless tin plating treatment is preferably performed by immersion treatment using, for example, a substitution tin plating bath or a substitution reduction tin plating bath.
　無電解金めっき処理は、例えば、置換金めっき浴を用い、浸漬処理により行うことが好ましい。 The electroless gold plating treatment is preferably performed by immersion treatment using, for example, a displacement gold plating bath.
　無電解ニッケル金めっき処理は、例えば、還元ニッケルめっき浴、置換金めっき浴または還元金メッキ浴を用い、無電解ニッケルめっき、無電解金メッキの順番で浸漬処理により行うことが好ましい。 The electroless nickel gold plating treatment is preferably performed by dipping treatment in the order of electroless nickel plating and electroless gold plating using, for example, a reduced nickel plating bath, a displacement gold plating bath or a reduced gold plating bath.
　無電解ニッケルパラジウム金めっき処理は、例えば、例えば、還元ニッケルめっき浴、還元パラジウムめっき浴、置換金めっき浴または還元金メッキ浴を用い、無電解ニッケルめっき、無電解パラジウムめっき、無電解金メッキの順番で浸漬処理により行うことが好ましい。 For example, the electroless nickel palladium gold plating treatment uses, for example, a reduced nickel plating bath, a reduced palladium plating bath, a displacement gold plating bath or a reduced gold plating bath, in the order of electroless nickel plating, electroless palladium plating, and electroless gold plating. It is preferable to carry out by immersion treatment.
・その他の工程：
　本発明の半導体パッケージ用回路基板の製造方法は、上述の各工程の他にも、任意の工程を有していてもよい。例えば、工程（１）でのソルダーレジスト形成後、工程（２）での半導体チップ搭載面側ソルダーレジストに対するブラインドビア形成とは別に、はんだボール搭載面のソルダーレジストに対しても、パターン化による開口の形成、電解めっき層の形成等の表面処理、はんだボールの取り付け等の処理を実施することが好ましい。 ・ Other processes:
The method for manufacturing a circuit board for a semiconductor package of the present invention may have an optional step in addition to the above-described steps. For example, after forming the solder resist in the step (1), the solder resist on the solder ball mounting surface is opened by patterning separately from the blind via formation on the semiconductor chip mounting surface side solder resist in the step (2). It is preferable to carry out a surface treatment such as formation of an electroplating layer, formation of an electrolytic plating layer, or a treatment such as attachment of a solder ball.
・半導体パッケージ用回路基板の製造方法の例：
　本発明の半導体パッケージ用回路基板の製造方法の一例を、図２（ａ）～（ｊ）のフローチャートに示す。まず、絶縁性基材にスルーホール及び配線パターンが形成されてなる配線基板（７）を用意する（図２（ａ））。この配線基板（７）の表面にソルダーレジスト（８）を形成し（工程（１））、はんだボール搭載面（Ｓ２）のソルダーレジストをパターン化し、配線パターンを露出させてはんだボールパッド（９）を形成する（図２（ｂ））。はんだボールパッド（９）上に表面処理層として電解めっき層（１０）を形成する（図２（ｃ））。続いて、半導体チップ搭載面（Ｓ１）側ソルダーレジストにレーザーでブラインドビア（ＢＶ）を形成する（工程（２）：図２（ｄ））。これによってブラインドビア（ＢＶ）内の配線パターン（２）が露出する。続いて、半導体チップ搭載面（Ｓ１）側ソルダーレジストに表面粗化処理を施した後（工程（２’））、ソルダーレジスト表面（及びブラインドビア（ＢＶ）内に露出した配線パターン（２）表面）に無電解めっき被膜（１１）を形成する（工程（３）：図２（ｅ））。次いで、配線基板の両面にめっきレジスト（１２）を形成し（工程（３’－１））、半導体チップ搭載面（Ｓ１）側のソルダーレジストのブラインドビアが露出するように開口部（Ｏ）を形成する（工程（３’－２）：図２（ｆ））。続いて、電解めっきによりブラインドビア（ＢＶ）のビアフィリングを行い、電解めっき層（１３）を形成する（工程（４）：図２（ｇ））。その後、めっきレジスト（１２）を除去する（工程（４’）：図２（ｈ））。半導体チップ搭載面（Ｓ１）側ソルダーレジスト表面のブラインドビア（ＢＶ）以外の部分の電解めっき層（１３）及び無電解めっき被膜（１１）をエッチングにより除去し、ソルダーレジストを露出させることにより、ブラインドビア（ＢＶ）内に電解めっき層（１３）及び無電解めっき被膜（１１）からなる表層接続パッド（１４）を形成する（工程（５）：図２（ｉ））。その後、表層接続パッド（１４）に表面処理を施し、無電解めっき層（１５）を形成することにより、半導体パッケージ用回路基板（１６）が作製される（工程（５’）：図２（ｊ））。 -Examples of methods for manufacturing circuit boards for semiconductor packages:
An example of a method for manufacturing a semiconductor package circuit board of the present invention is shown in the flowcharts of FIGS. First, a wiring board (7) in which through holes and wiring patterns are formed on an insulating base material is prepared (FIG. 2A). A solder resist (8) is formed on the surface of the wiring board (7) (step (1)), the solder resist on the solder ball mounting surface (S2) is patterned, the wiring pattern is exposed, and a solder ball pad (9) Is formed (FIG. 2B). An electrolytic plating layer (10) is formed on the solder ball pad (9) as a surface treatment layer (FIG. 2 (c)). Subsequently, a blind via (BV) is formed on the semiconductor chip mounting surface (S1) side solder resist with a laser (step (2): FIG. 2 (d)). As a result, the wiring pattern (2) in the blind via (BV) is exposed. Subsequently, after subjecting the solder resist on the semiconductor chip mounting surface (S1) side to surface roughening (step (2 ′)), the surface of the solder resist (and the surface of the wiring pattern (2) exposed in the blind via (BV)) ) To form an electroless plating film (11) (step (3): FIG. 2 (e)). Next, a plating resist (12) is formed on both surfaces of the wiring board (step (3'-1)), and openings (O) are formed so that the solder resist blind vias on the semiconductor chip mounting surface (S1) side are exposed. Form (step (3′-2): FIG. 2 (f)). Subsequently, blind via (BV) via filling is performed by electrolytic plating to form an electrolytic plating layer (13) (step (4): FIG. 2 (g)). Thereafter, the plating resist (12) is removed (step (4 ′): FIG. 2 (h)). By removing the electrolytic plating layer (13) and the electroless plating film (11) other than the blind via (BV) on the semiconductor chip mounting surface (S1) side solder resist surface by etching and exposing the solder resist, blinds are obtained. A surface layer connection pad (14) comprising an electrolytic plating layer (13) and an electroless plating film (11) is formed in the via (BV) (step (5): FIG. 2 (i)). Thereafter, the surface layer connection pad (14) is subjected to a surface treatment to form an electroless plating layer (15), thereby producing a circuit board (16) for a semiconductor package (step (5 ′): FIG. 2 (j). )).
　本発明の半導体パッケージ用回路基板の製造方法の別の具体例を、図３（ａ）～（ｊ）のフローチャートに示す。図３（ａ）～（ｊ）の手順は、以下に説明する点を除き、図２（ａ）～（ｊ）の手順と同一である。即ち、めっきレジストを、配線基板のはんだボール搭載面（Ｓ２）側のみに形成する（工程（３’－２）：図３（ｆ））。これにより、工程（５）でエッチングによって除去すべき電解めっき層（１３）及び無電解めっき被膜（１１）の量が多くなるため（図３（ｈ）、（ｉ））、結果として得られる表層接続パッド（１４）の厚みは上述の例と比べると薄くなるが（図３（ｊ））、より簡便な操作で半導体パッケージ用回路基板（１８）を得ることができる。
　但し、以上の製造方法はあくまでも例であって、本発明の半導体パッケージ用回路基板の製造方法は、これに限定されるものではない。 Another specific example of the method for manufacturing a circuit board for a semiconductor package of the present invention is shown in the flowcharts of FIGS. The procedures of FIGS. 3A to 3J are the same as the procedures of FIGS. 2A to 2J except for the points described below. That is, a plating resist is formed only on the solder ball mounting surface (S2) side of the wiring board (step (3′-2): FIG. 3 (f)). This increases the amount of the electrolytic plating layer (13) and the electroless plating film (11) to be removed by etching in the step (5) (FIGS. 3 (h) and (i)), so that the resulting surface layer Although the thickness of the connection pad (14) is smaller than that of the above example (FIG. 3 (j)), the semiconductor package circuit board (18) can be obtained by a simpler operation.
However, the above manufacturing method is merely an example, and the manufacturing method of the circuit board for a semiconductor package of the present invention is not limited to this.
［半導体パッケージ用回路基板］
　本発明の別の側面は、本発明の半導体パッケージ用回路基板の製造方法により製造される半導体パッケージ用回路基板に関する。 [Circuit board for semiconductor packages]
Another aspect of the present invention relates to a circuit board for a semiconductor package manufactured by the method for manufacturing a circuit board for a semiconductor package of the present invention.
　本発明の半導体パッケージ用回路基板の構成の例を、図４に模式的に示す。図４に示すように、本発明の半導体パッケージ用回路基板（１６、１８）は、半導体チップ搭載面（Ｓ１）及びはんだボール搭載面（Ｓ２）を有するとともに、
（ａ）絶縁性基材（１）にスルーホール（ＴＨ）及び配線パターン（２）が形成されてなる配線基板（７）と、
（ｂ）配線基板（７）の表面に形成され、半導体チップ搭載面（Ｓ１）及びはんだボール搭載面（Ｓ２）の各々に複数のブラインドビア（ＢＶ）を有するソルダーレジスト（８）と、
（ｃ）半導体チップ搭載面（Ｓ１）の複数のブラインドビア（ＢＶ）に設けられ、配線パターンと導通してなる複数の表層接続パッド（１４）と、
（ｄ）はんだボール搭載面（Ｓ２）の複数のブラインドビア（ＢＶ）に設けられ、配線パターンと導通してなる複数のはんだボールパッド（９）と
を備える。更に任意により、その他の層（例えば表面処理層（図２及び３の符号１０、１５、１７）等）を設けてもよい。なお、各構成要素の詳細については、本発明の半導体パッケージ用回路基板の製造方法において上述したとおりである。 An example of the configuration of the circuit board for a semiconductor package of the present invention is schematically shown in FIG. As shown in FIG. 4, the semiconductor package circuit board (16, 18) of the present invention has a semiconductor chip mounting surface (S1) and a solder ball mounting surface (S2),
(A) a wiring substrate (7) in which a through hole (TH) and a wiring pattern (2) are formed on an insulating substrate (1);
(B) a solder resist (8) formed on the surface of the wiring board (7) and having a plurality of blind vias (BV) on each of the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2);
(C) a plurality of surface layer connection pads (14) provided in the plurality of blind vias (BV) on the semiconductor chip mounting surface (S1) and electrically connected to the wiring pattern;
(D) A plurality of solder ball pads (9) provided on the plurality of blind vias (BV) on the solder ball mounting surface (S2) and connected to the wiring pattern. Further, other layers (for example, a surface treatment layer ( reference numerals 10, 15, and 17 in FIGS. 2 and 3) and the like) may be provided optionally. The details of each component are as described above in the method for manufacturing a circuit board for a semiconductor package of the present invention.
　更に、本発明の半導体パッケージ用回路基板（１６、１８）は、半導体チップ搭載面（Ｓ１）とはんだボール搭載面（Ｓ２）とを連結する配線パターン（２ａ）上に形成されたブラインドビア（ＢＶ）のみならず、半導体チップ搭載面（Ｓ１）同士を連結する配線パターン（２ｂ）上に形成されたブラインドビア（ＢＶ）にも、表層接続パッド（１４）を有する。言い換えれば、本発明の半導体パッケージ用回路基板（１６、１８）は、表層接続パッドの少なくとも一部が、はんだボールパッドと導通していない配線パターンと導通してなる。これにより、全ての配線パターン（２ａ，２ｂ）について、確実に導通を確保することができる。斯かる構成は、はんだボール搭載面の無電解めっき被膜からブラインドビア内に電流を供給し、電解めっきにより埋め込みバンプを形成する従来技術（図１０（ｂ）：特許文献２（特開２０１１－６１１７９）等）では、達成できなかった構成である。 Furthermore, the circuit board (16, 18) for a semiconductor package of the present invention has a blind via (BV) formed on a wiring pattern (2a) connecting the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2). ) As well as the blind vias (BV) formed on the wiring pattern (2b) connecting the semiconductor chip mounting surfaces (S1) to each other, have the surface layer connection pads (14). In other words, in the semiconductor package circuit board (16, 18) of the present invention, at least a part of the surface layer connection pads is electrically connected to the wiring pattern that is not electrically connected to the solder ball pads. Thereby, conduction | electrical_connection can be ensured reliably about all the wiring patterns (2a, 2b). Such a configuration is a conventional technique in which a current is supplied from the electroless plating film on the solder ball mounting surface into the blind via and a buried bump is formed by electrolytic plating (FIG. 10B: Patent Document 2 (JP 2011-61179 A). ) Etc.) is a configuration that could not be achieved.
　また、本発明の半導体パッケージ用回路基板（１６、１８）は、一般的な半導体パッケージ用回路基板の製造において（例えば、フリップチップバンプパッドの表面処理や、埋め込みバンプの形成、表面処理等に）使用されるが、配線パターンとしては使用されない、不要なバスラインを有さない。これに対し、埋め込みバンプ形成用のバスラインを用いる従来技術（図１０（ａ）：特許文献１（特開昭５２－１２５７５）等）では、斯かる不要なバスライン等の存在が、配線高密度化の大きな妨げとなる上に、半導体パッケージの動作に悪影響を与える原因ともなっていた。よって、斯かるバスラインの配設を不要とした本発明の構成は、配線高密度化及び動作安定化の面で非常に有利である。 Further, the semiconductor package circuit boards (16, 18) of the present invention are used in the manufacture of general semiconductor package circuit boards (for example, for surface treatment of flip chip bump pads, formation of embedded bumps, surface treatment, etc.). Although used, it is not used as a wiring pattern and does not have unnecessary bus lines. On the other hand, in the prior art using the bus line for forming the embedded bump (FIG. 10A: Patent Document 1 (Japanese Patent Laid-Open No. 52-12575), etc.), the presence of such an unnecessary bus line is caused by the high wiring height. In addition to greatly hindering the density increase, the operation of the semiconductor package is adversely affected. Therefore, the configuration of the present invention that eliminates the need for such bus lines is very advantageous in terms of increasing the wiring density and stabilizing the operation.
　このように、本発明によれば、半導体パッケージ用回路基板の配線を従来よりも高密度化することができる。具体的に、本発明によれば、半導体パッケージ用回路基板のバンプピッチ（バンプ中心間の距離）を、例えば２００μｍ以下、中でも１３０μｍ以下とすることが可能となる。
　上述のように、本発明の半導体パッケージ用回路基板は、従来技術により作製される埋め込みバンプを有する半導体パッケージ用回路基板とは、構成上明確に差別化され、且つ、極めて顕著な効果を有することが明らかである。 As described above, according to the present invention, the wiring of the circuit board for semiconductor package can be made higher in density than in the past. Specifically, according to the present invention, the bump pitch (distance between the bump centers) of the circuit board for semiconductor package can be set to 200 μm or less, particularly 130 μm or less, for example.
As described above, the circuit board for semiconductor package of the present invention is clearly differentiated in configuration from the circuit board for semiconductor package having embedded bumps manufactured by the prior art, and has a very remarkable effect. Is clear.
［半導体パッケージ］
　本発明の別の側面は、本発明の半導体パッケージ用回路基板を用いた半導体パッケージに関する。本発明の半導体パッケージは、上述の本発明の半導体パッケージ用回路基板と、前記半導体パッケージ用回路基板の半導体チップ搭載面に設けられる半導体チップとを備え、前記半導体パッケージ用回路基板の表層接続パッドと半導体チップとの導通が確保された構成を有する。 [Semiconductor package]
Another aspect of the present invention relates to a semiconductor package using the semiconductor package circuit board of the present invention. A semiconductor package of the present invention includes the above-described semiconductor package circuit board of the present invention and a semiconductor chip provided on a semiconductor chip mounting surface of the semiconductor package circuit board, and a surface layer connection pad of the semiconductor package circuit board; It has a configuration in which conduction with a semiconductor chip is ensured.
　半導体チップとしては、ＣＰＵ、半導体メモリ（ＳＲＡＭ、ＤＲＡＭ等）等、種々のものが存在する。これらの半導体チップは、目的とする半導体パッケージの仕様や用途に応じて適宜選択され、半導体パッケージ用回路基板の半導体チップ搭載面に配置されて、半導体パッケージ用回路基板との導通が形成される。 There are various types of semiconductor chips such as a CPU and a semiconductor memory (SRAM, DRAM, etc.). These semiconductor chips are appropriately selected according to the specifications and applications of the target semiconductor package, and are arranged on the semiconductor chip mounting surface of the semiconductor package circuit board to form electrical continuity with the semiconductor package circuit board.
　半導体パッケージ用回路基板と半導体チップとの導通を形成する手法としては、ワイヤーボンディング、フリップチップボンディング等が挙げられるが、半導体チップの集積化及び半導体パッケージの小型化の観点から、本発明による半導体パッケージ用回路基板と半導体チップとの導通を形成する手法としては、フリップチップボンディングが好ましい。上述のように、フリップチップボンディングは、半導体チップの電極部に予め形成したバンプを、半導体パッケージ用回路基板の電極部（フリップチップバンプパッド）と電気的に接続する方法である。半導体チップの電極部のバンプとしては、一般的に金や銅等の金属からなるピラーやはんだボールが用いられ、これらは目的とする半導体パッケージの仕様や用途に応じて適宜選択される。 Examples of the method for forming electrical connection between the circuit board for semiconductor package and the semiconductor chip include wire bonding and flip chip bonding. From the viewpoint of integration of the semiconductor chip and miniaturization of the semiconductor package, the semiconductor package according to the present invention. As a technique for forming electrical connection between the circuit board for use and the semiconductor chip, flip chip bonding is preferable. As described above, flip chip bonding is a method of electrically connecting a bump formed in advance on an electrode portion of a semiconductor chip to an electrode portion (flip chip bump pad) of a circuit board for a semiconductor package. Generally, pillars and solder balls made of metal such as gold or copper are used as the bumps of the electrode portions of the semiconductor chip, and these are appropriately selected according to the specifications and applications of the target semiconductor package.
　本発明の半導体パッケージは、半導体チップの電極部（バンプ）を、本発明の半導体パッケージ用回路基板が有する表層接続パッドと接触させ、電気的に接続することにより構成される。これにより、半導体チップの実装時に容易且つ確実に、半導体チップの電極部（バンプ）との導通を確保することができる。通常は、導通が確保された状態で、半導体チップを半導体パッケージ用回路基板に対して接着等の手段で固定する。更に必要に応じて、他の電子部品の装着や筐体への収納等、各種の工程を加えてもよい。 The semiconductor package of the present invention is configured by bringing the electrode portions (bumps) of the semiconductor chip into contact with the surface layer connection pads of the semiconductor package circuit board of the present invention and electrically connecting them. Thereby, electrical continuity with the electrode part (bump) of the semiconductor chip can be ensured easily and reliably when the semiconductor chip is mounted. Normally, the semiconductor chip is fixed to the circuit board for semiconductor package by means such as adhesion in a state where conduction is ensured. Furthermore, various processes such as mounting of other electronic components and storage in a housing may be added as necessary.
［集積回路］
　本発明の別の側面は、本発明の半導体パッケージを用いた集積回路に関する。本発明の集積回路は、集積回路用基板と、前記集積回路用基板上に配置された上述の本発明の半導体パッケージとを備え、半導体パッケージが有するはんだボールと前記集積回路用基板との導通が確保された構成を有する。 [Integrated circuit]
Another aspect of the present invention relates to an integrated circuit using the semiconductor package of the present invention. An integrated circuit of the present invention includes an integrated circuit substrate and the above-described semiconductor package of the present invention disposed on the integrated circuit substrate, and electrical connection between a solder ball of the semiconductor package and the integrated circuit substrate is provided. It has a secured configuration.
　集積回路用基板は、半導体パッケージ等を搭載して集積回路を構成するための基板である。通常は、絶縁性基材に、スルーホール及び回路パターンが形成されるとともに、回路パターンと半導体パッケージとの導通を確保するための電極部が構成されてなる。 The integrated circuit substrate is a substrate on which an integrated circuit is configured by mounting a semiconductor package or the like. Usually, a through hole and a circuit pattern are formed on an insulating base material, and an electrode portion for ensuring electrical connection between the circuit pattern and the semiconductor package is formed.
　前記半導体パッケージのはんだボールと前記集積回路用基板の電極部との導通を形成する手法としても、ワイヤーボンディング、フリップチップボンディング等が挙げられるが、集積回路は半導体パッケージよりも大型であるため、その製造における導通の形成には主にはんだボールによる接続が用いられる。はんだボールによる接続は、半導体パッケージのはんだボールと集積回路用基板の電極部とを、はんだボールで連結する手法である。その具体的な条件等は、目的とする集積回路の仕様や用途に応じて適宜選択される。更に通常は、導通が確保された状態で、半導体パッケージを集積回路用基板に対して接着等の手段で固定する。また、必要に応じて、その他の電子部品の装着や筐体への収納等、各種の工程を加えてもよい。 As a method for forming the conduction between the solder ball of the semiconductor package and the electrode portion of the integrated circuit substrate, wire bonding, flip chip bonding, and the like can be cited. However, since the integrated circuit is larger than the semiconductor package, Connection by solder balls is mainly used to form continuity in manufacturing. The connection by the solder ball is a method of connecting the solder ball of the semiconductor package and the electrode part of the substrate for the integrated circuit with the solder ball. Specific conditions and the like are appropriately selected according to the specifications and application of the target integrated circuit. Further, usually, the semiconductor package is fixed to the integrated circuit substrate by means of adhesion or the like in a state where conduction is ensured. Moreover, you may add various processes, such as mounting | wearing of another electronic component, and storage to a housing | casing as needed.
　以下、実施例を用いて本発明をより詳細に説明するが、本発明はこれらの実施例に限定されるものではなく、その主旨を逸脱しない範囲で適宜変更を加えて実施することが可能である。 Hereinafter, the present invention will be described in more detail with reference to examples. However, the present invention is not limited to these examples, and can be implemented with appropriate modifications without departing from the gist thereof. is there.
［参考例］
・配線基板の作製：
　図１（ａ）～（ｇ）に示す手順に従って、絶縁性基材にスルーホール及び配線パターンが形成された配線基板を作製した（なお、図１は本発明の実施形態を説明するのに使用した図であるが、参考例における配線基板の製造手順の説明にも流用するものとする。）。具体的には以下の通りである。 [Reference example]
-Fabrication of wiring board:
In accordance with the procedure shown in FIGS. 1 (a) to 1 (g), a wiring board having through holes and wiring patterns formed on an insulating base material was produced (note that FIG. 1 is used to explain an embodiment of the present invention). This figure is also used to explain the manufacturing procedure of the wiring board in the reference example.) Specifically, it is as follows.
　まず、絶縁性基材（１）（厚さ０．１ｍｍ）の両面に銅箔（２）（厚さ１２μｍ）を有する銅張積層板（３）（三菱ガス化学株式会社製、ＣＣＬ－ＨＬ８３２ＨＳ）を準備した（図１（ａ））。 First, a copper-clad laminate (3) having a copper foil (2) (thickness 12 μm) on both sides of an insulating substrate (1) (thickness 0.1 mm) (CCL-HL832HS manufactured by Mitsubishi Gas Chemical Co., Ltd.) Was prepared (FIG. 1 (a)).
　次に、この銅張積層板（３）に対して、ＣＯ２レーザーによりスルーホール（ＴＨ）（穴径φ１００μｍ）を形成し、ハーフエッチング液ＳＥ－０７（三菱ガス化学株式会社製）により両面の銅箔（２）を厚さ５μｍまでエッチングし、アルカリ膨潤処理液・過マンガン酸塩系処理液でデスミヤ処理を行った（図１（ｂ））。 Next, a through hole (TH) (hole diameter φ100 μm) is formed on the copper-clad laminate (3) with a CO2 laser, and copper on both sides is formed with a half etching solution SE-07 (Mitsubishi Gas Chemical Co., Ltd.). The foil (2) was etched to a thickness of 5 μm, and desmeared with an alkali swelling treatment liquid / permanganate treatment liquid (FIG. 1B).
　続いて、この銅張積層板（３）のスルーホール（ＴＨ）内を含む全面に、アクチベータネオガントＵ（アトテック株式会社製）を用いてパラジウム触媒を付着させ（０．１ｍｇ／ｄｍ２）、プリントガントＰ－ＤＫ（アトテック株式会社製）を用いて無電解銅めっきを施し、パラジウム触媒を含む無電解銅めっき層（４）（厚さ１μｍ）を形成した（図１（ｃ））。 Subsequently, a palladium catalyst was attached to the entire surface including the inside of the through hole (TH) of the copper-clad laminate (3) using an activator Neogant U (manufactured by Atotech Co., Ltd.) (0.1 mg / dm2), and printing was performed. Electroless copper plating was performed using Gantt P-DK (Atotech Co., Ltd.) to form an electroless copper plating layer (4) (thickness 1 μm) containing a palladium catalyst (FIG. 1 (c)).
　次に、この無電解銅めっき層（４）を電源供給層として、銅による電解パネルめっきを施し、電解銅めっき層（５）（厚さ１５μｍ）を形成した（図１（ｄ））。 Next, using this electroless copper plating layer (4) as a power supply layer, electrolytic panel plating with copper was performed to form an electrolytic copper plating layer (5) (thickness: 15 μm) (FIG. 1 (d)).
　その後、両面にめっきレジスト（ドライフィルム）（６）をラミネートし、パターンマスクフィルムを用いて露光、現像し、めっきレジスト（ドライフィルム）（６）のパターン化を行った（図１（ｅ））。 Thereafter, a plating resist (dry film) (6) was laminated on both sides, exposed and developed using a pattern mask film, and patterning of the plating resist (dry film) (6) was performed (FIG. 1 (e)). .
　続いて、塩化銅液にてエッチングを行い、めっきレジスト（ドライフィルム）（６）が存在しない領域の無電解銅めっき層（４）及び電解銅めっき層（５）を除去した（図１（ｆ））。 Subsequently, etching was performed with a copper chloride solution to remove the electroless copper plating layer (4) and the electrolytic copper plating layer (5) in the region where the plating resist (dry film) (6) does not exist (FIG. 1 (f )).
　その後、苛性ソーダ液でめっきレジスト（ドライフィルム）（６）を除去することにより、絶縁性基材にスルーホール（ＴＨ）及び配線パターン（２）が形成された配線基板（７）を得た（図１（ｇ））。 Thereafter, the plating resist (dry film) (6) was removed with caustic soda solution to obtain a wiring board (7) in which through holes (TH) and a wiring pattern (2) were formed on the insulating base material (FIG. 1 (g)).
［実施例１］
・半導体パッケージ用回路基板の作製：
　参考例の手順で得られた配線基板（７）を用い、図２（ａ）～（ｊ）に示す手順に従って、以下に説明する通りに半導体パッケージ用回路基板（１６）を作製した（なお、図２は本発明の実施形態を説明するのに使用した図であるが、実施例１における半導体パッケージ用回路基板の製造手順の説明にも流用するものとする。）。 [Example 1]
-Fabrication of circuit boards for semiconductor packages:
Using the wiring board (7) obtained by the procedure of the reference example, a semiconductor package circuit board (16) was produced as described below in accordance with the procedure shown in FIGS. FIG. 2 is a diagram used to explain the embodiment of the present invention, but it is also used to explain the manufacturing procedure of the circuit board for semiconductor package in Example 1.
　まず、参考例の手順で得られた配線基板（７）を用意し（図２（ａ））、その電解銅めっき層（５）表面に、エッチボンドＣＺ－８１００（メック株式会社製）で表面粗化処理を施した後、感光性ソルダーレジストインクＰＳＲ－４０００ＡＵＳ３０８（太陽インキ製造株式会社製）をロールコーティングし、乾燥した（乾燥後厚さ３０μｍ）。続いて、パターンマスクを介してＵＶ露光し、炭酸ソーダ水溶液で現像して、配線パターン（２）を露出させることにより、はんだボール搭載面にはんだボールパッド（９）を有するソルダーレジスト層（８）を形成した（工程（１）：図２（ｂ））。 First, a wiring board (7) obtained by the procedure of the reference example was prepared (FIG. 2 (a)), and the surface of the electrolytic copper plating layer (5) was etched with etch bond CZ-8100 (MEC Co., Ltd.). After the roughening treatment, photosensitive solder resist ink PSR-4000AUS308 (manufactured by Taiyo Ink Manufacturing Co., Ltd.) was roll-coated and dried (thickness after drying: 30 μm). Subsequently, the solder resist layer (8) having a solder ball pad (9) on the solder ball mounting surface is exposed by UV exposure through a pattern mask and developed with a sodium carbonate aqueous solution to expose the wiring pattern (2). (Step (1): FIG. 2B).
　得られたソルダーレジスト層（８）のはんだボールパッド（９）表面に、バスラインを使用して電解ニッケルめっき層及び電解金めっき層（１０）を形成した（図２（ｃ））。
　その後、半導体チップ搭載面のソルダーレジスト層（８）に、ＵＶ－ＹＡＧレーザーを用いてトレパニング加工によりブラインドビア（ＢＶ）（開口部径φ５０μｍ、底部径φ３０μｍ）を形成した（工程（２）：図２（ｄ））。 An electrolytic nickel plating layer and an electrolytic gold plating layer (10) were formed on the surface of the solder ball pad (9) of the obtained solder resist layer (8) using a bus line (FIG. 2 (c)).
Thereafter, blind vias (BV) (opening diameter φ50 μm, bottom diameter φ30 μm) were formed in the solder resist layer (8) on the semiconductor chip mounting surface by trepanning using a UV-YAG laser (step (2): FIG. 2 (d)).
　続いて、ジェットスクラブ処理（パーミス＃２４０、６０秒）を施してソルダーレジスト層（８）表面を粗化した後（工程（２’））、アクチベータネオガントＵ（アトテック株式会社製）により全面にパラジウム触媒を付着し（０．１ｍｇ／ｄｍ２）、プリントガントＰ－ＤＫ（アトテック株式会社製）により全面に無電解銅めっきを施し、パラジウム触媒を含む無電解銅めっき被膜（１１）（厚さ１μｍ）を形成した（工程（３）：図２（ｅ））。 Subsequently, the surface of the solder resist layer (8) is roughened by applying a jet scrub process (Permis # 240, 60 seconds) (step (2 ′)), and then the entire surface is activated by an activator Neogant U (manufactured by Atotech Co., Ltd.). A palladium catalyst was adhered (0.1 mg / dm 2 ), electroless copper plating was applied to the entire surface by Print Gantt P-DK (Atotech Co., Ltd.), and an electroless copper plating film (11) containing the palladium catalyst (thickness) 1 μm) was formed (step (3): FIG. 2 (e)).
　その後、両面にめっきレジスト（ドライフィルム）（１２）をラミネートし（工程（３’－１））、パターンマスクフィルムを用いて露光、現像し、半導体チップ搭載面のブラインドビア（ＢＶ）部分のめっきレジスト（ドライフィルム）（１２）を除去した。はんだボール面は全面めっきレジスト（ドライフィルム）（１２）を残した（工程（３’－２）：図２（ｆ））。 Thereafter, a plating resist (dry film) (12) is laminated on both surfaces (step (3'-1)), exposed and developed using a pattern mask film, and plating on the blind via (BV) portion of the semiconductor chip mounting surface The resist (dry film) (12) was removed. The entire surface of the solder ball was left with a plating resist (dry film) (12) (step (3'-2): FIG. 2 (f)).
　次に、半導体チップ搭載面の無電解銅めっき被膜（１１）を電源供給層として、ＴＦ－II（荏原ユージライト株式会社製）により電解銅めっきによるビアフィリングを施し、ブラインドビア（ＢＶ）を充填するように電解銅めっき層（１３）を形成した。ブラインドビア（ＢＶ）以外の部分の電解銅めっき層（１３）の厚さは１５μｍであった（工程（４）：図２（ｇ））。
　続いて、苛性ソーダ液により全面のめっきレジスト（ドライフィルム）（１２）を除去した（工程（４’）：図２（ｈ））。 Next, with the electroless copper plating film (11) on the semiconductor chip mounting surface as the power supply layer, via filling by electrolytic copper plating is performed with TF-II (manufactured by Sugawara Eugene Corporation), and the blind via (BV) is filled. Thus, an electrolytic copper plating layer (13) was formed. The thickness of the electrolytic copper plating layer (13) other than the blind via (BV) was 15 μm (step (4): FIG. 2 (g)).
Subsequently, the plating resist (dry film) (12) on the entire surface was removed with a caustic soda solution (step (4 ′): FIG. 2 (h)).
　次に、ＣＰＥ－８１０（三菱ガス化学株式会社製）によってブラインドビア（ＢＶ）部以外の電解銅めっき層（１３）及び無電解銅めっき被膜（１１）を除去し、更にメックリムーバーＰＪ－９７１０（メック株式会社）によってパラジウム除去処理を行うことにより、表層接続パッド（１４）を形成した（工程（５）：図２（ｉ））。 Next, the electrolytic copper plating layer (13) and the electroless copper plating film (11) other than the blind via (BV) portion are removed by CPE-810 (manufactured by Mitsubishi Gas Chemical Co., Ltd.). The surface layer connection pad (14) was formed by performing a palladium removal process by MEC Co., Ltd. (step (5): FIG. 2 (i)).
　その後、両面にめっきレジスト（ドライフィルム）をラミネートし、露光し、現像して、半導体チップ搭載面のめっきレジスト（ドライフィルム）を除去した後、表層接続パッド（１４）上に表面処理として、ＩＣＰニコロンＧＩＢ（奥野製薬工業株式会社製）により無電解ニッケルめっき（５μｍ）、ネオパラブライト（高純度化学株式会社製）により無電解パラジウムめっき（０．０６μｍ）、及びゴブライトＴＷＸ－４０（上村工業株式会社製）により無電解金めっき（０．１μｍ）を施し、無電解ニッケル／パラジウム／金めっき層（１５）を形成した（工程（５’）：図２（ｊ））。
　以上の手順により、半導体パッケージ用回路基板（１６）を作製した。 Thereafter, a plating resist (dry film) is laminated on both sides, exposed, developed, and the plating resist (dry film) on the semiconductor chip mounting surface is removed. Electroless nickel plating (5 μm) by Nicolon GIB (Okuno Pharmaceutical Co., Ltd.), electroless palladium plating (0.06 μm) by Neoparabright (High Purity Chemical Co., Ltd.), and Gobright TWX-40 (Uemura Industry Co., Ltd.) Electroless gold plating (0.1 μm) was applied to form an electroless nickel / palladium / gold plating layer (15) (step (5 ′): FIG. 2 (j)).
The semiconductor package circuit board (16) was produced by the above procedure.
・半導体パッケージ用回路基板の評価：
　上記手順で得られた半導体パッケージ用回路基板（１６）を、走査型電子顕微鏡（ＳＥＭ）及び光学顕微鏡で観察し、表層接続パッド（１４）の形状を測定したところ、上面径φ４５μｍ、底面径φ３２μｍ、高さ２５μｍ、ソルダーレジスト層（８）表面から表層接続パッド（１４）上面までの高さの差は３μｍであった。表層接続パッド（１４）領域のＳＥＭによる表面写真を図５（ａ１）に、光学顕微鏡による断面写真を図５（ａ２）に夫々示す。
　また、上記手順で得られた半導体パッケージ用回路基板（１６）のバンプピッチは、平均１００μｍであった。 ・ Evaluation of circuit boards for semiconductor packages:
The semiconductor package circuit board (16) obtained by the above procedure was observed with a scanning electron microscope (SEM) and an optical microscope, and the shape of the surface connection pad (14) was measured. As a result, the top surface diameter was 45 μm and the bottom surface diameter was 32 μm. The height difference from the surface of the solder resist layer (8) to the upper surface of the surface layer connection pad (14) was 3 μm. A surface photograph by SEM of the surface layer connection pad (14) region is shown in FIG. 5 (a1), and a cross-sectional photograph by an optical microscope is shown in FIG. 5 (a2).
Moreover, the bump pitch of the circuit board for semiconductor packages (16) obtained by the above procedure was an average of 100 μm.
　また、上記手順で得られた半導体パッケージ用回路基板（１６）について、配線パターン（２）によって連結された表層接続パッド（１４）とはんだボールパッド（９）上の電解めっき層（１０）との間の導通、及び、配線パターン（２）によって連結された表層接続パッド（１４）同士の導通を、導通テスター（横川電気株式会社製７５５５）により検証したところ、何れも導通が確保されており、接続不良は発生しなかった。 Further, for the semiconductor package circuit board (16) obtained by the above procedure, the surface layer connection pad (14) connected by the wiring pattern (2) and the electrolytic plating layer (10) on the solder ball pad (9). The conduction between the surface connection pads (14) connected by the wiring pattern (2) and the conduction between the surface layer connection pads (14) was verified by a conduction tester (Yokogawa Electric Corporation 7555). There was no connection failure.
［実施例２］
・半導体パッケージ用回路基板の作製：
　参考例の手順で得られた配線基板（７）を用い、図３（ａ）～（ｊ）に示す手順に従って、半導体パッケージ用回路基板（１８）を作製した（なお、図３は本発明の実施形態を説明するのに使用した図であるが、実施例２における半導体パッケージ用回路基板の製造手順の説明にも流用するものとする。）。その手順は、以下に説明する点を除き、図２（ａ）～（ｊ）に示す実施例１の手順と同様である。 [Example 2]
-Fabrication of circuit boards for semiconductor packages:
Using the wiring board (7) obtained by the procedure of the reference example, a semiconductor package circuit board (18) was produced according to the procedure shown in FIGS. 3 (a) to 3 (j). Although it is a figure used to explain the embodiment, it is also used for explanation of the manufacturing procedure of the circuit board for semiconductor package in Example 2. The procedure is the same as the procedure of the first embodiment shown in FIGS. 2A to 2J except for the points described below.
　まず、レーザーによるブラインドビア（ＢＶ）の形成時（図３（ｄ））に、ブラインドビア（ＢＶ）の開口部径をφ４５μｍ、底部径をφ２５μｍとした。 First, at the time of forming a blind via (BV) by a laser (FIG. 3D), the opening diameter of the blind via (BV) was set to 45 μm and the bottom diameter was set to 25 μm.
　また、めっきレジスト（ドライフィルム）（１２）の形成時（図３（ｆ））に、半導体チップ搭載面（Ｓ１）にはめっきレジスト（１２）を形成せず、はんだボール搭載面（Ｓ２）のみにめっきレジスト（１２）を形成した。 Further, when the plating resist (dry film) (12) is formed (FIG. 3 (f)), the plating resist (12) is not formed on the semiconductor chip mounting surface (S1), and only the solder ball mounting surface (S2). A plating resist (12) was formed on the substrate.
　また、表層接続パッド（１４）の形成後の表面処理の際（図３（ｊ））に、スタナテック２０００Ｖ（アトテックジャパン株式会社製）により無電解錫めっき（厚さ１．５μｍ）を施し、無電解錫めっき層（１７）を形成した。 In addition, during the surface treatment after the formation of the surface connection pad (14) (FIG. 3 (j)), electroless tin plating (thickness 1.5 μm) is applied by Stanatech 2000V (manufactured by Atotech Japan Co., Ltd.) An electrolytic tin plating layer (17) was formed.
・半導体パッケージ用回路基板の評価：
　上記手順で得られた半導体パッケージ用回路基板（１８）について、実施例１と同様の手法により、表層接続パッド（１４）の形状を測定したところ、上面径φ３２μｍ、底面径φ２６μｍ、高さ２４μｍ、ソルダーレジスト層（８）表面から表層接続パッド（１４）上面までの高さの差は５μｍであった。表層接続パッド（１４）領域のＳＥＭによる表面写真を図５（ｂ１）に、光学顕微鏡による断面写真を図５（ｂ２）に夫々示す。
　また、上記手順で得られた半導体パッケージ用回路基板（１８）のバンプピッチは、平均１００μｍであった。 ・ Evaluation of circuit boards for semiconductor packages:
With respect to the semiconductor package circuit board (18) obtained by the above procedure, the shape of the surface connection pad (14) was measured in the same manner as in Example 1. As a result, the top surface diameter was 32 μm, the bottom surface diameter was 26 μm, the height was 24 μm, The difference in height from the surface of the solder resist layer (8) to the upper surface of the surface layer connection pad (14) was 5 μm. A surface photograph of the surface layer connection pad (14) region by SEM is shown in FIG. 5 (b1), and a cross-sectional photograph by an optical microscope is shown in FIG. 5 (b2).
In addition, the bump pitch of the semiconductor package circuit board (18) obtained by the above procedure was 100 μm on average.
　また、上記手順で得られた半導体パッケージ用回路基板（１８）について、配線パターン（２）によって連結された表層接続パッド（１４）とはんだボールパッド（９）上の電解めっき層（１０）との間の導通、及び、配線パターン（２）によって連結された表層接続パッド（１４）同士の導通を、実施例１と同様の手法で検証したところ、接続不良は発生しなかった。 Further, for the semiconductor package circuit board (18) obtained by the above procedure, the surface layer connection pad (14) connected by the wiring pattern (2) and the electrolytic plating layer (10) on the solder ball pad (9). The connection between the surface connection pads (14) connected by the wiring pattern (2) and the connection between the surface layer connection pads (14) was verified by the same method as in Example 1, and no connection failure occurred.
　本発明によれば、バスライン等の余剰な配線を設けることなく、全てのブラインドビア内に表層接続パッドが形成された半導体パッケージ用回路基板を、簡便且つ安価に作製することができる。また、得られる半導体パッケージ用回路基板は、半導体チップ実装時の容易且つ確実な導通確保と、半導体パッケージの配線高密度化とを共に達成可能である。よって、本発明は、半導体パッケージ及び集積回路の分野において、多大なる利用可能性を有する。 According to the present invention, it is possible to easily and inexpensively manufacture a semiconductor package circuit board in which surface connection pads are formed in all the blind vias without providing extra wiring such as a bus line. In addition, the obtained circuit board for a semiconductor package can achieve both easy and reliable conduction when mounting a semiconductor chip and high wiring density of the semiconductor package. Thus, the present invention has great applicability in the field of semiconductor packages and integrated circuits.
　１　　絶縁性基材
　２　　金属層（銅箔）／配線パターン
　３　　金属積層板（銅張積層板）
　４　　無電解めっき被膜（無電解銅めっき）
　５　　電解めっき層（電解銅めっき）
　６　　めっきレジスト（ドライフィルム）
　７　　配線基板
　８　　ソルダーレジスト層
　９　　はんだボールパッド
　１０　　表面処理層（電解ニッケル／金めっき）
　１１　　無電解めっき被膜（無電解銅めっき）
　１２　　めっきレジスト（ドライフィルム）
　１３　　電解めっき層（電解銅めっき）
　１４　　表層接続パッド
　１５　　表面処理層（無電解ニッケル／パラジウム／金めっき）
　１６　　半導体パッケージ用回路基板
　１７　　表面処理層（無電解錫めっき）
　１８　　半導体パッケージ用回路基板
　１００　　半導体パッケージ用回路基板
　１００”　　埋め込みバンプを有する半導体パッケージ用回路基板
　１０１　　絶縁性基材
　１０２　　配線パターン
　１０３　　配線基板
　１０４　　ソルダーレジスト
　１０５　　電極部（フリップチップバンプパッド）
　１０５ａ　　半導体チップ搭載面とはんだボール搭載面とを接続するフリップチップバンプパッド
　１０５ｂ　　半導体チップ搭載面同士を接続するフリップチップバンプパッド
　１０６　　はんだボールパッド
　１０７　　埋め込みバンプ
　１０８　　バスライン
　１０９　　給電用無電解銅めっき被膜
　２００，２００’　　半導体チップ
　２００”　　埋め込みバンプを用いた半導体パッケージ
　２０１　　バンプ（はんだ）
　２０１’　　バンプ（ピラー）
　３００　　はんだボール
　９００，９００’，９００”　　半導体パッケージ
　ＢＶ　　ブラインドビア
　Ｏ　　開口部
　Ｓ１　　半導体チップ搭載面
　Ｓ２　　はんだボール搭載面
　ＴＨ　　スルーホール DESCRIPTION OF SYMBOLS 1 Insulating base material 2 Metal layer (copper foil) / wiring pattern 3 Metal laminated board (copper clad laminated board)
4 Electroless plating film (electroless copper plating)
5 Electrolytic plating layer (electrolytic copper plating)
6 Plating resist (dry film)
7 Wiring board 8 Solder resist layer 9 Solder ball pad 10 Surface treatment layer (electrolytic nickel / gold plating)
11 Electroless plating film (electroless copper plating)
12 Plating resist (dry film)
13 Electrolytic plating layer (Electrolytic copper plating)
14 Surface layer connection pad 15 Surface treatment layer (electroless nickel / palladium / gold plating)
16 Circuit board for semiconductor package 17 Surface treatment layer (electroless tin plating)
DESCRIPTION OF SYMBOLS 18 Circuit board for semiconductor packages 100 Circuit board for semiconductor packages 100 "Circuit board for semiconductor packages having embedded bumps 101 Insulating substrate 102 Wiring pattern 103 Wiring board 104 Solder resist 105 Electrode portion (flip chip bump pad)
105a Flip chip bump pad for connecting semiconductor chip mounting surface and solder ball mounting surface 105b Flip chip bump pad for connecting semiconductor chip mounting surfaces 106 Solder ball pad 107 Embedded bump 108 Bus line 109 Electroless copper plating film for feeding 200 , 200 'Semiconductor chip 200 "Semiconductor package using embedded bump 201 Bump (solder)
201 'Bump (pillar)
300 Solder ball 900, 900 ', 900 "Semiconductor package BV Blind via O Opening S1 Semiconductor chip mounting surface S2 Solder ball mounting surface TH Through hole

Claims (13)

  1. 　半導体チップ搭載面及びはんだボール搭載面を有する半導体パッケージ用回路基板を製造する方法であって、
    （１）絶縁性基材にスルーホール及び配線パターンが形成されてなる配線基板の表面に、ソルダーレジストを形成する工程、
    （２）前記（１）で形成された半導体チップ搭載面側のソルダーレジストに対して、レーザーにより穴径１００μｍ以下のブラインドビアを形成する工程、
    （３）前記（２）で形成されたブラインドビアを有する半導体チップ搭載面側のソルダーレジスト表面に、無電解めっき被膜を形成する工程、
    （４）前記（３）で表面に無電解めっき被膜を形成されたソルダーレジストのブラインドビアに対して、電解めっきによりビアフィリングを行い、電解めっき層を形成する工程、及び、
    （５）半導体チップ搭載面側のソルダーレジスト表面のブラインドビア以外の部分について、前記（４）で形成された電解めっき層、及び、前記（３）で形成された無電解めっき被膜をエッチングにより除去し、ソルダーレジストを露出させることにより、ブラインドビア内に電解めっき層及び無電解めっき被膜からなる表層接続パッドを形成する工程、
    を有する方法。     A method of manufacturing a circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface,
    (1) A step of forming a solder resist on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material;
    (2) A step of forming a blind via having a hole diameter of 100 μm or less by a laser with respect to the solder resist on the semiconductor chip mounting surface side formed in (1),
    (3) A step of forming an electroless plating film on the solder resist surface on the semiconductor chip mounting surface side having the blind via formed in (2),
    (4) A step of forming an electroplating layer by performing via filling by electrolytic plating on a solder resist blind via having an electroless plating film formed on the surface thereof in (3), and
    (5) For portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side, the electrolytic plating layer formed in the above (4) and the electroless plating film formed in the above (3) are removed by etching. And, by exposing the solder resist, forming a surface connection pad made of an electrolytic plating layer and an electroless plating film in the blind via,
    Having a method.
  2. 　前記（３）で形成された無電解めっき被膜を給電層として、前記（４）の電解めっきによるビアフィリングを行う、請求項１に記載の方法。 2. The method according to claim 1, wherein via filling by electrolytic plating of (4) is performed using the electroless plating film formed in (3) as a power feeding layer.
  3. 　前記（３）と前記（４）との間に、
    （３’－１）前記（３）で表面に無電解めっき被膜を形成されたソルダーレジストを有する配線基板の両面に、めっきレジストを形成する工程、及び、
    （３’－２）前記（３’－１）で形成されためっきレジストに対して、少なくとも半導体チップ搭載面側のソルダーレジストのブラインドビアが露出するように、開口部を形成する工程、
    を有すると共に、
    前記（４）と前記（５）との間に、
    （４’）前記（３’－１）で形成されためっきレジストを除去する工程、
    を有する、請求項１又は２に記載の方法。     Between (3) and (4) above,
    (3′-1) a step of forming a plating resist on both surfaces of a wiring substrate having a solder resist having an electroless plating film formed on the surface thereof in (3), and
    (3′-2) a step of forming an opening so that at least a blind via of a solder resist on the semiconductor chip mounting surface side is exposed to the plating resist formed in (3′-1);
    And having
    Between (4) and (5) above,
    (4 ′) a step of removing the plating resist formed in (3′-1),
    The method according to claim 1, comprising:
  4. 　前記（２）のレーザーによるブラインドビアの形成を、ＵＶレーザーを用いて行う、請求項１～３の何れか一項に記載の方法。 The method according to any one of claims 1 to 3, wherein the blind via formation by the laser of (2) is performed using a UV laser.
  5. 　前記（２）のＵＶレーザーによるブラインドビアの形成を、トレパニング加工により行う、請求項４に記載の方法。 The method according to claim 4, wherein the formation of the blind via by the UV laser of (2) is performed by trepanning.
  6. 　前記（３）の無電解めっきが、無電解銅めっきである、請求項１～５の何れか一項に記載の方法。 The method according to any one of claims 1 to 5, wherein the electroless plating of (3) is electroless copper plating.
  7. 　前記（５）の後に、
    （５’）前記（５）のエッチング後におけるブラインドビア内の表層接続パッドに表面処理を施す工程、
    を有する、請求項１～６の何れか一項に記載の方法。     After (5) above
    (5 ′) a step of surface-treating the surface layer connection pad in the blind via after the etching of (5),
    The method according to any one of claims 1 to 6, comprising:
  8. 　前記（５’）の表面処理が、無電解錫めっき処理、無電解金めっき処理、無電解ニッケル金めっき処理、無電解ニッケルパラジウム金めっき処理、及び有機防錆処理から選択される、請求項７に記載の方法。 The surface treatment of (5 ′) is selected from electroless tin plating, electroless gold plating, electroless nickel gold plating, electroless nickel palladium gold plating, and organic rust prevention treatment. The method described in 1.
  9. 　請求項１～８の何れか一項に記載の方法で製造された半導体パッケージ用回路基板。 A circuit board for a semiconductor package manufactured by the method according to any one of claims 1 to 8.
  10. 　半導体チップ搭載面及びはんだボール搭載面を有する半導体パッケージ用回路基板であって、
    （ａ）絶縁性基材にスルーホール及び配線パターンが形成されてなる配線基板と、
    （ｂ）配線基板の表面に形成され、半導体チップ搭載面及びはんだボール搭載面の各々に複数のブラインドビアを有するソルダーレジストと、
    （ｃ）半導体チップ搭載面の複数のブラインドビアに設けられ、配線パターンと導通してなる複数の表層接続パッドと、
    （ｄ）はんだボール搭載面の複数のブラインドビアに設けられ、配線パターンと導通してなる複数のはんだボールパッドとを備え、且つ、
    （ｉ）表層接続パッドの少なくとも一部が、はんだボールパッドと導通していない配線パターンと導通してなるとともに、
    （ii）半導体パッケージ用基板の製造に使用されるが配線パターンとしては使用されない、バスラインを有さない
    ことを特徴とする、半導体パッケージ用回路基板。     A circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface,
    (A) a wiring board in which through holes and wiring patterns are formed on an insulating substrate;
    (B) a solder resist formed on the surface of the wiring board and having a plurality of blind vias on each of the semiconductor chip mounting surface and the solder ball mounting surface;
    (C) a plurality of surface layer connection pads provided in the plurality of blind vias on the semiconductor chip mounting surface and connected to the wiring pattern;
    (D) provided with a plurality of blind vias on the solder ball mounting surface, and provided with a plurality of solder ball pads connected to the wiring pattern; and
    (I) At least a part of the surface layer connection pad is electrically connected to a wiring pattern that is not electrically connected to the solder ball pad,
    (Ii) A circuit board for a semiconductor package, which is used for manufacturing a substrate for a semiconductor package but is not used as a wiring pattern and does not have a bus line.
  11. 　請求項９又は１０に記載の半導体パッケージ用回路基板と、前記半導体パッケージ用回路基板の半導体チップ搭載面に設けられる半導体チップとを備え、前記半導体パッケージ用回路基板のはんだボールパッドにはんだボールが設けられ、前記半導体パッケージ用回路基板の表層接続パッドと前記半導体チップとの導通が確保された、半導体パッケージ。 11. A circuit board for semiconductor package according to claim 9 or 10, and a semiconductor chip provided on a semiconductor chip mounting surface of the circuit board for semiconductor package, and solder balls are provided on solder ball pads of the circuit board for semiconductor package. A semiconductor package in which electrical connection between a surface layer connection pad of the semiconductor package circuit board and the semiconductor chip is ensured.
  12. 　前記半導体パッケージ用回路基板の表層接続パッドと前記半導体チップとの導通がフリップチップボンディングで形成される、請求項１１に記載の半導体パッケージ。 12. The semiconductor package according to claim 11, wherein conduction between a surface layer connection pad of the semiconductor package circuit board and the semiconductor chip is formed by flip chip bonding.
  13. 　集積回路用基板と、前記集積回路用基板上に配置された請求項１１又は１２に記載の半導体パッケージとを備え、前記半導体パッケージのはんだボールと前記集積回路用基板との導通が確保された、集積回路。 An integrated circuit substrate and the semiconductor package according to claim 11 disposed on the integrated circuit substrate, wherein conduction between the solder balls of the semiconductor package and the integrated circuit substrate is ensured. Integrated circuit.
PCT/JP2013/070783 2012-08-07 2013-07-31 Circuit board for semiconductor package and method for producing same WO2014024754A1 (en)

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