WO2014008685A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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Publication number
WO2014008685A1
WO2014008685A1 PCT/CN2012/079177 CN2012079177W WO2014008685A1 WO 2014008685 A1 WO2014008685 A1 WO 2014008685A1 CN 2012079177 W CN2012079177 W CN 2012079177W WO 2014008685 A1 WO2014008685 A1 WO 2014008685A1
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Prior art keywords
gate
source
layer
stack structure
stress
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PCT/CN2012/079177
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English (en)
French (fr)
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殷华湘
梁擎擎
马小龙
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中国科学院微电子研究所
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Publication of WO2014008685A1 publication Critical patent/WO2014008685A1/zh
Priority to US14/266,521 priority Critical patent/US8936988B2/en

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    • H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
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Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a MOSFET using a high stress overlay stress memory method. Background technique
  • the Strain Channel Engineering has become more and more important to improve the channel carrier mobility.
  • a variety of uniaxial process induced stresses are integrated into the device process, that is, introducing compressive or tensile stresses in the channel direction to enhance carrier mobility and improve device performance.
  • an embedded SiGe (e-SiGe) source-drain or 100-crystal substrate is combined with a tensile stress etch barrier (tCESL) to provide compressive stress in a pMOS device; in the 65nm process, Based on the 90nm process, the first-generation source-drain stress memory technology (SMT X 1 ) is used, and a double-etch barrier layer is used. In the 45-nm process, the second-generation source-drain stress memory technology is used.
  • tCESL tensile stress etch barrier
  • SMT X2 using e-SiGe technology combined with single tCESL or dual CESL, and using Stress Proximity Technique (SPT), in addition to 110-sided substrate for pMOS and 100-sided substrate for nMOS; 32nm
  • SPT Stress Proximity Technique
  • SMT X3 third-generation source-drain stress memory technology
  • the embedded SiC source and drain were also selected to enhance the tensile stress in the nMOS device.
  • the technique of introducing stress into the channel can be realized by controlling the material and the cross-sectional shape of the channel or the side wall, in addition to changing the substrate and the source and drain materials.
  • double stress liner (DSL) technology is used, for nMOS, the tensile stress is ⁇ 1 ⁇ layer sidewall, and for pMOS, the compressive stress sidewall is used.
  • the cross section of the embedded SiGe source drain is formed into a meander shape to improve the channel stress of the pMOS.
  • the usual preparation method of DLC is to use magnetic filtration pulse cathode vacuum arc discharge (FCVA).
  • FCVA magnetic filtration pulse cathode vacuum arc discharge
  • the DLC structure is more similar to diamond instead of graphite, thus increasing the intrinsic stress.
  • this high stress DLC FCVA fabrication process is not a standard process for integrated circuit fabrication, such as incompatibility with common CMOS processes, requiring additional manufacturing equipment, process, and time cost.
  • the FCVA method will bring more particles, which affects the subsequent process of the integrated circuit, for example, the residual particles between the fine structures cause unnecessary conduction or insulation, or the subsequent film deposition is uneven, and the device thermal stress occurs. Changes, etc., reduce the reliability of the device.
  • the inventors' prior application discloses that high quality DLC can be deposited by methods such as PECVD, magnetron sputtering, etc., and the stress of the DLC can be adjusted by controlling the process parameters.
  • the DLC material itself is a diamond-like film, its hardness is high and the step coverage is poor, which faces many difficulties in the process for the stress liner layer.
  • One difficulty that can be envisioned is that when the DLC stress layer is covered on the gate, the gate spacer, and the source and drain regions, the DLC stress layer that is ultimately retained by the overall size of the device may be thin (eg, 10 to 50 nm). Due to the poor coverage of the steps, the DLC film near the foot where the gate spacer intersects the source and drain regions may be thinner or even missing, and this portion is closest to the channel region of the device, so the channel region cannot be effectively moved at the portion.
  • the existing high-stress DLC technology has the disadvantage of poor step coverage, and it is difficult to effectively increase the carrier mobility in the channel region, and it is also difficult to effectively improve the device driving capability.
  • an object of the present invention is to provide a semiconductor device manufacturing method capable of effectively applying stress to a channel region to improve carrier mobility.
  • the present invention provides a method of fabricating a semiconductor device, comprising: forming a gate stack junction on a substrate Forming a dummy gate spacer around the gate stack structure; depositing a stress pad layer of DLC material on the substrate, the gate stack structure, and the dummy gate sidewall; performing annealing to make the gate stack structure and the gate stack.
  • the channel region in the substrate under the structure memorizes the stress in the stress pad; the dummy gate spacer is removed; and the gate spacer is formed around the gate stack.
  • the gate stack structure is a dummy gate stack structure including a pad oxide layer and a dummy gate material layer, and the dummy gate material layer comprises polysilicon, amorphous silicon, and microcrystalline silicon.
  • the dummy gate spacer and/or the gate spacer include silicon nitride and silicon oxynitride.
  • the source and drain regions are formed in the substrate on both sides of the dummy gate sidewall.
  • the source and drain regions include lightly doped source and drain extension regions and/or halo source and drain doped regions, and heavily doped source and drain regions.
  • the source and drain regions are stress source and drain regions, including SiGe and Si: C.
  • the source and drain regions further include an elevated source and drain region formed by epitaxy.
  • a stress pad layer of DLC material is formed by PECVD and magnetron sputtering.
  • the performing annealing specifically includes: performing laser annealing 1100 ⁇ 1300°C, annealing time 5ms ⁇ 50ms; or, peak rapid annealing (Spike RTA) 1000 ⁇ 1100°C, annealing time 500ms ⁇ 2s.
  • the method further includes: forming a metal silicide on the source and drain regions; forming a contact etch stop layer on the metal silicide, the gate spacer, and the gate stack; on the contact etch stop layer Forming an interlayer dielectric layer; planarizing the interlayer dielectric layer until the gate stack structure is exposed.
  • the planarizing the interlayer dielectric layer further after exposing the gate stack structure further includes: etching removing the gate stack structure leaving a gate trench; depositing a gate insulating layer of a high-k material in the gate trench; A gate conductive layer is deposited on the gate insulating layer in the gate trench; the gate conductive layer is planarized until the interlayer dielectric layer is exposed.
  • the planarizing the gate conductive layer until after exposing the interlayer dielectric layer further comprises: sequentially forming a second contact etch stop layer and a second interlayer dielectric layer on the interlayer dielectric layer; sequentially etching the second interlayer dielectric layer a second contact etch stop layer, a first interlayer dielectric layer, a first contact etch stop layer, until the metal silicide is exposed, forming a source/drain contact hole; filling the source and drain contact holes with a metal to form a source/drain contact plug .
  • the high-stress DLC film is used to generate memory strain on the dummy gate and the channel region, thereby effectively improving the carrier mobility in the channel region and improving device performance.
  • FIG. 1 to 10 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention
  • Fig. 11 is a schematic flow chart showing a method of fabricating a semiconductor device in accordance with the present invention.
  • a (false) gate stack structure and dummy gate spacers are formed on the substrate, and source and drain regions are formed in the substrates on both sides of the (false) gate stack structure.
  • a (false) gate stack structure is formed on the substrate.
  • a substrate 1 is provided.
  • the substrate 1 is suitably selected according to the needs of the device, and may include single crystal silicon (Si), silicon on insulator (S0I), single crystal germanium (Ge), germanium on insulator (GeOI), strained silicon (strained Si), germanium silicon (SiGe). ), or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes and many more.
  • the substrate 1 is a bulk Si or S0I for compatibility with a CMOS process for making a large scale integrated circuit.
  • a shallow trench isolation (STI) 2 is formed in the substrate 1, for example, photolithography/etching of the substrate 1 to form a shallow trench, and then an insulating isolation material is deposited by conventional techniques such as LPCVD, PECVD, etc. and CMP is planarized until the substrate 1 is exposed.
  • the STI 2 is formed, and the filling material of the STI 2 may be a conventional insulating material such as an oxide, a nitride, or an oxynitride, or may be Bi. 95 La. ,.
  • the carrier mobility is further improved.
  • a gate insulating layer 3 and a gate material layer 4 are sequentially deposited over the entire wafer surface, i.e., the substrate 1 and the STI 2 surface, and etched to form a gate stack structure (3/4).
  • a back gate process is employed, so the gate stack structure is a dummy gate stack structure that will be removed in subsequent processes. Therefore, the gate insulating layer 3 is preferably a pad layer of silicon oxide; the gate material layer 4 is a dummy gate material layer, preferably polysilicon, amorphous silicon or microcrystalline silicon.
  • the gate insulating layer 3 is preferably silicon oxide, nitrogen-doped silicon oxide, silicon nitride, or other high-k material, and the high-k material includes, but is not limited to, selected from the group consisting of Hf0 2 , HfSiO x , HfSiON , HfA10 x , HfTaO x , a bismuth-based material of HfLaO x , HfAlSiO x , HfLaSiO x (wherein each material is appropriately adjusted according to a distribution ratio of a plurality of metal groups and a chemical price, and an oxygen atom content X can be appropriately adjusted, for example, 1 to 6 and not limited to an integer), or
  • the invention comprises a rare earth-based high-k dielectric material selected from the group consisting of
  • a barrier layer (not shown) of nitride is preferably formed between the gate material layer 4 and the gate insulating layer 3 by a conventional method such as PVD, CVD, ALD, etc., and the barrier layer is made of M x N y , M x Si y N z , M x Al y N z , M a Al x Si y N z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements. More preferably, the gate material layer 4 and the barrier layer not only adopt a composite layer structure stacked on top of each other, but also a mixed implant doped layer structure, that is, a material constituting the gate material layer 4 and the barrier layer is simultaneously deposited on the gate. On the pole insulating layer 3, the gate conductive layer thus comprises the material of the above barrier layer.
  • a dummy gate spacer 5 is formed on the substrate 1 around the (false) gate stack structure 3/4.
  • An insulating layer of silicon nitride or silicon oxynitride is deposited on the substrate 1 and the gate stack structure 3/4 by a conventional deposition method such as PECVD or HDPCVD, followed by photolithography/etching to form the dummy gate spacer 5.
  • the dummy gate spacers 5 are used to define the location of the source and drain regions later and to control the deposition location and quality of the DLC film during the DLC SMT process steps.
  • source and drain regions 6 are formed in the substrate 1 on both sides of the dummy gate spacer 5.
  • a first source-drain ion implantation may be performed prior to forming the dummy gate spacer 5 in FIG. 2, with a selected dose and energy being small to form a light-doped (eg, n- or P-) source-drain extension having a first conductivity type Zone and/or halo source/drain doping zone (none of which is shown); then after forming the dummy gate spacer 5 in FIG.
  • the source-drain region of the heavily doped (eg, n+ or p+) of the first conductivity type, the lightly doped source-drain extension region, the halo source-drain-doped region, and the heavily doped source-drain region together constitute the FIG.
  • the source/drain region 6, the substrate 1 between the source and drain regions 6 constitute a channel region.
  • ⁇ OS is doped with phosphorus P, arsenic As, ⁇ Sb, etc.
  • PM0S is doped with boron B, aluminum Al, gallium Ga, indium In, and the like.
  • CMOS device a substrate to constitute a CMOS device and a memory unit.
  • an embedded stressor drain region 6 can be formed.
  • the source and drain grooves (not shown) are formed in the substrate 1 on both sides of the dummy gate spacer 5 by plasma etching or TMAH wet etching using the dummy gate spacer 5 as a mask.
  • a stress layer of SiGe or Si:C is epitaxially formed in the source/drain groove, and a stress is applied to the channel region by the difference in lattice constant between the source and the channel region Si, thereby constituting the stressor drain region 6.
  • the in-situ doping may be performed while epitaxially forming the stressor source drain region 6, or after the formation of the stressor source drain region 6, the source-drain ion implantation having the first conductivity type may be formed using the aforementioned source-drain ion implantation.
  • a lift source drain (not shown) may be further epitaxially formed to reduce source-drain resistance, further improving device performance.
  • a DLC stress pad layer is formed, and the annealing causes the channel region and the gate stack structure to memorize the stress.
  • a stress pad layer 7 is formed over the entire device, covering STI 2, source and drain regions 6, dummy gate spacers 5, and gate material layer 4.
  • the material of the stress pad 7 is diamond-like amorphous carbon (DLC), and the deposition method may be a previous magnetic filtration pulse cathode vacuum arc discharge (FCVA), and then more preferably PECVD, magnetron sputtering in the embodiment of the present invention. . Since the material properties of the DLC film is largely dependent on the content of sp 3 bonds, the higher the sp 3 bonds such that the diamond-like DLC structure further graphite instead, thus increasing intrinsic stress.
  • FCVA magnetic filtration pulse cathode vacuum arc discharge
  • the process parameters are controlled such that the content of sp 3 bonds in the DLC is at least greater than 50%, the hydrogen atom content is less than 40%, and the nitrogen atom content is less than 20%, so that the stress pad layer 7 has stress (may be
  • the magnitude (absolute value) of the tensile stress or compressive stress is greater than 2 GPa, and preferably between 4 and 10 GPa.
  • Magnetron sputtering and PECVD are mainstream processes in CMOS. It is easy to control the quality of film formation by changing process parameters. It can form multi-element alloys with less film particles and good film shape retention. Therefore, the quality of DLC film formed by FCVA method is better. Better.
  • the target of the magnetron sputtering DLC is sapphire
  • the sputtering chamber is filled with Ar of 10 to 200 SC cm and preferably also the CH 4 of 1 to 200 sccm is added
  • the control gas pressure is 10 - 5 to 10 - 2 torr
  • sputtering The RF or DC power is 50 to 1000 W
  • the sputtering room temperature is about 500 °C.
  • PECVD is formed LDC feed gas (3 ⁇ 4 or C 6 H 6, pressure of 10- 5 ⁇ ltorr, RF power 500W ⁇ 10kW, the deposition temperature is 300 ⁇ 700 ° C.
  • the thickness of the stress pad layer 7 of the DLC material is, for example, 10 to 200 nm and preferably 30 to 100 nm.
  • the magnetron sputtering, PECVD forms the DLC stress pad layer 7, and simultaneously (in situ) is doped with Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Metal elements such as Zr, W, Ir, Eu, Nd, Er, La, etc. to adjust the stress.
  • an annealing process is performed such that the gate stack structure and the channel region memorize the stress of the stress pad layer 7.
  • the stress layer has been directed to the gate stack structure and the channel region. Stress is applied.
  • Annealing is then performed, for example, laser annealing is performed at 1100 to 1300 ° C and preferably 1200 ° C, annealing time is 5 ms to 50 ms and preferably 10 ms; or, peak rapid annealing (Spike RTA) 1000 to 1100 ° C and preferably 1050 ° C, annealing The time is 500ms ⁇ 2s and preferably ls.
  • the gate stack structure particularly the gate material layer 4, and the lattice of materials in the channel region (eg, polysilicon/microcrystalline silicon, and silicon, respectively) to be partially rearranged, thereby the gate material layer 4 and the channel.
  • the region memorizes the stress in the stress pad 7, or in other words is transferred from the DLC layer 7 into the gate material layer 4 and the channel region.
  • 5 ⁇ 6GPa The gate material layer 4 and the channel region of the stress may be less than or equal to the original stress of the DLC stressor layer 7, for example only 2. 5 ⁇ 6GPa.
  • the dummy gate spacer 5 is removed, and the gate spacer 8 is formed.
  • the dummy gate spacer 5 is removed by etching.
  • plasma etching can be used and the etching process parameters (such as etching gas type, flow rate, pressure, power, etc.) can be controlled to make the dummy gate spacer of silicon nitride and silicon oxynitride material.
  • the etching selectivity ratio between other materials such as silicon and silicon oxide is greater than 10: 1.
  • the dummy gate spacer 5 is completely etched and the gate is not etched substantially.
  • a hot phosphoric acid or a wet etching solution of sulfuric acid and hydrogen peroxide may be used to remove the dummy gate spacer 5 .
  • the gate spacers 8 are formed by a conventional process.
  • the silicon nitride, silicon oxynitride may be deposited by the same process as the dummy gate spacer 5, such as PECVD, HDPCVD, etc., and then etched to form the gate spacers 8. Since these conventional materials are soft and have good step coverage, insulation isolation of the gate sidewalls can be ensured.
  • a DLC material layer may be formed by PECVD, magnetron sputtering or the like and plasma gate etching may be used to form the gate spacers 8 to further enhance the stress in the channel region. Different from the stress pad layer 7 of the DLC, the gate spacer 8 of the DLC is thinner and the material is still hard. Therefore, in order to ensure good coverage of the gate sidewall insulating medium, it is preferable to also be in the DLC gate spacer.
  • a pad (not shown) of silicon oxide and/or silicon nitride is deposited before deposition.
  • the DLC stress pad 7 can be compared.
  • the technical stress coating layer is formed thicker and does not need to control its distribution and shape, whereby the disadvantage of poor step coverage of the DLC layer can be overcome by thickening the DLC layer.
  • a metal silicide 9 is formed in/on the source/drain region 6, and a contact etch stop layer 10 is formed over the entire device.
  • a self-aligned silicide process is performed, and a thin film of a metal such as Pt, Co, Ni, Ti, or a metal alloy is deposited on the entire surface of the device, and then annealed at a high temperature to make the source/drain region 6
  • the silicon contained reacts with the metal to form, for example, CoSi 2 , TiSi 2 , NiSi, PtSi, NiPtSi, CoGeSi, TiGeSi, NiGeSi
  • the metal silicide 9 is used to reduce the source-drain contact resistance, thereby further improving device performance.
  • a process such as PECVD or HDPCVD is used to deposit an insulating layer of silicon nitride or silicon oxynitride, covering STI2, metal silicide 9, gate spacer 8, gate material layer 4, etc., to form a contact etch stop layer ( CESL) 10 for protecting source and drain regions as well as metal silicide during later etching or planarization.
  • an interlayer dielectric layer (ILD) 11 is deposited and planarized until the gate material layer 4 is exposed.
  • ILD 11 is preferably a low-k material, including but not limited to organic low-k materials (eg, organic polymers containing aryl or polycyclic rings), inorganic low-k materials (eg, amorphous carbon-nitrogen thin films, polycrystalline boron-nitrogen thin films, fluorosilicate glass) , BSG, PSG, BPSG), porous low-k materials (eg, disilane trioxane (SSQ)-based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped amorphous carbon, porous Diamond, porous organic polymer).
  • the low-k material ILD 11 is deposited by spin coating, spray coating, screen printing, LPCVD, or the like.
  • the ILD 11 is then planarized by CMP or etch back until the gate material layer 4 is exposed.
  • TMAH wet etching or plasma dry etching to remove polysilicon, microcrystalline silicon, amorphous silicon dummy gate material layer 4, HF wet etching or plasma etching to remove silicon oxide dummy gate insulating layer (mat oxide Layer 3) leaves a gate trench defined by the gate spacer 8 in the ILD 11.
  • a high-k material gate insulating layer 12 is deposited in a gate trench by PECVD, HDPCVD, M0CVD, MBA, ALD, etc.
  • high-k materials include, but are not limited to, nitrides (eg, SiN, AlN, TiN), metal oxides (to the sub-soil and the lanthanide metals oxides such as A1 2 0 3, T3 ⁇ 40 5, Ti3 ⁇ 4, Zn0, Zr0 2, Hf0 2, Ce0 2, Y 2 0 3, L3 ⁇ 40 3), oxide perovskite phase (for example, PbZrxT x 0 3 ( ⁇ ), B3 ⁇ 4Si x Ti0 3 (BST)).
  • nitrides eg, SiN, AlN, TiN
  • metal oxides to the sub-soil and the lanthanide metals oxides such as A1 2 0 3, T3 ⁇ 40 5, Ti3 ⁇ 4, Zn0, Zr0 2, Hf0 2, Ce0 2, Y
  • the gate conductive layer 13 is deposited on the gate insulating layer 12 by a process such as MOCVD, evaporation, sputtering, etc., and the gate conductive layer 13 may be a single layer or a plurality of layers, and may include polysilicon, Silicon germanium, or metal, wherein the metal may include metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, etc. Elemental, or alloys of these metals and nitrides of these metals, the gate conductive layer 13 may be doped with elements such as (:, F, N, 0, B, P, As, etc. to adjust the work function.
  • a barrier layer (not shown) of nitride is also preferably formed between the gate insulating layer 12 and the gate insulating layer 12 by a conventional method such as PVD, CVD, ALD, etc., and the barrier layer is made of M x N y , M x Si y N z , M x . Al y N z , M a Al x Si y N z , where M is Ta, Ti, Hf, Zr, Mo, W or other elements. Thereafter, the gate conductive layer 13 and the gate insulating layer 12 are planarized until the ILD is exposed 11.
  • second CESL second contact etch stop layer
  • second ILD second interlayer dielectric of low k material Layer
  • the high-stress DLC film is used to generate memory strain on the dummy gate and the channel region, thereby effectively improving the carrier mobility in the channel region and improving device performance.

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Abstract

一种半导体器件制造方法，包括：在衬底（1）上形成栅极堆叠结构（3/4）；在栅极堆叠结构周围形成假栅极侧墙（5）；在衬底（1）、栅极堆叠结构（3/4）以及假栅极侧墙（5）上沉积DLC材质的应力垫层（7）；执行退火，使得栅极堆叠结构（3/4）和栅极堆叠结构（3/4）下方的衬底（1）中的沟道区记忆了应力垫层（7）中的应力；去除假栅极侧墙（5）；在栅极堆叠结构（3/4）周围形成栅极侧墙（8）。依照本发明的半导体器件制造方法，利用高应力DLC薄膜对假栅以及沟道区产生记忆应变，从而有效提升了沟道区载流子迁移率，提高了器件性能。

Description

半导体器件制造方法 本申请要求 2012年 7月 13日提交的、申请号为 201210244783. 9、发明名称为"半 导体器件制造方法"的中国专利申请的优先权，其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件制造方法，特别是涉及一种采用高应力覆盖层应力记 忆方法的 M0SFET制造方法。 背景技术
从 90nm CMOS集成电路工艺起， 随着器件特征尺寸的不断缩小， 以提高沟道载流 子迁移率为目的应力沟道工程 （Strain Channel Engineering ) 起到了越来越重要 的作用。 多种单轴工艺诱致应力被集成到器件工艺中去， 也即在沟道方向引入压应力 或拉应力从而增强载流子迁移率， 提高器件性能。 例如， 在 90nm工艺中， 采用嵌入 式 SiGe ( e-SiGe )源漏或 100晶向衬底并结合拉应力蚀刻阻障层（tCESL)来提供 pMOS 器件中的压应力； 在 65nm工艺中， 在 90nm工艺基础上进一步采用第一代源漏极应力 记忆技术（SMTX 1)， 并采用了双蚀刻阻障层； 45nm工艺中， 在之前基础上采用了第二 代源漏极应力记忆技术 （SMTX2)， 采用 e-SiGe技术结合单 tCESL或双 CESL， 并采用 了应力近临技术 （Stress Proximity Technique, SPT)， 此外还针对 pMOS采用 110 面衬底而针对 nMOS采用 100面衬底； 32nm之后， 采用了第三代源漏极应力记忆技术 ( SMTX3)， 在之前基础之上还选用了嵌入式 SiC源漏来增强 nMOS器件中的拉应力。
此外， 向沟道引入应力的技术除了改变衬底、 源漏材料， 还可以通过控制沟道或 侧墙的材质、 剖面形状来实现。 例如采用双应力衬垫 （DSL) 技术， 对于 nMOS采用拉 应力≤1^层侧墙， 对于 pMOS采用压应力侧墙。又例如将嵌入式 SiGe源漏的剖面制造 为∑形， 改善 pMOS的沟道应力。
然而， 这些常规应力技术效果随着器件尺寸持续缩小而被不断削弱。 对于 nMOS 而言， 随着特征尺寸缩减， 提供应力的各层薄膜之间的错位和偏移越来越明显， 这就 要求薄膜厚度减薄的同时还能精确提供更高的应力。对于 PM0S而言， 嵌入式 SiGe源 漏技术的沟道载流子迁移率显著取决于特征尺寸，尺寸缩减使得载流子迁移率提高的 效果大打折扣。 一种新的思路是采用类金刚石无定形碳 （DLC) 薄膜来提高器件的本征应力。 例 如 Kian-Ming Tan等人在 IEEE ELETRON DEVICE LETTERS, VOL. 29， NO. 2， FEBUARY 2008 上发表的《 High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET)), 在整个 MOSFET表面上覆盖比 SiN压应力高的 DLC， DLC的高应 力向下传递到沟道区， 从而相应地提高了沟道应力， 改善了器件的电学性能。 此外， 美国专利 US2010/0213554A1也采用了类似结构。
DLC的通常制备方法是采用磁过滤脉冲阴极真空弧放电 （FCVA), 通过提高 sp3键 的含量使得 DLC结构更类似于金刚石而不是石墨， 因此提高了本征应力。 但是， 该高 应力 DLC的 FCVA制备法并不是集成电路制作的标准工艺，例如与常用的 CMOS工艺不 兼容， 使得需要额外的制造设备、 工艺以及时间成本。此外， FCVA法会带来较多的颗 粒， 影响了集成电路后续工艺的进行， 例如颗粒残留在精细结构之间造成不必要的导 电或者绝缘， 又或者使得后续薄膜沉积不均匀、 器件热应力发生改变等等， 降低了器 件的可靠性。 作为替代， 本发明人的在先申请中公开了可以采用 PECVD、 磁控溅射等 方法来沉积高质量的 DLC， 并通过控制工艺参数来调整 DLC的应力大小。
然而， 不论是何种 DLC制造方法， 由于 DLC材质本身是类金刚石薄膜， 其硬度较 高而台阶覆盖性较差， 在用于应力衬垫层的工艺中面临了诸多困难。可以预想到的一 个困难在于， 在栅极、 栅极侧墙以及源漏区上覆盖 DLC应力层时， 受限于器件整体尺 寸最终保留的 DLC应力层可能较薄 （例如 10〜50nm)， 而由于台阶覆盖性较差， 栅极 侧墙与源漏区相交的脚部附近 DLC薄膜可能较薄乃至缺失，而该部分又距离器件沟道 区最近， 因此在该部分处无法有效向沟道区施加足够的应力， 使得载流子迁移率提高 程度有限， 进而使得器件性能提高无法满足预期。 此外， 当 DLC替代 SiN用作栅极侧 墙时， 如果栅极侧墙厚度需要比较薄， 则 DLC可能因为工艺原因在栅极侧面上断裂、 脱落， 因此完全无法向沟道区施加应力。
综上所述， 现有的高应力 DLC技术存在台阶覆盖性差的缺点， 难以有效提高沟道 区载流子迁移率， 也难以有效提高器件驱动能力。 发明内容
由上所述，本发明的目的在于提供一种能有效向沟道区施加应力从而提高载流子 迁移率的半导体器件制造方法。
为此， 本发明提供了一种半导体器件制造方法， 包括： 在衬底上形成栅极堆叠结 构； 在栅极堆叠结构周围形成假栅极侧墙； 在衬底、 栅极堆叠结构以及假栅极侧墙上 沉积 DLC材质的应力垫层； 执行退火， 使得栅极堆叠结构和栅极堆叠结构下方的衬底 中的沟道区记忆了应力垫层中的应力； 去除假栅极侧墙； 在栅极堆叠结构周围形成栅 极侧墙。
其中， 栅极堆叠结构是假栅极堆叠结构， 包括垫氧化层和假栅极材料层， 假栅极 材料层包括多晶硅、 非晶硅、 微晶硅。
其中， 假栅极侧墙和 /或栅极侧墙包括氮化硅、 氮氧化硅。
其中， 形成假栅极侧墙之后还包括在假栅极侧墙两侧的衬底中形成源漏区。 其中， 源漏区包括轻掺杂的源漏延伸区和 /或暈状源漏掺杂区、 以及重掺杂的源 漏区。
其中， 源漏区是应力源漏区， 包括 SiGe、 Si : C。
其中， 源漏区上还包括外延形成的提升源漏区。
其中， 通过 PECVD、 磁控溅射形成 DLC材质的应力垫层。
其中， 执行退火具体包括： 执行激光退火 1100〜1300°C， 退火时间 5ms〜50ms; 或者， 尖峰快速退火 ( Spike RTA) 1000〜1100°C， 退火时间 500ms〜2s。
其中， 形成栅极侧墙之后进一步包括： 在源漏区上形成金属硅化物； 在金属硅化 物、 栅极侧墙、 栅极堆叠结构上形成接触刻蚀停止层； 在接触刻蚀停止层上形成层间 介质层； 平坦化层间介质层直至暴露栅极堆叠结构。
其中， 平坦化层间介质层直至暴露栅极堆叠结构之后进一步包括： 刻蚀去除栅极 堆叠结构， 留下栅极沟槽； 在栅极沟槽中沉积高 k材料的栅极绝缘层； 在栅极沟槽中 栅极绝缘层上沉积栅极导电层； 平坦化栅极导电层直至暴露层间介质层。
其中， 平坦化栅极导电层直至暴露层间介质层之后进一步包括： 在层间介质层上 依次形成第二接触刻蚀停止层和第二层间介质层； 依次刻蚀第二层间介质层、第二接 触刻蚀停止层、 第一层间介质层层、 第一接触刻蚀停止层， 直至暴露金属硅化物， 形 成源漏接触孔； 在源漏接触孔中填充金属形成源漏接触塞。
依照本发明的半导体器件制造方法，利用高应力 DLC薄膜对假栅以及沟道区产生 记忆应变， 从而有效提升了沟道区载流子迁移率， 提高了器件性能。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中： 图 1至图 10为依照本发明的半导体器件制造方法各步骤的剖面示意图； 以及 图 11为依照本发明的半导体器件制造方法的示意性流程图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技 术效果， 公开了能有效控制沟道应力、提高载流子迁移率从而改善器件性能的半导体 器件制造方法。 需要指出的是， 类似的附图标记表示类似的结构， 本申请中所用的术 语 "第一"、 "第二"、 "上"、 "下"等等可用于修饰各种器件结构或制造工序。 这些修 饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、 次序或层级关系。
以下将结合图 11的流程图并且参照图 1至图 10的剖面示意图来详细说明依照本 发明的半导体器件制造方法各步骤。
参照图 11以及图 1〜图 3， 在衬底上形成 （假）栅极堆叠结构和假栅极侧墙、 以 及在 （假） 栅极堆叠结构两侧衬底中形成源漏区。
如图 1所示， 在衬底上形成 （假） 栅极堆叠结构。 提供衬底 1。 衬底 1依照器件 用途需要而合理选择， 可包括单晶体硅 （Si )、 绝缘体上硅 （S0I )、 单晶体锗 （Ge)、 绝缘体上锗（GeOI )、 应变硅（Strained Si )、 锗硅（SiGe)， 或是化合物半导体材料， 例如氮化镓 （GaN)、 砷化镓 （GaAs )、 磷化铟（InP)、 锑化铟 （InSb)， 以及碳基半导 体例如石墨烯、 SiC、 碳纳管等等。 优选地， 衬底 1为体 Si或 S0I以便与 CMOS工艺 兼容而用于制作大规模集成电路。
在衬底 1中形成浅沟槽隔离 （STI ) 2， 例如先光刻 /刻蚀衬底 1形成浅沟槽然后 采用 LPCVD、 PECVD等常规技术沉积绝缘隔离材料并 CMP平坦化直至露出衬底 1，形成 STI 2， 其中 STI 2的填充材料可以是氧化物、 氮化物、 氮氧化物等常规绝缘材料， 还可以是 Bi。.95La。,。5Ni03、 BiNi03、 ZrW208、 Ag3 [Co (CN) 6]等具有超大（正 /负）热膨胀系 数的材料（100K的温度下线性体积膨胀系数的绝对值大于 10— 7K)以便通过应力 STI 2 向沟道区施加应力从而进一步提高载流子迁移率。
在整个晶片表面也即衬底 1和 STI 2表面依次沉积栅极绝缘层 3和栅极材料层 4 并刻蚀形成栅极堆叠结构 （3/4)。 在本发明一个实施例中， 采用后栅工艺， 因此栅极 堆叠结构是假栅极堆叠结构， 将在后续工艺中去除。 因此栅极绝缘层 3优选为氧化硅 的垫层； 栅极材料层 4是假栅极材料层， 优选为多晶硅、 非晶硅或微晶硅。
值得注意的是， 除此之外， 在本发明其他实施例中， 可以采用前栅工艺， 栅极堆 叠结构将在后续工艺中保留。因此栅极绝缘层 3优选为氧化硅、掺氮氧化硅、氮化硅、 或其它高 K材料， 高 k材料包括但不限于包括选自 Hf02、 HfSiOx、 HfSiON、 HfA10x、 HfTaOx、 HfLaOx、 HfAlSiOx、 HfLaSiOx的铪基材料（其中， 各材料依照多元金属组分配 比以及化学价不同， 氧原子含量 X可合理调整， 例如可为 1〜6且不限于整数）， 或是 包括选自 Zr02、 La203、 LaA103、 Ti02、 Y203的稀土基高 K介质材料， 或是包括 Α1203， 以其上述材料的复合层； 栅极材料层 4则可为多晶硅、 多晶锗硅、 或金属， 其中金属 可包括 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 Ir、 Eu、 Nd、 Er、 La等金属单质、或这些金属的合金以及这些金属的氮化物， 栅极材料层 4中还可 掺杂有 C、 F、 N、 0、 B、 P、 As等元素以调节功函数。 栅极材料层 4与栅极绝缘层 3 之间还优选通过 PVD、 CVD、 ALD等常规方法形成氮化物的阻挡层 （未示出）， 阻挡层 材质为 MxNy、 MxSiyNz、 MxAlyNz、 MaAlxSiyNz， 其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W或其它元 素。 更优选地， 栅极材料层 4与阻挡层不仅采用上下叠置的复合层结构， 还可以采用 混杂的注入掺杂层结构，也即构成栅极材料层 4与阻挡层的材料同时沉积在栅极绝缘 层 3上， 因此栅极导电层包括上述阻挡层的材料。
如图 2所示， 在 （假） 栅极堆叠结构 3/4周围的衬底 1上形成假栅极侧墙 5。 采 用 PECVD、 HDPCVD等常规沉积方法， 在衬底 1、 栅极堆叠结构 3/4上沉积氮化硅、 氮 氧化硅材质的绝缘层， 随后光刻 /刻蚀形成假栅极侧墙 5。假栅极侧墙 5用于限定稍后 源漏区的位置以及 DLC SMT工艺步骤时控制 DLC薄膜的沉积位置和质量。
优选地， 如图 3所示， 在假栅极侧墙 5两侧的衬底 1中形成源漏区 6。 可以在图 2形成假栅极侧墙 5之前执行第一次源漏离子注入， 选择剂量和能量较小， 形成具有 第一导电类型的轻掺杂（例如 n-或 P-) 的源漏延伸区和 /或暈状源漏掺杂区 （均未示 出）； 然后在图 2形成假栅极侧墙 5之后， 执行第二次源漏离子注入， 选择剂量和能 量较大， 形成具有相同的第一导电类型的重掺杂 （例如 n+或 p+) 的源漏区， 上述轻 掺杂的源漏延伸区、暈状源漏掺杂区以及重掺杂的源漏区共同构成图 3所示的源漏区 6， 源漏区 6之间的衬底 1构成沟道区。 其中， 对于匪 OS而言掺杂磷 P、 砷 As、 锑 Sb 等， 对于 PM0S而言掺杂硼 B、 铝 Al、 镓 Ga、 铟 In等。 此外， 虽然本发明实施例中仅 示出了一种 M0SFET的制造流程，然而实际上可以在衬底上同时形成多个 PM0S和多个 匪 OS以及多个其他器件， 从而构成 CMOS器件、 存储器单元阵列、 光电探测器阵列等 等。
除了常规的离子注入形成源漏区 6之外， 还可以形成嵌入式的应力源漏区 6。 具 体地， 以假栅极侧墙 5为掩模， 采用等离子刻蚀或者 TMAH湿法腐蚀， 在假栅极侧墙 5 两侧的衬底 1中形成源漏凹槽 （未示出）。 在源漏凹槽中外延形成 SiGe或 Si : C的应 力层， 利用其与沟道区 Si之间晶格常数的差异而对沟道区施加应力， 因此构成了应 力源漏区 6。 优选地， 可以在外延形成应力源漏区 6的同时执行原位掺杂， 或者在形 成应力源漏区 6之后采用前述的源漏离子注入， 形成具有第一导电类型的源漏区 6。
此外， 除了图 3所示的与衬底表面平行的源漏区之外， 还可以进一步外延形成提 升源漏 （未示出） 以减小源漏电阻， 进一步提高器件性能。
参照图 11以及图 4、 图 5， 形成 DLC应力垫层， 退火使得沟道区以及栅极堆叠结 构记忆了应力。
如图 4所示， 在整个器件上形成应力垫层 7， 覆盖了 STI 2、 源漏区 6、 假栅极侧 墙 5、 栅极材料层 4。 应力垫层 7的材质为类金刚石无定形碳 （DLC)， 沉积方法可以 是先前的磁过滤脉冲阴极真空弧放电 （FCVA ) , 然后更优选地是本发明实施例中的 PECVD、磁控溅射。 由于 DLC薄膜的材料特性很大程度上取决于 sp3键的含量， 较高的 sp3键的含量使得 DLC结构更类似于金刚石而不是石墨， 因此提高本征应力。 具体地， 本发明优选实施例中控制工艺参数使得 DLC中 sp3键的含量至少大于 50 %、氢原子含 量少于 40 %、 氮原子含量少于 20 %， 使应力垫层 7具有应力 （可以是张应力或者压 应力） 的大小 （绝对值） 大于 2GPa、 并优选地介于 4〜10GPa。 磁控溅射和 PECVD属 于 CMOS主流工艺， 容易通过改变工艺参数来控制薄膜的形成质量， 可形成多元素合 金， 薄膜颗粒较少、 薄膜保形性良好， 因此较之 FCVA法形成的 DLC薄膜质量更佳。 例如， 磁控溅射 DLC的靶标为蓝宝石， 溅射室内通入 10〜200SCcm的 Ar并优选还加 入 l〜200sccm的 CH4，控制气压为 10— 5〜10— 2torr，溅射的 RF或 DC功率为 50〜1000W， 溅射室温约为 500°C。 PECVD形成 LDC的原料气为（¾或 C6H6， 气压为 10— 5〜ltorr， RF 功率为 500W〜10kW， 沉积室温为 300〜700°C。 值得注意的是， 尽管列举了以上形成 DLC工艺条件， 但是只要能使得薄膜质量良好， 其他范围的工艺条件也是可选的。 DLC 材质的应力垫层 7的厚度例如是 10〜200nm并优选 30〜100nm。
优选地， 在磁控溅射、 PECVD形成 DLC应力垫层 7的同时， 同步（原位）掺入 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 Ir、 Eu、 Nd、 Er、 La等金 属元素以调节应力。
如图 5所示， 执行退火工艺， 使得栅极堆叠结构和沟道区记忆了应力垫层 7的应 力。在图 4所示形成了 DLC应力垫层 7之后， 该应力层已经向栅极堆叠结构和沟道区 施加了应力。 随后执行退火， 例如， 执行激光退火 1100〜1300°C并优选 1200°C， 退 火时间 5ms〜50ms并优选 10ms; 或者， 尖峰快速退火 ( Spike RTA) 1000〜1100°C并 优选 1050°C， 退火时间 500ms〜2s并优选 ls。 如此使得栅极堆叠结构特别是栅极材 料层 4、 以及沟道区中材料 （例如分别为多晶硅 /微晶硅、 以及硅） 的晶格局部重排， 由此栅极材料层 4以及沟道区记忆了应力垫层 7中的应力，或者换言之由 DLC层 7转 移进入了栅极材料层 4以及沟道区。栅极材料层 4以及沟道区记忆的应力可能小于等 于 DLC应力垫层 7的原始应力， 例如仅为 2. 5〜6GPa。
参见图 11以及图 6、 图 7， 去除假栅极侧墙 5， 形成栅极侧墙 8。
如图 6所示， 刻蚀去除假栅极侧墙 5。 依照假栅极侧墙 5的材质， 可以采用等离 子刻蚀并且控制刻蚀工艺参数 （例如刻蚀气体种类、 流量、 压力、 功率等） 使得氮化 硅、氮氧化硅材质的假栅极侧墙 5与硅、氧化硅等周边其他材质之间的刻蚀选择比大 于 10 : 1，通过控制刻蚀速率和刻蚀时间，使得完全刻蚀去除假栅极侧墙 5而基本不刻 蚀栅极材料层 4、 源漏区 6等。 或者， 也可以采用热磷酸、 或者硫酸与双氧水的湿法 刻蚀液来去除假栅极侧墙 5。
如图 7所示， 采用常规工艺， 形成栅极侧墙 8。 可以与形成假栅极侧墙 5相同的 工艺， 例如 PECVD、 HDPCVD等沉积氮化硅、 氮氧化硅， 随后刻蚀形成栅极侧墙 8。 由 于这些常规材料较软， 台阶覆盖性良好， 因此可以确保栅极侧壁的绝缘隔离。 此外， 也可以采用 PECVD、 磁控溅射等形成 DLC材质层并等离子刻蚀形成栅极侧墙 8， 以进 一步增强沟道区应力。 与 DLC的应力垫层 7不同的是， DLC的栅极侧墙 8厚度较薄而 材质依然较硬， 因此为了确保栅极侧壁绝缘介质的良好覆盖， 优选地还要在 DLC栅极 侧墙 8沉积形成之前再沉积氧化硅和 /或氮化硅的垫层 （未示出）。
值得注意的是， 在图 4〜图 7所示的步骤中， 由于假栅极侧墙 5以及 DLC应力垫 层 7形成并且记忆了应力之后被完全除去， 因此 DLC应力垫层 7可以较之现有技术的 应力覆盖层形成的更厚并且无需控制其分布和形状， 由此可以通过增厚 DLC层来克服 DLC层台阶覆盖性不佳的缺点。
此后， 参照图 11以及图 8〜图 10， 完成后续工艺。
如图 8所示，在源漏区 6中 /上形成金属硅化物 9，在整个器件上形成接触刻蚀停 止层 10。 以栅极侧墙 8为掩模， 执行自对准硅化物工艺， 在整个器件表面沉积 Pt、 Co、 Ni、 Ti等金属或金属合金的薄膜， 然后高温退火处理， 使得源漏区 6中所含的硅 与金属发生反应生成如 CoSi2、 TiSi2、 NiSi、 PtSi、 NiPtSi、 CoGeSi、 TiGeSi、 NiGeSi 等金属硅化物 9以降低源漏接触电阻，从而进一步提高器件性能。采用 PECVD、 HDPCVD 等工艺， 沉积氮化硅、 氮氧化硅材质的绝缘层， 覆盖了 STI2、 金属硅化物 9、 栅极侧 墙 8、 栅极材料层 4等等， 构成接触刻蚀停止层 （CESL) 10， 以用于在稍后的刻蚀或 平坦化过程中保护源漏区以及金属硅化物。
如图 9所示， 沉积层间介质层（ILD) 11并平坦化直至露出栅极材料层 4。 ILD 11 优选低 k材料， 包括但不限于有机低 k材料（例如含芳基或者多元环的有机聚合物）、 无机低 k材料（例如无定形碳氮薄膜、 多晶硼氮薄膜、 氟硅玻璃、 BSG、 PSG、 BPSG)、 多孔低 k材料（例如二硅三氧烷（SSQ)基多孔低 k材料、多孔二氧化硅、多孔 SiOCH、 掺 C二氧化硅、 掺 F多孔无定形碳、 多孔金刚石、 多孔有机聚合物）。 通过旋涂、 喷 涂、 丝网印刷、 LPCVD等方式来沉积低 k材料的 ILD 11。 随后采用 CMP或者回刻处理 平坦化 ILD 11直至露出了栅极材料层 4。
以后栅工艺为例， 如图 10所示， 继续完成后续工艺。 TMAH湿法刻蚀或者等离子 干法刻蚀去除多晶硅、 微晶硅、 非晶硅的假栅极材料层 4， HF湿法腐蚀或者等离子体 刻蚀去除氧化硅的假栅极绝缘层 （垫氧化层） 3， 在 ILD 11中留下由栅极侧墙 8限定 出的栅极沟槽。在栅极沟槽中通过 PECVD、 HDPCVD, M0CVD、 MBA, ALD等工艺沉积高 k 材料的栅极绝缘层 12， 高 k材料包括但不限于氮化物 （例如 SiN、 A1N、 TiN)、 金属 氧化物（土要为副族和镧系金属元素氧化物，例如 A1203、 T¾05、 Ti¾、 Zn0、 Zr02、 Hf02、 Ce02、 Y203、 L¾03)、 钙钛矿相氧化物 （例如 PbZrxT x03 (ΡΖΤ)、 B¾Si xTi03 (BST))。 在栅极沟槽中栅极绝缘层 12上通过 M0CVD、蒸发、溅射等工艺沉积填充了栅极导电层 13， 栅极导电层 13可以是单层也可以是多层， 可以包括多晶硅、 多晶锗硅、 或金属， 其中金属可包括 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 Ir、 Eu、 Nd、 Er、 La等金属单质、 或这些金属的合金以及这些金属的氮化物， 栅极导电层 13中还可掺杂有（：、 F、 N、 0、 B、 P、 As等元素以调节功函数。 栅极导电层 13与栅极 绝缘层 12之间还优选通过 PVD、 CVD、 ALD等常规方法形成氮化物的阻挡层（未示出）， 阻挡层材质为 MxNy、 MxSiyNz、 MxAlyNz、 MaAlxSiyNz， 其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W 或其它元素。 此后， 平坦化栅极导电层 13、 栅极绝缘层 12直至暴露 ILD 11。 沉积形 成氮化硅的第二接触刻蚀停止层（第二 CESL) 14、以及低 k材料的第二层间介质层（第 二 ILD) 15。 依次刻蚀第二 ILD15、 第二 CESL14、 第一 CESL 10直至暴露金属硅化物 9， 形成源漏接触孔， 在源漏接触孔中通过蒸发、溅射、 M0CVD等工艺填充 W、 Al、 Ti、 Mo、 Ta、 Cu等金属及其氮化物形成源漏接触塞 16。 至此， 已经完成了依照本发明一 个实施例的 MOSFET制造。
此外， 虽然本发明附图中仅显示了平面沟道的匪 OS或 PM0S示意图， 但是本领域 技术人员应当知晓的是本发明可用于 CMOS结构， 也可应用于其他例如立体多栅、 垂 直沟道、 纳米线等器件结构。
依照本发明的半导体器件制造方法，利用高应力 DLC薄膜对假栅以及沟道区产生 记忆应变， 从而有效提升了沟道区载流子迁移率， 提高了器件性能。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需 脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外， 由所公开的教 导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。 因此， 本发明的 目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公 开的器件结构及其制造方法将包括落入本发明范闱内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件制造方法， 包括：
在衬底上形成栅极堆叠结构；
在栅极堆叠结构周围形成假栅极侧墙；
在衬底、 栅极堆叠结构以及假栅极侧墙上沉积 DLC材质的应力垫层；
执行退火，使得栅极堆叠结构和栅极堆叠结构下方的衬底中的沟道区记忆了应力 垫层中的应力；
去除假栅极侧墙；
在栅极堆叠结构周围形成栅极侧墙。
2. 如权利要求 1 的方法， 其中， 栅极堆叠结构是假栅极堆叠结构， 包括垫氧化 层和假栅极材料层， 假栅极材料层包括多晶硅、 非晶硅、 微晶硅。
3. 如权利要求 1的方法， 其中， 假栅极侧墙和 /或栅极侧墙包括氮化硅、 氮氧化
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4. 如权利要求 1 的方法， 其中， 形成假栅极侧墙之后还包括在假栅极侧墙两侧 的衬底中形成源漏区。
5. 如权利要求 4的方法， 其中， 源漏区包括轻掺杂的源漏延伸区和 /或暈状源漏 掺杂区、 以及重掺杂的源漏区。
6. 如权利要求 4的方法， 其中， 源漏区是应力源漏区， 包括 SiGe、 Si : C。
7. 如权利要求 4的方法， 其中， 源漏区上还包括外延形成的提升源漏区。
8. 如权利要求 1的方法， 其中， 通过 PECVD、 磁控溅射形成 DLC材质的应力垫 层。
9. 如权利要求 1的方法，其中，执行退火具体包括：执行激光退火 1100〜1300°C， 退火时间 5ms〜50ms; 或者， 尖峰快速退火 （Spike RTA) 1000〜1100°C， 退火时间 500ms〜2s。
10. 如权利要求 4的方法， 其中， 形成栅极侧墙之后进一步包括：
在源漏区上形成金属硅化物；
在金属硅化物、 栅极侧墙、 栅极堆叠结构上形成接触刻蚀停止层；
在接触刻蚀停止层上形成层间介质层；
平坦化层间介质层直至暴露栅极堆叠结构。
11. 如权利要求 10的方法， 其中， 平坦化层间介质层直至暴露栅极堆叠结构 之后进一步包括：
刻蚀去除栅极堆叠结构， 留下栅极沟槽；
在栅极沟槽中沉积高 k材料的栅极绝缘层；
在栅极沟槽中栅极绝缘层上沉积栅极导电层；
平坦化栅极导电层直至暴露层间介质层。
12. 如权利要求 11的方法， 其中， 平坦化栅极导电层直至暴露层间介质层之 后进一步包括：
在层间介质层上依次形成第二接触刻蚀停止层和第二层间介质层；
依次刻蚀第二层间介质层、 第二接触刻蚀停止层、 第一层间介质层层、 第一接触 刻蚀停止层， 直至暴露金属硅化物， 形成源漏接触孔；
在源漏接触孔中填充金属形成源漏接触塞。
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