WO2013143321A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2013143321A1
WO2013143321A1 PCT/CN2012/086403 CN2012086403W WO2013143321A1 WO 2013143321 A1 WO2013143321 A1 WO 2013143321A1 CN 2012086403 W CN2012086403 W CN 2012086403W WO 2013143321 A1 WO2013143321 A1 WO 2013143321A1
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Prior art keywords
black matrix
photoresist
layer
array substrate
substrate
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PCT/CN2012/086403
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English (en)
French (fr)
Inventor
徐传祥
薛建设
孙雯雯
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京东方科技集团股份有限公司
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Publication of WO2013143321A1 publication Critical patent/WO2013143321A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display device. Background technique
  • the aperture ratio of a liquid crystal panel is an important product index.
  • the data lines, scanning lines, and thin film transistors in the liquid crystal panel are usually blocked by a black matrix disposed in the color filter layer, and the black matrix region is not transparent.
  • the aperture ratio of the liquid crystal panel refers to the ratio between the area of the portion through which the light passes and the area of the entire liquid crystal panel. The higher the aperture ratio, the more efficient the light passes.
  • the high aperture ratio of the liquid crystal panel is important for improving the clarity, brightness, and energy saving of the liquid crystal panel.
  • a conventional liquid crystal panel generally includes an array substrate, a color filter substrate, and a liquid crystal layer, and the liquid crystal layer is mounted between the array substrate and the color filter substrate.
  • the color filter substrate comprises a transparent substrate, a black matrix, a color film layer and a common electrode
  • the array substrate comprises a substrate, a scan line, a data line, a thin film transistor and a pixel electrode.
  • the black matrix of the color film substrate and the thin film transistor, the scanning line, and the data line of the array substrate are difficult to accurately correspond, or when the liquid crystal panel is used, the impact of the external force is also It may cause the black matrix of the color filter substrate to deviate from the thin film transistor, the scan line, and the data line of the array substrate, which may cause light leakage.
  • defects in light leakage at the position of the thin film transistor, the scanning line, and the data line on the array substrate can be avoided by increasing the area of the black matrix.
  • increasing the area of the black matrix causes the aperture ratio of the liquid crystal panel to decrease, and the display luminance of the liquid crystal panel is low.
  • the display panel such as the OLED display panel or the electronic paper display panel also includes the array substrate of the similar structure described above.
  • the display panels need to be provided with a black matrix on another substrate disposed opposite to the array substrate, there is also a problem caused by the black matrix mismatch described above. Summary of the invention
  • An embodiment of the present disclosure provides an array substrate including a substrate, and a thin film transistor, a scan line, a data line, and a pixel electrode formed on the substrate, wherein a gate and a source of the thin film transistor are respectively The scan line is connected to the data line, and the drain of the thin film transistor is connected to the pixel electrode.
  • the array substrate further includes: a black matrix, the black matrix and the thin film transistor, the scan line and the data line Corresponding settings.
  • the black matrix and the pixel electrode are staggered and arranged in a complementary manner.
  • the black matrix is formed over the thin film transistor, the scan line or the data line.
  • the black matrix is formed under the thin film transistor, the scan line or the data line.
  • the array substrate further includes a common electrode, wherein the common electrode is located above or below the pixel electrode, and the upper portion of the common electrode and the pixel electrode is in a slit shape.
  • This is an ADS type array substrate.
  • a black matrix can be disposed on the passivation layer.
  • the black matrix is disposed between the passivation layer and the substrate.
  • the present disclosure also provides a display device including the above array substrate.
  • the present disclosure also provides a method for fabricating an array substrate, comprising: preparing a thin film transistor, a scan line, a data line, and a pixel electrode on a substrate, wherein the manufacturing method further includes:
  • a black matrix is prepared over the substrate, and the black matrix is disposed corresponding to the scan line, the data line, and the thin film transistor.
  • preparing the black matrix above the substrate comprises:
  • Step 1 Depositing a black matrix layer and a photoresist layer on a substrate on which a gate electrode, a gate insulating layer, an active layer, a source/drain electrode, and a data line are formed; wherein, the black matrix layer and the photoresist layer a photoresist material having the same photo-sensing property;
  • Step 2 patterning the substrate of the step 1 by using a gray tone mask or a halftone mask to obtain via holes, and then ashing to remove the photoresist and the black matrix layer on the pixel electrode region while being on the substrate Retaining a predetermined thickness of the photoresist layer in the remaining positions; and
  • Step 3 Deposit a transparent conductive layer on the substrate on which the step 2 is completed, and peel off the remaining photoresist layer and the transparent conductive layer thereon by a lift off process to form a pattern of the pixel electrode and expose the black matrix.
  • the step 2 includes:
  • Step 21 using the gray tone mask or the halftone mask to face the black matrix layer and the photoresist layer Exposure and development processes are performed to form a photoresist semi-reserved area, a photoresist complete removal area, and a photoresist completely reserved area, wherein the photoresist semi-reserved area corresponds to the pixel electrode area, and the photoresist complete removal area corresponds to the via hole. a region, a photoresist completely reserved region corresponding to the black matrix layer region, the photoresist in the photoresist semi-reserved region is completely removed and the black matrix layer is retained, and the photoresist completely removes the photoresist and the black matrix in the region Completely removed;
  • Step 22 etching a passivation layer of the complete removal region of the photoresist to form a pattern of via holes; and step 23, performing ashing treatment on the substrate of the completion step 22, and controlling the ashing processing time to remove the pixel electrode region
  • the black matrix layer simultaneously retains a predetermined thickness of the photoresist layer at the remaining positions of the substrate.
  • the black matrix layer and the photoresist layer are each formed of a negative photoresist material.
  • the method of manufacturing the array substrate further includes:
  • a common electrode is formed on the substrate on which the step 3 is completed, and the common electrode has a slit shape.
  • the array substrate and the display device provided by the present disclosure avoid the blackness disposed on the color filter substrate in the conventional display device by disposing the black matrix on the array substrate and correspondingly setting the black matrix with the thin film transistor, the scan line and the data line.
  • the deviation between the matrix and the thin film transistor, the data line and the scanning line on the array substrate solves the light leakage phenomenon caused by the above deviation, and also reduces the area of the black matrix, and increases the aperture ratio of the display panel such as the liquid crystal panel. , Improve the brightness of display panels such as LCD panels.
  • the manufacturing method of the array substrate provided by the present disclosure can be prepared by using a mask process of three times, and the black matrix array substrate is disposed, and the black matrix is matched with the thin film transistor, the scan line and the data line, which not only avoids the setting in the conventional display device.
  • Light leakage caused by deviation between the black matrix on the color filter substrate and the thin film transistor, the data line and the scanning line on the array substrate which is advantageous for reducing the area of the black matrix, increasing the aperture ratio of the display panel such as the liquid crystal panel, and improving
  • the brightness of the display panel such as the liquid crystal panel also reduces the manufacturing process steps, improves the utilization rate of the exposure machine that restricts the production efficiency, and reduces the production cost.
  • FIG. 1 is a top plan view of an embodiment of an array substrate of the present disclosure
  • Figure 2 is a cross-sectional view taken along line A-A of Figure 1;
  • FIG. 3 is a schematic structural view of an embodiment of a liquid crystal panel of the present disclosure.
  • FIG. 4 is a flow chart of an embodiment of a method of fabricating an array substrate of the present disclosure
  • 5 to 11 are schematic views showing the structure of the device obtained at each stage of a manufacturing method of the array substrate of the present disclosure. detailed description
  • An embodiment of the present disclosure provides an array substrate, including a substrate, and a thin film transistor, a scan line, a data line, and a pixel electrode formed on the substrate.
  • the gate and the source of the thin film transistor are respectively connected to the scan line and the data line, and the thin film transistor is connected.
  • the drain is connected to the pixel electrode.
  • the array substrate further includes: a black matrix disposed corresponding to the thin film transistor, the scan line, and the data line.
  • the corresponding settings mainly refer to the black matrix covering the thin film transistor, the scan line and the data line.
  • FIG. 1 is a plan view of an embodiment of an array substrate according to the present disclosure
  • FIG. 2 is a cross-sectional view taken along line AA of FIG.
  • the array substrate in this embodiment includes a substrate 101, a pixel electrode 110, a scan line 111 and a data line 112, and a thin film transistor including a gate electrode 102, a gate insulating layer 103, and an active layer.
  • 104a source 105 and drain 106.
  • a gate electrode 102, a gate insulating layer 103, an active layer 104a, a source electrode 105, a drain electrode 106, a pixel electrode 110, a scan line 111, and a data line 112 are prepared on the substrate 101; wherein the gate insulating layer 103 covers On the gate electrode 102, the active layer 104a is disposed on the gate insulating layer 103, and the ohmic contact layer 104b may be selectively formed between the active layer 104a and the source 105/drain 106 such that the active layer 104a passes the ohmic Contact layer 104b Connected to the source 105 and the drain 106, respectively, the pixel electrode 110 is connected to the drain 106 through the via 109.
  • the source 105 and the drain 106 may be covered with a protective passivation layer 107, the gate 102 is connected to the scan line 111, and the source 105 is connected to the data line 112.
  • a passivation layer 107 above the source 105 and the drain 106 is further covered with a black matrix 108, which is disposed corresponding to the thin film transistor, the scan line 111 and the data line 112. Considering the need to connect the pixel electrodes, the via region of the thin film transistor does not cover the black matrix.
  • the black matrix 108 and the pixel electrode 110 in this embodiment are disposed on the top layer of the array substrate, and the black matrix 108 is located on the adjacent sides of the pixel electrode 110.
  • the projection of the black matrix 108 on the substrate 101 will completely cover the projection of the thin film transistor, the scan line 111 and the data line 112 on the substrate 101, and the black matrix 108 is disposed complementary to the pixel electrode 110, that is, the black matrix 108 and the pixel electrode.
  • the projection patterns on the plane of the substrate 101 are complementary or approximately complementary so that the black matrix 108 can block light leakage in an area other than the pixel electrode 110 without interfering with light transmission of the pixel electrode 110.
  • the light When the light is incident perpendicular to the substrate 101, the light will exit from the transparent pixel electrode 110, and the light passing through the thin film transistor, the scanning line 111 and the data line 112 will be blocked by the black matrix 108, thereby ensuring that the light is emitted only from the pixel electrode 110. .
  • the I region corresponds to the pixel electrode 110 of the array substrate
  • the II region corresponds to the via 109 in the passivation layer 107
  • the III region corresponds to the black matrix 108 of the array substrate.
  • the black matrix 108 may be disposed at any position on the substrate 101, that is, the black matrix 108 may be located above the thin film transistor, the scan line or the data line, or may be located in the thin film transistor, the scan Below the line or data line, it is only necessary to ensure that the projection of the black matrix 108 on the substrate 101 will completely cover the projection of the thin film transistor, the scan line 111 and the data line 112 on the substrate 101, avoiding the black matrix 108 and the thin film transistor, the scan line 111 and data line 112 are deviated.
  • the via region of the thin film transistor may not cover the black matrix; since the drain metal formed at the bottom of the via hole also has a light blocking effect, the shading effect at the via hole is not affected.
  • the black matrix arrangement of the present disclosure may also be implemented in an electric field of a mode such as ADS, that is, the array substrate may further include a common electrode, wherein the common electrode is located above or below the pixel electrode, The upper side of the common electrode and the pixel electrode is in the shape of a slit.
  • Embodiments of the present disclosure also provide a display device using the above array substrate.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, and a number Any product or component with a display function such as a photo frame, mobile phone, or tablet.
  • the following is an example of a liquid crystal panel.
  • the liquid crystal panel of the present embodiment includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30, wherein the array substrate 10 uses any of the above array substrates, the black matrix 108 of the array substrate 10, and a thin film transistor, The scan line 111 and the data line 112 are correspondingly arranged.
  • the array substrate 10 is configured with the structure shown in FIGS. 1 and 2. Since the black matrix layer for preventing light leakage is already disposed on the array substrate 10, black is not required in the color filter substrate 30 in this embodiment. matrix.
  • the black matrix is disposed on the array substrate, and the black matrix is disposed corresponding to the thin film transistor, the scan line and the data line, thereby avoiding the black matrix and the array substrate disposed on the color filter substrate in the conventional display device.
  • the deviation between the thin film transistor, the data line and the scanning line solves the light leakage phenomenon caused by the above deviation, and also helps to reduce the area of the black matrix, increase the aperture ratio of the liquid crystal panel, and improve the brightness of the liquid crystal panel.
  • the display device provided by the embodiment of the present disclosure, because the black matrix on the array substrate is disposed corresponding to the thin film transistor, the scan line and the data line, avoiding the black matrix being disposed on the color filter substrate in the conventional display device, due to the color film substrate and the array The alignment of the substrate is inaccurate, causing the black matrix to deviate from the thin film transistor, the scan line and the data line on the array substrate, preventing light leakage caused by the above deviation, and also reducing the area of the black matrix, increasing the liquid crystal panel, etc.
  • the aperture ratio of the display panel increases the brightness of the display panel such as the liquid crystal panel.
  • the present disclosure also provides a method of fabricating an array substrate.
  • the method includes preparing a thin film transistor, a scan line, a data line, a pixel electrode, and a passivation layer on a substrate.
  • the method further includes preparing a black matrix on the array substrate, the black matrix is disposed corresponding to the thin film transistor, the scan line and the data line, and the black matrix may be located on the top layer of the array substrate or at any position between the substrate and the passivation layer. Just make sure that the projection of the black matrix on the substrate completely covers the projection of the thin film transistor, scan lines and data lines on the substrate.
  • FIG. 4 is a flow chart of an embodiment of a method for fabricating an array substrate of the present disclosure
  • FIGS. 5 to 11 are schematic structural views of devices obtained at various stages of a method for fabricating an array substrate of the present disclosure.
  • the manufacturing method of the array substrate of this embodiment specifically includes the following steps. Step 401: Prepare a gate on the substrate.
  • a metal layer and a photoresist layer are deposited on the substrate 101, and then the gate electrode 102, the scan line 111 and the common electrode are obtained through a mask process (in the figure).
  • the mask process includes a photolithography process of exposing and developing the photoresist to form a photoresist pattern of the gate electrode 102, the scan line and the common electrode in the photoresist layer, and then using the photoresist The pattern is used as an etch layer to etch the metal layer to obtain the gate 102, the scan lines, and the common electrode, and then proceeds to step 402.
  • Step 402 preparing a gate insulating layer, an active layer, a source electrode, and a drain electrode on the substrate on which the above steps are completed.
  • a gate insulating layer 103, a semiconductor material layer, a metal layer and a photoresist layer are sequentially deposited on the device for performing the above step 401, and then the photoresist layer is performed.
  • the electrode 106 and the data line 112, wherein the semiconductor material layer can be deposited from a semiconductor material such as a-Si, p-Si, IGZO (In-Ga-Zn-O).
  • a semiconductor material such as a-Si, p-Si, IGZO (In-Ga-Zn-O).
  • ion implantation may be performed on the semiconductor material layer after the deposition of the semiconductor material layer to obtain the ohmic contact layer 104b.
  • Step 403 preparing a passivation layer, a black matrix, and a pixel electrode on the substrate on which the above steps are completed.
  • a passivation layer 107, a black matrix 108, and a photoresist layer 119 are sequentially deposited on the device for performing the above steps, wherein the black matrix layer 108 and the photoresist layer 119 have the same Photosensitive material of the photoresist material; preferably, the black matrix 108 and the photoresist layer 119 are both negative photoresist materials, and the unexposed negative photoresist can be removed by the developer.
  • the photoresist layer is covered with a gray mask or a halftone mask.
  • the I region on the substrate 101 corresponds to a half-exposure region of the gray tone mask or the halftone mask
  • the II region corresponds to the unexposed region of the gray tone mask or the halftone mask
  • the III region corresponds to the gray
  • the photoresist layer 119 on the 1 region is removed but the black matrix layer of the region is removed.
  • 108 is retained, the photoresist layer 119 and the black matrix layer 108 on the II region are completely removed, and the photoresist layer 119 and the black matrix 108 on the III region are retained, thereby obtaining a photoresist layer pattern and black.
  • Matrix layer pattern is
  • the passivation layer 107 is etched using the photoresist layer pattern and the black matrix layer pattern obtained in Fig. 8 as a mask layer to obtain a pattern of via holes 109.
  • the photoresist 119 and the black matrix 108 on the substrate in FIG. 9 are subjected to ashing processing to control the time of the ashing process, and the black matrix 108 on the I region is completely removed, and the III region is simultaneously The photoresist layer 119 is partially removed so that a certain thickness of the photoresist layer 119 remains on the III region.
  • a layer of transparent conductive material 120 is deposited on the device shown in Fig. 10 to prepare a pixel electrode.
  • the transparent conductive material layer 120 may be, for example, indium tin oxide (ITO) or the like. Since the thickness of the black matrix 108 and the photoresist layer 119 on the III region is large, the top of the photoresist layer 119 on the III region is longer from the bottom of the via 109, so a transparent conductive material having a smaller thickness is deposited.
  • the transparent conductive material layer 120 is broken at the sidewall of the via hole 109 near the III region, resulting in the transparent conductive material layer on the I region and the transparent conductive material layer on the III region being independent of each other;
  • the lift off process strips the photoresist layer 119 by stripping off the photoresist layer 119 and the transparent conductive material layer 120 over the photoresist layer 119, and the stripping solution is
  • the black matrix 108 has no peeling effect.
  • the transparent conductive material layer on the photoresist layer 119 on the III region is stripped by the stripping solution, since the transparent conductive material layers on the I region and the III region are independent of each other, the transparent conductive material layer on the photoresist layer 119 on the III region.
  • the method further includes: forming a common electrode on the substrate on which the above steps are completed, the common electrode being slit-shaped.
  • the step of forming the common electrode of the ADS may further include the step of forming an insulating layer, which is no different from the prior art.
  • the step of forming the common electrode can also be arranged between certain steps of the above various steps according to the actual design to form different types of ADS structures.
  • the black matrix may be disposed at any position between the substrate and the passivation layer, as long as the dielectric constant of the black matrix is ensured to meet the electrical requirements of the array substrate, and details are not described herein.
  • a black matrix array substrate can be prepared by three mask processes.
  • the ADS mode needs to increase the masking process accordingly.
  • the black matrix is set corresponding to the thin film transistor, the scanning line and the data line, which not only avoids the black matrix and the array substrate disposed on the color film substrate in the conventional display device.
  • the leakage phenomenon caused by the deviation between the thin film transistor, the data line and the scanning line is beneficial to reducing the area of the black matrix, increasing the aperture ratio of the liquid crystal panel, improving the brightness of the display panel such as the liquid crystal panel, and reducing the preparation.
  • the process steps increase the utilization rate of the exposure machine that restricts the production efficiency and reduce the production cost.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及其制造方法和显示装置。阵列基板包括基板（101）以及在基板（101）上形成的薄膜晶体管、扫描线（111）、数据线（112）和像素电极（110）。薄膜晶体管中的栅极（102）和源极（105）分别与扫描线（111）和数据线（112）连接，薄膜晶体管的漏极（106）与像素电极（110）连接。阵列基板还包括黑矩阵（108）。黑矩阵（108）与薄膜晶体管、扫描线（111）和数据线（112）对应设置。通过将黑矩阵（108）设置在阵列基板上，并将黑矩阵（108）与薄膜晶体管、扫描线（111）和数据线（112）对应设置，避免了黑矩阵（108）与阵列基板的薄膜晶体管，数据线（112）和扫描线（111）之间发生的偏离，解决了由于上述偏离造成的漏光现象，同时也有利于降低黑矩阵的面积，增大了显示面板的开口率，提高显示面板的亮度。

Description

阵列基板及其制造方法和显示装置 技术领域
本公开涉及显示技术领域， 具体地， 涉及一种阵列基板及其制造方法和 显示装置。 背景技术
在薄月莫晶体管液晶显示器 (Thin Film Transistor Liquid Crystal Display, TFT-LCD)的生产领域， 液晶面板的开口率是一个重要的产品指标。 液晶面板 中的数据线、扫描线和薄膜晶体管，通常釆用设置在彩膜层中的黑矩阵遮挡， 黑矩阵区域不能透光。 液晶面板的开口率是指光线通过的那一部分的面积与 液晶面板整体的面积之间的比值。 开口率越高， 光线通过的效率越高。 而且， 液晶面板的高开口率对于提高液晶面板的清晰度、 亮度以及节省能源等方面 都具有重要意义。
常规的液晶面板通常包括阵列基板、 彩膜基板和液晶层， 液晶层对盒封 装在阵列基板和彩膜基板之间。 彩膜基板包括透明基板、 黑矩阵、 彩膜层和 公共电极， 阵列基板包括基板、 扫描线、 数据线、 薄膜晶体管和像素电极。 将阵列基板和彩膜基板对盒封装之后， 彩膜基板的黑矩阵与阵列基板的薄膜 晶体管、 扫描线和数据线对应设置， 以遮挡阵列基板的薄膜晶体管、 扫描线 和数据线位置处产生的漏光。 然而， 由于实际生产中的设备精度和工艺条件 的限制， 彩膜基板的黑矩阵与阵列基板的薄膜晶体管、 扫描线、 数据线很难 精确对应， 或者在使用液晶面板的时候， 外力的冲击也可能造成彩膜基板的 黑矩阵相对于阵列基板的薄膜晶体管、 扫描线、 数据线偏离， 都可能导致漏 光。 现有技术中， 可以通过增大黑矩阵的面积来避免阵列基板上的薄膜晶体 管、 扫描线、 数据线位置处的漏光产生的缺陷。 但是， 增大黑矩阵的面积将 导致液晶面板的开口率减小， 液晶面板的显示亮度低。
并且， OLED显示面板， 电子纸显示面板等显示面板也包括上述类似结 构的阵列基板。 当这些显示面板需要在与阵列基板相对设置的另一基板上设 置黑矩阵时， 同样存在上述黑矩阵失配造成的问题。 发明内容
本公开的实施例提供了一种阵列基板， 其包括基板， 以及在所述基板上 形成的薄膜晶体管、 扫描线、 数据线和像素电极， 所述薄膜晶体管的栅极和 源极分别与所述扫描线和数据线连接， 所述薄膜晶体管的漏极与所述像素电 极连接， 其特征在于， 所述阵列基板还包括： 黑矩阵， 所述黑矩阵与所述薄 膜晶体管、 扫描线和数据线对应设置。
在一个示例中， 所述黑矩阵和所述像素电极交错互补设置。
上述黑矩阵形成于所述薄膜晶体管、 所述扫描线或数据线上方。
上述黑矩阵形成于所述薄膜晶体管、 所述扫描线或数据线下方。
在一个示例中， 所述阵列基板还包括公共电极， 其中， 所述公共电极位 于所述像素电极的上方或者下方， 所述公共电极和所述像素电极中位于上方 者为狭缝状。 此时为 ADS型阵列基板。
在一个示例中， 黑矩阵可设置在钝化层上。 黑矩阵设置在钝化层与基板 之间。
本公开还提供一种显示装置， 其中包括上述的阵列基板。
本公开还提供一种阵列基板的制造方法， 包括在基板上制备薄膜晶体 管、 扫描线、 数据线和像素电极， 其中， 所述制造方法还包括：
在所述基板的上方制备黑矩阵， 所述黑矩阵与所述扫描线、 数据线和薄 膜晶体管对应设置。
其中， 所述在所述基板上方制备黑矩阵包括：
步骤 1、 在制备栅极、 栅绝缘层、 有源层、 源 /漏电极和数据线的基板上 沉积黑矩阵层和光刻胶层； 其中， 所述黑矩阵层和所述光刻胶层为具有相同 光感应特性的光刻胶材料；
步骤 2、 通过灰色调掩膜板或半色调掩膜板对完成步骤 1的基板进行构 图工艺以得到过孔， 然后灰化去除像素电极区域上的光刻胶和黑矩阵层， 同 时在基板的其余位置保留预设厚度的光刻胶层； 和
步骤 3、在完成步骤 2的基板上沉积透明导电层，利用离地剥离（lift off) 工艺剥离掉保留的光刻胶层以及其上的透明导电层， 形成像素电极的图形并 露出黑矩阵。
在一个示例中， 所述步骤 2包括：
步骤 21、利用灰色调掩膜板或半色调掩膜板对所述黑矩阵层和光刻胶层 进行曝光和显影处理， 形成光刻胶半保留区、 光刻胶完全去除区和光刻胶完 全保留区， 其中， 光刻胶半保留区对应像素电极区域， 光刻胶完全去除区对 应过孔区域， 光刻胶完全保留区对应黑矩阵层区域， 所述光刻胶半保留区域 中光刻胶被完全去除且黑矩阵层保留， 所述光刻胶完全去除区中光刻胶和黑 矩阵被完全去除；
步骤 22、 刻蚀所述光刻胶完全去除区的钝化层形成过孔的图形； 和 步骤 23、 对完成步骤 22的基板进行灰化处理， 控制灰化处理时间以去 除像素电极区域上的黑矩阵层， 同时在基板的其余位置保留预设厚度的光刻 胶层。
在一个示例中， 所述黑矩阵层和光刻胶层均由负性光刻胶材料形成。 在一个示例中， 所述阵列基板的制造方法还包括：
在完成所述步骤 3的基板上形成公共电极， 所述公共电极为狭缝状。 本公开提供的阵列基板和显示装置， 通过将黑矩阵设置在阵列基板上， 并将黑矩阵与薄膜晶体管、 扫描线和数据线对应设置， 避免了常规显示装置 中设置在彩膜基板上的黑矩阵与阵列基板上的薄膜晶体管、 数据线和扫描线 之间发生的偏离， 解决了由于上述偏离造成的漏光现象， 同时也有利于降低 黑矩阵的面积， 增大液晶面板等显示面板的开口率， 提高液晶面板等显示面 板的亮度。
本公开提供的阵列基板的制造方法， 通过 3次掩膜工艺就可以制备得到 设置有黑矩阵阵列基板， 黑矩阵与薄膜晶体管、 扫描线和数据线对应设置， 不仅避免了常规显示装置中设置在彩膜基板上的黑矩阵与阵列基板上的薄膜 晶体管、 数据线和扫描线之间发生偏离而造成的漏光现象， 有利于降低黑矩 阵的面积， 增大液晶面板等显示面板的开口率， 提高液晶面板等显示面板的 亮度， 同时也减少了制备的工艺步骤， 提高了制约生产效率的曝光机的利用 率， 降低了生产成本。 附图说明
为了更清楚地说明本公开或现有技术中的技术方案， 下面将对本公开提 供的技术方案或现有技术描述中所需要使用的附图作简单地介绍， 显而易见 地， 下面描述中的附图仅仅是本公开的技术方案的部分具体实施方式图示说 明， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以 根据这些附图获得其他的附图。
为了更清楚地说明本公开实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本公开的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1为本公开一种阵列基板实施例的俯视图；
图 2为图 1中 A-A方向的切面图；
图 3为本公开液晶面板实施例的结构示意图；
图 4为本公开阵列基板的一种制造方法实施例的流程图；
图 5至图 11为本公开阵列基板的一种制造方法的各个阶段所获得的装 置的结构示意图。 具体实施方式
下面将结合本公开实施例中的附图， 对本公开实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本公开一部分实施例， 而 不是全部的实施例。 基于本公开中的实施例， 本领域普通技术人员在没有作 出创造性劳动前提下所获得的所有其他实施例， 都属于本公开保护的范围。
本公开实施例提供一种阵列基板， 包括基板， 以及在基板上形成的薄膜 晶体管、 扫描线、 数据线和像素电极， 薄膜晶体管的栅极和源极分别与扫描 线和数据线连接， 薄膜晶体管的漏极与像素电极连接。 该阵列基板还包括： 黑矩阵， 该黑矩阵与薄膜晶体管、 扫描线和数据线对应设置。 对应设置主要 指黑矩阵覆盖薄膜晶体管、 扫描线和数据线。 下面， 以一个典型的实施例具 体介绍本公开实施例的阵列基板结构。
图 1为本公开一种阵列基板实施例的俯视图，图 2为图 1中 A-A方向的 切面图。 如图 1和图 2所示， 本实施例中阵列基板包括基板 101、 像素电极 110、 扫描线 111和数据线 112和薄膜晶体管， 该薄膜晶体管包括栅极 102、 栅绝缘层 103、 有源层 104a、 源极 105和漏极 106。 具体地， 在基板 101上 制备有栅极 102、 栅绝缘层 103、 有源层 104a、 源极 105、 漏极 106、 像素电 极 110、 扫描线 111和数据线 112; 其中， 栅绝缘层 103覆盖在栅极 102上， 有源层 104a设置在栅绝缘层 103上， 欧姆接触层 104b可以选择性地形成于 有源层 104a和源极 105/漏极 106之间，从而有源层 104a通过欧姆接触层 104b 分别与源极 105和漏极 106连接， 像素电极 110通过过孔 109与漏极 106相 连。 在源极 105和漏极 106上可覆盖一层具有保护作用的钝化层 107, 栅极 102与扫描线 111连接， 源极 105与数据线 112连接。 本实施例阵列基板中， 在源极 105和漏极 106等上方的钝化层 107上还覆盖一层黑矩阵 108, 黑矩 阵 108与薄膜晶体管、 扫描线 111和数据线 112对应设置。 考虑连接像素电 极的需要， 薄膜晶体管的过孔区域没有覆盖黑矩阵。
由图 2得知， 本实施例中的黑矩阵 108和像素电极 110设置于阵列基板 的顶层， 黑矩阵 108位于像素电极 110相邻的两侧。 其中， 黑矩阵 108在基 板 101上的投影将完全覆盖住薄膜晶体管、 扫描线 111和数据线 112在基板 101上的投影， 而且黑矩阵 108与像素电极 110互补设置， 即黑矩阵 108与 像素电极 110在基板 101的平面上的投影图形互补或近似互补， 以使黑矩阵 108既能阻挡除像素电极 110之外区域的漏光， 又不妨碍像素电极 110的透 光。 当光线垂直于基板 101入射时， 光线将从透明的像素电极 110出射， 而 经过薄膜晶体管、 扫描线 111和数据线 112的光线将被黑矩阵 108遮挡住， 从而确保光线只从像素电极 110出射。
由图 1所示， I区域对应阵列基板的像素电极 110, II区域对应钝化层 107中的过孔 109, III区域对应阵列基板的黑矩阵 108。
在实际应用中， 可以将黑矩阵 108设置在基板 101上的任何位置， 即黑 矩阵 108可位于所述薄膜晶体管、 所述扫描线或数据线上方， 也可位于所述 薄膜晶体管、 所述扫描线或数据线下方， 只要确保黑矩阵 108在基板 101上 的投影将完全覆盖住薄膜晶体管、 扫描线 111和数据线 112在基板 101上的 投影即可， 避免黑矩阵 108与薄膜晶体管、 扫描线 111和数据线 112发生偏 离。 当然， 考虑到连接像素电极的需要， 薄膜晶体管的过孔区域可以不覆盖 黑矩阵； 由于形成于过孔底部的漏极金属同样具有遮光作用， 因此并不影响 过孔处的遮光效果。
以上实施例描述的是传统的 TN模式的阵列基板。 进一步地， 本公开的 黑矩阵设置方式也可以在 ADS等模式的电场中实现，即所述阵列基板可以还 包括公共电极， 其中， 所述公共电极位于所述像素电极的上方或者下方， 所 述公共电极和所述像素电极中位于上方的为狭缝状。
本公开实施例还提供一种显示装置， 使用了上述的阵列基板。 所述显示 装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数 码相框、 手机、 平板电脑等任何具有显示功能的产品或部件。 下面以液晶面 板为例进行阐释。
图 3为本公开液晶面板实施例的结构示意图。 如图 3所示， 本实施例液 晶面板包括阵列基板 10、彩膜基板 20和液晶层 30, 其中， 阵列基板 10釆用 上述任意一种阵列基板， 阵列基板 10的黑矩阵 108与薄膜晶体管、 扫描线 111和数据线 112对应设置。 在本实施例中， 阵列基板 10釆用图 1、 2所示 的结构， 由于阵列基板 10上已经设置有防止漏光的黑矩阵层，所以本实施例 中的彩膜基板 30中不需要设置黑矩阵。
本实施例液晶面板中， 将黑矩阵设置在阵列基板上， 并将黑矩阵与薄膜 晶体管、 扫描线和数据线对应设置， 避免了常规显示装置中设置在彩膜基板 上的黑矩阵与阵列基板上的薄膜晶体管、 数据线和扫描线之间发生的偏离， 解决了由于上述偏离造成的漏光现象， 同时也有利于降低黑矩阵的面积， 增 大液晶面板的开口率， 提高液晶面板的亮度。
本公开实施例提供的显示装置， 由于阵列基板上的黑矩阵与薄膜晶体 管、 扫描线和数据线对应设置， 避免了常规显示装置中将黑矩阵设置在彩膜 基板时， 由于彩膜基板与阵列基板的对位不精确而导致黑矩阵与阵列基板上 的薄膜晶体管、 扫描线和数据线发生偏离， 防止由于上述偏离造成的漏光现 象， 同时也有利于降低黑矩阵的面积， 增大液晶面板等显示面板的开口率， 提高液晶面板等显示面板的亮度。
本公开还提供一种阵列基板的制造方法。 该方法包括在基板上制备薄膜 晶体管、 扫描线、 数据线、 像素电极和钝化层。 该方法还包括在阵列基板上 制备一层黑矩阵， 黑矩阵与薄膜晶体管、 扫描线和数据线对应设置， 黑矩阵 可以位于阵列基板的顶层， 也可以位于基板与钝化层之间的任意位置， 只要 确保黑矩阵在基板上的投影完全覆盖住薄膜晶体管、 扫描线和数据线在基板 上的投影即可。 当光线进入阵列基板时， 阵列基板的薄膜晶体管、 扫描线和 数据线的位置处的光线将被黑矩阵阻挡， 因此不会有光线输出。 在利用该阵 列基板制备的液晶面板时， 可以避免光线经过阵列基板的薄膜晶体管、 扫描 线和数据线的位置输出， 从而解决了液晶面板的漏光现象。
图 4为本公开的阵列基板的一种制造方法实施例的流程图，图 5至图 11 为本公开的阵列基板的一种制造方法的各个阶段所获得的装置的结构示意 图。 如图 4所示， 本实施例阵列基板的制造方法具体包括如下步骤。 步骤 401、 在基板上制备栅极。
在本步骤中， 如图 5所示并参阅图 1和 2, 在基板 101上沉积一金属层 和光刻胶层， 然后通过掩膜工艺得到栅极 102、 扫描线 111和公共电极 (图中 未示出），掩膜工艺包括对光刻胶进行曝光和显影的光刻工艺， 以在光刻胶层 中形成栅极 102、 扫描线和公共电极的光刻胶图案， 然后利用光刻胶图案作 为遮挡层对金属层进行刻蚀工艺， 从而得到栅极 102、 扫描线和公共电极， 然后进入步骤 402。
步骤 402、 在完成上述步骤的基板上制备栅绝缘层、 有源层、 源电极和 漏电极。
本步骤中， 如图 6所示并参阅图 1和 2, 在完成上述步骤 401的装置上 依次沉积栅绝缘层 103、 半导体材料层、 金属层和光刻胶层， 然后对光刻胶 层进行光刻以得到光刻胶图案， 然后利用该光刻胶图案作为遮挡层对半导体 材料层和金属层进行刻蚀， 以由半导体材料层得到有源层 104a, 由金属层得 到源极 105、 漏极 106和数据线 112, 其中， 半导体材料层可以由 a-Si、 p-Si、 IGZO ( In-Ga-Zn-O)等半导体材料沉积得到。在实际应用中， 为了增大有源层 140a与源极 105和漏极 106欧姆接触， 可以在沉积半导体材料层之后， 对半 导体材料层进行离子注入以得到欧姆接触层 104b。
在基板 101上制备栅绝缘层 103、有源层 104a、源电极 105和漏电极 106 之后， 进入步骤 403。
步骤 403、 在完成上述步骤的基板上制备钝化层、 黑矩阵和像素电极。 在本步骤中， 如图 7 所示， 在完成上述步骤的装置上依次沉积钝化层 107、 黑矩阵 108和光刻胶层 119, 其中， 黑矩阵层 108和光刻胶层 119为具 有相同光感应特性的光刻胶材料； 优选地， 黑矩阵 108和光刻胶层 119均为 负性光刻胶材料， 未被曝光的负性光刻胶可以被显影液去除。
如图 8所示并参阅图 1 , 利用灰色调掩膜板或半色调掩膜板对光刻胶层
119进行曝光,基板 101上的 I区域对应灰色调掩膜板或半色调掩膜板的半曝 光区域， II区域对应灰色调掩膜板或半色调掩膜板的未曝光区域， III区域对 应灰色调掩膜板或半色调掩膜板的完全曝光区域， 对经过曝光的黑矩阵 108 和光刻胶层 119进行显影之后，1区域上的光刻胶层 119被去除但该区域的黑 矩阵层 108则被保留， II区域上的光刻胶层 119和黑矩阵层 108被完全去除， III区域上的光刻胶层 119和黑矩阵 108被保留， 从而得到光刻胶层图案和黑 矩阵层图案。
如图 9所示， 利用图 8中得到的光刻胶层图案和黑矩阵层图案作为遮挡 层刻蚀钝化层 107以得到过孔 109的图形。
如图 10所示， 对图 9中的基板上的光刻胶 119和黑矩阵 108进行灰化 处理， 控制灰化处理的时间， 将 I区域上的黑矩阵 108全部去除， 同时将 III 区域上的光刻胶层 119部分去除，使 III区域上仍然保留一定厚度的光刻胶层 119。
如图 11所示， 在图 10所示的装置上沉积一层透明导电材料层 120以制 备像素电极。 透明导电材料层 120可以例如为铟锡氧化物 (ITO)等。 由于 III 区域上的黑矩阵 108和光刻胶层 119的厚度较大，因此 III区域上的光刻胶层 119的顶部距离过孔 109的底部较长， 所以在沉积厚度较小的透明导电材料 层 120时， 透明导电材料层 120在过孔 109靠近 III区域的侧壁处发生断裂， 导致 I区域上的透明导电材料层与 III区域上的透明导电材料层相互独立；参 阅图 2, 利用离地剥离 (Lift Off)工艺剥离光刻胶层 119, 该离地剥离工艺就是 利用剥离液来剥离掉光刻胶层 119以及光刻胶层 119上方的透明导电材料层 120, 而且该剥离液对黑矩阵 108无剥离作用。本实施例在釆用剥离液来剥离 III区域上的光刻胶层 119时，由于 I区域和 III区域上的透明导电材料层相互 独立， III区域上光刻胶层 119上的透明导电材料层也将随着光刻胶层 119而 脱离阵列基板， 从而露出黑矩阵 108, 而沉积在 I区域上的透明导电材料层 则形成像素电极 110, 从而得到包括有黑矩阵 108的阵列基板， 阵列基板如 图 1或 2所示。
以上工艺步骤， 实现了典型的 TN模式的阵列基板的制造。
在一个示例中， 在完成上述步骤后， 所述方法还包括： 在完成上述步骤 的基板上形成公共电极， 所述公共电极为狭缝状。 这样就形成了一种典型的 ADS模式的阵列基板结构。 本领域的技术人员可以理解， 上述形成 ADS的 公共电极的步骤， 还可能包括形成绝缘层的步骤， 其与现有技术无异， 此处 不赘。 当然， 形成公共电极的步骤也可以根据实际设计安排在上述各个步骤 的某些步骤之间， 以形成不同类型的 ADS结构。
在实际应用中， 也可以将黑矩阵设置在基板和钝化层之间的任意位置， 只要确保黑矩阵的介电常数符合阵列基板的电学要求即可， 在此不再赘述。
本实施例中， 通过 3次掩膜工艺就可以制备得到设置有黑矩阵阵列基板 (针对 TN模式， 制作 ADS模式需相应增加掩摸工艺 ), 黑矩阵与薄膜晶体 管、 扫描线和数据线对应设置， 不仅避免了常规显示装置中设置在彩膜基板 上的黑矩阵与阵列基板上的薄膜晶体管、 数据线和扫描线之间发生偏离而造 成的漏光现象， 有利于降低黑矩阵的面积， 增大液晶面板的开口率， 提高液 晶面板等显示面板的亮度， 同时也减少了制备的工艺步骤， 提高了制约生产 效率的曝光机的利用率， 降低了生产成本。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本发明的范畴， 本发明的专 利保护范围应由权利要求限定。

Claims

权利要求书
1. 一种阵列基板， 包括基板， 以及在所述基板上形成的薄膜晶体管、 扫 描线、 数据线和像素电极， 所述薄膜晶体管的栅极和源极分别与所述扫描线 和数据线连接， 所述薄膜晶体管的漏极与所述像素电极连接， 其特征在于， 所述阵列基板还包括：
黑矩阵， 所述黑矩阵与所述薄膜晶体管、 扫描线和数据线对应设置。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 所述黑矩阵和所述像 素电极互补设置。
3. 根据权利要求 1或 2所述的阵列基板，其特征在于上述黑矩阵形成于 所述薄膜晶体管、 所述扫描线或数据线上方。
4. 根据权利要求 1-3任一所述的阵列基板，其特征在于上述黑矩阵形成 于所述薄膜晶体管、 所述扫描线或数据线下方。
5. 根据权利要求 1-4任一所述的阵列基板， 其特征在于， 所述阵列基板 还包括公共电极， 其中， 所述公共电极位于所述像素电极的上方或者下方， 所述公共电极和所述像素电极中位于上方者为狭缝状。
6. 一种显示装置，其特征在于， 包括权利要求 1~5任一项所述的阵列基 板。
7. 一种阵列基板的制造方法， 包括在基板上制备薄膜晶体管、 扫描线、 数据线和像素电极， 其特征在于还包括：
在所述基板的上方制备黑矩阵， 所述黑矩阵与所述扫描线、 数据线和薄 膜晶体管对应设置。
8. 根据权利要求 7所述的阵列基板的制造方法， 其特征在于， 所述在所 述基板上方制备黑矩阵包括：
步骤 1、 在制备栅极、 栅绝缘层、 有源层、 源 /漏极和数据线的基板上沉 积黑矩阵层和光刻胶层； 其中， 所述黑矩阵层和所述光刻胶层为具有相同光 感应特性的光刻胶材料；
步骤 2、 通过灰色调掩膜板或半色调掩膜板对完成步骤 1的基板进行构 图工艺以得到过孔， 然后灰化去除像素电极区域上的光刻胶和黑矩阵层， 同 时在基板的其余位置保留预设厚度的光刻胶层；
步骤 3、在完成步骤 2的基板上沉积透明导电层，利用离地剥离（lift off ) 工艺剥离掉保留的光刻胶层以及其上的透明导电层， 形成像素电极的图形并 露出黑矩阵。
9. 根据权利要求 8所述的阵列基板的制造方法， 其特征在于， 所述步骤 2包括：
步骤 21、利用灰色调掩膜板或半色调掩膜板对所述黑矩阵层和光刻胶层 进行曝光和显影处理， 形成光刻胶半保留区、 光刻胶完全去除区和光刻胶完 全保留区， 其中， 光刻胶半保留区对应像素电极区域， 光刻胶完全去除区对 应过孔区域， 光刻胶完全保留区对应黑矩阵层区域， 所述光刻胶半保留区域 中光刻胶被完全去除且黑矩阵层保留， 所述光刻胶完全去除区中光刻胶和黑 矩阵被完全去除；
步骤 22、 刻蚀所述光刻胶完全去除区的钝化层形成过孔的图形； 步骤 23、 对完成步骤 22的基板进行灰化处理， 控制灰化处理时间以去 除像素电极区域上的黑矩阵层， 而且在基板的其余位置保留预设厚度的光刻 胶层。
10. 根据权利要求 8所述的阵列基板的制造方法， 其特征在于， 所述黑矩阵层和光刻胶层均由负性光刻胶材料形成。
11. 根据权利要求 8所述的阵列基板的制造方法， 其特征在于，还包括： 在完成所述步骤 3的基板上形成公共电极， 所述公共电极为狭缝状。
PCT/CN2012/086403 2012-03-31 2012-12-12 阵列基板及其制造方法和显示装置 WO2013143321A1 (zh)

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CN102981306B (zh) * 2012-12-07 2016-03-30 京东方科技集团股份有限公司 一种彩色滤光片的制作方法
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